MT41K128M16JT-125 IT:K

MT41K128M16JT-125 IT:K is a 1.35V DDR3L SDRAM device. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one half-clock-cycle data transfers at the I/O pins. The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is centre-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. The DDR3 SDRAM operates from a differential clock (CKandCK#).

• 128 Meg x 16 configuration, tCK = 1.25ns, CL = 11 speed grade, 16 Meg x 16 x 8 banks configuration
• 8K refresh count, 16K A[13:0] row address, 8 BA[2:0] bank address, 1K A[9:0] column address
• 1866MT/s data rate, 11-11-11 target tRCDt-RP-CL, 13.75ns tRCD, 13.75ns tRP, 13.75ns CL
• VDD = VDDQ = 1.35V (1.283–1.45V), backward-compatible to VDD = VDDQ = 1.5V ±0.075V
• Differential bidirectional data strobe, 8n-bit prefetch architecture self refresh mode
• Differential clock inputs (CK, CK#), 8 internal banks, programmable CAS (WRITE) latency (CWL)
• Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
• Programmable CAS (READ) latency (CL), programmable posted CAS additive latency (AL)
• Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])
• 96-ball FBGA package, industrial operating temperature range from -40°C to +95°C