D1216ECMDXGJD-U
DRAM, DDR3/3L, 2 Gb, 128M x 16bit, 933 MHz, 96 Pins, FBGA
- RoHS 10 Compliant
- Tariff Charges
D1216ECMDXGJD-U is a DDR3/3L DRAM. It is a on-board DRAM that is designed to meet the needs of embedded applications and offers a low-voltage option for lower power consumption. The bi-directional differential data strobe (DOS and /DQS) is transmitted/received with data for capturing data at the receiver. Market segments are industrial IoT / robotics and factory automation, 5G networking/telecommunications communication modules (Wi-Fi routers and mesh devices), wearables (smart watches, health monitors, AR and VR), smart home (sound bars, thermostats, fitness equipment, vacuums, beds, taps), smart city (HVAC, lighting, power monitoring/metering, parking meters).
- High-speed data transfer is realised by 8 bits prefetch pipelined architecture
- Double Data Rate (DDR) architecture: two data transfers per clock cycle
- DOS is edge-aligned with data for READS; centre-aligned with data for WRITES
- Differential clock inputs (CK and /CK), DLL aligns DQ and DOS transitions with CK transitions
- Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
- Data mask (DM) for write data, on-die termination (ODD for better signal quality)
- Multi-purpose register (MPR) for predefined pattern read out, ZQ calibration for DO drive and ODT
- Programmable partial array self-refresh (PASR), RESET pin for power-up sequence and reset function
- 2Gb capacity, 128Mx16 configuration (words x bits), 1866Mbps speed
- 1.35V VDD/VDDQ, 0°C to +95°C operating temperature, 96-ball FBGA package
Technical Attributes
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ECCN / UNSPSC / COO
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| Country of Origin: | null |
| ECCN: | EAR99 |
| HTSN: | null |
| Schedule B: | null |