IS61LPS25636A-200TQLI
SRAM Chip Sync Quad 3.3V 9M-Bit 256K x 36 3.1ns 100-Pin TQFP
The ISSI IS61LPS25636A is a highspeed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61LPS25636A is organized as 262,144 words by 36 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAMcore, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs.
- Internal self-timed write cycle
- Individual Byte Write Control and Global Write
- Clock controlled, registered address, data and control
- Burst sequence control using MODE input
- Three chip enable option for simple depth expansion and address pipelining
- Common data inputs and data outputs
- Auto Power-down during deselect
- Single cycle deselect
- Snooze MODE for reduced-power standby
- JTAG Boundary Scan for BGA package
- Power Supply LPS: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%
- JEDEC 100-Pin QFP, 119-ball BGA, and 165-ball BGA packages
- Lead-free available
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| 18 Bit | ||
| Pipelined | ||
| 200 MHz | ||
| SDR | ||
| 9 Mbit | ||
| Matte Tin | ||
| 260 | ||
| 200 MHz | ||
| 275 mA | ||
| 3.1 ns | ||
| 9 Mbit | ||
| Surface Mount | ||
| MSL 3 - 168 hours | ||
| 100 | ||
| 36 Bit | ||
| 36 Bit | ||
| 4 | ||
| 256 kWords | ||
| -40 to 85 °C | ||
| 85 °C | ||
| -40 °C | ||
| 100TQFP | ||
| 100 | ||
| 20.1 x 14.1 x 1.45 mm | ||
| No | ||
| Industrial | ||
| TQFP | ||
| 3.465 V | ||
| 3.135 V | ||
| 3.3 V | ||
| Synchronous | ||
| 3.3000 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | null |
| ECCN: | EAR99 |
| HTSN: | PARTS... |
| Schedule B: | PARTS... |