New Product Introduction

XILINX Spartan-7 FPGAs I/O optimization

Spartan®-7 FPGAs devices offer roughly 50% power reduction vs. previous Spartan families, while at the same time delivering a 30% performance improvement.

XILINX Spartan-7 FPGAs product image

Spartan®-7 devices offer roughly 50% power reduction vs. previous Spartan families, while at the same time delivering a 30% performance improvement.

The devices are supported by the free Vivado HL WebPACK Edition to help increase design productivity. Vivado IP Integrator provides correct-by-construction block-level design with a catalog of over 200 available IP solutions, while proven place and route technology enables faster timing closure and higher utilization.

 

Key features

  • Scalable 7 series CLB architecture
  • Small form factor, high performance-per-watt
  • Manufactured with TSMC’s 28nm HPL process
  • RoHS-compliant packaging for optimized connectivity solution

 

Additional features

28nm TSMC HPL Process Technology

  • Flexible LUTs are configurable as logic, distributed RAM, or shift registers
  • From 6K – 102K logic cells for system-level integration

Cost-Optimized 

  • Multiple efficient integrated blocks for BOM cost reduction, including XADC dual 12-bit analog-to-digital converters with supply voltage and thermal monitoring
  • Optimized selection of I/O standards

Embedded Processing

  • MicroBlaze soft processor with over 200DMIPS processing power

Integrated Memory Block Capacity up to 4.2MB

  • Efficient and high-performance block RAM with byte write enables optional FIFO configuration
  • 36K blocks can be split into two independent 18K block RAMs

Soft Memory Controller

  • DDR3/DDR2/LPDDR2 support
  • Data rates up to 800Mb/s (25.6Gb/s peak bandwidth)
  • Ultimate pinout flexibility
  • Software wizard to guide through the entire process

SelectIO Interface Technology

  • Up to 1.25Gb/s LVDS data rate, with up to 240Gb/s aggregate bandwidth
  • 3.3V to 1.2V I/O standards and protocols
  • HSTL and SSTL memory interfaces
  • Adjustable slew rates for added signal integrity

Efficent DSP48E1 Slices

  • Each slice contains a fast 18x25 wide multiplier with 48-bitaccumulator and 25-bit pre-add
  • Capable of up to 176GMACs at 551MHz
  • Pipelining, balancing, cascading, SIMD support, integrated pattern detect and ALU

Design Security

  • Device DNA serial number and eFUSE identifier
  • AES256 decryption and SHA-256 authentication for bitstream
  • Tamper monitoring and response

Small, RoHS 6/6 Compliant Packaging

  • 8mm – 27mm package footprints at 0.5mm – 1mm pitch

 

Applications

  • Machine Vision Interfacing
  • Single-Axis Motor Control
  • Industrial/automotive connectivity and processing
  • Infotainment, consumer, communications