2018-06 NXP MCUXpresso Workshop DE + CH

Display portlet menu

i.MX RT hands-on Seminar

04 Oct 2018 - 18 Oct 2018

Germany & Switzerland


NXP
 

Avnet Silica and NXP invite you to discover the new i.MX RT  «Crossover» Processor in a free-of-charge workshop. 

You will have the opportunity to assist to presentations and run hands-on trainings around the new Industry’s first «Crossover» processor. This device is  based on the ARM® Cortex®-M7 and delivers a CoreMark score of 3020, 1284 DMIPS and 20ns interrupt latency at 600 MHz – Available now and priced at a fraction of the cost of competing solutions.

This new portfolio of i.MX RT, a « Crossover »  solution bridges the gap between high performance and integration while minimizing costs. As the need for smarter and more ‘aware’ edge computing grows and becomes critical to the development of the Internet of Things (IoT), edge devices are expected to provide the highest compute performance together with reliable security at the lowest cost possible.

These essential capabilities with enablers like graphics, display support and seamless connectivity increase system-level costs and extend time-to-market. NXP tackles this challenge by architecting i.MX RT crossover processors to deliver high performance and functional capabilities of applications processors, but with the ease-of-use and real-time deterministic operation of traditional microcontrollers (MCUs). Ideal applications include audio subsystems, consumer and healthcare, home and building automation, industrial computing, motor control and power conversion.

During the training you will run labs on the i.MX RT1050 Evaluation Kit with the new free of charge IDE, MCUXpresso.
 

Date & venue

  • October 04, 2018 - Rothrist - Avnet EMG AG, Rössliweg 29b, 4852 Rothrist

  • October 16, 2018 - Stuttgart - relexa Waldhotel Schatten, Magstadter Str. 2-4, 70569 Stuttgart

Agenda

08:30 Registration
09:00 Welcome
09:10 NXP MCU/MPU Strategy
09:40 i.MX RT overview (Block diagram, peripherals, security) & around the core overview
10:30 Getting Started with MCUXpresso SDK for i.MXRT105X (pre-installation is required)
10:45 Break
11:00
LAB 1 – Hello world plus
  • Run the application from different memory targets
  • Demonstrates Pin Tool for pin configuration of i.MXRT1050
12:30 Lunch break
13:30 LAB 2 - Graphics & PXP Hands-On Lab
  • Demo example to place a graphic image into SDRAM
  • Configure the PXP to rotate, scale, chroma-key process and flip (mirror) the image.
14:30 Meeting the memory challenge
15:00 Break
15:15
LAB 3 – Zephyr: A Small, Scalable Open Source RTOS for IoT Embedded Devices
  • Introduction to RTOS and Zephyr
  • Demo: Building a Zephyr Application
  • Lab: Testing the Demo
16:45 End

 

Contact

Uwe Hirsch
Area Technical Manager

Registration

Please note that the number of seats are limited due to the limited number of places (hardware).

 

See details

2018-06 NXP MCUXpresso Workshop DE + CH

Display portlet menu

RELATED EVENTS

Avnet Silica & Xilinx SpeedWays

MiniZed SpeedWay Design Workshops™

20 Feb 2018 - 31 Dec 2018
pan-European, Multiple dates / locations

The MiniZed SpeedWay Design Workshops presented by Avnet Silica help engineers jump-start the development of single-core Xilinx Zynq-7000 All Programmable SoC devices using the Avnet MiniZed Zynq SoC development kit.

Avnet Silica and Microchip Seminar

Cloud in 10 Minutes based on AE-Cloud1 Kit

28 Nov 2018 - 28 Nov 2018
Dortmund, Germany

In this one-day workshop, you will learn how Renesas Synergy accelerates the development of complex embedded apllications with the Synergy Enterprise Cloud Toolbox. (More details in German).

Avnet Silica and Microchip Seminar

Microchip SAMA5 SOM hands-on training

09 Oct 2018 - 15 Nov 2018
Multiple dates / locations

Avnet Silica and Microchip are pleased to invite you to the first European training sessions for the SAMA5D2 System-on-Module.