Jump-start your AI based FPGA application
19 Nov 2019 - 21 Nov 2019
Switzerland, multiple locations
Learn how easy it is to realize your own AI application with the Xilinx edge machine learning flow
We'd like to invite you to this free seminar, arranged by Enclustra and Avnet SILICA, on FPGA-based AI applications.
It has never been so easy to jump-start AI applications. Thanks to FPGAs, like the Xilinx Zynq UltraScale+ MPSoCs, the power of AI can now also be used offline and on the edge. Be it image detection and classification, pattern or voice recognition for manufacturing, health care, automotive or financial services: the combination of an Enclustra SoC Module together with the Xilinx Machine Learning (ML) Suite that provides users with the tools to develop and deploy Machine Learning applications for Real-time Inference make it a snap to integrate AI in your application.
During this event, expert engineers from Avnet SILICA and Enclustra will give an introduction to AI and machine learning, and explain concepts, tools and realization on FPGAs. Based on the Enclustra Mars XU3 Xilinx Zynq UltraScale+ MPSoC Module it is shown how to implement a vision system that is recognigzing fruits, even with minimal VHDL and FPGA know-how.
Take the opportunity to benefit from the experience of the Avnet SILICA and Enclustra engineers. For all participants we do offer an AI starter kit for a special price of only CHF 349. (regular price over CHF 500).
Who should join
The seminar is aimed at all developers working with SoCs and FPGAs, in particular
- Embedded software developers
- System and software architects
- FPGA/SoC developers
- FPGA/SoC newcomers
- Project managers
- Team leaders
Dates and venues
- Registration closed for November 19, 2019 - EPFL Lausanne - Building Odyssee (ODY), Room -1 0020 (Route Cantonale 1015 Lausanne, Switzerland)
- November 21, 2019 - ZHaW Zürcher Hochschule für Angewandte Wissenschaften Winterthur - Room TP 408 (Technikumstrasse 9, 8401 Winterthur, Switzerland)
- 08:45 - 09:00 - Registration
- 09:00 - 09:25 - Welcome and introduction
- 09:25 - 10:00 - Introduction to artificial intelligence
- 10:00 - 10:30 - Introduction to machine learning on FPGAs
- 10:30 - 10:45 - Break & Table show
- 10:45 - 11:15 - Xilinx Deep Learning Solutions
- 11:15 - 12:00 - Keras/TensorFlow ResNet50 Training: Building a «Fruit Recognizer» on the Enclustra Mars XU3 SOM
- 12:00 - 13:00 - Lunch
- 13:00 - 13:30 - Integration of the Deep Learning Processing Unit in Vivado
- 13:30 - 14:15 - Xilinx DNNDK: From a Tensor Flow net to the DPU Firmware
- 14:15 - 14:30 - Break & Table show
- 14:30 - 15:00 - Programming Model: The DPU API
- 15:00 - 15:30 - Lausanne: Introduction of the Embedded Systems Laboratory
Winterthur: Direct communication between FPGA and GPU using Frame Based DMA (FDMA)
- 15:30-16:00 - Round-up, questions and answers
- 16:00-16:30 - Table show & meet the experts
Registration is closed.