Zero Downtime Industrial IoT Using Programmable SoCs
Armando Astarloa, SoC-e CEO
Michael Zapke, Xilinx Product Marketing Manager
Matthew Brown, Avnet Technical Marketing Manager
Industry 4.0 and Industrial IoT (IIoT) systems rely on robust communication networks. Protocols such as HSR (High-availability Seamless Redundancy) and PRP (Parallel Redundancy Protocol) ensure high availability for networks on critical infrastructure, offering zero-delay recovery time and no frames lost in the case of a network failure. This paper describes an IP design from SoC-e for the Xilinx Zynq®-7000 SoC, providing a flexible solution for equipment that will be connected to HSR rings, PRP LANs, or will work as a network bridge in the context of IEC 61850. In order to demonstrate the design, we use Avnet’s MicroZed™ Industry 4.0 Ethernet Kit to evaluate different modes of operation and node topologies regarding time-aware (IEEE 1588) high availability networks.
Understanding HSR and PRP Networks
Reliable Ethernet Networks are gaining acceptance for many Industrial Automation applications. One illustrative example of this evolution is the adoption by the International Electrotechnical Commission (IEC) of the High-availability Seamless Redundancy (HSR) Ethernet based protocol and Parallel Redundancy Protocol (PRP) for Power Substations Automation (IEC 62439-3 clauses 4 and 5). Both protocols offer zero switchover delay time, no-frames lost in case of failure, and strong means for network supervision at Layer 2. Moreover, both protocols support IEEE 1588 synchronization over redundant paths.
The redundancy of PRP is implemented in the nodes rather than in the network. Specially adapted nodes (Dual Attached Nodes- DANs), are connected to two independent Ethernet networks (LAN A and LAN B), and send the same frames over both networks. Figure 1 depicts a basic PRP network representation. In a fault-free state, destination nodes (Single Attached Nodes – SANs) consume the first received frame and discard the duplicates. In case of a fault in one of the networks, the frames will still be transmitted and received through the other.
End nodes that require redundancy but lack two network ports and do not themselves implement PRP are connected to both networks through a so-called redundancy box (RedBox). The RedBox provides connection to both LANs and serves as a proxy for these end nodes. In this topology, nodes behind a RedBox appear as DANs on the network and are therefore referred to as Virtual DANs (VDANs).
In the case of HSR, redundancy is provided by sending packets in both directions through a ring network. This type of network consists of HSR capable Doubly Attached bridging Nodes (DANHs), each having two Ethernet ports. An HSR capable node sends the same frame over both ports. An HSR capable destination node receives, in a fault-free state, two identical frames over both ports respectively within a certain interval. The first received frame is accepted while the duplicate is discarded. In the event of an interruption in the ring, the frame will always be received through the other port. Figure 2 summarizes a basic HSR network configuration.
Often a system will implement both protocols in order to increase reliability and provide greater safety. Figure 3 depicts an application implementing both HSR and PRP protocols together in the automation for a Power Substation. HSR has been designed to meet the strict communications requirements set for Process Bus in the IEC 61850. Thus, it is applied for Intra-Bay communications. HSR interconnects Intelligent Electronic Devices (IEDs) in each bay. Thanks to each IED functioning as a DANH there is no need for additional switches to conform the ring. As can be seen in “Substation Bay 2,” the conventional Ethernet devices (with single Ethernet ports) are attached to the HSR ring through a RedBox device.
PRP is suitable to be used for Station and Inter-Bay Buses. Thanks to its flexibility, it can attach many heterogeneous devices. Equipment with redundant needs is connected to both Ethernet LANs (LAN A and LAN B in Figure 3). As with HSR, network devices with RedBox topology can be used to attach equipment with a single Ethernet port to a PRP set-up composed of two independent LANs.
As depicted in this example, in order to maintain redundancy in the communications, the interconnection between PRP and HSR networks is performed using redundant gateways. Each HSR link is connected to each PRP LAN using two gateway devices. Thus, a potential single point of failure is avoided.
Other critical systems like Transportation and Industry benefit from these high availability protocols. Zero delay recovery time means, from the functional point of view, seamless “Plug and Work” operation. As an example, Figure 4 shows an HSR topology suitable for train communications. In this setup, the plug and un-plug operations among vehicles do not interrupt the communication.
All Programmable SoC for Deterministic Connectivity
Designers of HSR and PRP equipment face multiple challenges when deploying robust yet flexible hardware. For example, industrial communication comes with requirements that go beyond the features of standard IT network connectivity. Pure software implementations of protocols like HSR and PRP suffer latency and compromise determinism as more is demanded of the host processor. On the other hand, typical system architectures place a communication processor and/or an application processor next to the industrial network interface. A heterogeneous integration of controllers with deterministic hardware is needed.
The challenge is further complicated by the constant evolution of Industrial IoT protocols, even if they rely on IEEE and IEC standards. HSR and PRP have seen changes in IEC 62439-3 with influence on their implementation. A programmable solution with deterministic circuits is the most flexible and efficient way to meet this challenge while maintaining compatibility with the installed base and new networks.
Finally bandwidth requirements differ across applications. Solutions ideally support scaling without performance loss, allowing the addition of multiple instances of an interface in one system-on-chip or the flexibility of I/Os to communicate with various physical layer devices.
All Programmable SoCs provide ideal device architecture: Programmable Logic (also known as FPGA fabric) for deterministic network frontends in hardware circuitry, resources for executing communication stacks in a softcore microcontroller, and Dual ARM® Cortex™ A9 application processors. Xilinx’ Zynq product lineups have devices with different sizes of Programmable Logic, so that scaling to multiple network interfaces without compromising performance is more practicable than with any other device technology. In addition, the Processing System of Xilinx Zynq comes with built-in peripherals for Gigabit Ethernet, memory controllers, CAN, USB, etc. This provides all functions for differentiating features on the same chip with high performance and strictly deterministic networks.
Leading innovation drivers provide the newest network technologies as IP Cores implemented in the Zynq Programmable Logic. This allows for almost immediate prototyping and fast time to market with the capability to remotely adapt to standards evolution even in products which are already in stock or even shipped to the end customer. HSR/PRP switching IP cores from Xilinx Alliance Partner SoC-e are evidence for this as they have innovative features, high performance, and suitability for a respectable number of applications in various market segments. These IP Cores have already been licensed to more than 30 companies worldwide.
Anatomy of the SoC-e HSR/PRP Switch for Zync
The SoC-e HSR/PRP Switch IP is implemented entirely in the Programmable Logic (PL) of a Zynq-7000 device. Figure 6 presents the block diagram of the design executed on Avnet’s Industry 4.0 Ethernet Kit (I4EK), based on their MicroZed™ System-on-Module (SOM) shown in Figure 5.
MicroZed SOMs are compact modules designed for prototype and quick integration into your end application, even within industrial temperature environments. Embedded processing with the Zynq Z-7010 or Z-7020 SoC integrates a Dual ARM Cortex-A9 MPCore processor subsystem (PS) with programmable logic (PL). MicroZed provides built-in peripherals like USB 2.0, Gigabit Ethernet, and DDR3 memory. A module like this forms a pre-built embedded processing and control system, allowing differentiated features and interfaces to be added as a custom carrier card.
In this system a VITA57 compliant daughter card (AES-FMC-ISMNET2-G) presents two 10/100 Mb/s Ethernet interfaces and a variety of other industrial-type connections. The MicroZed FMC Carrier provides power to the MicroZed SOM, connection to the FMC card, and expansion Pmod™ I/O headers.
The SoC-e Switch IP uses the Zynq PL to host the 1588-aware HSR/PRP Switch (HPS) and the Precise Time Basic (PTB) IP. HPS in this design is configured with three Fast Ethernet ports. Port A and Port B are the external connections. The remaining port internally links the Zynq PL-based switch to one of the Zynq PS GMAC peripherals. An external enterprise Ethernet port is also provided at Port C using the other Zynq PS GMAC peripheral. The PTB module is in charge of time stamping and sniffing IEEE 1588v2 traffic. Additionally, this IP embeds a 64 bit IEEE 1588v2 synchronized timer. Finally, the design also includes connections to a Zynq PS UART for testing purposes and to provide simple means to interact with the demo.
In order to evaluate the IP on the MicroZed I4EK platform, SoC-e provides Linux-based applications for configuration and network visualization. From the software point of view, the demo boots Linux from an SD card located on the MicroZed SOM. An HTML5 RESTAPI runs under Linux and provides a user-friendly interface to configure the switch, monitor the network, and remotely update firmware (see Figure 7). A PTP Software stack runs an IEEE 1588v2 Ordinary Clock functionality on the nodes.
While useful for evaluation and development, this software is in no way required to operate the HSR/PRP network. The 3-port Ethernet HSR/PRP switch executes autonomously in the Zynq PL and therefore does not require any software to provide HSR/PRP networking. Similarly the IEEE 1588v2 P2P Transparent Clock operation is autonomously performed by the dedicated IP in the Zynq PL.
Getting started with an HSR/PRP demonstration on the MicroZed I4EK is easy. Simply download the boot file, copy it to the provided SD card, and boot the system. To start designing with the IP an example Xilinx Vivado™ project is provided after signing a license agreement.
When you are ready to move your design from prototype to production, MicroZed SOM was built for end-product deployment and may be purchased in volume. The MicroZed portfolio includes versions rated for industrial temperature ranges.
SoC-e IP cores support flexible licensing schemes, from royalties to site source code. These modules are fully configurable by VHDL generics, in order to provide optimized solutions from a simple Fast Ethernet 3 Port Switch up to multi-port complex GbE switching matrixes combining different network protocols. SoC-e also offers custom modification and dedicated engineering support team.
Written By: Armando Astarloa, Matt Brown and Michael Zapke
Armando Astarloa received the M.Sc. and Ph.D. degree in Electrical Engineering from the University of the Basque Country, Spain, in 1999 and 2005 respectively. After several years developing his professional career as development engineer in the private sector, in 2001 he joined the staff of the University of the Basque Country in the School of Engineering of Bilbao as a full time researcher and professor. He is founding member of the Research Applied Electronics Research Team (APERT) and his research has been focused on the design of reliable electronic systems based on reconfigurable devices. He is committee member in IEC and IEEE working groups and, as a result of this research activity. He is co-author of dozens of scientific contributions in international journals, book chapters, patents and papers in scientific conferences. In 2008 he enrolled in the Institute of Microelectronics and Wireless Systems in Ireland as a visiting researcher and in 2010, he launched System-on-Chip engineering S.L. (SoC-e.com) business project. Since January 2016, he is SoC-e CEO.
Matt Brown is an engineer in Avnet’s Technical Marketing group, creating development kits and reference designs featuring new technology for industrial control and software-defined radios. During his career, Matt has designed hardware at Motorola for the Iridium™ satellite phone and high-performance signal processing algorithms in FPGAs as a field applications engineer at Avnet. Matt has a Bachelor’s Degree of Science in Electrical Engineering from the University of Michigan.
Michael Zapke is Product Marketing Manager for Industrial Applications at Xilinx in Munich, Germany. He has over 20 years in as Project Manager for ASIC and FPGA designs and as the Head of Systems Engineering for Telecom infrastructure equipment. For Xilinx he shapes since 2013 innovations for industrial applications on All Programmable technologies from Xilinx in close cooperation with leading companies and Universities.