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ISSI introduces new 16Mb low-power asynchronous SRAM

The ISSI IS62/65WV102416GALL/BLL are high-speed, low power, 16M bit static RAMs organized as 1024K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology.

This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CS1# is HIGH (deselected) or when CS2 is LOW (deselected) or when CS1# is LOW, CS2 is HIGH and both LB# and UB# are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels.

Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE#) controls both writing and reading of the memory. A data byte allows Upper Byte (UB#) and Lower Byte (LB#) access.

The device supports 16 I/Os when BYTE# is High, and 8 I/Os when BYTE# is Low. In x8 mode, UB#, LB#, and I/O8~I/O14 are not used, and I/O15 becomes A20.

The IS62/65WV102416GALL/BLL are packaged in the JEDEC standard 48-Pin TSOP (TYPE I)

Key features

  • ISSI IS62/65WV102416GALL/BLL sample imageHigh-speed access time: 45ns, 55ns
  • CMOS low power operation
    • Operating Current: 36mA (max.)
    • CMOS standby Current: 5.8uA (typ.)
  • TTL compatible interface levels
  • Single power supply
    • 1.65V-2.2V VDD (IS62/65WV102416GALL)
    • 2.2V-3.6V VDD (IS62/65WV102416GBLL)
  • Three state outputs
  • Commercial, Industrial and Automotive temperature support
  • Lead-free available
     

Block diagram

ISSI IS62/65WV102416GALL/BLL block diagram

ISSI IS62/65WV102416GALL/BLL product image

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