Alliance Memory 16Gb mobile LPDDR3 SDRAM offers low power consumption to optimize battery life in mobile devices
Alliance Memory introduces a new high-speed CMOS mobile low-power DDR3 (LPDDR3) SDRAM designed to extend battery life in compact portable devices. Featuring low voltage operation of 1.2V/1.8V and a number of power-saving features, the 16Gb AS4C512M32MD3 is offered in the 11.0mm by 11.5mm 178-ball FBGA package.
With each new product generation, designers of mobile devices such as smartphones, tablets, and virtual and augmented reality (VR and AR) headsets are tasked with providing more functionality in less space while using less power. To meet this demand, the LPDDR3 device features auto temperature-compensated self-refresh (TCSR) to minimize power consumption at lower ambient temperatures. In addition, its partial-array self-refresh (PASR) feature reduces power by only refreshing critical data, while a deep power down (DPD) mode provides an ultra-low power state when data retention isn't required.
Reducing IC power consumption can directly increase battery life in portable devices, so the applications for LPDDR3 SDRAMs in the consumer and mobile communication markets continue to grow. At the same time, the number of suppliers for these devices is decreasing. Alliance Memory is offering designers a new alternative and shorter lead times for the low power consumption they require. Devices such as new 16Gb AS4C512M32MD3 provide reliable drop-in, pin-for-pin-compatible replacements for a number of similar solutions in high-bandwidth, high-performance memory system applications.
Manufactured using a 20nm process, the AS4C512M32MD3 is internally configured as 8 banks x 32 Mbit x 32. The device offers high-speed operation with a clock frequency of 667MHz and data rate of 1333Mbps, and it features an extended commercial temperature range of -25°C to +85°C. The LPDDR3 SDRAM offers fully synchronous operation and programmable read or write burst lengths of 4, 8, or 16. An auto pre-charge function provides a self-timed row pre-charge initiated at the end of the burst sequence. Easy-to-use refresh functions include auto- or self-refresh. The RoHS-compliant device is lead (Pb)- and halogen-free.
- Low power consumption
- Eight-bit prefetch DDR architecture and BL8 only
- Eight internal banks for concurrent operation
- Double data rate architecture for command, address and data Bus
- Bidirectional and differential data strobe per byte of data (DQS and DQS)
- DQS is edge-aligned with data for READs, centeraligned with data for WRITEs
- Differential clock inputs (CK and CK)
- Data mask (DM) for write data
- Programmable READ and WRITE latencies (RL/WL)
- Auto Refresh and Self Refresh
- Per-bank refresh for concurrent operation
- Partial-array self refresh (PASR)
- On-chip temperature sensor to control self refresh rate for temperature compensated self refresh (TCSR)
- Deep power-down mode (DPD)
- Selectable output drive strength (DS)
- Selectable On-Die Termination
- CA Training
- Write leveling via MR setting
- Clock stop capability
- DQ calibration offering specific DQ output patterns
- ZQ calibration