Microchip MG2RTP - rad-hard 190K used gates 0.5 µm CMOS Sea of Gates
The MG2RTP series is a 0.5 micron, array based, CMOS product family. Several arrays up to 270K gates cover most system integration needs. The MG2RTP is manufactured using a 0.5 micron drawn, 3 metal layers CMOS process, called SCMOS 3/2 RTP.
The base cell architecture of the MG2RTP series provides high routability of logic with extremely dense compiled memories: RAM and DPRAM. ROM can be generated using synthesis tools.
Accurate control of clock distribution can be achieved by PLL hardware and CTS (Clock Tree Synthesis) software. New noise prevention techniques are applied in the array and in the periphery: three or more independent supplies, internal decoupling; customization dependent supply routing, noise filtering, skew controlled I/Os, low swing differential I/Os, all contribute to improve the noise immunity and reduce the emission level.
The MG2RTP is supported by an advanced software environment based on industry standards linking proprietary and commercial tools. Verilog, Modelsym and Design Compiler are the reference front end tools. Floor planning associated with timing driven layout provides a short back end cycle.
- Full Range of Matrices up to 270K Gates
- 0.5 µm Drawn CMOS, 3 Metal Layers, Sea of Gates
- RAM and DPRAM Compilers
- Library Optimized for Synthesis, Floor Plan and Automatic Test Generation (ATG)
- 3 and 5 Volts Operation; Single or Dual Supply Mode
- High Speed Performances:
- 505 ps Max NAND2 Propagation Delay at 4.5V, 825 ps at 2.7V and FO = 5
- Min 440 MHz Toggle Frequency at 4.5V, 230 MHz at 2.7V
- Programmable PLL Available upon Request
- High System Frequency Skew Control through Clock Tree Synthesis Software
- Low Power Consumption:
- 2.7 µW/Gate/MHz at 5V
- 0.86 µW/Gate/MHz at 3V
- Integrated Power On Reset