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Micron’s DDR5 SDRAM enables the next generation of server workloads by delivering more than an 85% increase in memory performance

Micron DDR5 SDRAM - angled back side

DDR5, the most technologically advanced DRAM to date, will enable the next generation of server workloads by delivering more than an 85% increase in memory performance. DDR5 doubles memory density while improving reliability at a time when data center system architects seek to supply rapidly growing processor core counts with increased memory bandwidth and capacity.

Advanced workloads resulting from rapidly expanding datasets and compute-intensive applications have fueled processor core count growth which will be bandwidth-starved by current DRAM technology. DDR5 will deliver more than a 1.85x increase in performance compared to DDR4. DDR5 also enables the increased reliability, availability and serviceability (RAS) that modern data centers require.

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Micron DDR5 Technical Enablement Program (TEP)

Approved partners can get access to:

  • Technical resources such as data sheets, electrical, thermal and simulation models to aid in product development and platform bring-up
  • Select DDR5 component and module samples as they become available


  • Connection with other ecosystem partners that can aid in the design and bring up of DDR5-enabled platforms
  • Technical support and training materials


Why DDR5?

  • Multi-core CPU architectures have enabled year-over-year compute performance gains to continue
  • CPU core counts increasing at a rate that minimizes available memory bandwidth per core
  • DDR4 has reached maximum data rates and cannot continue to scale memory bandwidth
  • New memory architectures are required to meet next-generation bandwidth per core requirements in x86 CPUs
  • DDR5 data rates, as defined today, offer up to a 2x increase when compared to DDR4


Advantages of DDR5

  • Device and DIMM architectures totally optimized for high performance in server applications
  • Everything doubles…Data rates 3200-6400, 2 channels per DIMM, BL16, 2x Bank Groups (and Banks)
  • Same Bank Refresh allows 6-10% improvement in BW alone
  • ~30% BW improvement at 3200 vs. DDR4
  • PMIC on DIMM allows optimized local power, solving the PDN problem at the module
  • Memory density scaling
  • RAS improvements (On-die ECC / ECC transparency and RFM)


New features: DDR5

Feature DDR5 Improvement
Multi-Purpose Command (MPC) Single-cycle commands associated with initialization/training/calibration that can be done across multiple cycles (extended setup/hold), aka, before training.
Loopback One Loopback DQ and Loopback DQS that allow memory controllers to test instruments to monitor data sent to the DRAM without having to write/read to the array.
Package Output Driver Test Mode Optional mode allows for characterization of the DRAM package by allowing the host to individually turn the output driver of a signal DM/DQ while all the other bits remain terminated.
Optional Refresh Management (RFM) RH mitigation similar in concept to Targeted Row Refresh (TRR) in DDR4 which monitors excessive ACT per-row. RFM is instead based on ACT per-bank and the host must track the counts. Similarly optional to the DRAM device, designated in MR. Adds extra layer of refreshes (RFMs) required on top of the "normal" refreshes.
Same Bank Refresh (REF_sb) Allows refreshes to one bank, while not locking out other banks within the BG — significant BW/performance improvements.


Basic architecture: DDR5 vs. DDR4

Feature DDR4 DDR5 DDR5 Improvement
Core and I/O 1.2V 1.1V Lower VDD and VDDQ power
VPP 2.5V 1.8V Power efficiency
Vref Inputs 1 — ADDR/CMD All Internal Improved CMD/ADDR signaling
Densities 2Gb, 4Gb, 8Gb, 16Gb 8Gb*, 16Gb, 24Gb, 32Gb, 64Gb Supports a large range of capacity
Bank Groups (BG) 4 (x4,x8), 2 (x16) 8 (x4,x8), 4 (x16) 2x BG
Banks / BG 4 4 (8Gb = 2) On-par, except 8Gb has half as many as DDR4
Organization x4/x8/x16 x4/x8/x16 x16 package has additional pins (96B→102B)
Page Size (x4/x8/x16) 512B/1KB/2KB 1KB/1KB/2KB D5 X4/X8 page size the same
Mulitplex ADDR/CMD 3 All Pin Reduction
ADDR/CMD Inputs 24 14 2 cycle (ACT, RD*, WR*, MRW*, MRR*)
CKE AND ODT Inputs Required ODT (for DM/DQ/DQS ODT) and CKE pins removed, CA_ODT pin added for CA ODT DM/DQ/DQS ODT command encoded in DDR5 for pin reduction. CA_ODT now brings ODT to the CA pins.
ACT_n Input Yes, multiplex RAS/CAS/WE No Pin reduction, CA0 handles this
On-die ECC Not supported Required Improved RAS features
ECC Transparency No Yes Support RAS


Video: Avnet capabilities


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