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ADC

 

Analog-to-Digital Converter

 

AGP

 

Accelerated Graphics Port - An interface specification from INTEL that enables 3D-graphics to display very fast. AGP is based on PCI, but is designed especially for the high throughput requirements of 3D-graphics.

 

AHDL

 

a) Altera (specific) Hardware Description Language - vendor specific HDL b) Analog Hardware Description Language - for analog designs/systems

 

Aliasing

 

is a distortion-producing reflection caused by the fact that all frequency components higher than half the sampling-frequency are reflected in the lower range. (To avoid, a low-pass filter is required, Anti-Aliasing)

 

ALM

 

Adaptive Logic Module - vendor specific name for a coarse-grained FPGA logic-module (e.g. Altera StratixII)

 

ALSI

 

Analog Large Scale Integration - complex analog chip design

 

AMPP

 

Altera Megafunction Partners Program - A program that was established in 1995 to bring the advantage of megafunction (IP) to Altera PLD users.

 

Anti-Aliasing

 

is a procedure to avoid aliasing

 

Antifuse

 

Opposite of a 'fuse', where a link is grown (not blown) to make a electrically connection by passing current through

 

APU

 

Altera Programming Unit

 

ASIC

 

Application Specific Integrated Circuit - A custom or semicustom integrated circuit, such as a cell or gate array, created for a specific application.

 

ASSP

 

Application Specific Standard Part - integrated circuit (IC) for standard application (e.g. 74xx-series standard logic products)

 

ATA

 

Advanced Technology Attachment - a disk drive interface standard for IDE (Integrated Drive Electronics)

 

ATPG

 

Automatic Test Pattern Generator

 

Backannotation

 

typically means to write back the calculated propagation delays after the place&route-process for a post-layout simulation (standard format : SDF)

 

BC

 

Best Conditions for a timing-logic-simulation reflects 1.) max. supply-voltage 2.) min. temperature 3.) best technology process (typ. for hold-time violation check)

 

BGA

 

Ball Grid Array - type of chip connection/packaging methodology

 

BIST

 

Build-In Self Test - additional on-chip circuitry for an self-test

 

Boundary Scan

 

is a methodology allowing complete controllability and observability of the boundary pins of a JTAG compatible device via software control. This capability enables in-circuit testing without the need of bed-of-nail in-circuit test equipment. (sometimes abbreviated with BST)

 

BPPG

 

Boundary-Scan PLD Programming Generator - JTAG trademark (see also IEEE 1532)

 

BPSK

 

Bi-Phase Shift Keying - is a digital frequency modulation technique used for sending data over a coaxial cable network.

 

BQFP

 

Bumpered Quad Flat Pack - type of chip connection/packaging methodology

 

BRAM

 

a) Buffer RAM (AT&T)

 

Breadboard

 

is used to assemble preliminary circuits and parts to prove the feasibility of a device, circuit or system without regard to the final configuration or packaging of the parts.

 

BSDL

 

Boundary Scan Description Language - language to describe the Boundary Scan behaviour of a device

 

BST

 

Boundary Scan Test - see also "Boundary Scan"

 

CAD

 

Computer Aided Design - computer aided design tools to develop something

 

CAE

 

Computer Aided Engineering - computer aided engineering tools to develop something

 

CAM

 

Content Addressable Memory - is a kind of storage device that includes comparison logic with each bit of storage. A data value is broadcasted to all words of storage and compared with the values therein. Words that match are flagged. (Also known as "associative memory")

 

CBGA

 

Ceramic Ball Grid Array - type of chip connection/packaging methodology

 

CDIP

 

Ceramic Dual In-Line Package - type of chip connection/packaging methodology

 

CDR

 

Clock Data Recovery - procedure to recover clock and data from a serial bitstream

 

CFM

 

Configuration Flash Memory - vendor specific name for a on-chip configuration memory on volatile PLDs, for automatic configuration after power-on (e.g. ALTERA MAX2-devices)

 

CLCC

 

Ceramic J-Leaded Chip Carrier - type of chip connection/packaging methodology

 

CLK

 

CLocK - a global net/signal which is the heartbeat of all digital synchronous designs/circuits.

 

CMOS

 

Complementary Metal-Oxide-Semiconductor - technology with two complementary unipolar (N-MOS and P-MOS) Field-Effect-Transistors (FET)

 

Codec

 

COmpressor / DECompressor - any technology for compressing and decompressing data.

 

CPGA

 

Ceramic Pin Grid Array - type of chip connection/packaging methodology

 

CPLD

 

Complex Programmable Logic Device - PLD architecture type

 

CQFP

 

Ceramic Quad Flat Pack - type of chip connection/packaging methodology

 

CRC

 

Cyclic Redundancy Check - procedure to prevent errors at data transmissions by adding a measure of redundancy to data

 

CSBGA

 

Chip Scale Ball Grid Array - type of chip connection/packaging methodology

 

CSoC

 

Configurable System-on-Chip

 

CSOP

 

Ceramic Small-Outline Package - type of chip connection/packaging methodology

 

CSP

 

Chip Scale Package - type of chip connection/packaging methodology

 

CuPL

 

CuPL - is a description language for programmable logic (PLDs)

 

DAC

 

Digital-to-Analog Converter

 

DDR

 

Double Data Rate - property of a device, that works on both clock-edges (e.g. DDR-SDRAM)

 

DES

 

Data Encryption Standard - transmission procedure for security applications

 

DFS

 

Digital Frequency Synthesizer

 

Die

 

Die - name for the small silicon plate inside a chip

 

DIP (DIL)

 

Dual In-Line Package - type of chip connection/packaging methodology

 

DLL

 

Delay Locked Loop - digital circuitry for frequency multiply, phase-shift, ... (similar analog PLL)

 

DMA

 

Direct Memory Access/Addressing - is a method of transferring data from one memory area to another without having to go through the central processing unit.

 

DPA

 

Dynamic Phase Alignment - PLL-core feature of e.g. Altera StratixGX FPGAs

 

DPS

 

Digital Phase Shifter

 

DRAM

 

Dynamic RAM - volatile read/write memory, content only stable for some milliseconds, refreshcycles required

 

DRC

 

Design Rule Check

 

DSP

 

Digital Signal Processor - device or module to process analog signals which have been converted to digital form (audio, video, ...).

 

EAB

 

Embedded Array Block - vendor specific name for embedded on-chip RAM structures (ALTERA e.g. ACEX-1K-family)

 

EDA

 

Electronic Design Automation - Application Software tools for the development of integrated circuits and systems

 

EEPLD

 

Electrically Erasable PLD

 

EEPROM

 

Electrically Erasable PROM - electrically erasable PROM

 

EIA

 

Electronic Industry Association

 

ELA

 

Embedded Logic Analyzer

 

EPLD

 

Electrically PLD

 

EPROM

 

Erasable PROM - by UV-light erasable PROM, normally in a windowed package

 

ESB

 

Embedded System Block - vendor specific name for flexible embedded on-chip RAM structures (ALTERA e.g. APEX-II-family)

 

ESP

 

Embedded Standard Product - a device that consist of pre-determined functions customized and supported by user-configurable logic (FPGAs) on the same piece of silicon.

 

Fan In

 

Fan In - is a term, that defines the input-load of the affected input, typically '1' (see "Fan Out").

 

Fan Out

 

Fan Out - is a term, that defines the maximum number of digital inputs (Fan In) which can be driven by the affected output.

 

FBGA

 

Fine Pitch (Fine-Line) Ball Grid Array - type of chip connection/packaging methodology

 

FCBGA

 

Fine Pitch Ceramic Ball Grid Array - type of chip connection/packaging methodology

 

FCRAM

 

Fast Cycle RAM

 

FDIP

 

Windowed Frit Seal Dual In-Line Package - type of chip connection/packaging methodology

 

FEC

 

Forward Error Correction - (algorithm) a class of methods for controlling errors in a one-way communication system. FEC sends extra information along with the data, which can be used by the receiver to check and correct the data.

 

FEPROM

 

Flash Erasable PROM - see "FLASH"

 

FET

 

Field Effect Transistor

 

FFT

 

Fast Fourier Transform - An algorithm for computing the "Fourier transform" of a set of discrete data values given for a finite set of data points.

 

FIFO

 

First-In First-Out - type of memory management

 

FIR

 

Finite Impulse Response - methodology of a digital filter

 

FLASH

 

Flash - abbreviation of "Flash EPROM", like an EEPROM but faster electrically erasable (whole chip at one time)

 

FLEX

 

Flexible Logic Element MatriX - FPGA product name of ALTERA (e.g. FLEX8000, FLEX10K)

 

Flip Chip

 

Flip Chip Ball Grid Array - type of chip connection/packaging methodology

 

Flip-Flop

 

is a basic digital logic circuit that can storage two states (high and low) controlled by an edge-triggered input

 

FMBGA

 

Fine Pitch Metall Ball Grid Array - type of chip connection/packaging methodology

 

FPBGA

 

Fine Pitch Plastic Ball Grid Array - type of chip connection/packaging methodology

 

FPLA

 

Field Programmable Logic Array - CPLD-like devices with programmable AND/OR matrix (SIGNETICS Corporation or National Semiconductors MAPL-family)

 

FSK

 

Frequency Shift Keying - the use of frequency modulation to transmit digital data. (i.e. two different carrier frequencies are used to represent '0' and '1')

 

FSM

 

Finite State Machine - a very important circuitry to realize timing-driven tasks in realtime. The three basic FSM-types are : 1.) Medvedev 2.) Moore 3.) Mealy

 

FTBGA

 

Fine Pitch Thin Ball Grid Array - type of chip connection/packaging methodology

 

Gate

 

a) basic element to perform logical functions, like a digital switch that can be turned open or closed depending on the input signals (min. two)

 

Glue Logic

 

a generic term for any interface logic or protocol that connects two component blocks. Hardware designers call anything used to connect LSI or circuit blocks "glue logic".

 

GTL

 

Gunning Transceiver Logic - is a standard for electric signals in CMOS circuits that is used to provide high data transfer speeds with small voltage swings.

 

HAL

 

Hard Array Logic - hardwired/masked PAL-device

 

HDL

 

Hardware Description Language - a kind of language used for the conceptual design of integrated circuits (i.e. VHDL and Verilog).

 

hold time

 

- is the succeeding time value, typically for a register (D-FlipFlop), to avoid metastability after a data-transfer into the register-cell (see also "setup time")

 

HQFP

 

Heat-Sink Quad Flat Pack - type of chip connection/packaging methodology

 

HSOP

 

Heat-Sink Small-Outline Package - type of chip connection/packaging methodology

 

HSSOP

 

Heat-Sink Shrink Small-Outline Package - type of chip connection/packaging methodology

 

HSTL

 

High Speed Transceiver Logic - a high speed interface standard (JEDEC standard EIA/JESD8-6)

 

HTSSOP

 

Heat-Sink Thin Shrink Small-Outline Package - type of chip connection/packaging methodology

 

IBA

 

Integrated Bus Analyzer - on-chip debugging tool

 

ICR

 

In-Circuit Reconfigurability - possibility to reconfigure a device, which is PCB-mounted

 

ILA

 

Integrated Logic Analyzer - on-chip debugging tool

 

IP

 

Intellectual Property - a IP-core is a hardwired or soft-based (sourcecode or netlist) reusable circuitry that can be implemented in a new chip design

 

ISP

 

In System Programmable - property of a device, that is in-system programmable

 

JEDEC

 

The Joint Electron Device Engineering Council was originally created in 1960 as a joint activity between EIA an NEMA, to cover the standardization of discrete semiconductor devices and later expanded in 1970 to include integrated circuits. www.jedec.org

 

JTAG

 

Joint Test Action Group - a standard specifying how to control and monitor the pins of compliant devices on a circuit board. Created in 1993. (IEEE standard 1149.1 and 1532 )

 

LAB

 

Logic Array Block - vendor specific name for a CPLD logic-block or a FPGA logic-module (ALTERA)

 

Latch

 

is a basic digital logic circuit that can storage two states (high and low) controlled by an level-triggered input (Latch-Up Effect)

 

LE

 

Logic Element - vendor specific name for a small logic-unit (LUT+FF) of a coarse-grained FPGA logic-module (ALTERA-devices)

 

LFSR

 

Linear Feedback Shift Register - usually used for generating sequences for scrambling / descrambling methods

 

LPM

 

Library of Parametrized Modules - library of customizable basic functions (multiply, shift, ...) for usage in PLD-design process (forced by ALTERA)

 

LQFP

 

Low Profile Quad Flat Pack - type of chip connection/packaging methodology

 

LSB

 

Least Significant Bit

 

LUT

 

Look-Up Table - an array or matrix of fix (complex) data-values that can be read out (very fast) by addressing them through input data-values

 

LVCMOS

 

Low Voltage CMOS

 

LVDS

 

Low Voltage Differential Signalling - low-power & low-noise differential signalling technology for high speed transmission

 

LVPECL

 

Low Voltage Positive Emitter Coupled Logic - low-voltage PECL

 

LVTTL

 

Low Voltage Transistor-Transistor Logic

 

MAPLD

 

Military and Aerospace Applications of PLDs

 

MAX

 

Multiple Array matriX - CPLD product name of ALTERA's EPLD-family (MAX5xxx,MAX7xxx)

 

MBGA

 

Metall Ball Grid Array - type of chip connection/packaging methodology

 

MCP

 

Multi Chip Package - package with two or more dies inside

 

MDIP

 

Molded Dual In-Line Package - type of chip connection/packaging methodology

 

MIPS

 

Million Instructions Per Second - Indicator for computing performance

 

MOSFET

 

Metal Oxide Semiconductor Field Effect Transistor - is a transistor in which the conducting channel is insulated from the gate terminal by a layer of oxide. Therefore, it does not conduct even if a reverse voltage is applied to the gate.

 

MPGA

 

Mask Programmable Gate Array

 

MPI

 

Microprocessor Interface

 

MPLD

 

Mask-Programmed Logic Devices - masked versions of programmable logic devices

 

MQFP

 

Metal Quad Flat Pack - type of chip connection/packaging methodology

 

MSB

 

Most Significant Bit

 

MSOP

 

Mini Small-Outline Package - type of chip connection/packaging methodology

 

N-MOS

 

N-MOS - abbreviation of N-channel MOSFET (see also "CMOS" and "P-MOS")

 

NEPP

 

NASA Electronic Parts & Packaging

 

NRE

 

Non-Recurring Engineering costs - e.g.: the costs to design and manufacture the process-masks for an ASIC are NRE-costs

 

OCM

 

On-Chip Memory

 

OTP

 

One Time Programmable - property of a device which is not reprogrammable or erasable

 

P-MOS

 

P-MOS - abbreviation of P-channel MOSFET (see also "CMOS" and "N-MOS")

 

PALASM

 

- is an early hardware description language (HDL), used for PAL-devices introduced by Monolithic Memories (MMI). Developed by John Birkner in the early 1980s.

 

PAR

 

Place-And-Route

 

PBGA

 

Plastic Ball Grid Array - type of chip connection/packaging methodology

 

PCB

 

Printed Circuit Board

 

PCI

 

Peripheral Component Interconnect - a personal computer loacl bus designed by Intel

 

PDIP

 

Plastic Dual In-Line Package - type of chip connection/packaging methodology

 

PECL

 

Positive Emitter Coupled Logic - a high speed interface standard

 

PGA

 

Pin Grid Array - type of chip connection/packaging methodology

 

PIA

 

Programmable Interconnect Array - vendor specific name for a CPLD switch-matrix (ALTERA, e.g. MAX5000,MAX7000-family)

 

PIP

 

Programmable Interconnect Point - to program a link between two crossing nets

 

PLA

 

Programmable Logic Array - PLD device with SPLD-architecture, where the AND- and OR-matrix is programmable

 

PLCC

 

Plastic J-Leaded Chip Carrier - type of chip connection/packaging methodology

 

PLD

 

Programmable Logic Device - topic term for all SPLDs, CPLDs and FPGAs.

 

PLL

 

Phase Locked Loop - analog circuitry to multiply/divide frequencies phase-locked

 

PLS

 

Programmable Logic Sequencer

 

PPGA

 

Plastic Pin Grid Array - type of chip connection/packaging methodology

 

PQFP

 

Plastic Quad Flat Pack - type of chip connection/packaging methodology

 

PREP

 

PRogrammable Electronics Performance Corporation - organization founded in 1992 to specify benchmarks for programmable logic devices

 

PROM

 

Programmable ROM - on-time programmable (OTP) memory

 

PSG

 

Programmable Sequence Generator

 

QDR

 

Quad Data Rate - known from QDR-SRAMs which have two independent DDR (double-data-rate) ports

 

QML

 

Qualified Manufacturer Listing

 

RAM

 

Random Access Memory - random read/write memory

 

RLDRAM

 

Reduced Latency DRAM - low latency high performance DRAM with SRAM-like random access (co-developed by Micron & Infineon) www.rldram.com

 

ROM

 

Read Only Memory - memory with fix content

 

RQFP

 

Plastic PoweR Quad Flat Pack - type of chip connection/packaging methodology

 

RST

 

ReSeT - a global net/signal to (re)set a synchronous digital circuitry into a defined state. There are two kinds of reset, asynchronous or synchronous.

 

RTL

 

Register Transfer Level - a kind of hardware description language used in describing the registers of a digital electronic system, and the way in which data is transferred between the registers.

 

SDF

 

Standard Delay Format - is an IEEE-standard for the representation and interpretation of timing data for use at any stage of an electronic design process, especially during timing simulations.

 

SDIP

 

Shrink Dual In-Line Package - type of chip connection/packaging methodology

 

SDRAM

 

Synchronous DRAM - volatile memory with fast synchronous interface, content only stable for some milliseconds, refreshcycles required

 

SDT

 

Schematic Design Tool

 

SERDES

 

Serializer Deserializer - fast serial receiver/transmitter hardware

 

setup time

 

- is the preceding time value, typically for a register (D-FlipFlop), to avoid metastability before a data-transfer into the register-cell (see also "hold time")

 

SMT

 

Surface Mount Technology - for PCBs

 

SoC

 

System on Chip

 

SOIC

 

Small-Outline Integrated Circuit - type of chip connection/packaging methodology

 

SOJ

 

Small-Outline Integrated Circuit with J-Leads - type of chip connection/packaging methodology

 

SOP

 

Small-Outline Package - type of chip connection/packaging methodology

 

SOPC

 

System On Programmable Chip - name for a PLD with high densities and embedded structures on one chip

 

SPLD

 

a) Simple PLD - PLD architecture-type

 

SQFP

 

Shrink Quad Flat Pack - type of chip connection/packaging methodology

 

SRAM

 

Static RAM - volatile memory (synchronous or asynchronous interfaces possible), content only stable at power-on

 

SSOIC

 

Shrink Small-Outline Integrated Circuit - type of chip connection/packaging methodology

 

SSOP

 

Shrink Small-Outline Package - type of chip connection/packaging methodology

 

SSTL

 

Solid State Track Link

 

STA

 

Static Timing Analysis - the calculation of the longest or critical pathes of a design, supported by CAD/CAE-tools

 

TAP

 

Test Access Port - i.e. for JTAG BST

 

TC

 

Typical Conditions for a timing-logic-simulation reflects 1.) typ. supply-voltage 2.) room-temperature 3.) nominal technology process

 

TCL

 

Tool Command Language - mainly used as a script file to control CAE-tools or give additional project informations, constraints or assignments

 

TQFP

 

Thin Quad Flat Pack - type of chip connection/packaging methodology

 

TSOP

 

Thin Small-Outline Package - type of chip connection/packaging methodology

 

TSSOP

 

Thin Shrink Small-Outline Package - type of chip connection/packaging methodology

 

UBGA

 

Ultra Fin-Line Ball Grid Array - type of chip connection/packaging methodology

 

UFM

 

User Flash Memory - non-volatile onchip flash memory for user-data (e.g. ALTERA MAX2-devices)

 

ULSI

 

Ultra Large Scale Integration - superlative of VLSI

 

Verilog

 

is a hardware description language for digital electronic design and gate-level-netlist

 

VHDL

 

VHSIC Hardware Description Language - standardized language for ASIC/PLD-designers (IEEE 1076)

 

VHSIC

 

Very High Speed Integrated Circuit

 

VLSI

 

Very Large Scale Integration - the process of placing thousands of electronic components on a single chip.

 

VQFP

 

Very Thin Quad Flat Pack - type of chip connection/packaging methodology

 

VSOP

 

Very Small-Outline Package - type of chip connection/packaging methodology

 

VST

 

Verification and Simulation Tool

 

WC

 

Worst Conditions for a timing-logic-simulation reflects 1.) min. supply-voltage 2.) max. temperature 3.) worst technology process (typ. for setup-time violation check)

 

ZBT

 

Zero Bus Turnaround - is a synchronous SRAM architecture optimized for networking and telecommunications applications