Xilinx and EBV @ FPGA Europe Digital Conference
29 Sep 2020 - 30 Sep 2020
FPGAs have made a regular evolutional leap forward in terms of new approaches and solutions for both hardware- and software developers.
The FPGA-Conference Europe is addressing that progress across all major manufacturers. It focusses on user-oriented, practically applicable solutions that developers can quickly integrate into their own everyday work.
Take advantage of the combined knowledge of top-class FPGA experts!
EBV Elektronik will be present with two speeches:
Introduction to Vitis AI – unified development environment for AI inference (45 min)
Date and time: Sep 30, 2020 at 02:45 pm
Speaker: Speaker: Stanislaw Klinke, EBV Elektronik GmbH & Co. KG
Vitis AI is unified AI Platform which allows development for both cloud and edge applications.
In this session participants can learn how Vitis AI supports mainstream frameworks and the latest models capable of diverse deep learning tasks.
All the powerful components of Vitis AI will be explained in the details:
- Quantizer that supports model quantization, calibration, and fine tuning
- AI Optimizer that can prune the deep learning model
- Profiler, which provides layer by layer analysis to help with computation bottlenecks
- AI library offers unified high-level C++ and Python APIs for maximum portability from edge to cloud
- Comprehensive set of pre-optimized models that are ready to deploy on Xilinx devices
There will be also architecture and adoption of Deep Learning Processor Unit (DPU) presented.
After that session, participants should be able to understand how to implement trained deep learning model into Xilinx device with support of Vitis AI design flow.
Xilinx Versal, the first Adaptive Compute Acceleration Platform (45 min)
Date and time: Sep 30, 2020 at 04:00 pm
Speaker: Speaker: Saad Qazi, EBV Elektronik GmbH & Co. KG
Introduction to the new 7nm fully software-programmable heterogeneous compute platform. This new category of devices allows users to customize their own domain-specific architecture. It combines Scalar Engines, Adaptable Engines and Intelligent Engines to achieve high performance improvements compared to the existing CPU or FPGA implementations. Especially interesting for Data Center, wired network, 5G wireless, and automotive driver assist applications.
After that session, participants should be able to understand how the ACAP architecture significantly extends the capabilities of programmable logic alone by combining the hybrid of programmable logic, scalar-, adaptable- and intelligent Engines.
Register now via the link below and you’ll get 50€ discount!
The discount code is already noted in the form.
NXP Webinar: Machine Learning Discovery Solutions
NXP Semiconductors and EBV Elektronik have the pleasure to invite you for a series of webinars focusing on Machine Learning Technology. Over three days NXP and EBV will guide you through the Machine Learning applications starting from Convolutional Neural Network theory, moving on to some real life applications like Predictive Maintenance in Motor Control applications and turnkey solutions for voice, face and object recognition. All presentations will be held by NXP and EBV Application Engineers.
Renesas Webinar: Embedded Artificial Intelligence / Machine Learning
Presented by EBV, Witekio and Renesas AI/ML Technology Specialists this technical workshop will cover Convolutional Neural Networks Theory , practical embedded design considerations , Renesas e-AI RZ/A2M MPU details, e-AI design flow example and Vehicle Number Plate recognition demo implementation running on the RZ evaluation board.
Zynq UltraScale + RFSoC and Application to the Remote PHY Node in Cable Access
This webinar will provide a brief overview of the Zynq UltraScale+ RFSoC and its application to a remote PHY node in Cable Access. We’ll first provide a technology overview of the world’s only hardware programmable System-on-Chip with integrated analog data converters, along with key performance metrics. We’ll then discuss its application to Remote PHY nodes leveraging key IP blocks available by Xilinx partner Calian SED.