IDT 3.3V PCI Express (9FGL06/08) clock generators
The 9FGL06 and 9FGL08 devices’ ultra-compact 5x5 mm and 6x6 mm packages can deliver up to a 90 percent reduction in board area.
The 9FGL06 and 9FGL08 devices’ ultra-compact 5x5 mm and 6x6 mm packages can deliver up to a 90 percent reduction in board area. Factory programmable versions provide quick turn device optimizations to meet exact customer requirements.
The 3.3 V devices are pin-compatible to IDT’s highly successful 1.5 V 9FGU-series and 1.8 V 9FGV-series PCIe clock generators. The timing family targets power- and space-constrained designs in both consumer and high-performance applications, providing enterprise-level performance while lowering the total cost of ownership. Potential applications include multi-function printers, servers, set-top boxes and solid state drives. The entire family is compliant with PCIe generations 1, 2 and 3.
The 3.3 V (L-series) family offers industry firsts that include:
Output-by-Output configuration of output impedances, allowing a single part to be used in mixed impedance environments without external termination components.
Factory programmable versions allow user-defined default configurations including output impedance, control input polarity, internal pull up or pull down resistors, and wake-on-LAN mode for the crystal oscillator. This removes the need for practically all external glue logic.
The 9FGL PCIe clock generator family includes devices with 2, 4, 6, or 8 outputs. The clock generators support both the PCIe Common Clock architecture with or without spread spectrum, and the PCIe Independent Reference (IR) clock architecture (non-spreading). The devices also provide a copy of the reference clock, saving a crystal in the design.
The 6-output 9FGL06xx and 8-output 9FGL08xx PCIe clock generators are available now.
The 2-output 9FGL02 and 4-output 9FGL04 clock generators will be available in Q3, 2015.
9FGL06/08P1 devices are fully OTP programmable.
Stage 1 OTP Programming “Soft-Launch” will allow factory customization of the following:
Control input polarity and internal pull-up/pull-down
Output impedance per output
Slew rate per output – including REF
DIF amplitude – global to device
Wake-on-LAN enabling for REF
Stage 2 complete OTP Programming will allow factory customization of PLL:
Input and output frequencies other than 25 in / 100 out.
Example: 24 in /100 out or 19.2 in / 100 out
Timing Commander Support
- 9FGL06/08P1 has factory OTP to program user-defined power up defaults
- 25 MHz XTAL or clock in 6 or 8 100M LP-HCSL outputs
- Individual Zo selection (33 W, 85 W, 100 W)
- Individual slew rate selection
- Global amplitude selection
- REF output
- <1.5 ps rms with SSC on
- <300 fs rms with SSC off
- REF output Wake-on-Lan (WOL) mode (runs in power down)
- Simplified BOM - single part supports:
- PCIe Gen1-2-3
- Spread Spectrum Clocking (SSC):
- Off, -0.25%, -0.5%
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