Enhancing the performance of 5G

The onset of 5G has led to new applications as well as new requirements. To increase the flexibility of the network, the radio access network (RAN) architecture is now split into the centralized unit (CU) and the distributed unit (DU). These distributed units in turn require a high performance low-density parity check (LDPC) encoder/decoder to offload x86 CPU loading. To meet this requirement, users can use Xilinx XCZU21DR with hardcore LDPC as well as integrate 5G High PHY protocol.

Developers who need to hasten their time to market can use the Xilinx Alveo Data Center accelerator cards like the U50 to implement soft LDPC IP. Future networking applications will also be able to ride on the speed and intelligence of the upcoming Xilinx SmartNIC card.


  • Xilinx XCZU21DR has 8xSD-FEC that support high performance LDPC Enc/Dec
  • Xilinx 16nm FPGA supports PCIe Gen3x16 high bandwidth to interface with x86 server
  • Xilinx Alveo card is dedicated or the production card that can build LDPC IP inside


  • Xilinx XCZU21DR (LDPC x8 hardcore)
  • Xilinx Alveo Card U50 (Xilinx LDPC Soft IP)
  • Xilinx Alveo U25 (SmartNIC coming soon)

Target applications

  • 5G DU LDPC acceleration
  • 5G DU High PHY integration
  • 5G SmartNIC and Networking Security




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