Winning Combinations to Design Faster

Xilinx 7nm Versal ACAP

Precise, adaptable timing and power

One of Xilinx’s newest SoC families is the Versal Adaptive Compute Acceleration Platform (ACAP). It contains scalar processing engines, adaptable hardware, intelligent engines (SW programmable and HW adaptable) and Network-On-Chip, a SW programmable infrastructure. This requires precise, adaptable timing and power.

This winning combination highlights the timing solution that Xilinx used on their reference design and the suggested power devices.

Visit the Versal ACAP page to learn more.

Key features:

  • Digital multi-phase power to deliver up to 165A at 0.78V to meet the strict specs set forth by Xilinx
  • Pre-programmed PMICs helps meet any use case required
  • FemtoClock®NG Universal Translator capable of supporting 10G/40G/100G SONET/SDH and Ethernet networks
  • Added a system synchronizer for IEEE 1588
server racks in data center

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Block diagram

block diagram of Xilinx Versal ACAP device

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