#-----------------------------------------------------------
# Vivado v2013.4 (64-bit)
# SW Build 351683 on Wed Dec  4 19:12:58 MST 2013
# IP Build 208076 on Mon Dec  2 12:38:17 MST 2013
# Start of session at: Fri Jan 31 19:02:21 2014
# Process ID: 17232
# Log file: C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.runs/impl_1/zynq_system_wrapper.rdi
# Journal file: C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.runs/impl_1\vivado.jou
#-----------------------------------------------------------
Attempting to get a license: Implementation
Feature available: Implementation
Loading parts and site information from C:/Xilinx/Vivado/2013.4/data/parts/arch.xml
Parsing RTL primitives file [C:/Xilinx/Vivado/2013.4/data/parts/xilinx/rtl/prims/rtl_prims.xml]
Finished parsing RTL primitives file [C:/Xilinx/Vivado/2013.4/data/parts/xilinx/rtl/prims/rtl_prims.xml]
source zynq_system_wrapper.tcl -notrace
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2013.4
Loading clock regions from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/zynq/zynq/xc7z100/ClockRegion.xml
Loading clock buffers from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/zynq/zynq/xc7z100/ClockBuffers.xml
Loading clock placement rules from C:/Xilinx/Vivado/2013.4/data/parts/xilinx/zynq/ClockPlacerRules.xml
Loading package pin functions from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/zynq/PinFunctions.xml...
Loading package from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/zynq/zynq/xc7z100/ffg900/Package.xml
Loading io standards from C:/Xilinx/Vivado/2013.4/data\./parts/xilinx/zynq/IOStandards.xml
INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers.
INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers.
Parsing XDC File [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/zynq_system_processing_system7_0_0.xdc] for cell 'zynq_system_i/processing_system7_0/inst'
Finished Parsing XDC File [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/zynq_system_processing_system7_0_0.xdc] for cell 'zynq_system_i/processing_system7_0/inst'
Parsing XDC File [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/zynq_system_axi_gpio_0_0.xdc] for cell 'zynq_system_i/axi_gpio_0/U0'
Finished Parsing XDC File [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/zynq_system_axi_gpio_0_0.xdc] for cell 'zynq_system_i/axi_gpio_0/U0'
Parsing XDC File [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/zynq_system_axi_gpio_0_0_board.xdc] for cell 'zynq_system_i/axi_gpio_0/U0'
Finished Parsing XDC File [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/zynq_system_axi_gpio_0_0_board.xdc] for cell 'zynq_system_i/axi_gpio_0/U0'
Parsing XDC File [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_rst_processing_system7_0_50M_0/zynq_system_rst_processing_system7_0_50M_0.xdc] for cell 'zynq_system_i/rst_processing_system7_0_50M/U0'
Finished Parsing XDC File [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_rst_processing_system7_0_50M_0/zynq_system_rst_processing_system7_0_50M_0.xdc] for cell 'zynq_system_i/rst_processing_system7_0_50M/U0'
Parsing XDC File [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_rst_processing_system7_0_50M_0/zynq_system_rst_processing_system7_0_50M_0_board.xdc] for cell 'zynq_system_i/rst_processing_system7_0_50M/U0'
Finished Parsing XDC File [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_rst_processing_system7_0_50M_0/zynq_system_rst_processing_system7_0_50M_0_board.xdc] for cell 'zynq_system_i/rst_processing_system7_0_50M/U0'
Parsing XDC File [C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/constrs_1/imports/new/design_1.xdc]
Finished Parsing XDC File [C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/constrs_1/imports/new/design_1.xdc]
Parsing XDC File [C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.runs/impl_1/.Xil/Vivado-17232-avnet-wks2/dcp/zynq_system_wrapper.xdc]
Finished Parsing XDC File [C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.runs/impl_1/.Xil/Vivado-17232-avnet-wks2/dcp/zynq_system_wrapper.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s).
INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: 
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

link_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 980.504 ; gain = 787.254
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z100'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z100'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.154 . Memory (MB): peak = 983.512 ; gain = 2.992

Starting Logic Optimization Task
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 259b26521

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.245 . Memory (MB): peak = 995.074 ; gain = 11.563

Phase 2 Constant Propagation
INFO: [Opt 31-138] Pushed 0 inverter(s).
INFO: [Opt 31-10] Eliminated 259 cells.
Phase 2 Constant Propagation | Checksum: 14114ff64

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.635 . Memory (MB): peak = 995.074 ; gain = 11.563

Phase 3 Sweep
INFO: [Opt 31-12] Eliminated 416 unconnected nets.
INFO: [Opt 31-11] Eliminated 327 unconnected cells.
Phase 3 Sweep | Checksum: 207ffc1ef

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.974 . Memory (MB): peak = 995.074 ; gain = 11.563
Ending Logic Optimization Task | Checksum: 207ffc1ef

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.995 . Memory (MB): peak = 995.074 ; gain = 11.563
Implement Debug Cores | Checksum: 259b26521
Logic Optimization | Checksum: 259b26521

Starting Power Optimization Task
Ending Power Optimization Task | Checksum: 207ffc1ef

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.052 . Memory (MB): peak = 995.074 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
INFO: [Timing 38-35] Done setting XDC timing constraints.
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.174 . Memory (MB): peak = 996.563 ; gain = 0.035
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z100'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z100'
Running DRC as a precondition to command place_design
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Core
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1005.813 ; gain = 0.000

Phase 1.1.1 Mandatory Logic Optimization
INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers.
INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers.
INFO: [Opt 31-138] Pushed 0 inverter(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1005.813 ; gain = 0.000
Phase 1.1.1 Mandatory Logic Optimization | Checksum: 139ad4e5a

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.150 . Memory (MB): peak = 1005.813 ; gain = 0.000

Phase 1.1.2 Build Super Logic Region (SLR) Database
Phase 1.1.2 Build Super Logic Region (SLR) Database | Checksum: 139ad4e5a

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.221 . Memory (MB): peak = 1005.813 ; gain = 0.000

Phase 1.1.3 Add Constraints
Phase 1.1.3 Add Constraints | Checksum: 139ad4e5a

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.222 . Memory (MB): peak = 1005.813 ; gain = 0.000

Phase 1.1.4 Build Macros
Phase 1.1.4 Build Macros | Checksum: 1c66e1f97

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.474 . Memory (MB): peak = 1005.813 ; gain = 0.000

Phase 1.1.5 Implementation Feasibility check
Phase 1.1.5 Implementation Feasibility check | Checksum: 1c66e1f97

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.617 . Memory (MB): peak = 1005.813 ; gain = 0.000

Phase 1.1.6 Pre-Place Cells
Phase 1.1.6 Pre-Place Cells | Checksum: 1c66e1f97

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.625 . Memory (MB): peak = 1005.813 ; gain = 0.000

Phase 1.1.7 IO Placement/ Clock Placement/ Build Placer Device
Phase 1.1.7 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1ecbe17d7

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1011.688 ; gain = 5.875

Phase 1.1.8 Build Placer Netlist Model

Phase 1.1.8.1 Place Init Design

Phase 1.1.8.1.1 Build Clock Data
Phase 1.1.8.1.1 Build Clock Data | Checksum: 2b03cc5af

Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1016.527 ; gain = 10.715
Phase 1.1.8.1 Place Init Design | Checksum: 2c66445de

Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1016.527 ; gain = 10.715
Phase 1.1.8 Build Placer Netlist Model | Checksum: 2c66445de

Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1016.527 ; gain = 10.715

Phase 1.1.9 Constrain Clocks/Macros

Phase 1.1.9.1 Constrain Global/Regional Clocks
Phase 1.1.9.1 Constrain Global/Regional Clocks | Checksum: 2c66445de

Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1016.527 ; gain = 10.715
Phase 1.1.9 Constrain Clocks/Macros | Checksum: 2c66445de

Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1016.527 ; gain = 10.715
Phase 1.1 Placer Initialization Core | Checksum: 2c66445de

Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1016.527 ; gain = 10.715
Phase 1 Placer Initialization | Checksum: 2c66445de

Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1016.527 ; gain = 10.715

Phase 2 Global Placement

Phase 2.1 Run Budgeter
Phase 2.1 Run Budgeter | Checksum: 220eba368

Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1042.918 ; gain = 37.105
Phase 2 Global Placement | Checksum: 2431c0a3c

Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1042.918 ; gain = 37.105

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 2431c0a3c

Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1042.918 ; gain = 37.105

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 214e74fe9

Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 1042.918 ; gain = 37.105

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1f74f37cd

Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 1042.918 ; gain = 37.105

Phase 3.4 Timing Path Optimizer
Phase 3.4 Timing Path Optimizer | Checksum: 1df03d8ef

Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 1042.918 ; gain = 37.105

Phase 3.5 Commit Small Macros & Core Logic
Phase 3.5 Commit Small Macros & Core Logic | Checksum: 173a42408

Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1065.938 ; gain = 60.125

Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 173a42408

Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1065.938 ; gain = 60.125
Phase 3 Detail Placement | Checksum: 173a42408

Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1065.938 ; gain = 60.125

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 PCOPT Shape updates
Phase 4.1 PCOPT Shape updates | Checksum: 19dba3924

Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1065.938 ; gain = 60.125

Phase 4.2 Post Placement Optimization

Phase 4.2.1 Post Placement Timing Optimization
Phase 4.2.1 Post Placement Timing Optimization | Checksum: 186ef4baf

Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1065.938 ; gain = 60.125
Phase 4.2 Post Placement Optimization | Checksum: 186ef4baf

Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1065.938 ; gain = 60.125

Phase 4.3 Post Placement Cleanup
Phase 4.3 Post Placement Cleanup | Checksum: 186ef4baf

Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1065.938 ; gain = 60.125

Phase 4.4 Placer Reporting

Phase 4.4.1 Congestion Reporting
Phase 4.4.1 Congestion Reporting | Checksum: 186ef4baf

Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1065.938 ; gain = 60.125

Phase 4.4.2 updateTiming final
Phase 4.4.2 updateTiming final | Checksum: 197679d44

Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1065.938 ; gain = 60.125

Phase 4.4.3 Dump Critical Paths 
Phase 4.4.3 Dump Critical Paths  | Checksum: 197679d44

Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1065.938 ; gain = 60.125

Phase 4.4.4 Restore STA
Phase 4.4.4 Restore STA | Checksum: 197679d44

Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1065.938 ; gain = 60.125

Phase 4.4.5 Print Final WNS
INFO: [Place 30-100] Post Placement Timing Summary | WNS=16.030 | TNS=0.000  |

Phase 4.4.5 Print Final WNS | Checksum: 197679d44

Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1065.938 ; gain = 60.125
Phase 4.4 Placer Reporting | Checksum: 197679d44

Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1065.938 ; gain = 60.125

Phase 4.5 Final Placement Cleanup
Phase 4.5 Final Placement Cleanup | Checksum: 1d0c1e4e1

Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1065.938 ; gain = 60.125
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1d0c1e4e1

Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1065.938 ; gain = 60.125
Ending Placer Task | Checksum: 13b0f8c15

Time (s): cpu = 00:00:00 ; elapsed = 00:00:13 . Memory (MB): peak = 1065.938 ; gain = 60.125
INFO: [Common 17-83] Releasing license: Implementation
31 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1065.938 ; gain = 69.375
INFO: [Timing 38-163] DEBUG : Generate clock report | CPU: 0 secs 

report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.104 . Memory (MB): peak = 1065.938 ; gain = 0.000
INFO: [Designutils 20-134] DEBUG : Generate Control Sets report | CPU: 0 secs 
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.255 . Memory (MB): peak = 1065.938 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z100'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z100'
Running DRC as a precondition to command route_design
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs

Starting Route Task

Phase 1 Build RT Design

Phase 1.1 Build Netlist & NodeGraph
Phase 1.1 Build Netlist & NodeGraph | Checksum: 13b0f8c15

Time (s): cpu = 00:03:36 ; elapsed = 00:01:37 . Memory (MB): peak = 1365.113 ; gain = 228.922
Phase 1 Build RT Design | Checksum: 110b3580a

Time (s): cpu = 00:03:37 ; elapsed = 00:01:38 . Memory (MB): peak = 1365.113 ; gain = 228.922

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 110b3580a

Time (s): cpu = 00:03:37 ; elapsed = 00:01:38 . Memory (MB): peak = 1365.113 ; gain = 228.922

Phase 2.2 Restore Routing
Phase 2.2 Restore Routing | Checksum: 110b3580a

Time (s): cpu = 00:03:37 ; elapsed = 00:01:38 . Memory (MB): peak = 1389.484 ; gain = 253.293

Phase 2.3 Special Net Routing
 Number of Nodes with overlaps = 0
Phase 2.3 Special Net Routing | Checksum: 139a7c183

Time (s): cpu = 00:03:38 ; elapsed = 00:01:39 . Memory (MB): peak = 1460.590 ; gain = 324.398

Phase 2.4 Local Clock Net Routing
Phase 2.4 Local Clock Net Routing | Checksum: 139a7c183

Time (s): cpu = 00:03:38 ; elapsed = 00:01:39 . Memory (MB): peak = 1460.590 ; gain = 324.398

Phase 2.5 Update Timing

Phase 2.5.1 Update timing with NCN CRPR

Phase 2.5.1.1 Hold Budgeting
Phase 2.5.1.1 Hold Budgeting | Checksum: 139a7c183

Time (s): cpu = 00:03:39 ; elapsed = 00:01:40 . Memory (MB): peak = 1460.590 ; gain = 324.398
Phase 2.5.1 Update timing with NCN CRPR | Checksum: 139a7c183

Time (s): cpu = 00:03:39 ; elapsed = 00:01:40 . Memory (MB): peak = 1460.590 ; gain = 324.398
Phase 2.5 Update Timing | Checksum: 139a7c183

Time (s): cpu = 00:03:39 ; elapsed = 00:01:40 . Memory (MB): peak = 1460.590 ; gain = 324.398
INFO: [Route 35-57] Estimated Timing Summary | WNS=16.1   | TNS=0      | WHS=-0.23  | THS=-53.3  |


Phase 2.6 Budgeting
Phase 2.6 Budgeting | Checksum: 139a7c183

Time (s): cpu = 00:03:39 ; elapsed = 00:01:40 . Memory (MB): peak = 1460.590 ; gain = 324.398
Phase 2 Router Initialization | Checksum: 139a7c183

Time (s): cpu = 00:03:39 ; elapsed = 00:01:40 . Memory (MB): peak = 1460.590 ; gain = 324.398

Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 13366bacb

Time (s): cpu = 00:03:40 ; elapsed = 00:01:40 . Memory (MB): peak = 1460.590 ; gain = 324.398

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0

Phase 4.1.1 Remove Overlaps
 Number of Nodes with overlaps = 72
 Number of Nodes with overlaps = 0
Phase 4.1.1 Remove Overlaps | Checksum: 1d5733790

Time (s): cpu = 00:03:40 ; elapsed = 00:01:40 . Memory (MB): peak = 1460.590 ; gain = 324.398

Phase 4.1.2 Update Timing
Phase 4.1.2 Update Timing | Checksum: 1d5733790

Time (s): cpu = 00:03:40 ; elapsed = 00:01:41 . Memory (MB): peak = 1460.590 ; gain = 324.398
INFO: [Route 35-57] Estimated Timing Summary | WNS=15.5   | TNS=0      | WHS=N/A    | THS=N/A    |


Phase 4.1.3 collectNewHoldAndFix
Phase 4.1.3 collectNewHoldAndFix | Checksum: 1356d436d

Time (s): cpu = 00:03:40 ; elapsed = 00:01:41 . Memory (MB): peak = 1460.590 ; gain = 324.398
Phase 4.1 Global Iteration 0 | Checksum: 1356d436d

Time (s): cpu = 00:03:40 ; elapsed = 00:01:41 . Memory (MB): peak = 1460.590 ; gain = 324.398

Phase 4.2 Global Iteration 1

Phase 4.2.1 Remove Overlaps
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0
Phase 4.2.1 Remove Overlaps | Checksum: 1b36997aa

Time (s): cpu = 00:03:40 ; elapsed = 00:01:41 . Memory (MB): peak = 1460.590 ; gain = 324.398

Phase 4.2.2 Update Timing
Phase 4.2.2 Update Timing | Checksum: 1b36997aa

Time (s): cpu = 00:03:40 ; elapsed = 00:01:41 . Memory (MB): peak = 1460.590 ; gain = 324.398
INFO: [Route 35-57] Estimated Timing Summary | WNS=15.5   | TNS=0      | WHS=N/A    | THS=N/A    |


Phase 4.2.3 collectNewHoldAndFix
Phase 4.2.3 collectNewHoldAndFix | Checksum: 1b36997aa

Time (s): cpu = 00:03:40 ; elapsed = 00:01:41 . Memory (MB): peak = 1460.590 ; gain = 324.398
Phase 4.2 Global Iteration 1 | Checksum: 1b36997aa

Time (s): cpu = 00:03:40 ; elapsed = 00:01:41 . Memory (MB): peak = 1460.590 ; gain = 324.398
Phase 4 Rip-up And Reroute | Checksum: 1b36997aa

Time (s): cpu = 00:03:40 ; elapsed = 00:01:41 . Memory (MB): peak = 1460.590 ; gain = 324.398

Phase 5 Delay CleanUp

Phase 5.1 Update Timing
Phase 5.1 Update Timing | Checksum: 1b36997aa

Time (s): cpu = 00:03:40 ; elapsed = 00:01:41 . Memory (MB): peak = 1460.590 ; gain = 324.398
INFO: [Route 35-57] Estimated Timing Summary | WNS=15.6   | TNS=0      | WHS=N/A    | THS=N/A    |

Phase 5 Delay CleanUp | Checksum: 1b36997aa

Time (s): cpu = 00:03:40 ; elapsed = 00:01:41 . Memory (MB): peak = 1460.590 ; gain = 324.398

Phase 6 Post Hold Fix

Phase 6.1 Full Hold Analysis

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 1b36997aa

Time (s): cpu = 00:03:40 ; elapsed = 00:01:41 . Memory (MB): peak = 1460.590 ; gain = 324.398
INFO: [Route 35-57] Estimated Timing Summary | WNS=15.6   | TNS=0      | WHS=0.051  | THS=0      |

Phase 6.1 Full Hold Analysis | Checksum: 1b36997aa

Time (s): cpu = 00:03:41 ; elapsed = 00:01:41 . Memory (MB): peak = 1460.590 ; gain = 324.398
Phase 6 Post Hold Fix | Checksum: 1b36997aa

Time (s): cpu = 00:03:41 ; elapsed = 00:01:41 . Memory (MB): peak = 1460.590 ; gain = 324.398

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.0347249 %
  Global Horizontal Routing Utilization  = 0.060753 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0


Phase 7 Verifying routed nets

 Verification completed successfully
Phase 7 Verifying routed nets | Checksum: 1b36997aa

Time (s): cpu = 00:03:41 ; elapsed = 00:01:41 . Memory (MB): peak = 1460.590 ; gain = 324.398

Phase 8 Depositing Routes
Phase 8 Depositing Routes | Checksum: 15f5523a5

Time (s): cpu = 00:03:41 ; elapsed = 00:01:41 . Memory (MB): peak = 1460.590 ; gain = 324.398

Phase 9 Post Router Timing
INFO: [Route 35-20] Post Routing Timing Summary | WNS=15.588 | TNS=0.000  | WHS=0.053  | THS=0.000  |

INFO: [Route 35-61] The design met the timing requirement.
Phase 9 Post Router Timing | Checksum: 15f5523a5

Time (s): cpu = 00:03:42 ; elapsed = 00:01:42 . Memory (MB): peak = 1460.590 ; gain = 324.398
INFO: [Route 35-16] Router Completed Successfully
Ending Route Task | Checksum: 15f5523a5

Time (s): cpu = 00:00:00 ; elapsed = 00:01:42 . Memory (MB): peak = 1460.590 ; gain = 324.398

Routing Is Done.

Time (s): cpu = 00:00:00 ; elapsed = 00:01:42 . Memory (MB): peak = 1460.590 ; gain = 324.398
INFO: [Common 17-83] Releasing license: Implementation
47 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:03:43 ; elapsed = 00:01:43 . Memory (MB): peak = 1460.590 ; gain = 394.652
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.runs/impl_1/zynq_system_wrapper_drc_routed.rpt.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max, Constraints type: SDC.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.327 . Memory (MB): peak = 1460.590 ; gain = 0.000
INFO: [Common 17-206] Exiting Vivado at Fri Jan 31 19:04:51 2014...
