Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2013.4 (win64) Build 351683 Wed Dec  4 19:12:58 MST 2013
| Date         : Tue Feb 04 15:59:08 2014
| Host         : avnet-wks2 running 64-bit Service Pack 1  (build 7601)
| Command      : report_timing_summary -file zynq_system_wrapper_timing_summary_routed.rpt -pb zynq_system_wrapper_timing_summary_routed.pb
| Design       : zynq_system_wrapper
| Device       : 7z100-ffg900
| Speed File   : -2  PRODUCTION 1.09 2013-11-22
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Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Check Timing
| ------------
------------------------------------------------------------------------------------------------


Checking 'no_clock'.
 There are 0 register/latch pins with no clock.
 There is 1 register/latch pin with constant_clock.

Checking 'unconstrained_internal_endpoints'.
 There are 6 pins that are not constrained for maximum delay.
 There are 0 pins that are not constrained for maximum delay due to constant clock.

Checking 'no_input_delay'.
 There are 3 input ports with no input delay specified.

Checking 'no_output_delay'.
 There are 8 ports with no output delay specified.

Checking 'multiple_clock'.
 There are 0 register/latch pins with related clocks.
 There are 0 register/latch pins with exclusive clocks.

Checking 'generated_clocks'.
 There are 0 generated clocks that are not connected to a clock source.

Checking 'loops'.
 There are 0 combinational loops in the design.

Checking 'partial_input_delay'.
 There are 0 input ports with partial input delay specified.

Checking 'partial_output_delay'.
 There are 0 ports with partial output delay specified.

Checking 'unexpandable_clocks'.
 There are 0 related clock pairs.
 There are 0 User Ignored clock pairs.

Checking 'latch_loops'.
 There are 0 combinational latch loops in the design through latch input

------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
     15.588        0.000                      0                 1768        0.053        0.000                      0                 1768        9.358        0.000                       0                   909  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock       Waveform(ns)       Period(ns)      Frequency(MHz)
-----       ------------       ----------      --------------
clk_fpga_0  {0.000 10.000}     20.000          50.000          


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
clk_fpga_0         15.588        0.000                      0                 1768        0.053        0.000                      0                 1768        9.358        0.000                       0                   909  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  clk_fpga_0
  To Clock:  clk_fpga_0

Setup :            0  Failing Endpoints,  Worst Slack       15.588ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.053ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        9.358ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             15.588ns  (required time - arrival time)
  Source:                 zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/m_payload_i_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_fpga_0  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            zynq_system_i/axi_gpio_0/U0/gpio_core_1/Dual.gpio_OE_reg[10]/CE
                            (rising edge-triggered cell FDSE clocked by clk_fpga_0  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             clk_fpga_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            20.000ns  (clk_fpga_0 rise@20.000ns - clk_fpga_0 rise@0.000ns)
  Data Path Delay:        3.880ns  (logic 0.521ns (13.426%)  route 3.359ns (86.573%))
  Logic Levels:           3  (LUT5=2 LUT6=1)
  Clock Path Skew:        -0.029ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.991ns = ( 24.991 - 20.000 ) 
    Source Clock Delay      (SCD):    5.714ns
    Clock Pessimism Removal (CPR):    0.694ns
  Clock Uncertainty:      0.302ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.600ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_fpga_0 rise edge)
                                                      0.000     0.000 r  
    PS7_X0Y0             PS7                          0.000     0.000 r  zynq_system_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
                         net (fo=1, routed)           3.958     3.958    zynq_system_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.093     4.051 r  zynq_system_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
                         net (fo=909, routed)         1.663     5.714    zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/aclk
    SLICE_X28Y291                                                     r  zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/m_payload_i_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X28Y291        FDRE (Prop_fdre_C_Q)         0.204     5.918 f  zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/m_payload_i_reg[3]/Q
                         net (fo=9, routed)           1.155     7.073    zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/si_rs_araddr[3]
    SLICE_X34Y288        LUT6 (Prop_lut6_I5_O)        0.126     7.199 f  zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/m_axi_araddr[3]_INST_0/O
                         net (fo=67, routed)          1.321     8.520    zynq_system_i/axi_gpio_0/U0/s_axi_araddr[3]
    SLICE_X38Y300        LUT5 (Prop_lut5_I1_O)        0.053     8.573 f  zynq_system_i/axi_gpio_0/U0/Dual.gpio_OE[0]_i_2/O
                         net (fo=8, routed)           0.474     9.047    zynq_system_i/axi_gpio_0/U0/n_0_Dual.gpio_OE[0]_i_2
    SLICE_X35Y300        LUT5 (Prop_lut5_I4_O)        0.138     9.185 r  zynq_system_i/axi_gpio_0/U0/Dual.gpio_OE[3]_i_1/O
                         net (fo=29, routed)          0.410     9.594    zynq_system_i/axi_gpio_0/U0/n_0_Dual.gpio_OE[3]_i_1
    SLICE_X35Y303        FDSE                                         r  zynq_system_i/axi_gpio_0/U0/gpio_core_1/Dual.gpio_OE_reg[10]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_fpga_0 rise edge)
                                                     20.000    20.000 r  
    PS7_X0Y0             PS7                          0.000    20.000 r  zynq_system_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
                         net (fo=1, routed)           3.347    23.347    zynq_system_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.083    23.430 r  zynq_system_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
                         net (fo=909, routed)         1.561    24.991    zynq_system_i/axi_gpio_0/U0/s_axi_aclk
    SLICE_X35Y303                                                     r  zynq_system_i/axi_gpio_0/U0/gpio_core_1/Dual.gpio_OE_reg[10]/C
                         clock pessimism              0.694    25.685    
                         clock uncertainty           -0.302    25.383    
    SLICE_X35Y303        FDSE (Setup_fdse_C_CE)      -0.201    25.182    zynq_system_i/axi_gpio_0/U0/gpio_core_1/Dual.gpio_OE_reg[10]
  -------------------------------------------------------------------
                         required time                         25.182    
                         arrival time                          -9.594    
  -------------------------------------------------------------------
                         slack                                 15.588    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.053ns  (arrival time - required time)
  Source:                 zynq_system_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_fpga_0  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32/D
                            (rising edge-triggered cell SRLC32E clocked by clk_fpga_0  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             clk_fpga_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
  Data Path Delay:        0.185ns  (logic 0.091ns (49.160%)  route 0.094ns (50.840%))
  Logic Levels:           0  
  Clock Path Skew:        0.014ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.537ns
    Source Clock Delay      (SCD):    2.896ns
    Clock Pessimism Removal (CPR):    0.627ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_fpga_0 rise edge)
                                                      0.000     0.000 r  
    PS7_X0Y0             PS7                          0.000     0.000 r  zynq_system_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
                         net (fo=1, routed)           2.122     2.122    zynq_system_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.148 r  zynq_system_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
                         net (fo=909, routed)         0.748     2.896    zynq_system_i/axi_gpio_0/U0/s_axi_aclk
    SLICE_X35Y296                                                     r  zynq_system_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y296        FDRE (Prop_fdre_C_Q)         0.091     2.987 r  zynq_system_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[28]/Q
                         net (fo=1, routed)           0.094     3.081    zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/m_axi_rdata[28]
    SLICE_X34Y295        SRLC32E                                      r  zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_fpga_0 rise edge)
                                                      0.000     0.000 r  
    PS7_X0Y0             PS7                          0.000     0.000 r  zynq_system_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
                         net (fo=1, routed)           2.512     2.512    zynq_system_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.030     2.542 r  zynq_system_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
                         net (fo=909, routed)         0.995     3.537    zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/aclk
    SLICE_X34Y295                                                     r  zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32/CLK
                         clock pessimism             -0.627     2.910    
    SLICE_X34Y295        SRLC32E (Hold_srlc32e_CLK_D)
                                                      0.118     3.028    zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32
  -------------------------------------------------------------------
                         required time                         -3.028    
                         arrival time                           3.081    
  -------------------------------------------------------------------
                         slack                                  0.053    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_fpga_0
Waveform:           { 0 10 }
Period:             20.000
Sources:            { zynq_system_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] }

Check Type        Corner  Lib Pin      Reference Pin  Required  Actual  Slack   Location        Pin
Min Period        n/a     BUFG/I       n/a            1.408     20.000  18.591  BUFGCTRL_X0Y16  zynq_system_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/I
Low Pulse Width   Slow    SRLC32E/CLK  n/a            0.642     10.000  9.358   SLICE_X34Y291   zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32/CLK
High Pulse Width  Fast    SRLC32E/CLK  n/a            0.642     10.000  9.358   SLICE_X34Y291   zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32/CLK



