Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------
| Tool Version : Vivado v.2013.4 (win64) Build 351683 Wed Dec  4 19:12:58 MST 2013
| Date         : Tue Feb 04 15:59:05 2014
| Host         : avnet-wks2 running 64-bit Service Pack 1  (build 7601)
| Command      : report_drc
-----------------------------------------------------------------------------------

Report DRC

Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS

1. REPORT SUMMARY
-----------------

REPORT SUMMARY
            Netlist: netlist
          Floorplan: design_1
      Design limits: <entire design considered>
             Checks: defined_DATA_WIDTH
                     DSP48E1_AregAcascreg
                     Bank IO standard internal Vref conflict
                     Bank IO standard limits
                     Bank IO standard Support
                     Bank IO standard Vcc
                     Bank IO standard Vref utilization
                     Bank IO standard Vref
                     Bank IO standard Termination
                     Input Buffer Connections
                     Missing CFGBVS and CONFIG_VOLTAGE Design Properties
                     Design Rule Check Disabled
                     DCI Cascade IO standard
                     DCI Cascade with part compatibility
                     DCI Cascade Checks
                     Bank IO standard VRN/VRP Occupied
                     Inconsistent Diff pair IOStandards
                     Inconsistent Diff pair IOStandards
                     Inconsistent Diff pair IOStandards
                     DSP48 Buffering
                     DSP48 Cascade
                     DSP input pipelining
                     DSP input registers
                     DSP output pipelining
                     DSP output registers
                     DSP48E1_PregOpmodeZmuxP
                     Cascade input routing
                     Area group tile alignment
                     Pblock overlap
                     Pblock partition
                     FIFO_SynSameClk
                     RESET_AFTER_RECONFIG only supported on reconfigurable pblocks
                     Black Box Instances
                     IN_TERM / OUT_TERM requirements
                     IO Bus SLR Crossings
                     Number of IOs
                     IOB clock sharing
                     IOs crosstalk to MGT
                     Directionless IOs
                     Differential IO pads
                     Part compatibility for differing bank types.
                     Incompatible BUFGs among compatible parts.
                     MGT not allowed for part compatibility
                     Part compatibility implied prohibits not respected
                     Part compatibility between monolithic and multi-die devices.
                     IOs placed on disallowed sites
                     IOB set reset sharing
                     IOStandard Type
                     INTERNAL_VREF
                     Longest carry chain height
                     HLUTNM on instances assigned to non-overlapping pblocks
                     Pblock ranges contradict LOC constraints on logic assigned to the pblock
                     LUTNM on instances assigned to non-overlapping pblocks
                     Combinatorial Loop
                     Bidirection LVDS IOs
                     Multiple Driver Nets
                     Crossing SLR boundary
                     Driverless Nets
                     Unspecified I/O Standard
                     defined_IBUF_LOW_PWR
                     connects_TDO
                     Invalid Site Configuration
                     BSCAN_JtagChain
                     Non-Optimal connections to BUFG
                     Unroutable connections to BUFG
                     DRC check of BUFIO loads
                     Clock Placer Checks
                     Placement Constraints Check for Clock Region(s)
                     Design Exceptions
                     Placement Constraints Check for Design Lock
                     DSP Connectivity Checks
                     Unroutable connections to GTH instance
                     Non-Optimal connections which could lead to hold violations
                     IDELAYCTRL DRC Checks
                     IDELAY DRC Checks
                     Dangling IBUFDS output inside IOBUFDS_DIFF_OUT macro 
                     Unroutable connection between IOB and IDDR
                     DRC check between IO and buffer(IBUF/OBUF)
                     IOSTANDARD violations
                     Placement Constraints Check for IO constraints
                     ODELAY Check for 3.3 V standard
                     Inconsistent port properties
                     RAMB output registers
                     connects_I0_connects_I1
                     IO port drives logic
                     Unrouted net
                     Missing Site Driver
                     OSERDES driving OBUF
                     Unconstrained Logical Port
                     Resource utilization
                     VCCAUX_IO unsupported with I/O Standard
                     VCCAUX
                     Vccaux voltage requirement for LVCMOS25
                     VCCOSENSEMODE not supported
                     Runtime intensive exceptions
                     Hold option missing in multicycle path constraint
                     Delay constraint missing on IO port
                     PS7 block required
           Max violations: <unlimited>
         Violations found: 156

2. REPORT DETAILS
-----------------
CFGBVS-1#1 Warning
Missing CFGBVS and CONFIG_VOLTAGE Design Properties  
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:

 set_property CFGBVS value1 [current_design]
 #where value1 is either VCCO or GND

 set_property CONFIG_VOLTAGE value2 [current_design]
 #where value2 is the voltage provided to configuration bank 0

Refer to the device configuration user guide for more information.
Related violations: <none>

CHECK-1#1 Warning
Design Rule Check Disabled  
The following rules are disabled: , , , 
Related violations: <none>

RPBF-3#1 Warning
IO port buffering is incomplete  
Device port DDR_addr[0] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#2 Warning
IO port buffering is incomplete  
Device port DDR_addr[10] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#3 Warning
IO port buffering is incomplete  
Device port DDR_addr[11] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#4 Warning
IO port buffering is incomplete  
Device port DDR_addr[12] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#5 Warning
IO port buffering is incomplete  
Device port DDR_addr[13] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#6 Warning
IO port buffering is incomplete  
Device port DDR_addr[14] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#7 Warning
IO port buffering is incomplete  
Device port DDR_addr[1] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#8 Warning
IO port buffering is incomplete  
Device port DDR_addr[2] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#9 Warning
IO port buffering is incomplete  
Device port DDR_addr[3] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#10 Warning
IO port buffering is incomplete  
Device port DDR_addr[4] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#11 Warning
IO port buffering is incomplete  
Device port DDR_addr[5] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#12 Warning
IO port buffering is incomplete  
Device port DDR_addr[6] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#13 Warning
IO port buffering is incomplete  
Device port DDR_addr[7] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#14 Warning
IO port buffering is incomplete  
Device port DDR_addr[8] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#15 Warning
IO port buffering is incomplete  
Device port DDR_addr[9] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#16 Warning
IO port buffering is incomplete  
Device port DDR_ba[0] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#17 Warning
IO port buffering is incomplete  
Device port DDR_ba[1] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#18 Warning
IO port buffering is incomplete  
Device port DDR_ba[2] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#19 Warning
IO port buffering is incomplete  
Device port DDR_cas_n expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#20 Warning
IO port buffering is incomplete  
Device port DDR_ck_n expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#21 Warning
IO port buffering is incomplete  
Device port DDR_ck_p expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#22 Warning
IO port buffering is incomplete  
Device port DDR_cke expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#23 Warning
IO port buffering is incomplete  
Device port DDR_cs_n expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#24 Warning
IO port buffering is incomplete  
Device port DDR_dm[0] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#25 Warning
IO port buffering is incomplete  
Device port DDR_dm[1] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#26 Warning
IO port buffering is incomplete  
Device port DDR_dm[2] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#27 Warning
IO port buffering is incomplete  
Device port DDR_dm[3] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#28 Warning
IO port buffering is incomplete  
Device port DDR_dq[0] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#29 Warning
IO port buffering is incomplete  
Device port DDR_dq[10] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#30 Warning
IO port buffering is incomplete  
Device port DDR_dq[11] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#31 Warning
IO port buffering is incomplete  
Device port DDR_dq[12] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#32 Warning
IO port buffering is incomplete  
Device port DDR_dq[13] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#33 Warning
IO port buffering is incomplete  
Device port DDR_dq[14] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#34 Warning
IO port buffering is incomplete  
Device port DDR_dq[15] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#35 Warning
IO port buffering is incomplete  
Device port DDR_dq[16] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#36 Warning
IO port buffering is incomplete  
Device port DDR_dq[17] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#37 Warning
IO port buffering is incomplete  
Device port DDR_dq[18] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#38 Warning
IO port buffering is incomplete  
Device port DDR_dq[19] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#39 Warning
IO port buffering is incomplete  
Device port DDR_dq[1] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#40 Warning
IO port buffering is incomplete  
Device port DDR_dq[20] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#41 Warning
IO port buffering is incomplete  
Device port DDR_dq[21] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#42 Warning
IO port buffering is incomplete  
Device port DDR_dq[22] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#43 Warning
IO port buffering is incomplete  
Device port DDR_dq[23] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#44 Warning
IO port buffering is incomplete  
Device port DDR_dq[24] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#45 Warning
IO port buffering is incomplete  
Device port DDR_dq[25] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#46 Warning
IO port buffering is incomplete  
Device port DDR_dq[26] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#47 Warning
IO port buffering is incomplete  
Device port DDR_dq[27] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#48 Warning
IO port buffering is incomplete  
Device port DDR_dq[28] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#49 Warning
IO port buffering is incomplete  
Device port DDR_dq[29] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#50 Warning
IO port buffering is incomplete  
Device port DDR_dq[2] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#51 Warning
IO port buffering is incomplete  
Device port DDR_dq[30] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#52 Warning
IO port buffering is incomplete  
Device port DDR_dq[31] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#53 Warning
IO port buffering is incomplete  
Device port DDR_dq[3] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#54 Warning
IO port buffering is incomplete  
Device port DDR_dq[4] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#55 Warning
IO port buffering is incomplete  
Device port DDR_dq[5] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#56 Warning
IO port buffering is incomplete  
Device port DDR_dq[6] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#57 Warning
IO port buffering is incomplete  
Device port DDR_dq[7] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#58 Warning
IO port buffering is incomplete  
Device port DDR_dq[8] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#59 Warning
IO port buffering is incomplete  
Device port DDR_dq[9] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#60 Warning
IO port buffering is incomplete  
Device port DDR_dqs_n[0] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#61 Warning
IO port buffering is incomplete  
Device port DDR_dqs_n[1] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#62 Warning
IO port buffering is incomplete  
Device port DDR_dqs_n[2] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#63 Warning
IO port buffering is incomplete  
Device port DDR_dqs_n[3] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#64 Warning
IO port buffering is incomplete  
Device port DDR_dqs_p[0] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#65 Warning
IO port buffering is incomplete  
Device port DDR_dqs_p[1] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#66 Warning
IO port buffering is incomplete  
Device port DDR_dqs_p[2] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#67 Warning
IO port buffering is incomplete  
Device port DDR_dqs_p[3] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#68 Warning
IO port buffering is incomplete  
Device port DDR_odt expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#69 Warning
IO port buffering is incomplete  
Device port DDR_ras_n expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#70 Warning
IO port buffering is incomplete  
Device port DDR_reset_n expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#71 Warning
IO port buffering is incomplete  
Device port DDR_we_n expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#72 Warning
IO port buffering is incomplete  
Device port FIXED_IO_ddr_vrn expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#73 Warning
IO port buffering is incomplete  
Device port FIXED_IO_ddr_vrp expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#74 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[0] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#75 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[10] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#76 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[11] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#77 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[12] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#78 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[13] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#79 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[14] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#80 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[15] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#81 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[16] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#82 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[17] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#83 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[18] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#84 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[19] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#85 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[1] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#86 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[20] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#87 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[21] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#88 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[22] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#89 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[23] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#90 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[24] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#91 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[25] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#92 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[26] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#93 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[27] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#94 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[28] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#95 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[29] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#96 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[2] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#97 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[30] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#98 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[31] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#99 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[32] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#100 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[33] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#101 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[34] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#102 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[35] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#103 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[36] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#104 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[37] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#105 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[38] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#106 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[39] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#107 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[3] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#108 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[40] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#109 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[41] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#110 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[42] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#111 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[43] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#112 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[44] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#113 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[45] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#114 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[46] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#115 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[47] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#116 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[48] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#117 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[49] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#118 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[4] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#119 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[50] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#120 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[51] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#121 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[52] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#122 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[53] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#123 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[5] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#124 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[6] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#125 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[7] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#126 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[8] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#127 Warning
IO port buffering is incomplete  
Device port FIXED_IO_mio[9] expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#128 Warning
IO port buffering is incomplete  
Device port FIXED_IO_ps_clk expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#129 Warning
IO port buffering is incomplete  
Device port FIXED_IO_ps_porb expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

RPBF-3#130 Warning
IO port buffering is incomplete  
Device port FIXED_IO_ps_srstb expects both input and output buffering but the buffers are incomplete.
Related violations: <none>

XDCM-1#1 Warning
Delay constraint missing on IO port  
The port 'DDR_addr[0], DDR_addr[1], DDR_addr[2], DDR_addr[3], DDR_addr[4], DDR_addr[5], DDR_addr[6], DDR_addr[7], DDR_addr[8], DDR_addr[9], DDR_addr[10], DDR_addr[11], DDR_addr[12], DDR_addr[13], DDR_addr[14] (the first 15 of 15 listed)' does not have any I/O delay defined. It is necessary to have I/O (input or output) delays defined on all the ports to properly time the FPGA interface.
Related violations: <none>

XDCM-1#2 Warning
Delay constraint missing on IO port  
The port 'DDR_ba[0], DDR_ba[1], DDR_ba[2]' does not have any I/O delay defined. It is necessary to have I/O (input or output) delays defined on all the ports to properly time the FPGA interface.
Related violations: <none>

XDCM-1#3 Warning
Delay constraint missing on IO port  
The port 'DDR_cas_n' does not have any I/O delay defined. It is necessary to have I/O (input or output) delays defined on all the ports to properly time the FPGA interface.
Related violations: <none>

XDCM-1#4 Warning
Delay constraint missing on IO port  
The port 'DDR_ck_n' does not have any I/O delay defined. It is necessary to have I/O (input or output) delays defined on all the ports to properly time the FPGA interface.
Related violations: <none>

XDCM-1#5 Warning
Delay constraint missing on IO port  
The port 'DDR_ck_p' does not have any I/O delay defined. It is necessary to have I/O (input or output) delays defined on all the ports to properly time the FPGA interface.
Related violations: <none>

XDCM-1#6 Warning
Delay constraint missing on IO port  
The port 'DDR_cke' does not have any I/O delay defined. It is necessary to have I/O (input or output) delays defined on all the ports to properly time the FPGA interface.
Related violations: <none>

XDCM-1#7 Warning
Delay constraint missing on IO port  
The port 'DDR_cs_n' does not have any I/O delay defined. It is necessary to have I/O (input or output) delays defined on all the ports to properly time the FPGA interface.
Related violations: <none>

XDCM-1#8 Warning
Delay constraint missing on IO port  
The port 'DDR_dm[0], DDR_dm[1], DDR_dm[2], DDR_dm[3]' does not have any I/O delay defined. It is necessary to have I/O (input or output) delays defined on all the ports to properly time the FPGA interface.
Related violations: <none>

XDCM-1#9 Warning
Delay constraint missing on IO port  
The port 'DDR_dq[0], DDR_dq[1], DDR_dq[2], DDR_dq[3], DDR_dq[4], DDR_dq[5], DDR_dq[6], DDR_dq[7], DDR_dq[8], DDR_dq[9], DDR_dq[10], DDR_dq[11], DDR_dq[12], DDR_dq[13], DDR_dq[14] (the first 15 of 32 listed)' does not have any I/O delay defined. It is necessary to have I/O (input or output) delays defined on all the ports to properly time the FPGA interface.
Related violations: <none>

XDCM-1#10 Warning
Delay constraint missing on IO port  
The port 'DDR_dqs_n[0], DDR_dqs_n[1], DDR_dqs_n[2], DDR_dqs_n[3]' does not have any I/O delay defined. It is necessary to have I/O (input or output) delays defined on all the ports to properly time the FPGA interface.
Related violations: <none>

XDCM-1#11 Warning
Delay constraint missing on IO port  
The port 'DDR_dqs_p[0], DDR_dqs_p[1], DDR_dqs_p[2], DDR_dqs_p[3]' does not have any I/O delay defined. It is necessary to have I/O (input or output) delays defined on all the ports to properly time the FPGA interface.
Related violations: <none>

XDCM-1#12 Warning
Delay constraint missing on IO port  
The port 'DDR_odt' does not have any I/O delay defined. It is necessary to have I/O (input or output) delays defined on all the ports to properly time the FPGA interface.
Related violations: <none>

XDCM-1#13 Warning
Delay constraint missing on IO port  
The port 'DDR_ras_n' does not have any I/O delay defined. It is necessary to have I/O (input or output) delays defined on all the ports to properly time the FPGA interface.
Related violations: <none>

XDCM-1#14 Warning
Delay constraint missing on IO port  
The port 'DDR_reset_n' does not have any I/O delay defined. It is necessary to have I/O (input or output) delays defined on all the ports to properly time the FPGA interface.
Related violations: <none>

XDCM-1#15 Warning
Delay constraint missing on IO port  
The port 'DDR_we_n' does not have any I/O delay defined. It is necessary to have I/O (input or output) delays defined on all the ports to properly time the FPGA interface.
Related violations: <none>

XDCM-1#16 Warning
Delay constraint missing on IO port  
The port 'FIXED_IO_ddr_vrn' does not have any I/O delay defined. It is necessary to have I/O (input or output) delays defined on all the ports to properly time the FPGA interface.
Related violations: <none>

XDCM-1#17 Warning
Delay constraint missing on IO port  
The port 'FIXED_IO_ddr_vrp' does not have any I/O delay defined. It is necessary to have I/O (input or output) delays defined on all the ports to properly time the FPGA interface.
Related violations: <none>

XDCM-1#18 Warning
Delay constraint missing on IO port  
The port 'FIXED_IO_mio[0], FIXED_IO_mio[1], FIXED_IO_mio[2], FIXED_IO_mio[3], FIXED_IO_mio[4], FIXED_IO_mio[5], FIXED_IO_mio[6], FIXED_IO_mio[7], FIXED_IO_mio[8], FIXED_IO_mio[9], FIXED_IO_mio[10], FIXED_IO_mio[11], FIXED_IO_mio[12], FIXED_IO_mio[13], FIXED_IO_mio[14] (the first 15 of 54 listed)' does not have any I/O delay defined. It is necessary to have I/O (input or output) delays defined on all the ports to properly time the FPGA interface.
Related violations: <none>

XDCM-1#19 Warning
Delay constraint missing on IO port  
The port 'FIXED_IO_ps_clk' does not have any I/O delay defined. It is necessary to have I/O (input or output) delays defined on all the ports to properly time the FPGA interface.
Related violations: <none>

XDCM-1#20 Warning
Delay constraint missing on IO port  
The port 'FIXED_IO_ps_porb' does not have any I/O delay defined. It is necessary to have I/O (input or output) delays defined on all the ports to properly time the FPGA interface.
Related violations: <none>

XDCM-1#21 Warning
Delay constraint missing on IO port  
The port 'FIXED_IO_ps_srstb' does not have any I/O delay defined. It is necessary to have I/O (input or output) delays defined on all the ports to properly time the FPGA interface.
Related violations: <none>

XDCM-1#22 Warning
Delay constraint missing on IO port  
The port 'InputButtons[0], InputButtons[1], InputButtons[2]' does not have any I/O delay defined. It is necessary to have I/O (input or output) delays defined on all the ports to properly time the FPGA interface.
Related violations: <none>

XDCM-1#23 Warning
Delay constraint missing on IO port  
The port 'LEDs_8Bits[0], LEDs_8Bits[1], LEDs_8Bits[2], LEDs_8Bits[3], LEDs_8Bits[4], LEDs_8Bits[5], LEDs_8Bits[6], LEDs_8Bits[7]' does not have any I/O delay defined. It is necessary to have I/O (input or output) delays defined on all the ports to properly time the FPGA interface.
Related violations: <none>

RTSTAT-10#1 Advisory
No routable loads  
94 net(s) have no routable loads. The problem net(s) are zynq_system_i/processing_system7_0/inst/GPIO_O[0], zynq_system_i/processing_system7_0/inst/GPIO_O[1], zynq_system_i/processing_system7_0/inst/GPIO_O[2], zynq_system_i/processing_system7_0/inst/M_AXI_GP0_ARADDR[12], zynq_system_i/processing_system7_0/inst/M_AXI_GP0_ARADDR[13], zynq_system_i/processing_system7_0/inst/M_AXI_GP0_ARADDR[14], zynq_system_i/processing_system7_0/inst/M_AXI_GP0_ARADDR[15], zynq_system_i/processing_system7_0/inst/M_AXI_GP0_ARADDR[16], zynq_system_i/processing_system7_0/inst/M_AXI_GP0_ARADDR[17], zynq_system_i/processing_system7_0/inst/M_AXI_GP0_ARADDR[18], zynq_system_i/processing_system7_0/inst/M_AXI_GP0_ARADDR[19], zynq_system_i/processing_system7_0/inst/M_AXI_GP0_ARADDR[20], zynq_system_i/processing_system7_0/inst/M_AXI_GP0_ARADDR[21], zynq_system_i/processing_system7_0/inst/M_AXI_GP0_ARADDR[22], zynq_system_i/processing_system7_0/inst/M_AXI_GP0_ARADDR[23] (the first 15 of 94 listed).
Related violations: <none>


