
*** Running vivado
    with args -log zynq_system_wrapper.rds -m64 -mode batch -messageDb vivado.pb -source zynq_system_wrapper.tcl


****** Vivado v2013.4 (64-bit)
  **** SW Build 351683 on Wed Dec  4 19:12:58 MST 2013
  **** IP Build 208076 on Mon Dec  2 12:38:17 MST 2013
    ** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.

Attempting to get a license: Implementation
Feature available: Implementation
Loading parts and site information from C:/Xilinx/Vivado/2013.4/data/parts/arch.xml
Parsing RTL primitives file [C:/Xilinx/Vivado/2013.4/data/parts/xilinx/rtl/prims/rtl_prims.xml]
Finished parsing RTL primitives file [C:/Xilinx/Vivado/2013.4/data/parts/xilinx/rtl/prims/rtl_prims.xml]
source zynq_system_wrapper.tcl
# set_param gui.test TreeTableDev
# set_msg_config -id {HDL 9-1061} -limit 100000
# set_msg_config -id {HDL 9-1654} -limit 100000
# create_project -in_memory -part xc7z100ffg900-2
# set_property target_language Verilog [current_project]
# set_param project.compositeFile.enableAutoGeneration 0
# set_property ip_repo_paths C:/Projects/Vivado_IP_Repository [current_fileset]
# add_files C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/zynq_system.bd
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Projects/Vivado_IP_Repository'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2013.4/data/ip'.
# set_property used_in_implementation false [get_files -all c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/zynq_system_processing_system7_0_0.xdc]
# set_property used_in_implementation false [get_files -all c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/zynq_system_axi_gpio_0_0_ooc.xdc]
# set_property used_in_implementation false [get_files -all c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/zynq_system_axi_gpio_0_0.xdc]
# set_property used_in_implementation false [get_files -all c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/zynq_system_axi_gpio_0_0_board.xdc]
# set_property used_in_implementation false [get_files -all c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_rst_processing_system7_0_50M_0/zynq_system_rst_processing_system7_0_50M_0.xdc]
# set_property used_in_implementation false [get_files -all c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_rst_processing_system7_0_50M_0/zynq_system_rst_processing_system7_0_50M_0_ooc.xdc]
# set_property used_in_implementation false [get_files -all c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_rst_processing_system7_0_50M_0/zynq_system_rst_processing_system7_0_50M_0_board.xdc]
# set_property used_in_implementation false [get_files -all c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_4/zynq_system_auto_pc_4_ooc.xdc]
# set_property used_in_implementation false [get_files -all C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/zynq_system_ooc.xdc]
# set_msg_config -id {IP_Flow 19-2162} -severity warning -new_severity info
# set_property is_locked true [get_files C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/zynq_system.bd]
# read_verilog C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/hdl/zynq_system_wrapper.v
# read_xdc C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/constrs_1/imports/new/design_1.xdc
# set_property used_in_implementation false [get_files C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/constrs_1/imports/new/design_1.xdc]
# read_xdc dont_touch.xdc
# set_property used_in_implementation false [get_files dont_touch.xdc]
# set_param synth.vivado.isSynthRun true
# set_property webtalk.parent_dir C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.data/wt [current_project]
# set_property parent.project_dir C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI [current_project]
# synth_design -top zynq_system_wrapper -part xc7z100ffg900-2
Command: synth_design -top zynq_system_wrapper -part xc7z100ffg900-2

Starting synthesis...

Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100'
WARNING: [Synth 8-2611] redeclaration of ansi port PWM_out is not allowed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_PWM_Controller_0_0/work/PWM_Controller.srcs/sources_1/imports/hdl/PWM_Controller.v:35]
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:01:14 ; elapsed = 00:01:22 . Memory (MB): peak = 275.883 ; gain = 120.332
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'zynq_system_wrapper' [C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/hdl/zynq_system_wrapper.v:3]
INFO: [Synth 8-638] synthesizing module 'zynq_system' [C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/hdl/zynq_system.v:299]
INFO: [Synth 8-638] synthesizing module 'GND' [C:/Xilinx/Vivado/2013.4/scripts/rt/data/unisim_comp.v:4176]
INFO: [Synth 8-256] done synthesizing module 'GND' (1#1) [C:/Xilinx/Vivado/2013.4/scripts/rt/data/unisim_comp.v:4176]
INFO: [Synth 8-638] synthesizing module 'zynq_system_PWM_Controller_0_0' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_PWM_Controller_0_0/synth/zynq_system_PWM_Controller_0_0.v:57]
INFO: [Synth 8-638] synthesizing module 'PWM_Controller' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_PWM_Controller_0_0/work/PWM_Controller.srcs/sources_1/imports/hdl/PWM_Controller.v:23]
	Parameter period bound to: 20 - type: integer 
WARNING: [Synth 8-567] referenced signal 'count' should be on the sensitivity list [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_PWM_Controller_0_0/work/PWM_Controller.srcs/sources_1/imports/hdl/PWM_Controller.v:40]
WARNING: [Synth 8-567] referenced signal 'DutyCycle' should be on the sensitivity list [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_PWM_Controller_0_0/work/PWM_Controller.srcs/sources_1/imports/hdl/PWM_Controller.v:40]
INFO: [Synth 8-256] done synthesizing module 'PWM_Controller' (2#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_PWM_Controller_0_0/work/PWM_Controller.srcs/sources_1/imports/hdl/PWM_Controller.v:23]
INFO: [Synth 8-256] done synthesizing module 'zynq_system_PWM_Controller_0_0' (3#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_PWM_Controller_0_0/synth/zynq_system_PWM_Controller_0_0.v:57]
INFO: [Synth 8-638] synthesizing module 'VCC' [C:/Xilinx/Vivado/2013.4/scripts/rt/data/unisim_comp.v:35748]
INFO: [Synth 8-256] done synthesizing module 'VCC' (4#1) [C:/Xilinx/Vivado/2013.4/scripts/rt/data/unisim_comp.v:35748]
INFO: [Synth 8-638] synthesizing module 'zynq_system_axi_gpio_0_0' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/synth/zynq_system_axi_gpio_0_0.vhd:86]
	Parameter C_FAMILY bound to: zynq - type: string 
	Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer 
	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
	Parameter C_GPIO_WIDTH bound to: 32 - type: integer 
	Parameter C_GPIO2_WIDTH bound to: 3 - type: integer 
	Parameter C_ALL_INPUTS bound to: 0 - type: integer 
	Parameter C_ALL_INPUTS_2 bound to: 1 - type: integer 
	Parameter C_ALL_OUTPUTS bound to: 1 - type: integer 
	Parameter C_ALL_OUTPUTS_2 bound to: 0 - type: integer 
	Parameter C_INTERRUPT_PRESENT bound to: 1 - type: integer 
	Parameter C_DOUT_DEFAULT bound to: 32'b00000000000000000000000000000000 
	Parameter C_TRI_DEFAULT bound to: 32'b11111111111111111111111111111111 
	Parameter C_IS_DUAL bound to: 1 - type: integer 
	Parameter C_DOUT_DEFAULT_2 bound to: 32'b00000000000000000000000000000000 
	Parameter C_TRI_DEFAULT_2 bound to: 32'b11111111111111111111111111111111 
INFO: [Synth 8-3491] module 'axi_gpio' declared at 'c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/axi_gpio_v2_0/hdl/src/vhdl/axi_gpio.vhd:190' bound to instance 'U0' of component 'axi_gpio' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/synth/zynq_system_axi_gpio_0_0.vhd:167]
INFO: [Synth 8-638] synthesizing module 'axi_gpio__parameterized0' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/axi_gpio_v2_0/hdl/src/vhdl/axi_gpio.vhd:283]
	Parameter C_FAMILY bound to: zynq - type: string 
	Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer 
	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
	Parameter C_GPIO_WIDTH bound to: 32 - type: integer 
	Parameter C_GPIO2_WIDTH bound to: 3 - type: integer 
	Parameter C_ALL_INPUTS bound to: 0 - type: integer 
	Parameter C_ALL_INPUTS_2 bound to: 1 - type: integer 
	Parameter C_ALL_OUTPUTS bound to: 1 - type: integer 
	Parameter C_ALL_OUTPUTS_2 bound to: 0 - type: integer 
	Parameter C_INTERRUPT_PRESENT bound to: 1 - type: integer 
	Parameter C_DOUT_DEFAULT bound to: 0 - type: integer 
	Parameter C_TRI_DEFAULT bound to: -1 - type: integer 
	Parameter C_IS_DUAL bound to: 1 - type: integer 
	Parameter C_DOUT_DEFAULT_2 bound to: 0 - type: integer 
	Parameter C_TRI_DEFAULT_2 bound to: -1 - type: integer 
INFO: [Synth 8-4472] Detected and applied attribute max_fanout = 10000 [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/axi_gpio_v2_0/hdl/src/vhdl/axi_gpio.vhd:220]
INFO: [Synth 8-4472] Detected and applied attribute max_fanout = 10000 [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/axi_gpio_v2_0/hdl/src/vhdl/axi_gpio.vhd:221]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/axi_lite_ipif_v2_0/hdl/src/vhdl/axi_lite_ipif.vhd:253]
	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
	Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer 
	Parameter C_S_AXI_MIN_SIZE bound to: 32'b00000000000000000000000111111111 
	Parameter C_USE_WSTRB bound to: 0 - type: integer 
	Parameter C_DPHASE_TIMEOUT bound to: 8 - type: integer 
	Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111100000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111111 
	Parameter C_ARD_NUM_CE_ARRAY bound to: 64'b0000000000000000000000000001000000000000000000000000000000000100 
	Parameter C_FAMILY bound to: zynq - type: string 
INFO: [Synth 8-638] synthesizing module 'slave_attachment' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/axi_lite_ipif_v2_0/hdl/src/vhdl/slave_attachment.vhd:243]
	Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111100000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111111 
	Parameter C_ARD_NUM_CE_ARRAY bound to: 64'b0000000000000000000000000001000000000000000000000000000000000100 
	Parameter C_IPIF_ABUS_WIDTH bound to: 9 - type: integer 
	Parameter C_IPIF_DBUS_WIDTH bound to: 32 - type: integer 
	Parameter C_S_AXI_MIN_SIZE bound to: 511 - type: integer 
	Parameter C_USE_WSTRB bound to: 0 - type: integer 
	Parameter C_DPHASE_TIMEOUT bound to: 8 - type: integer 
	Parameter C_FAMILY bound to: zynq - type: string 
INFO: [Synth 8-638] synthesizing module 'address_decoder' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/axi_lite_ipif_v2_0/hdl/src/vhdl/address_decoder.vhd:188]
	Parameter C_BUS_AWIDTH bound to: 9 - type: integer 
	Parameter C_S_AXI_MIN_SIZE bound to: 511 - type: integer 
	Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111100000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111111 
	Parameter C_ARD_NUM_CE_ARRAY bound to: 64'b0000000000000000000000000001000000000000000000000000000000000100 
	Parameter C_FAMILY bound to: nofamily - type: string 
INFO: [Synth 8-638] synthesizing module 'pselect_f' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
	Parameter C_AB bound to: 5 - type: integer 
	Parameter C_AW bound to: 9 - type: integer 
	Parameter C_BAR bound to: 9'b000000000 
	Parameter C_FAMILY bound to: nofamily - type: string 
INFO: [Synth 8-256] done synthesizing module 'pselect_f' (5#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized0' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
	Parameter C_AB bound to: 2 - type: integer 
	Parameter C_AW bound to: 2 - type: integer 
	Parameter C_BAR bound to: 2'b00 
	Parameter C_FAMILY bound to: nofamily - type: string 
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized0' (5#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized1' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
	Parameter C_AB bound to: 2 - type: integer 
	Parameter C_AW bound to: 2 - type: integer 
	Parameter C_BAR bound to: 2'b01 
	Parameter C_FAMILY bound to: nofamily - type: string 
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized1' (5#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized2' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
	Parameter C_AB bound to: 2 - type: integer 
	Parameter C_AW bound to: 2 - type: integer 
	Parameter C_BAR bound to: 2'b10 
	Parameter C_FAMILY bound to: nofamily - type: string 
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized2' (5#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized3' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
	Parameter C_AB bound to: 2 - type: integer 
	Parameter C_AW bound to: 2 - type: integer 
	Parameter C_BAR bound to: 2'b11 
	Parameter C_FAMILY bound to: nofamily - type: string 
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized3' (5#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized4' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
	Parameter C_AB bound to: 1 - type: integer 
	Parameter C_AW bound to: 9 - type: integer 
	Parameter C_BAR bound to: 9'b100000000 
	Parameter C_FAMILY bound to: nofamily - type: string 
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized4' (5#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized5' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
	Parameter C_AB bound to: 4 - type: integer 
	Parameter C_AW bound to: 4 - type: integer 
	Parameter C_BAR bound to: 4'b0000 
	Parameter C_FAMILY bound to: nofamily - type: string 
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized5' (5#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized6' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
	Parameter C_AB bound to: 4 - type: integer 
	Parameter C_AW bound to: 4 - type: integer 
	Parameter C_BAR bound to: 4'b0001 
	Parameter C_FAMILY bound to: nofamily - type: string 
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized6' (5#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized7' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
	Parameter C_AB bound to: 4 - type: integer 
	Parameter C_AW bound to: 4 - type: integer 
	Parameter C_BAR bound to: 4'b0010 
	Parameter C_FAMILY bound to: nofamily - type: string 
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized7' (5#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized8' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
	Parameter C_AB bound to: 4 - type: integer 
	Parameter C_AW bound to: 4 - type: integer 
	Parameter C_BAR bound to: 4'b0011 
	Parameter C_FAMILY bound to: nofamily - type: string 
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized8' (5#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized9' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
	Parameter C_AB bound to: 4 - type: integer 
	Parameter C_AW bound to: 4 - type: integer 
	Parameter C_BAR bound to: 4'b0100 
	Parameter C_FAMILY bound to: nofamily - type: string 
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized9' (5#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized10' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
	Parameter C_AB bound to: 4 - type: integer 
	Parameter C_AW bound to: 4 - type: integer 
	Parameter C_BAR bound to: 4'b0101 
	Parameter C_FAMILY bound to: nofamily - type: string 
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized10' (5#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized11' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
	Parameter C_AB bound to: 4 - type: integer 
	Parameter C_AW bound to: 4 - type: integer 
	Parameter C_BAR bound to: 4'b0110 
	Parameter C_FAMILY bound to: nofamily - type: string 
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized11' (5#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized12' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
	Parameter C_AB bound to: 4 - type: integer 
	Parameter C_AW bound to: 4 - type: integer 
	Parameter C_BAR bound to: 4'b0111 
	Parameter C_FAMILY bound to: nofamily - type: string 
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized12' (5#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized13' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
	Parameter C_AB bound to: 4 - type: integer 
	Parameter C_AW bound to: 4 - type: integer 
	Parameter C_BAR bound to: 4'b1000 
	Parameter C_FAMILY bound to: nofamily - type: string 
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized13' (5#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized14' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
	Parameter C_AB bound to: 4 - type: integer 
	Parameter C_AW bound to: 4 - type: integer 
	Parameter C_BAR bound to: 4'b1001 
	Parameter C_FAMILY bound to: nofamily - type: string 
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized14' (5#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized15' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
	Parameter C_AB bound to: 4 - type: integer 
	Parameter C_AW bound to: 4 - type: integer 
	Parameter C_BAR bound to: 4'b1010 
	Parameter C_FAMILY bound to: nofamily - type: string 
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized15' (5#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized16' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
	Parameter C_AB bound to: 4 - type: integer 
	Parameter C_AW bound to: 4 - type: integer 
	Parameter C_BAR bound to: 4'b1011 
	Parameter C_FAMILY bound to: nofamily - type: string 
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized16' (5#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized17' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
	Parameter C_AB bound to: 4 - type: integer 
	Parameter C_AW bound to: 4 - type: integer 
	Parameter C_BAR bound to: 4'b1100 
	Parameter C_FAMILY bound to: nofamily - type: string 
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized17' (5#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized18' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
	Parameter C_AB bound to: 4 - type: integer 
	Parameter C_AW bound to: 4 - type: integer 
	Parameter C_BAR bound to: 4'b1101 
	Parameter C_FAMILY bound to: nofamily - type: string 
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized18' (5#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized19' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
	Parameter C_AB bound to: 4 - type: integer 
	Parameter C_AW bound to: 4 - type: integer 
	Parameter C_BAR bound to: 4'b1110 
	Parameter C_FAMILY bound to: nofamily - type: string 
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized19' (5#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized20' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
	Parameter C_AB bound to: 4 - type: integer 
	Parameter C_AW bound to: 4 - type: integer 
	Parameter C_BAR bound to: 4'b1111 
	Parameter C_FAMILY bound to: nofamily - type: string 
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized20' (5#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd:169]
INFO: [Synth 8-256] done synthesizing module 'address_decoder' (6#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/axi_lite_ipif_v2_0/hdl/src/vhdl/address_decoder.vhd:188]
INFO: [Synth 8-226] default block is never used [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/axi_lite_ipif_v2_0/hdl/src/vhdl/slave_attachment.vhd:401]
INFO: [Synth 8-256] done synthesizing module 'slave_attachment' (7#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/axi_lite_ipif_v2_0/hdl/src/vhdl/slave_attachment.vhd:243]
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif' (8#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/axi_lite_ipif_v2_0/hdl/src/vhdl/axi_lite_ipif.vhd:253]
INFO: [Synth 8-638] synthesizing module 'interrupt_control' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/interrupt_control_v3_0/hdl/src/vhdl/interrupt_control.vhd:260]
	Parameter C_NUM_CE bound to: 16 - type: integer 
	Parameter C_NUM_IPIF_IRPT_SRC bound to: 1 - type: integer 
	Parameter C_IP_INTR_MODE_ARRAY bound to: 64'b0000000000000000000000000000010100000000000000000000000000000101 
	Parameter C_INCLUDE_DEV_PENCODER bound to: 0 - type: bool 
	Parameter C_INCLUDE_DEV_ISC bound to: 0 - type: bool 
	Parameter C_IPIF_DWIDTH bound to: 32 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'interrupt_control' (9#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/interrupt_control_v3_0/hdl/src/vhdl/interrupt_control.vhd:260]
INFO: [Synth 8-638] synthesizing module 'GPIO_Core' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/axi_gpio_v2_0/hdl/src/vhdl/gpio_core.vhd:173]
	Parameter C_DW bound to: 32 - type: integer 
	Parameter C_AW bound to: 9 - type: integer 
	Parameter C_GPIO_WIDTH bound to: 32 - type: integer 
	Parameter C_GPIO2_WIDTH bound to: 3 - type: integer 
	Parameter C_MAX_GPIO_WIDTH bound to: 32 - type: integer 
	Parameter C_INTERRUPT_PRESENT bound to: 1 - type: integer 
	Parameter C_DOUT_DEFAULT bound to: 0 - type: integer 
	Parameter C_TRI_DEFAULT bound to: -1 - type: integer 
	Parameter C_IS_DUAL bound to: 1 - type: integer 
	Parameter C_DOUT_DEFAULT_2 bound to: 0 - type: integer 
	Parameter C_TRI_DEFAULT_2 bound to: -1 - type: integer 
	Parameter C_FAMILY bound to: zynq - type: string 
INFO: [Synth 8-226] default block is never used [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/axi_gpio_v2_0/hdl/src/vhdl/gpio_core.vhd:579]
INFO: [Synth 8-638] synthesizing module 'cdc_sync' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/cdc_sync.vhd:104]
	Parameter C_CDC_TYPE bound to: 1 - type: integer 
	Parameter C_RESET_STATE bound to: 0 - type: integer 
	Parameter C_SINGLE_BIT bound to: 0 - type: integer 
	Parameter C_FLOP_INPUT bound to: 0 - type: integer 
	Parameter C_VECTOR_WIDTH bound to: 32 - type: integer 
	Parameter C_MTBF_STAGES bound to: 4 - type: integer 
INFO: [Synth 8-4472] Detected and applied attribute async_reg = true [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/cdc_sync.vhd:385]
INFO: [Synth 8-4472] Detected and applied attribute async_reg = true [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/cdc_sync.vhd:387]
INFO: [Synth 8-4472] Detected and applied attribute async_reg = true [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/cdc_sync.vhd:388]
INFO: [Synth 8-4472] Detected and applied attribute async_reg = true [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/cdc_sync.vhd:389]
INFO: [Synth 8-4472] Detected and applied attribute async_reg = true [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/cdc_sync.vhd:390]
INFO: [Synth 8-4472] Detected and applied attribute async_reg = true [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/cdc_sync.vhd:391]
INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (10#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/cdc_sync.vhd:104]
INFO: [Synth 8-638] synthesizing module 'cdc_sync__parameterized0' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/cdc_sync.vhd:104]
	Parameter C_CDC_TYPE bound to: 1 - type: integer 
	Parameter C_RESET_STATE bound to: 0 - type: integer 
	Parameter C_SINGLE_BIT bound to: 0 - type: integer 
	Parameter C_FLOP_INPUT bound to: 0 - type: integer 
	Parameter C_VECTOR_WIDTH bound to: 3 - type: integer 
	Parameter C_MTBF_STAGES bound to: 4 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'cdc_sync__parameterized0' (10#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/cdc_sync.vhd:104]
INFO: [Synth 8-256] done synthesizing module 'GPIO_Core' (11#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/axi_gpio_v2_0/hdl/src/vhdl/gpio_core.vhd:173]
INFO: [Synth 8-256] done synthesizing module 'axi_gpio__parameterized0' (12#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/axi_gpio_v2_0/hdl/src/vhdl/axi_gpio.vhd:283]
INFO: [Synth 8-256] done synthesizing module 'zynq_system_axi_gpio_0_0' (13#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/synth/zynq_system_axi_gpio_0_0.vhd:86]
INFO: [Synth 8-638] synthesizing module 'zynq_system_processing_system7_0_0' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/synth/zynq_system_processing_system7_0_0.v:57]
INFO: [Synth 8-638] synthesizing module 'processing_system7_v5_3_processing_system7' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:153]
	Parameter C_USE_DEFAULT_ACP_USER_VAL bound to: 0 - type: integer 
	Parameter C_S_AXI_ACP_ARUSER_VAL bound to: 31 - type: integer 
	Parameter C_S_AXI_ACP_AWUSER_VAL bound to: 31 - type: integer 
	Parameter C_M_AXI_GP0_THREAD_ID_WIDTH bound to: 12 - type: integer 
	Parameter C_M_AXI_GP1_THREAD_ID_WIDTH bound to: 12 - type: integer 
	Parameter C_M_AXI_GP0_ENABLE_STATIC_REMAP bound to: 0 - type: integer 
	Parameter C_M_AXI_GP1_ENABLE_STATIC_REMAP bound to: 0 - type: integer 
	Parameter C_M_AXI_GP0_ID_WIDTH bound to: 12 - type: integer 
	Parameter C_M_AXI_GP1_ID_WIDTH bound to: 12 - type: integer 
	Parameter C_S_AXI_GP0_ID_WIDTH bound to: 6 - type: integer 
	Parameter C_S_AXI_GP1_ID_WIDTH bound to: 6 - type: integer 
	Parameter C_S_AXI_HP0_ID_WIDTH bound to: 6 - type: integer 
	Parameter C_S_AXI_HP1_ID_WIDTH bound to: 6 - type: integer 
	Parameter C_S_AXI_HP2_ID_WIDTH bound to: 6 - type: integer 
	Parameter C_S_AXI_HP3_ID_WIDTH bound to: 6 - type: integer 
	Parameter C_S_AXI_ACP_ID_WIDTH bound to: 3 - type: integer 
	Parameter C_S_AXI_HP0_DATA_WIDTH bound to: 64 - type: integer 
	Parameter C_S_AXI_HP1_DATA_WIDTH bound to: 64 - type: integer 
	Parameter C_S_AXI_HP2_DATA_WIDTH bound to: 64 - type: integer 
	Parameter C_S_AXI_HP3_DATA_WIDTH bound to: 64 - type: integer 
	Parameter C_INCLUDE_ACP_TRANS_CHECK bound to: 0 - type: integer 
	Parameter C_NUM_F2P_INTR_INPUTS bound to: 1 - type: integer 
	Parameter C_FCLK_CLK0_BUF bound to: true - type: string 
	Parameter C_FCLK_CLK1_BUF bound to: false - type: string 
	Parameter C_FCLK_CLK2_BUF bound to: false - type: string 
	Parameter C_FCLK_CLK3_BUF bound to: false - type: string 
	Parameter C_EMIO_GPIO_WIDTH bound to: 3 - type: integer 
	Parameter C_INCLUDE_TRACE_BUFFER bound to: 0 - type: integer 
	Parameter C_TRACE_BUFFER_FIFO_SIZE bound to: 128 - type: integer 
	Parameter C_TRACE_BUFFER_CLOCK_DELAY bound to: 12 - type: integer 
	Parameter USE_TRACE_DATA_EDGE_DETECTOR bound to: 0 - type: integer 
	Parameter C_PS7_SI_REV bound to: PRODUCTION - type: string 
	Parameter C_EN_EMIO_ENET0 bound to: 0 - type: integer 
	Parameter C_EN_EMIO_ENET1 bound to: 0 - type: integer 
	Parameter C_EN_EMIO_TRACE bound to: 0 - type: integer 
	Parameter C_DQ_WIDTH bound to: 32 - type: integer 
	Parameter C_DQS_WIDTH bound to: 4 - type: integer 
	Parameter C_DM_WIDTH bound to: 4 - type: integer 
	Parameter C_MIO_PRIMITIVE bound to: 54 - type: integer 
	Parameter C_PACKAGE_NAME bound to: ffg900 - type: string 
INFO: [Synth 8-638] synthesizing module 'BUFG' [C:/Xilinx/Vivado/2013.4/scripts/rt/data/unisim_comp.v:612]
INFO: [Synth 8-256] done synthesizing module 'BUFG' (14#1) [C:/Xilinx/Vivado/2013.4/scripts/rt/data/unisim_comp.v:612]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2171]
INFO: [Synth 8-638] synthesizing module 'BIBUF' [C:/Xilinx/Vivado/2013.4/scripts/rt/data/unisim_comp.v:268]
INFO: [Synth 8-256] done synthesizing module 'BIBUF' (15#1) [C:/Xilinx/Vivado/2013.4/scripts/rt/data/unisim_comp.v:268]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2172]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2173]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2174]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2175]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2176]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2177]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2178]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2179]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2180]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2181]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2182]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2183]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2184]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2189]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2195]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2195]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2195]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2201]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2201]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2201]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2201]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2201]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2201]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2201]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2201]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2201]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2201]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2201]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2201]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2201]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2201]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2201]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2207]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2207]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2207]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2207]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2213]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2213]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2213]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2213]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2213]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2213]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2213]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2213]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2213]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:2213]
INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-638] synthesizing module 'PS7' [C:/Xilinx/Vivado/2013.4/scripts/rt/data/unisim_comp.v:26737]
INFO: [Synth 8-256] done synthesizing module 'PS7' (16#1) [C:/Xilinx/Vivado/2013.4/scripts/rt/data/unisim_comp.v:26737]
WARNING: [Synth 8-3848] Net ENET0_GMII_TX_EN in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:210]
WARNING: [Synth 8-3848] Net ENET0_GMII_TX_ER in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:211]
WARNING: [Synth 8-3848] Net ENET0_GMII_TXD in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:227]
WARNING: [Synth 8-3848] Net ENET1_GMII_TX_EN in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:241]
WARNING: [Synth 8-3848] Net ENET1_GMII_TX_ER in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:242]
WARNING: [Synth 8-3848] Net ENET1_GMII_TXD in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:256]
WARNING: [Synth 8-3848] Net ENET0_GMII_COL_i in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:1033]
WARNING: [Synth 8-3848] Net ENET0_GMII_CRS_i in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:1034]
WARNING: [Synth 8-3848] Net ENET0_GMII_RXD_i in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:1037]
WARNING: [Synth 8-3848] Net ENET0_GMII_RX_DV_i in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:1035]
WARNING: [Synth 8-3848] Net ENET0_GMII_RX_ER_i in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:1036]
WARNING: [Synth 8-3848] Net ENET1_GMII_COL_i in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:1042]
WARNING: [Synth 8-3848] Net ENET1_GMII_CRS_i in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:1043]
WARNING: [Synth 8-3848] Net ENET1_GMII_RXD_i in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:1046]
WARNING: [Synth 8-3848] Net ENET1_GMII_RX_DV_i in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:1044]
WARNING: [Synth 8-3848] Net ENET1_GMII_RX_ER_i in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:1045]
WARNING: [Synth 8-3848] Net FTMD_TRACEIN_ATID_i in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:1055]
WARNING: [Synth 8-3848] Net FTMD_TRACEIN_DATA_i in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:1053]
WARNING: [Synth 8-3848] Net FTMD_TRACEIN_VALID_i in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:1054]
INFO: [Synth 8-256] done synthesizing module 'processing_system7_v5_3_processing_system7' (17#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:153]
WARNING: [Synth 8-350] instance 'inst' of module 'processing_system7_v5_3_processing_system7' requires 673 connections, but only 660 given [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/synth/zynq_system_processing_system7_0_0.v:341]
INFO: [Synth 8-256] done synthesizing module 'zynq_system_processing_system7_0_0' (18#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/synth/zynq_system_processing_system7_0_0.v:57]
WARNING: [Synth 8-350] instance 'processing_system7_0' of module 'zynq_system_processing_system7_0_0' requires 82 connections, but only 72 given [C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/hdl/zynq_system.v:468]
INFO: [Synth 8-638] synthesizing module 'zynq_system_processing_system7_0_axi_periph_1' [C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/hdl/zynq_system.v:615]
INFO: [Synth 8-638] synthesizing module 's00_couplers_imp_156Q4UY' [C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/hdl/zynq_system.v:3]
INFO: [Synth 8-638] synthesizing module 'zynq_system_auto_pc_4' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_4/synth/zynq_system_auto_pc_4.v:57]
INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_axi_protocol_converter' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi_protocol_converter.v:62]
	Parameter C_FAMILY bound to: zynq - type: string 
	Parameter C_M_AXI_PROTOCOL bound to: 2 - type: integer 
	Parameter C_S_AXI_PROTOCOL bound to: 1 - type: integer 
	Parameter C_IGNORE_ID bound to: 0 - type: integer 
	Parameter C_AXI_ID_WIDTH bound to: 12 - type: integer 
	Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer 
	Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer 
	Parameter C_AXI_SUPPORTS_WRITE bound to: 1 - type: integer 
	Parameter C_AXI_SUPPORTS_READ bound to: 1 - type: integer 
	Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer 
	Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_TRANSLATION_MODE bound to: 2 - type: integer 
	Parameter P_AXI4 bound to: 0 - type: integer 
	Parameter P_AXI3 bound to: 1 - type: integer 
	Parameter P_AXILITE bound to: 2 - type: integer 
	Parameter P_AXILITE_SIZE bound to: 3'b010 
	Parameter P_INCR bound to: 2'b01 
	Parameter P_DECERR bound to: 2'b11 
	Parameter P_SLVERR bound to: 2'b10 
	Parameter P_PROTECTION bound to: 1 - type: integer 
	Parameter P_CONVERSION bound to: 2 - type: integer 
INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_b2s' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s.v:39]
	Parameter C_S_AXI_PROTOCOL bound to: 1 - type: integer 
	Parameter C_AXI_ID_WIDTH bound to: 12 - type: integer 
	Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer 
	Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer 
	Parameter C_AXI_SUPPORTS_WRITE bound to: 1 - type: integer 
	Parameter C_AXI_SUPPORTS_READ bound to: 1 - type: integer 
INFO: [Synth 8-638] synthesizing module 'axi_register_slice_v2_1_axi_register_slice' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axi_register_slice.v:64]
	Parameter C_FAMILY bound to: virtex6 - type: string 
	Parameter C_AXI_PROTOCOL bound to: 1 - type: integer 
	Parameter C_AXI_ID_WIDTH bound to: 12 - type: integer 
	Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer 
	Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer 
	Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer 
	Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_REG_CONFIG_AW bound to: 1 - type: integer 
	Parameter C_REG_CONFIG_W bound to: 0 - type: integer 
	Parameter C_REG_CONFIG_B bound to: 1 - type: integer 
	Parameter C_REG_CONFIG_AR bound to: 1 - type: integer 
	Parameter C_REG_CONFIG_R bound to: 1 - type: integer 
	Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 0 - type: integer 
	Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer 
	Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer 
	Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer 
	Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer 
	Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_AWSIZE_WIDTH bound to: 3 - type: integer 
	Parameter G_AXI_AWBURST_INDEX bound to: 38 - type: integer 
	Parameter G_AXI_AWBURST_WIDTH bound to: 2 - type: integer 
	Parameter G_AXI_AWCACHE_INDEX bound to: 40 - type: integer 
	Parameter G_AXI_AWCACHE_WIDTH bound to: 4 - type: integer 
	Parameter G_AXI_AWLEN_INDEX bound to: 44 - type: integer 
	Parameter G_AXI_AWLEN_WIDTH bound to: 4 - type: integer 
	Parameter G_AXI_AWLOCK_INDEX bound to: 48 - type: integer 
	Parameter G_AXI_AWLOCK_WIDTH bound to: 2 - type: integer 
	Parameter G_AXI_AWID_INDEX bound to: 50 - type: integer 
	Parameter G_AXI_AWID_WIDTH bound to: 12 - type: integer 
	Parameter G_AXI_AWQOS_INDEX bound to: 62 - type: integer 
	Parameter G_AXI_AWQOS_WIDTH bound to: 4 - type: integer 
	Parameter G_AXI_AWREGION_INDEX bound to: 66 - type: integer 
	Parameter G_AXI_AWREGION_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWUSER_INDEX bound to: 66 - type: integer 
	Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 66 - type: integer 
	Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer 
	Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer 
	Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer 
	Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer 
	Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_ARSIZE_WIDTH bound to: 3 - type: integer 
	Parameter G_AXI_ARBURST_INDEX bound to: 38 - type: integer 
	Parameter G_AXI_ARBURST_WIDTH bound to: 2 - type: integer 
	Parameter G_AXI_ARCACHE_INDEX bound to: 40 - type: integer 
	Parameter G_AXI_ARCACHE_WIDTH bound to: 4 - type: integer 
	Parameter G_AXI_ARLEN_INDEX bound to: 44 - type: integer 
	Parameter G_AXI_ARLEN_WIDTH bound to: 4 - type: integer 
	Parameter G_AXI_ARLOCK_INDEX bound to: 48 - type: integer 
	Parameter G_AXI_ARLOCK_WIDTH bound to: 2 - type: integer 
	Parameter G_AXI_ARID_INDEX bound to: 50 - type: integer 
	Parameter G_AXI_ARID_WIDTH bound to: 12 - type: integer 
	Parameter G_AXI_ARQOS_INDEX bound to: 62 - type: integer 
	Parameter G_AXI_ARQOS_WIDTH bound to: 4 - type: integer 
	Parameter G_AXI_ARREGION_INDEX bound to: 66 - type: integer 
	Parameter G_AXI_ARREGION_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARUSER_INDEX bound to: 66 - type: integer 
	Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 66 - type: integer 
	Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer 
	Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer 
	Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer 
	Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer 
	Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer 
	Parameter G_AXI_WLAST_WIDTH bound to: 1 - type: integer 
	Parameter G_AXI_WID_INDEX bound to: 37 - type: integer 
	Parameter G_AXI_WID_WIDTH bound to: 12 - type: integer 
	Parameter G_AXI_WUSER_INDEX bound to: 49 - type: integer 
	Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_WPAYLOAD_WIDTH bound to: 49 - type: integer 
	Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer 
	Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer 
	Parameter G_AXI_BID_INDEX bound to: 2 - type: integer 
	Parameter G_AXI_BID_WIDTH bound to: 12 - type: integer 
	Parameter G_AXI_BUSER_INDEX bound to: 14 - type: integer 
	Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_BPAYLOAD_WIDTH bound to: 14 - type: integer 
	Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer 
	Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer 
	Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer 
	Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer 
	Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer 
	Parameter G_AXI_RLAST_WIDTH bound to: 1 - type: integer 
	Parameter G_AXI_RID_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_RID_WIDTH bound to: 12 - type: integer 
	Parameter G_AXI_RUSER_INDEX bound to: 47 - type: integer 
	Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_RPAYLOAD_WIDTH bound to: 47 - type: integer 
INFO: [Synth 8-638] synthesizing module 'axi_infrastructure_v1_1_axi2vector' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_infrastructure_v1_1/hdl/verilog/axi_infrastructure_v1_1_axi2vector.v:60]
	Parameter C_AXI_PROTOCOL bound to: 1 - type: integer 
	Parameter C_AXI_ID_WIDTH bound to: 12 - type: integer 
	Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer 
	Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer 
	Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer 
	Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 0 - type: integer 
	Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AWPAYLOAD_WIDTH bound to: 66 - type: integer 
	Parameter C_WPAYLOAD_WIDTH bound to: 49 - type: integer 
	Parameter C_BPAYLOAD_WIDTH bound to: 14 - type: integer 
	Parameter C_ARPAYLOAD_WIDTH bound to: 66 - type: integer 
	Parameter C_RPAYLOAD_WIDTH bound to: 47 - type: integer 
	Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer 
	Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer 
	Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer 
	Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer 
	Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_AWSIZE_WIDTH bound to: 3 - type: integer 
	Parameter G_AXI_AWBURST_INDEX bound to: 38 - type: integer 
	Parameter G_AXI_AWBURST_WIDTH bound to: 2 - type: integer 
	Parameter G_AXI_AWCACHE_INDEX bound to: 40 - type: integer 
	Parameter G_AXI_AWCACHE_WIDTH bound to: 4 - type: integer 
	Parameter G_AXI_AWLEN_INDEX bound to: 44 - type: integer 
	Parameter G_AXI_AWLEN_WIDTH bound to: 4 - type: integer 
	Parameter G_AXI_AWLOCK_INDEX bound to: 48 - type: integer 
	Parameter G_AXI_AWLOCK_WIDTH bound to: 2 - type: integer 
	Parameter G_AXI_AWID_INDEX bound to: 50 - type: integer 
	Parameter G_AXI_AWID_WIDTH bound to: 12 - type: integer 
	Parameter G_AXI_AWQOS_INDEX bound to: 62 - type: integer 
	Parameter G_AXI_AWQOS_WIDTH bound to: 4 - type: integer 
	Parameter G_AXI_AWREGION_INDEX bound to: 66 - type: integer 
	Parameter G_AXI_AWREGION_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWUSER_INDEX bound to: 66 - type: integer 
	Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 66 - type: integer 
	Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer 
	Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer 
	Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer 
	Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer 
	Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_ARSIZE_WIDTH bound to: 3 - type: integer 
	Parameter G_AXI_ARBURST_INDEX bound to: 38 - type: integer 
	Parameter G_AXI_ARBURST_WIDTH bound to: 2 - type: integer 
	Parameter G_AXI_ARCACHE_INDEX bound to: 40 - type: integer 
	Parameter G_AXI_ARCACHE_WIDTH bound to: 4 - type: integer 
	Parameter G_AXI_ARLEN_INDEX bound to: 44 - type: integer 
	Parameter G_AXI_ARLEN_WIDTH bound to: 4 - type: integer 
	Parameter G_AXI_ARLOCK_INDEX bound to: 48 - type: integer 
	Parameter G_AXI_ARLOCK_WIDTH bound to: 2 - type: integer 
	Parameter G_AXI_ARID_INDEX bound to: 50 - type: integer 
	Parameter G_AXI_ARID_WIDTH bound to: 12 - type: integer 
	Parameter G_AXI_ARQOS_INDEX bound to: 62 - type: integer 
	Parameter G_AXI_ARQOS_WIDTH bound to: 4 - type: integer 
	Parameter G_AXI_ARREGION_INDEX bound to: 66 - type: integer 
	Parameter G_AXI_ARREGION_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARUSER_INDEX bound to: 66 - type: integer 
	Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 66 - type: integer 
	Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer 
	Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer 
	Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer 
	Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer 
	Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer 
	Parameter G_AXI_WLAST_WIDTH bound to: 1 - type: integer 
	Parameter G_AXI_WID_INDEX bound to: 37 - type: integer 
	Parameter G_AXI_WID_WIDTH bound to: 12 - type: integer 
	Parameter G_AXI_WUSER_INDEX bound to: 49 - type: integer 
	Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_WPAYLOAD_WIDTH bound to: 49 - type: integer 
	Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer 
	Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer 
	Parameter G_AXI_BID_INDEX bound to: 2 - type: integer 
	Parameter G_AXI_BID_WIDTH bound to: 12 - type: integer 
	Parameter G_AXI_BUSER_INDEX bound to: 14 - type: integer 
	Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_BPAYLOAD_WIDTH bound to: 14 - type: integer 
	Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer 
	Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer 
	Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer 
	Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer 
	Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer 
	Parameter G_AXI_RLAST_WIDTH bound to: 1 - type: integer 
	Parameter G_AXI_RID_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_RID_WIDTH bound to: 12 - type: integer 
	Parameter G_AXI_RUSER_INDEX bound to: 47 - type: integer 
	Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_RPAYLOAD_WIDTH bound to: 47 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'axi_infrastructure_v1_1_axi2vector' (19#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_infrastructure_v1_1/hdl/verilog/axi_infrastructure_v1_1_axi2vector.v:60]
INFO: [Synth 8-638] synthesizing module 'axi_register_slice_v2_1_axic_register_slice' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62]
	Parameter C_FAMILY bound to: virtex6 - type: string 
	Parameter C_DATA_WIDTH bound to: 66 - type: integer 
	Parameter C_REG_CONFIG bound to: 1 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'axi_register_slice_v2_1_axic_register_slice' (20#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62]
INFO: [Synth 8-638] synthesizing module 'axi_register_slice_v2_1_axic_register_slice__parameterized0' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62]
	Parameter C_FAMILY bound to: virtex6 - type: string 
	Parameter C_DATA_WIDTH bound to: 49 - type: integer 
	Parameter C_REG_CONFIG bound to: 0 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'axi_register_slice_v2_1_axic_register_slice__parameterized0' (20#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62]
INFO: [Synth 8-638] synthesizing module 'axi_register_slice_v2_1_axic_register_slice__parameterized1' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62]
	Parameter C_FAMILY bound to: virtex6 - type: string 
	Parameter C_DATA_WIDTH bound to: 14 - type: integer 
	Parameter C_REG_CONFIG bound to: 1 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'axi_register_slice_v2_1_axic_register_slice__parameterized1' (20#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62]
INFO: [Synth 8-638] synthesizing module 'axi_register_slice_v2_1_axic_register_slice__parameterized2' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62]
	Parameter C_FAMILY bound to: virtex6 - type: string 
	Parameter C_DATA_WIDTH bound to: 47 - type: integer 
	Parameter C_REG_CONFIG bound to: 1 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'axi_register_slice_v2_1_axic_register_slice__parameterized2' (20#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62]
INFO: [Synth 8-638] synthesizing module 'axi_infrastructure_v1_1_vector2axi' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_infrastructure_v1_1/hdl/verilog/axi_infrastructure_v1_1_vector2axi.v:60]
	Parameter C_AXI_PROTOCOL bound to: 1 - type: integer 
	Parameter C_AXI_ID_WIDTH bound to: 12 - type: integer 
	Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer 
	Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer 
	Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer 
	Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 0 - type: integer 
	Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AWPAYLOAD_WIDTH bound to: 66 - type: integer 
	Parameter C_WPAYLOAD_WIDTH bound to: 49 - type: integer 
	Parameter C_BPAYLOAD_WIDTH bound to: 14 - type: integer 
	Parameter C_ARPAYLOAD_WIDTH bound to: 66 - type: integer 
	Parameter C_RPAYLOAD_WIDTH bound to: 47 - type: integer 
	Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer 
	Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer 
	Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer 
	Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer 
	Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_AWSIZE_WIDTH bound to: 3 - type: integer 
	Parameter G_AXI_AWBURST_INDEX bound to: 38 - type: integer 
	Parameter G_AXI_AWBURST_WIDTH bound to: 2 - type: integer 
	Parameter G_AXI_AWCACHE_INDEX bound to: 40 - type: integer 
	Parameter G_AXI_AWCACHE_WIDTH bound to: 4 - type: integer 
	Parameter G_AXI_AWLEN_INDEX bound to: 44 - type: integer 
	Parameter G_AXI_AWLEN_WIDTH bound to: 4 - type: integer 
	Parameter G_AXI_AWLOCK_INDEX bound to: 48 - type: integer 
	Parameter G_AXI_AWLOCK_WIDTH bound to: 2 - type: integer 
	Parameter G_AXI_AWID_INDEX bound to: 50 - type: integer 
	Parameter G_AXI_AWID_WIDTH bound to: 12 - type: integer 
	Parameter G_AXI_AWQOS_INDEX bound to: 62 - type: integer 
	Parameter G_AXI_AWQOS_WIDTH bound to: 4 - type: integer 
	Parameter G_AXI_AWREGION_INDEX bound to: 66 - type: integer 
	Parameter G_AXI_AWREGION_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWUSER_INDEX bound to: 66 - type: integer 
	Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 66 - type: integer 
	Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer 
	Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer 
	Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer 
	Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer 
	Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_ARSIZE_WIDTH bound to: 3 - type: integer 
	Parameter G_AXI_ARBURST_INDEX bound to: 38 - type: integer 
	Parameter G_AXI_ARBURST_WIDTH bound to: 2 - type: integer 
	Parameter G_AXI_ARCACHE_INDEX bound to: 40 - type: integer 
	Parameter G_AXI_ARCACHE_WIDTH bound to: 4 - type: integer 
	Parameter G_AXI_ARLEN_INDEX bound to: 44 - type: integer 
	Parameter G_AXI_ARLEN_WIDTH bound to: 4 - type: integer 
	Parameter G_AXI_ARLOCK_INDEX bound to: 48 - type: integer 
	Parameter G_AXI_ARLOCK_WIDTH bound to: 2 - type: integer 
	Parameter G_AXI_ARID_INDEX bound to: 50 - type: integer 
	Parameter G_AXI_ARID_WIDTH bound to: 12 - type: integer 
	Parameter G_AXI_ARQOS_INDEX bound to: 62 - type: integer 
	Parameter G_AXI_ARQOS_WIDTH bound to: 4 - type: integer 
	Parameter G_AXI_ARREGION_INDEX bound to: 66 - type: integer 
	Parameter G_AXI_ARREGION_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARUSER_INDEX bound to: 66 - type: integer 
	Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 66 - type: integer 
	Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer 
	Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer 
	Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer 
	Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer 
	Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer 
	Parameter G_AXI_WLAST_WIDTH bound to: 1 - type: integer 
	Parameter G_AXI_WID_INDEX bound to: 37 - type: integer 
	Parameter G_AXI_WID_WIDTH bound to: 12 - type: integer 
	Parameter G_AXI_WUSER_INDEX bound to: 49 - type: integer 
	Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_WPAYLOAD_WIDTH bound to: 49 - type: integer 
	Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer 
	Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer 
	Parameter G_AXI_BID_INDEX bound to: 2 - type: integer 
	Parameter G_AXI_BID_WIDTH bound to: 12 - type: integer 
	Parameter G_AXI_BUSER_INDEX bound to: 14 - type: integer 
	Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_BPAYLOAD_WIDTH bound to: 14 - type: integer 
	Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer 
	Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer 
	Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer 
	Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer 
	Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer 
	Parameter G_AXI_RLAST_WIDTH bound to: 1 - type: integer 
	Parameter G_AXI_RID_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_RID_WIDTH bound to: 12 - type: integer 
	Parameter G_AXI_RUSER_INDEX bound to: 47 - type: integer 
	Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_RPAYLOAD_WIDTH bound to: 47 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'axi_infrastructure_v1_1_vector2axi' (21#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_infrastructure_v1_1/hdl/verilog/axi_infrastructure_v1_1_vector2axi.v:60]
INFO: [Synth 8-256] done synthesizing module 'axi_register_slice_v2_1_axi_register_slice' (22#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axi_register_slice.v:64]
INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_b2s_aw_channel' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_aw_channel.v:5]
	Parameter C_ID_WIDTH bound to: 12 - type: integer 
	Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer 
INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_b2s_cmd_translator' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_cmd_translator.v:17]
	Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer 
	Parameter P_AXBURST_FIXED bound to: 2'b00 
	Parameter P_AXBURST_INCR bound to: 2'b01 
	Parameter P_AXBURST_WRAP bound to: 2'b10 
INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_b2s_incr_cmd' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_incr_cmd.v:11]
	Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer 
	Parameter L_AXI_ADDR_LOW_BIT bound to: 12 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_b2s_incr_cmd' (23#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_incr_cmd.v:11]
INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_b2s_wrap_cmd' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_wrap_cmd.v:11]
	Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer 
	Parameter L_AXI_ADDR_LOW_BIT bound to: 12 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_b2s_wrap_cmd' (24#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_wrap_cmd.v:11]
INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_b2s_cmd_translator' (25#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_cmd_translator.v:17]
INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_b2s_wr_cmd_fsm' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_wr_cmd_fsm.v:10]
	Parameter SM_IDLE bound to: 2'b00 
	Parameter SM_CMD_EN bound to: 2'b01 
	Parameter SM_CMD_ACCEPTED bound to: 2'b10 
	Parameter SM_DONE_WAIT bound to: 2'b11 
INFO: [Synth 8-226] default block is never used [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_wr_cmd_fsm.v:64]
INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_b2s_wr_cmd_fsm' (26#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_wr_cmd_fsm.v:10]
INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_b2s_aw_channel' (27#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_aw_channel.v:5]
INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_b2s_b_channel' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_b_channel.v:10]
	Parameter C_ID_WIDTH bound to: 12 - type: integer 
	Parameter LP_RESP_OKAY bound to: 2'b00 
	Parameter LP_RESP_EXOKAY bound to: 2'b01 
	Parameter LP_RESP_SLVERROR bound to: 2'b10 
	Parameter LP_RESP_DECERR bound to: 2'b11 
	Parameter P_WIDTH bound to: 20 - type: integer 
	Parameter P_DEPTH bound to: 4 - type: integer 
	Parameter P_AWIDTH bound to: 2 - type: integer 
	Parameter P_RWIDTH bound to: 2 - type: integer 
	Parameter P_RDEPTH bound to: 4 - type: integer 
	Parameter P_RAWIDTH bound to: 2 - type: integer 
INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_b2s_simple_fifo' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_simple_fifo.v:9]
	Parameter C_WIDTH bound to: 20 - type: integer 
	Parameter C_AWIDTH bound to: 2 - type: integer 
	Parameter C_DEPTH bound to: 4 - type: integer 
	Parameter C_EMPTY bound to: 2'b11 
	Parameter C_EMPTY_PRE bound to: 2'b00 
	Parameter C_FULL bound to: 2'b10 
	Parameter C_FULL_PRE bound to: 2'b01 
INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_b2s_simple_fifo' (28#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_simple_fifo.v:9]
INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_b2s_simple_fifo__parameterized0' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_simple_fifo.v:9]
	Parameter C_WIDTH bound to: 2 - type: integer 
	Parameter C_AWIDTH bound to: 2 - type: integer 
	Parameter C_DEPTH bound to: 4 - type: integer 
	Parameter C_EMPTY bound to: 2'b11 
	Parameter C_EMPTY_PRE bound to: 2'b00 
	Parameter C_FULL bound to: 2'b10 
	Parameter C_FULL_PRE bound to: 2'b01 
INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_b2s_simple_fifo__parameterized0' (28#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_simple_fifo.v:9]
INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_b2s_b_channel' (29#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_b_channel.v:10]
INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_b2s_ar_channel' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_ar_channel.v:5]
	Parameter C_ID_WIDTH bound to: 12 - type: integer 
	Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer 
INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_b2s_rd_cmd_fsm' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_rd_cmd_fsm.v:10]
	Parameter SM_IDLE bound to: 2'b00 
	Parameter SM_CMD_EN bound to: 2'b01 
	Parameter SM_CMD_ACCEPTED bound to: 2'b10 
	Parameter SM_DONE bound to: 2'b11 
INFO: [Synth 8-226] default block is never used [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_rd_cmd_fsm.v:72]
INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_b2s_rd_cmd_fsm' (30#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_rd_cmd_fsm.v:10]
INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_b2s_ar_channel' (31#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_ar_channel.v:5]
INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_b2s_r_channel' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_r_channel.v:21]
	Parameter C_ID_WIDTH bound to: 12 - type: integer 
	Parameter C_DATA_WIDTH bound to: 32 - type: integer 
	Parameter P_WIDTH bound to: 13 - type: integer 
	Parameter P_DEPTH bound to: 32 - type: integer 
	Parameter P_AWIDTH bound to: 5 - type: integer 
	Parameter P_D_WIDTH bound to: 34 - type: integer 
	Parameter P_D_DEPTH bound to: 32 - type: integer 
	Parameter P_D_AWIDTH bound to: 5 - type: integer 
INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_b2s_simple_fifo__parameterized1' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_simple_fifo.v:9]
	Parameter C_WIDTH bound to: 34 - type: integer 
	Parameter C_AWIDTH bound to: 5 - type: integer 
	Parameter C_DEPTH bound to: 32 - type: integer 
	Parameter C_EMPTY bound to: 5'b11111 
	Parameter C_EMPTY_PRE bound to: 5'b00000 
	Parameter C_FULL bound to: 5'b11110 
	Parameter C_FULL_PRE bound to: 5'b11010 
INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_b2s_simple_fifo__parameterized1' (31#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_simple_fifo.v:9]
INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_b2s_simple_fifo__parameterized2' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_simple_fifo.v:9]
	Parameter C_WIDTH bound to: 13 - type: integer 
	Parameter C_AWIDTH bound to: 5 - type: integer 
	Parameter C_DEPTH bound to: 32 - type: integer 
	Parameter C_EMPTY bound to: 5'b11111 
	Parameter C_EMPTY_PRE bound to: 5'b00000 
	Parameter C_FULL bound to: 5'b11110 
	Parameter C_FULL_PRE bound to: 5'b11010 
INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_b2s_simple_fifo__parameterized2' (31#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_simple_fifo.v:9]
INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_b2s_r_channel' (32#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_r_channel.v:21]
INFO: [Synth 8-638] synthesizing module 'axi_register_slice_v2_1_axi_register_slice__parameterized0' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axi_register_slice.v:64]
	Parameter C_FAMILY bound to: virtex6 - type: string 
	Parameter C_AXI_PROTOCOL bound to: 2 - type: integer 
	Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer 
	Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer 
	Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer 
	Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_REG_CONFIG_AW bound to: 0 - type: integer 
	Parameter C_REG_CONFIG_W bound to: 0 - type: integer 
	Parameter C_REG_CONFIG_B bound to: 0 - type: integer 
	Parameter C_REG_CONFIG_AR bound to: 0 - type: integer 
	Parameter C_REG_CONFIG_R bound to: 0 - type: integer 
	Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 0 - type: integer 
	Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer 
	Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer 
	Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer 
	Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer 
	Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_AWSIZE_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWBURST_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_AWBURST_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWCACHE_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_AWCACHE_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWLEN_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_AWLEN_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWLOCK_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_AWLOCK_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWID_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_AWID_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWQOS_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_AWQOS_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWREGION_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_AWREGION_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWUSER_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 35 - type: integer 
	Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer 
	Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer 
	Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer 
	Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer 
	Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_ARSIZE_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARBURST_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_ARBURST_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARCACHE_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_ARCACHE_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARLEN_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_ARLEN_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARLOCK_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_ARLOCK_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARID_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_ARID_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARQOS_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_ARQOS_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARREGION_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_ARREGION_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARUSER_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 35 - type: integer 
	Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer 
	Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer 
	Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer 
	Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer 
	Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer 
	Parameter G_AXI_WLAST_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_WID_INDEX bound to: 36 - type: integer 
	Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_WUSER_INDEX bound to: 36 - type: integer 
	Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_WPAYLOAD_WIDTH bound to: 36 - type: integer 
	Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer 
	Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer 
	Parameter G_AXI_BID_INDEX bound to: 2 - type: integer 
	Parameter G_AXI_BID_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_BUSER_INDEX bound to: 2 - type: integer 
	Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_BPAYLOAD_WIDTH bound to: 2 - type: integer 
	Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer 
	Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer 
	Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer 
	Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer 
	Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer 
	Parameter G_AXI_RLAST_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_RID_INDEX bound to: 34 - type: integer 
	Parameter G_AXI_RID_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_RUSER_INDEX bound to: 34 - type: integer 
	Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_RPAYLOAD_WIDTH bound to: 34 - type: integer 
INFO: [Synth 8-638] synthesizing module 'axi_infrastructure_v1_1_axi2vector__parameterized0' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_infrastructure_v1_1/hdl/verilog/axi_infrastructure_v1_1_axi2vector.v:60]
	Parameter C_AXI_PROTOCOL bound to: 2 - type: integer 
	Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer 
	Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer 
	Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer 
	Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 0 - type: integer 
	Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AWPAYLOAD_WIDTH bound to: 35 - type: integer 
	Parameter C_WPAYLOAD_WIDTH bound to: 36 - type: integer 
	Parameter C_BPAYLOAD_WIDTH bound to: 2 - type: integer 
	Parameter C_ARPAYLOAD_WIDTH bound to: 35 - type: integer 
	Parameter C_RPAYLOAD_WIDTH bound to: 34 - type: integer 
	Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer 
	Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer 
	Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer 
	Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer 
	Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_AWSIZE_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWBURST_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_AWBURST_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWCACHE_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_AWCACHE_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWLEN_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_AWLEN_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWLOCK_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_AWLOCK_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWID_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_AWID_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWQOS_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_AWQOS_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWREGION_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_AWREGION_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWUSER_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 35 - type: integer 
	Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer 
	Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer 
	Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer 
	Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer 
	Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_ARSIZE_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARBURST_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_ARBURST_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARCACHE_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_ARCACHE_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARLEN_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_ARLEN_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARLOCK_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_ARLOCK_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARID_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_ARID_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARQOS_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_ARQOS_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARREGION_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_ARREGION_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARUSER_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 35 - type: integer 
	Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer 
	Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer 
	Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer 
	Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer 
	Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer 
	Parameter G_AXI_WLAST_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_WID_INDEX bound to: 36 - type: integer 
	Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_WUSER_INDEX bound to: 36 - type: integer 
	Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_WPAYLOAD_WIDTH bound to: 36 - type: integer 
	Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer 
	Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer 
	Parameter G_AXI_BID_INDEX bound to: 2 - type: integer 
	Parameter G_AXI_BID_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_BUSER_INDEX bound to: 2 - type: integer 
	Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_BPAYLOAD_WIDTH bound to: 2 - type: integer 
	Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer 
	Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer 
	Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer 
	Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer 
	Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer 
	Parameter G_AXI_RLAST_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_RID_INDEX bound to: 34 - type: integer 
	Parameter G_AXI_RID_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_RUSER_INDEX bound to: 34 - type: integer 
	Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_RPAYLOAD_WIDTH bound to: 34 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'axi_infrastructure_v1_1_axi2vector__parameterized0' (32#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_infrastructure_v1_1/hdl/verilog/axi_infrastructure_v1_1_axi2vector.v:60]
INFO: [Synth 8-638] synthesizing module 'axi_register_slice_v2_1_axic_register_slice__parameterized3' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62]
	Parameter C_FAMILY bound to: virtex6 - type: string 
	Parameter C_DATA_WIDTH bound to: 35 - type: integer 
	Parameter C_REG_CONFIG bound to: 0 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'axi_register_slice_v2_1_axic_register_slice__parameterized3' (32#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62]
INFO: [Synth 8-638] synthesizing module 'axi_register_slice_v2_1_axic_register_slice__parameterized4' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62]
	Parameter C_FAMILY bound to: virtex6 - type: string 
	Parameter C_DATA_WIDTH bound to: 36 - type: integer 
	Parameter C_REG_CONFIG bound to: 0 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'axi_register_slice_v2_1_axic_register_slice__parameterized4' (32#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62]
INFO: [Synth 8-638] synthesizing module 'axi_register_slice_v2_1_axic_register_slice__parameterized5' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62]
	Parameter C_FAMILY bound to: virtex6 - type: string 
	Parameter C_DATA_WIDTH bound to: 2 - type: integer 
	Parameter C_REG_CONFIG bound to: 0 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'axi_register_slice_v2_1_axic_register_slice__parameterized5' (32#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62]
INFO: [Synth 8-638] synthesizing module 'axi_register_slice_v2_1_axic_register_slice__parameterized6' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62]
	Parameter C_FAMILY bound to: virtex6 - type: string 
	Parameter C_DATA_WIDTH bound to: 34 - type: integer 
	Parameter C_REG_CONFIG bound to: 0 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'axi_register_slice_v2_1_axic_register_slice__parameterized6' (32#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62]
INFO: [Synth 8-638] synthesizing module 'axi_infrastructure_v1_1_vector2axi__parameterized0' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_infrastructure_v1_1/hdl/verilog/axi_infrastructure_v1_1_vector2axi.v:60]
	Parameter C_AXI_PROTOCOL bound to: 2 - type: integer 
	Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer 
	Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer 
	Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer 
	Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 0 - type: integer 
	Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AWPAYLOAD_WIDTH bound to: 35 - type: integer 
	Parameter C_WPAYLOAD_WIDTH bound to: 36 - type: integer 
	Parameter C_BPAYLOAD_WIDTH bound to: 2 - type: integer 
	Parameter C_ARPAYLOAD_WIDTH bound to: 35 - type: integer 
	Parameter C_RPAYLOAD_WIDTH bound to: 34 - type: integer 
	Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer 
	Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer 
	Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer 
	Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer 
	Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_AWSIZE_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWBURST_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_AWBURST_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWCACHE_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_AWCACHE_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWLEN_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_AWLEN_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWLOCK_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_AWLOCK_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWID_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_AWID_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWQOS_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_AWQOS_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWREGION_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_AWREGION_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWUSER_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 35 - type: integer 
	Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer 
	Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer 
	Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer 
	Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer 
	Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_ARSIZE_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARBURST_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_ARBURST_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARCACHE_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_ARCACHE_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARLEN_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_ARLEN_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARLOCK_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_ARLOCK_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARID_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_ARID_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARQOS_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_ARQOS_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARREGION_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_ARREGION_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARUSER_INDEX bound to: 35 - type: integer 
	Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 35 - type: integer 
	Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer 
	Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer 
	Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer 
	Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer 
	Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer 
	Parameter G_AXI_WLAST_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_WID_INDEX bound to: 36 - type: integer 
	Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_WUSER_INDEX bound to: 36 - type: integer 
	Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_WPAYLOAD_WIDTH bound to: 36 - type: integer 
	Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer 
	Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer 
	Parameter G_AXI_BID_INDEX bound to: 2 - type: integer 
	Parameter G_AXI_BID_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_BUSER_INDEX bound to: 2 - type: integer 
	Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_BPAYLOAD_WIDTH bound to: 2 - type: integer 
	Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer 
	Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer 
	Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer 
	Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer 
	Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer 
	Parameter G_AXI_RLAST_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_RID_INDEX bound to: 34 - type: integer 
	Parameter G_AXI_RID_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_RUSER_INDEX bound to: 34 - type: integer 
	Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer 
	Parameter G_AXI_RPAYLOAD_WIDTH bound to: 34 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'axi_infrastructure_v1_1_vector2axi__parameterized0' (32#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_infrastructure_v1_1/hdl/verilog/axi_infrastructure_v1_1_vector2axi.v:60]
INFO: [Synth 8-256] done synthesizing module 'axi_register_slice_v2_1_axi_register_slice__parameterized0' (32#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axi_register_slice.v:64]
INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_b2s' (33#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s.v:39]
INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_axi_protocol_converter' (34#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi_protocol_converter.v:62]
INFO: [Synth 8-256] done synthesizing module 'zynq_system_auto_pc_4' (35#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_4/synth/zynq_system_auto_pc_4.v:57]
WARNING: [Synth 8-350] instance 'auto_pc' of module 'zynq_system_auto_pc_4' requires 59 connections, but only 57 given [C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/hdl/zynq_system.v:238]
INFO: [Synth 8-256] done synthesizing module 's00_couplers_imp_156Q4UY' (36#1) [C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/hdl/zynq_system.v:3]
INFO: [Synth 8-256] done synthesizing module 'zynq_system_processing_system7_0_axi_periph_1' (37#1) [C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/hdl/zynq_system.v:615]
INFO: [Synth 8-638] synthesizing module 'zynq_system_rst_processing_system7_0_50M_0' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_rst_processing_system7_0_50M_0/synth/zynq_system_rst_processing_system7_0_50M_0.vhd:71]
	Parameter C_FAMILY bound to: zynq - type: string 
	Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer 
	Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer 
	Parameter C_EXT_RESET_HIGH bound to: 1'b0 
	Parameter C_AUX_RESET_HIGH bound to: 1'b0 
	Parameter C_NUM_BUS_RST bound to: 1 - type: integer 
	Parameter C_NUM_PERP_RST bound to: 1 - type: integer 
	Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer 
	Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer 
INFO: [Synth 8-3491] module 'proc_sys_reset' declared at 'c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_rst_processing_system7_0_50M_0/proc_sys_reset_v5_0/hdl/src/vhdl/proc_sys_reset.vhd:140' bound to instance 'U0' of component 'proc_sys_reset' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_rst_processing_system7_0_50M_0/synth/zynq_system_rst_processing_system7_0_50M_0.vhd:117]
INFO: [Synth 8-638] synthesizing module 'proc_sys_reset__parameterized0' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_rst_processing_system7_0_50M_0/proc_sys_reset_v5_0/hdl/src/vhdl/proc_sys_reset.vhd:199]
	Parameter C_FAMILY bound to: zynq - type: string 
	Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer 
	Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer 
	Parameter C_EXT_RESET_HIGH bound to: 1'b0 
	Parameter C_AUX_RESET_HIGH bound to: 1'b0 
	Parameter C_NUM_BUS_RST bound to: 1 - type: integer 
	Parameter C_NUM_PERP_RST bound to: 1 - type: integer 
	Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer 
	Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer 
INFO: [Synth 8-638] synthesizing module 'lpf' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_rst_processing_system7_0_50M_0/proc_sys_reset_v5_0/hdl/src/vhdl/lpf.vhd:136]
	Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer 
	Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer 
	Parameter C_EXT_RESET_HIGH bound to: 1'b0 
	Parameter C_AUX_RESET_HIGH bound to: 1'b0 
INFO: [Synth 8-3491] module 'SRL16' declared at 'C:/Xilinx/Vivado/2013.4/scripts/rt/data/unisim_comp.v:34784' bound to instance 'POR_SRL_I' of component 'SRL16' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_rst_processing_system7_0_50M_0/proc_sys_reset_v5_0/hdl/src/vhdl/lpf.vhd:188]
INFO: [Synth 8-638] synthesizing module 'SRL16' [C:/Xilinx/Vivado/2013.4/scripts/rt/data/unisim_comp.v:34784]
	Parameter INIT bound to: 16'b0000000000000000 
INFO: [Synth 8-256] done synthesizing module 'SRL16' (38#1) [C:/Xilinx/Vivado/2013.4/scripts/rt/data/unisim_comp.v:34784]
INFO: [Synth 8-256] done synthesizing module 'lpf' (39#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_rst_processing_system7_0_50M_0/proc_sys_reset_v5_0/hdl/src/vhdl/lpf.vhd:136]
INFO: [Synth 8-638] synthesizing module 'sequence' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_rst_processing_system7_0_50M_0/proc_sys_reset_v5_0/hdl/src/vhdl/sequence.vhd:146]
INFO: [Synth 8-638] synthesizing module 'upcnt_n' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_rst_processing_system7_0_50M_0/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd:126]
	Parameter C_SIZE bound to: 6 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'upcnt_n' (40#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_rst_processing_system7_0_50M_0/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd:126]
INFO: [Synth 8-256] done synthesizing module 'sequence' (41#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_rst_processing_system7_0_50M_0/proc_sys_reset_v5_0/hdl/src/vhdl/sequence.vhd:146]
INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset__parameterized0' (42#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_rst_processing_system7_0_50M_0/proc_sys_reset_v5_0/hdl/src/vhdl/proc_sys_reset.vhd:199]
INFO: [Synth 8-256] done synthesizing module 'zynq_system_rst_processing_system7_0_50M_0' (43#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_rst_processing_system7_0_50M_0/synth/zynq_system_rst_processing_system7_0_50M_0.vhd:71]
WARNING: [Synth 8-350] instance 'rst_processing_system7_0_50M' of module 'zynq_system_rst_processing_system7_0_50M_0' requires 10 connections, but only 7 given [C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/hdl/zynq_system.v:603]
INFO: [Synth 8-638] synthesizing module 'zynq_system_xlconstant_0_0' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_xlconstant_0_0/synth/zynq_system_xlconstant_0_0.v:57]
INFO: [Synth 8-638] synthesizing module 'xlconstant' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_xlconstant_0_0/work/xlconstant.v:23]
	Parameter CONST_VAL bound to: 0 - type: integer 
	Parameter CONST_WIDTH bound to: 1 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'xlconstant' (44#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_xlconstant_0_0/work/xlconstant.v:23]
INFO: [Synth 8-256] done synthesizing module 'zynq_system_xlconstant_0_0' (45#1) [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_xlconstant_0_0/synth/zynq_system_xlconstant_0_0.v:57]
INFO: [Synth 8-256] done synthesizing module 'zynq_system' (46#1) [C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/hdl/zynq_system.v:299]
INFO: [Synth 8-256] done synthesizing module 'zynq_system_wrapper' (47#1) [C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/hdl/zynq_system_wrapper.v:3]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:01:40 ; elapsed = 00:01:48 . Memory (MB): peak = 356.059 ; gain = 200.508
---------------------------------------------------------------------------------

---------------------------------------------------------------------------------
Start RTL Optimization
---------------------------------------------------------------------------------

Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
Loading clock regions from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/zynq/zynq/xc7z100/ClockRegion.xml
Loading clock buffers from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/zynq/zynq/xc7z100/ClockBuffers.xml
Loading clock placement rules from C:/Xilinx/Vivado/2013.4/data/parts/xilinx/zynq/ClockPlacerRules.xml
Loading package pin functions from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/zynq/PinFunctions.xml...
Loading package from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/zynq/zynq/xc7z100/ffg900/Package.xml
Loading io standards from C:/Xilinx/Vivado/2013.4/data\./parts/xilinx/zynq/IOStandards.xml

Processing XDC Constraints
Parsing XDC File [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/zynq_system_processing_system7_0_0.xdc] for cell 'zynq_system_i/processing_system7_0/inst'
Finished Parsing XDC File [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/zynq_system_processing_system7_0_0.xdc] for cell 'zynq_system_i/processing_system7_0/inst'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/zynq_system_processing_system7_0_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.runs/synth_1/.Xil/zynq_system_wrapper_propImpl.xdc].
Resolution: To avoid this message, exclude constraints listed in [C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.runs/synth_1/.Xil/zynq_system_wrapper_propImpl.xdc] from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/zynq_system_axi_gpio_0_0.xdc] for cell 'zynq_system_i/axi_gpio_0/U0'
Finished Parsing XDC File [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/zynq_system_axi_gpio_0_0.xdc] for cell 'zynq_system_i/axi_gpio_0/U0'
Parsing XDC File [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/zynq_system_axi_gpio_0_0_board.xdc] for cell 'zynq_system_i/axi_gpio_0/U0'
Finished Parsing XDC File [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/zynq_system_axi_gpio_0_0_board.xdc] for cell 'zynq_system_i/axi_gpio_0/U0'
Parsing XDC File [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_rst_processing_system7_0_50M_0/zynq_system_rst_processing_system7_0_50M_0.xdc] for cell 'zynq_system_i/rst_processing_system7_0_50M/U0'
Finished Parsing XDC File [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_rst_processing_system7_0_50M_0/zynq_system_rst_processing_system7_0_50M_0.xdc] for cell 'zynq_system_i/rst_processing_system7_0_50M/U0'
Parsing XDC File [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_rst_processing_system7_0_50M_0/zynq_system_rst_processing_system7_0_50M_0_board.xdc] for cell 'zynq_system_i/rst_processing_system7_0_50M/U0'
Finished Parsing XDC File [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_rst_processing_system7_0_50M_0/zynq_system_rst_processing_system7_0_50M_0_board.xdc] for cell 'zynq_system_i/rst_processing_system7_0_50M/U0'
Parsing XDC File [C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/constrs_1/imports/new/design_1.xdc]
Finished Parsing XDC File [C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/constrs_1/imports/new/design_1.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/constrs_1/imports/new/design_1.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.runs/synth_1/.Xil/zynq_system_wrapper_propImpl.xdc].
Resolution: To avoid this message, exclude constraints listed in [C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.runs/synth_1/.Xil/zynq_system_wrapper_propImpl.xdc] from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.runs/synth_1/dont_touch.xdc]
Finished Parsing XDC File [C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.runs/synth_1/dont_touch.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.runs/synth_1/dont_touch.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.runs/synth_1/.Xil/zynq_system_wrapper_propImpl.xdc].
Resolution: To avoid this message, exclude constraints listed in [C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.runs/synth_1/.Xil/zynq_system_wrapper_propImpl.xdc] from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints

INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: 
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 1 instances were transformed.
  SRL16 => SRL16E: 1 instances


---------------------------------------------------------------------------------
Start RTL Optimization
---------------------------------------------------------------------------------

---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property DONT_TOUCH = true. (constraint file  C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.runs/synth_1/dont_touch.xdc, line 7).
Applied set_property DONT_TOUCH = true. (constraint file  C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.runs/synth_1/dont_touch.xdc, line 10).
Applied set_property DONT_TOUCH = true. (constraint file  C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.runs/synth_1/dont_touch.xdc, line 13).
Applied set_property DONT_TOUCH = true. (constraint file  C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.runs/synth_1/dont_touch.xdc, line 16).
Applied set_property DONT_TOUCH = true. (constraint file  C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.runs/synth_1/dont_touch.xdc, line 19).
Applied set_property DONT_TOUCH = true. (constraint file  C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.runs/synth_1/dont_touch.xdc, line 22).
Applied set_property DONT_TOUCH = true. (constraint file  C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.runs/synth_1/dont_touch.xdc, line 25).
Applied set_property DONT_TOUCH = true. (constraint file  C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.runs/synth_1/dont_touch.xdc, line 28).
Applied set_property DONT_TOUCH = true. (constraint file  C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.runs/synth_1/dont_touch.xdc, line 31).
Applied set_property DONT_TOUCH = true. (constraint file  C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.runs/synth_1/dont_touch.xdc, line 36).
Applied set_property DONT_TOUCH = true. (constraint file  C:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.runs/synth_1/dont_touch.xdc, line 42).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:01:54 ; elapsed = 00:02:03 . Memory (MB): peak = 629.082 ; gain = 473.531
---------------------------------------------------------------------------------

---------------------------------------------------------------------------------
Finished RTL Optimization : Time (s): cpu = 00:01:54 ; elapsed = 00:02:03 . Memory (MB): peak = 629.082 ; gain = 473.531
---------------------------------------------------------------------------------

INFO: [Synth 8-4471] merging register 'seq_cnt_en_reg' into 'from_sys_reg' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_rst_processing_system7_0_50M_0/proc_sys_reset_v5_0/hdl/src/vhdl/sequence.vhd:222]
WARNING: [Synth 8-3848] Net ENET0_GMII_TX_EN in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:210]
WARNING: [Synth 8-3848] Net ENET0_GMII_TX_ER in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:211]
WARNING: [Synth 8-3848] Net ENET0_GMII_TXD in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:227]
WARNING: [Synth 8-3848] Net ENET1_GMII_TX_EN in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:241]
WARNING: [Synth 8-3848] Net ENET1_GMII_TX_ER in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:242]
WARNING: [Synth 8-3848] Net ENET1_GMII_TXD in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:256]
WARNING: [Synth 8-3848] Net ENET0_GMII_COL_i in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:1033]
WARNING: [Synth 8-3848] Net ENET0_GMII_CRS_i in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:1034]
WARNING: [Synth 8-3848] Net ENET0_GMII_RXD_i in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:1037]
WARNING: [Synth 8-3848] Net ENET0_GMII_RX_DV_i in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:1035]
WARNING: [Synth 8-3848] Net ENET0_GMII_RX_ER_i in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:1036]
WARNING: [Synth 8-3848] Net ENET1_GMII_COL_i in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:1042]
WARNING: [Synth 8-3848] Net ENET1_GMII_CRS_i in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:1043]
WARNING: [Synth 8-3848] Net ENET1_GMII_RXD_i in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:1046]
WARNING: [Synth 8-3848] Net ENET1_GMII_RX_DV_i in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:1044]
WARNING: [Synth 8-3848] Net ENET1_GMII_RX_ER_i in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:1045]
WARNING: [Synth 8-3848] Net FTMD_TRACEIN_ATID_i in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:1055]
WARNING: [Synth 8-3848] Net FTMD_TRACEIN_DATA_i in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:1053]
WARNING: [Synth 8-3848] Net FTMD_TRACEIN_VALID_i in module/entity processing_system7_v5_3_processing_system7 does not have driver. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_processing_system7.v:1054]

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+

---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7z100ffg900-2
Part Resources:
DSPs: 2020 (col length:140)
BRAMs: 1510 (col length: RAMB18 140 RAMB36 70)
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:02:04 ; elapsed = 00:02:13 . Memory (MB): peak = 678.438 ; gain = 522.887
---------------------------------------------------------------------------------


---------------------------------------------------------------------------------
Start RTL Component Statistics 
---------------------------------------------------------------------------------
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     12 Bit       Adders := 6     
	   2 Input     10 Bit       Adders := 2     
	   2 Input      9 Bit       Adders := 2     
	   2 Input      8 Bit       Adders := 1     
	   2 Input      6 Bit       Adders := 3     
	   2 Input      5 Bit       Adders := 4     
	   2 Input      4 Bit       Adders := 5     
	   2 Input      2 Bit       Adders := 2     
+---XORs : 
	   2 Input     32 Bit         XORs := 1     
	   2 Input      3 Bit         XORs := 1     
	   2 Input      1 Bit         XORs := 2     
+---Registers : 
	               66 Bit    Registers := 4     
	               47 Bit    Registers := 2     
	               32 Bit    Registers := 10    
	               14 Bit    Registers := 2     
	               12 Bit    Registers := 7     
	                9 Bit    Registers := 2     
	                8 Bit    Registers := 2     
	                6 Bit    Registers := 1     
	                5 Bit    Registers := 4     
	                4 Bit    Registers := 7     
	                3 Bit    Registers := 11    
	                2 Bit    Registers := 13    
	                1 Bit    Registers := 132   
+---Muxes : 
	   2 Input     47 Bit        Muxes := 1     
	   3 Input     32 Bit        Muxes := 2     
	   2 Input     32 Bit        Muxes := 13    
	   2 Input     14 Bit        Muxes := 1     
	   2 Input     12 Bit        Muxes := 4     
	   2 Input      9 Bit        Muxes := 5     
	   2 Input      6 Bit        Muxes := 1     
	   2 Input      5 Bit        Muxes := 4     
	   2 Input      4 Bit        Muxes := 8     
	   2 Input      3 Bit        Muxes := 5     
	   4 Input      2 Bit        Muxes := 5     
	   2 Input      2 Bit        Muxes := 11    
	   2 Input      1 Bit        Muxes := 63    

---------------------------------------------------------------------------------
Finished RTL Component Statistics 
---------------------------------------------------------------------------------

---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics 
---------------------------------------------------------------------------------
Hierarchical RTL Component report 
Module zynq_system_wrapper 
Detailed RTL Component Info : 
Module PWM_Controller 
Detailed RTL Component Info : 
Module zynq_system_PWM_Controller_0_0 
Detailed RTL Component Info : 
Module pselect_f 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module pselect_f__parameterized4 
Detailed RTL Component Info : 
Module pselect_f__parameterized0 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module pselect_f__parameterized1 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module pselect_f__parameterized2 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module pselect_f__parameterized3 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module pselect_f__parameterized5 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module pselect_f__parameterized6 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module pselect_f__parameterized7 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module pselect_f__parameterized8 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module pselect_f__parameterized9 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module pselect_f__parameterized10 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module pselect_f__parameterized11 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module pselect_f__parameterized12 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module pselect_f__parameterized13 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module pselect_f__parameterized14 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module pselect_f__parameterized15 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module pselect_f__parameterized16 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module pselect_f__parameterized17 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module pselect_f__parameterized18 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module pselect_f__parameterized19 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module pselect_f__parameterized20 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module address_decoder 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 23    
Module slave_attachment 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      4 Bit       Adders := 1     
+---Registers : 
	               32 Bit    Registers := 1     
	                4 Bit    Registers := 1     
	                2 Bit    Registers := 3     
	                1 Bit    Registers := 3     
+---Muxes : 
	   2 Input      9 Bit        Muxes := 1     
	   4 Input      2 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 3     
	   2 Input      1 Bit        Muxes := 9     
Module axi_lite_ipif 
Detailed RTL Component Info : 
Module cdc_sync 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 4     
Module cdc_sync__parameterized0 
Detailed RTL Component Info : 
+---Registers : 
	                3 Bit    Registers := 4     
Module GPIO_Core 
Detailed RTL Component Info : 
+---XORs : 
	   2 Input     32 Bit         XORs := 1     
	   2 Input      3 Bit         XORs := 1     
+---Registers : 
	               32 Bit    Registers := 4     
	                3 Bit    Registers := 4     
	                1 Bit    Registers := 36    
+---Muxes : 
	   2 Input     32 Bit        Muxes := 5     
	   2 Input      3 Bit        Muxes := 5     
	   4 Input      2 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 4     
Module interrupt_control 
Detailed RTL Component Info : 
+---XORs : 
	   2 Input      1 Bit         XORs := 2     
+---Registers : 
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 11    
+---Muxes : 
	   2 Input     32 Bit        Muxes := 3     
	   2 Input      1 Bit        Muxes := 4     
Module axi_gpio__parameterized0 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 1     
	                1 Bit    Registers := 8     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
Module zynq_system_axi_gpio_0_0 
Detailed RTL Component Info : 
Module processing_system7_v5_3_processing_system7 
Detailed RTL Component Info : 
Module zynq_system_processing_system7_0_0 
Detailed RTL Component Info : 
Module axi_infrastructure_v1_1_axi2vector 
Detailed RTL Component Info : 
Module axi_register_slice_v2_1_axic_register_slice 
Detailed RTL Component Info : 
+---Registers : 
	               66 Bit    Registers := 2     
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 2     
Module axi_register_slice_v2_1_axic_register_slice__parameterized0 
Detailed RTL Component Info : 
Module axi_register_slice_v2_1_axic_register_slice__parameterized1 
Detailed RTL Component Info : 
+---Registers : 
	               14 Bit    Registers := 2     
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input     14 Bit        Muxes := 1     
Module axi_register_slice_v2_1_axic_register_slice__parameterized2 
Detailed RTL Component Info : 
+---Registers : 
	               47 Bit    Registers := 2     
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input     47 Bit        Muxes := 1     
Module axi_infrastructure_v1_1_vector2axi 
Detailed RTL Component Info : 
Module axi_register_slice_v2_1_axi_register_slice 
Detailed RTL Component Info : 
Module axi_protocol_converter_v2_1_b2s_incr_cmd 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     12 Bit       Adders := 2     
	   2 Input     10 Bit       Adders := 1     
	   2 Input      9 Bit       Adders := 1     
+---Registers : 
	                9 Bit    Registers := 1     
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      9 Bit        Muxes := 2     
	   2 Input      4 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 4     
Module axi_protocol_converter_v2_1_b2s_wrap_cmd 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     12 Bit       Adders := 1     
	   2 Input      6 Bit       Adders := 1     
	   2 Input      5 Bit       Adders := 1     
	   2 Input      4 Bit       Adders := 2     
+---Registers : 
	               12 Bit    Registers := 2     
	                5 Bit    Registers := 1     
	                4 Bit    Registers := 3     
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input     12 Bit        Muxes := 2     
	   2 Input      5 Bit        Muxes := 2     
	   2 Input      4 Bit        Muxes := 3     
	   2 Input      1 Bit        Muxes := 4     
Module axi_protocol_converter_v2_1_b2s_cmd_translator 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 3     
+---Muxes : 
	   3 Input     32 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 4     
Module axi_protocol_converter_v2_1_b2s_wr_cmd_fsm 
Detailed RTL Component Info : 
+---Registers : 
	                2 Bit    Registers := 1     
+---Muxes : 
	   4 Input      2 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 2     
Module axi_protocol_converter_v2_1_b2s_aw_channel 
Detailed RTL Component Info : 
+---Registers : 
	               12 Bit    Registers := 1     
	                8 Bit    Registers := 1     
Module axi_protocol_converter_v2_1_b2s_simple_fifo 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                2 Bit    Registers := 1     
+---Muxes : 
	   2 Input      2 Bit        Muxes := 1     
Module axi_protocol_converter_v2_1_b2s_simple_fifo__parameterized0 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                2 Bit    Registers := 1     
+---Muxes : 
	   2 Input      2 Bit        Muxes := 1     
Module axi_protocol_converter_v2_1_b2s_b_channel 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      8 Bit       Adders := 1     
+---Registers : 
	                8 Bit    Registers := 1     
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 3     
Module axi_protocol_converter_v2_1_b2s_rd_cmd_fsm 
Detailed RTL Component Info : 
+---Registers : 
	                2 Bit    Registers := 1     
+---Muxes : 
	   4 Input      2 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 2     
Module axi_protocol_converter_v2_1_b2s_ar_channel 
Detailed RTL Component Info : 
+---Registers : 
	               12 Bit    Registers := 1     
Module axi_protocol_converter_v2_1_b2s_simple_fifo__parameterized1 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      5 Bit       Adders := 1     
+---Registers : 
	                5 Bit    Registers := 1     
+---Muxes : 
	   2 Input      2 Bit        Muxes := 1     
Module axi_protocol_converter_v2_1_b2s_simple_fifo__parameterized2 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      5 Bit       Adders := 1     
+---Registers : 
	                5 Bit    Registers := 1     
+---Muxes : 
	   2 Input      2 Bit        Muxes := 1     
Module axi_protocol_converter_v2_1_b2s_r_channel 
Detailed RTL Component Info : 
+---Registers : 
	               12 Bit    Registers := 1     
	                1 Bit    Registers := 2     
Module axi_infrastructure_v1_1_axi2vector__parameterized0 
Detailed RTL Component Info : 
Module axi_register_slice_v2_1_axic_register_slice__parameterized3 
Detailed RTL Component Info : 
Module axi_register_slice_v2_1_axic_register_slice__parameterized4 
Detailed RTL Component Info : 
Module axi_register_slice_v2_1_axic_register_slice__parameterized5 
Detailed RTL Component Info : 
Module axi_register_slice_v2_1_axic_register_slice__parameterized6 
Detailed RTL Component Info : 
Module axi_infrastructure_v1_1_vector2axi__parameterized0 
Detailed RTL Component Info : 
Module axi_register_slice_v2_1_axi_register_slice__parameterized0 
Detailed RTL Component Info : 
Module axi_protocol_converter_v2_1_b2s 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module axi_protocol_converter_v2_1_axi_protocol_converter 
Detailed RTL Component Info : 
Module zynq_system_auto_pc_4 
Detailed RTL Component Info : 
Module s00_couplers_imp_156Q4UY 
Detailed RTL Component Info : 
Module zynq_system_processing_system7_0_axi_periph_1 
Detailed RTL Component Info : 
Module lpf 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 13    
Module upcnt_n 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      6 Bit       Adders := 1     
+---Registers : 
	                6 Bit    Registers := 1     
+---Muxes : 
	   2 Input      6 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 1     
Module sequence 
Detailed RTL Component Info : 
+---Registers : 
	                3 Bit    Registers := 3     
	                1 Bit    Registers := 5     
Module proc_sys_reset__parameterized0 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 5     
Module zynq_system_rst_processing_system7_0_50M_0 
Detailed RTL Component Info : 
Module xlconstant 
Detailed RTL Component Info : 
Module zynq_system_xlconstant_0_0 
Detailed RTL Component Info : 
Module zynq_system 
Detailed RTL Component Info : 

---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------

---------------------------------------------------------------------------------
Start Cross Boundary Optimization
---------------------------------------------------------------------------------
INFO: [Synth 8-3332] Sequential element (\AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/MEM_DECODE_GEN[1].cs_out_i_reg[1] ) is unused and will be removed from module axi_gpio__parameterized0.
INFO: [Synth 8-3332] Sequential element (\AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] ) is unused and will be removed from module axi_gpio__parameterized0.
INFO: [Synth 8-3332] Sequential element (\AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ) is unused and will be removed from module axi_gpio__parameterized0.
INFO: [Synth 8-3332] Sequential element (\AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ) is unused and will be removed from module axi_gpio__parameterized0.
INFO: [Synth 8-3332] Sequential element (\AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ) is unused and will be removed from module axi_gpio__parameterized0.
INFO: [Synth 8-4471] merging register 'AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst_reg' into 'bus2ip_reset_reg' [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_axi_gpio_0_0/axi_lite_ipif_v2_0/hdl/src/vhdl/slave_attachment.vhd:386]
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/skid_buffer_reg[65] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/skid_buffer_reg[64] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/skid_buffer_reg[63] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/skid_buffer_reg[62] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/skid_buffer_reg[49] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/skid_buffer_reg[48] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/skid_buffer_reg[43] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/skid_buffer_reg[42] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/skid_buffer_reg[41] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/skid_buffer_reg[40] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/skid_buffer_reg[37] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/m_payload_i_reg[65] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/m_payload_i_reg[64] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/m_payload_i_reg[63] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/m_payload_i_reg[62] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/m_payload_i_reg[49] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/m_payload_i_reg[48] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/m_payload_i_reg[43] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/m_payload_i_reg[42] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/m_payload_i_reg[41] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/m_payload_i_reg[40] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/m_payload_i_reg[37] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/skid_buffer_reg[65] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/skid_buffer_reg[64] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/skid_buffer_reg[63] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/skid_buffer_reg[62] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/skid_buffer_reg[49] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/skid_buffer_reg[48] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/skid_buffer_reg[43] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/skid_buffer_reg[42] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/skid_buffer_reg[41] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/skid_buffer_reg[40] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/skid_buffer_reg[37] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/m_payload_i_reg[65] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/m_payload_i_reg[64] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/m_payload_i_reg[63] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/m_payload_i_reg[62] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/m_payload_i_reg[49] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/m_payload_i_reg[48] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/m_payload_i_reg[43] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/m_payload_i_reg[42] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/m_payload_i_reg[41] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/m_payload_i_reg[40] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/m_payload_i_reg[37] ) is unused and will be removed from module zynq_system_auto_pc_4.
WARNING: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/m_payload_i_reg' and it is trimmed from '66' to '62' bits. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:121]
WARNING: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/m_payload_i_reg' and it is trimmed from '66' to '62' bits. [c:/Projects/2014/ZMITX_7100_OOB_Linux_VIV2013_4/Xil/IPI/OOB_Linux.srcs/sources_1/bd/zynq_system/ip/zynq_system_auto_pc_2/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:121]
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/m_payload_i_reg[49] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/m_payload_i_reg[48] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/m_payload_i_reg[43] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/m_payload_i_reg[42] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/m_payload_i_reg[41] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/m_payload_i_reg[40] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/m_payload_i_reg[37] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/m_payload_i_reg[49] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/m_payload_i_reg[48] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/m_payload_i_reg[43] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/m_payload_i_reg[42] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/m_payload_i_reg[41] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/m_payload_i_reg[40] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/m_payload_i_reg[37] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/skid_buffer_reg[65] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/skid_buffer_reg[64] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/skid_buffer_reg[63] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/skid_buffer_reg[62] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/skid_buffer_reg[49] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/skid_buffer_reg[48] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/skid_buffer_reg[43] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/skid_buffer_reg[42] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/skid_buffer_reg[41] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/skid_buffer_reg[40] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/skid_buffer_reg[37] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/skid_buffer_reg[65] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/skid_buffer_reg[64] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/skid_buffer_reg[63] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/skid_buffer_reg[62] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/skid_buffer_reg[49] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/skid_buffer_reg[48] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/skid_buffer_reg[43] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/skid_buffer_reg[42] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/skid_buffer_reg[41] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/skid_buffer_reg[40] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/skid_buffer_reg[37] ) is unused and will be removed from module zynq_system_auto_pc_4.
---------------------------------------------------------------------------------
Finished Cross Boundary Optimization : Time (s): cpu = 00:02:04 ; elapsed = 00:02:14 . Memory (MB): peak = 688.266 ; gain = 532.715
---------------------------------------------------------------------------------

---------------------------------------------------------------------------------
Start RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------

---------------------------------------------------------------------------------
Start Area Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Area Optimization : Time (s): cpu = 00:02:06 ; elapsed = 00:02:16 . Memory (MB): peak = 713.770 ; gain = 558.219
---------------------------------------------------------------------------------


---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------

---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
INFO: Moved 1 constraints on hierarchical pins to their respective driving/loading pins
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:02:09 ; elapsed = 00:02:18 . Memory (MB): peak = 861.293 ; gain = 705.742
---------------------------------------------------------------------------------

---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:02:09 ; elapsed = 00:02:19 . Memory (MB): peak = 877.230 ; gain = 721.680
---------------------------------------------------------------------------------


---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-3332] Sequential element (\AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_reg[1] ) is unused and will be removed from module axi_gpio__parameterized0.
INFO: [Synth 8-3332] Sequential element (\AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_reg[0] ) is unused and will be removed from module axi_gpio__parameterized0.
INFO: [Synth 8-3332] Sequential element (\AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg[1] ) is unused and will be removed from module axi_gpio__parameterized0.
INFO: [Synth 8-3332] Sequential element (\AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg[0] ) is unused and will be removed from module axi_gpio__parameterized0.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/cmd_translator_0/wrap_cmd_0/axlen_cnt_reg[4] ) is unused and will be removed from module zynq_system_auto_pc_4.
INFO: [Synth 8-3332] Sequential element (\inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/cmd_translator_0/wrap_cmd_0/axlen_cnt_reg[4] ) is unused and will be removed from module zynq_system_auto_pc_4.
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:02:11 ; elapsed = 00:02:21 . Memory (MB): peak = 886.238 ; gain = 730.688
---------------------------------------------------------------------------------


---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------

---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------

---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------

---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
design zynq_system_auto_pc_4 has 4 max_fanout violations cannot be satisfied

---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
Gated Clock Conversion mode: off
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:02:13 ; elapsed = 00:02:23 . Memory (MB): peak = 886.238 ; gain = 730.688
---------------------------------------------------------------------------------


Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+

---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:02:13 ; elapsed = 00:02:23 . Memory (MB): peak = 886.238 ; gain = 730.688
---------------------------------------------------------------------------------


---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:02:13 ; elapsed = 00:02:23 . Memory (MB): peak = 886.238 ; gain = 730.688
---------------------------------------------------------------------------------

---------------------------------------------------------------------------------
Start RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------

Dynamic Shift Register:
+------------+----------------+--------+------------+--------+---------+--------+--------+--------+
|Module Name | RTL Name       | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 | 
+------------+----------------+--------+------------+--------+---------+--------+--------+--------+
|dsrl        | memory_reg[3]  | 4      | 20         | 20     | 0       | 0      | 0      | 0      | 
|dsrl__1     | memory_reg[3]  | 4      | 2          | 2      | 0       | 0      | 0      | 0      | 
|dsrl__2     | memory_reg[31] | 32     | 34         | 0      | 34      | 0      | 0      | 0      | 
|dsrl__3     | memory_reg[31] | 32     | 13         | 0      | 13      | 0      | 0      | 0      | 
+------------+----------------+--------+------------+--------+---------+--------+--------+--------+

---------------------------------------------------------------------------------
Finished RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------

---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes: 
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage: 
+------+--------+------+
|      |Cell    |Count |
+------+--------+------+
|1     |BIBUF   |   130|
|2     |BUFG    |     1|
|3     |CARRY4  |    27|
|4     |GND     |     1|
|5     |LUT1    |    91|
|6     |LUT2    |    65|
|7     |LUT3    |   267|
|8     |LUT4    |    91|
|9     |LUT5    |   176|
|10    |LUT6    |   213|
|11    |PS7     |     1|
|12    |SRL16   |     1|
|13    |SRL16E  |    22|
|14    |SRLC32E |    47|
|15    |VCC     |     1|
|16    |FDRE    |  1013|
|17    |FDSE    |    95|
|18    |IBUF    |     3|
|19    |OBUF    |     8|
+------+--------+------+

Report Instance Areas: 
+------+------------------------------------+----------------------------------------------+------+
|      |Instance                            |Module                                        |Cells |
+------+------------------------------------+----------------------------------------------+------+
|1     |top                                 |                                              |  2253|
|2     |  zynq_system_i                     |zynq_system                                   |  2242|
|3     |    PWM_Controller_0                |zynq_system_PWM_Controller_0_0                |    74|
|4     |    axi_gpio_0                      |zynq_system_axi_gpio_0_0                      |   662|
|5     |      U0                            |axi_gpio__parameterized0                      |   662|
|6     |    processing_system7_0            |zynq_system_processing_system7_0_0            |   160|
|7     |      inst                          |processing_system7_v5_3_processing_system7    |   160|
|8     |    processing_system7_0_axi_periph |zynq_system_processing_system7_0_axi_periph_1 |  1279|
|9     |      \s00_couplers/auto_pc         |zynq_system_auto_pc_4                         |  1279|
|10    |    rst_processing_system7_0_50M    |zynq_system_rst_processing_system7_0_50M_0    |    65|
|11    |      U0                            |proc_sys_reset__parameterized0                |    65|
|12    |    xlconstant_0                    |zynq_system_xlconstant_0_0                    |     0|
+------+------------------------------------+----------------------------------------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:02:13 ; elapsed = 00:02:23 . Memory (MB): peak = 886.238 ; gain = 730.688
---------------------------------------------------------------------------------

Synthesis finished with 0 errors, 0 critical warnings and 21 warnings.
Synthesis Optimization Complete : Time (s): cpu = 00:02:13 ; elapsed = 00:02:23 . Memory (MB): peak = 886.238 ; gain = 730.688
INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers.
INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers.
INFO: [Opt 31-138] Pushed 0 inverter(s).
INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: 
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 1 instances were transformed.
  SRL16 => SRL16E: 1 instances

INFO: [Common 17-83] Releasing license: Synthesis
288 Infos, 147 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:02:25 ; elapsed = 00:02:34 . Memory (MB): peak = 1306.617 ; gain = 1098.145
# write_checkpoint zynq_system_wrapper.dcp
INFO: [Timing 38-35] Done setting XDC timing constraints.
# report_utilization -file zynq_system_wrapper_utilization_synth.rpt -pb zynq_system_wrapper_utilization_synth.pb
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.076 . Memory (MB): peak = 1306.617 ; gain = 0.000
INFO: [Common 17-206] Exiting Vivado at Tue Feb 04 15:56:39 2014...
