Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2013.4 (win64) Build 351683 Wed Dec  4 19:12:58 MST 2013
| Date         : Tue Feb 04 15:57:21 2014
| Host         : avnet-wks2 running 64-bit Service Pack 1  (build 7601)
| Command      : report_control_sets -verbose -file zynq_system_wrapper_control_sets_placed.rpt
| Design       : zynq_system_wrapper
| Device       : xc7z100
------------------------------------------------------------------------------------------------

Control Set Information

Table of Contents
-----------------
1. Summary
2. Flip-Flop Distribution
3. Detailed Control Set Information

1. Summary
----------

+-------------------------------------------------------------------+-------+
|                               Status                              | Count |
+-------------------------------------------------------------------+-------+
| Number of unique control sets                                     |    36 |
| Minimum Number of register sites lost to control set restrictions |    82 |
+-------------------------------------------------------------------+-------+


2. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |             194 |           94 |
| No           | No                    | Yes                    |               0 |            0 |
| No           | Yes                   | No                     |             176 |           55 |
| Yes          | No                    | No                     |             339 |           93 |
| Yes          | No                    | Yes                    |               0 |            0 |
| Yes          | Yes                   | No                     |             129 |           31 |
+--------------+-----------------------+------------------------+-----------------+--------------+


3. Detailed Control Set Information
-----------------------------------

+----------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+
|                    Clock Signal                    |                                                               Enable Signal                                                              |                                                             Set/Reset Signal                                                             | Slice Load Count | Bel Load Count |
+----------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 | zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_push   |                                                                                                                                          |                1 |              2 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 |                                                                                                                                          | zynq_system_i/axi_gpio_0/U0/n_0_INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1                                                                     |                1 |              4 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 | zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/n_0_axlen_cnt[3]_i_1                                                  |                                                                                                                                          |                1 |              4 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 | zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/n_0_axlen_cnt[6]_i_1                                                  | zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/n_0_axlen_cnt[8]_i_1                                                  |                1 |              4 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 | zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/n_0_axlen_cnt[3]_i_1__0                                               |                                                                                                                                          |                1 |              4 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 | zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/n_0_axlen_cnt[3]_i_1__1                                               |                                                                                                                                          |                2 |              4 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 | zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/n_0_axlen_cnt[3]_i_1__0                                               | zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/n_0_axlen_cnt[8]_i_1__0                                               |                2 |              5 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 | zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/n_0_axlen_cnt[6]_i_1                                                  |                                                                                                                                          |                2 |              5 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 | zynq_system_i/rst_processing_system7_0_50M/U0/SEQ/seq_cnt_en                                                                             | zynq_system_i/rst_processing_system7_0_50M/U0/clear                                                                                      |                1 |              6 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 | zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/mhandshake_r | zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/s_bresp_acc0 |                2 |              8 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 |                                                                                                                                          | zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/n_0_areset_d1_i_1                                                     |                4 |              8 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 | zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/n_0_axaddr_wrap[11]_i_1__0                                            |                                                                                                                                          |                4 |             12 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 | zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/n_0_wrap_boundary_axaddr_r[11]_i_1__0                                 |                                                                                                                                          |                4 |             12 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 | zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/n_0_wrap_boundary_axaddr_r[11]_i_1                                    |                                                                                                                                          |                6 |             12 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 | zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/n_0_axaddr_wrap[11]_i_1                                               |                                                                                                                                          |                6 |             12 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 | zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/n_0_axaddr_incr[0]_i_1                                                |                                                                                                                                          |                3 |             12 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 | zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/n_0_axaddr_incr[0]_i_1__0                                             |                                                                                                                                          |                3 |             12 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 | zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/r_push_r     |                                                                                                                                          |                5 |             13 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 | zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/b_pipe/p_1_in        |                                                                                                                                          |                4 |             14 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 | zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/si_rs_bready                |                                                                                                                                          |                3 |             14 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 | zynq_system_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start                                                                     | zynq_system_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/cs_ce_clr                                                       |                6 |             16 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 | zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/b_push                      |                                                                                                                                          |                3 |             20 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 | zynq_system_i/axi_gpio_0/U0/n_0_Dual.gpio_OE[3]_i_1                                                                                      | zynq_system_i/axi_gpio_0/U0/bus2ip_reset                                                                                                 |                5 |             29 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 | zynq_system_i/axi_gpio_0/U0/n_0_Dual.gpio_Data_Out[3]_i_1                                                                                | zynq_system_i/axi_gpio_0/U0/bus2ip_reset                                                                                                 |                7 |             29 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 | zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/p_1_in       |                                                                                                                                          |               10 |             32 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 | zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/p_1_in       |                                                                                                                                          |               10 |             32 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 | zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/s_axi_awready                                                         |                                                                                                                                          |                9 |             32 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 | zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/s_axi_arready                                                         |                                                                                                                                          |                7 |             32 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 | zynq_system_i/axi_gpio_0/U0/n_0_s_axi_rdata_i[31]_i_1                                                                                    | zynq_system_i/axi_gpio_0/U0/bus2ip_reset                                                                                                 |                7 |             32 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 | zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/wr_en0       |                                                                                                                                          |                9 |             34 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 |                                                                                                                                          | zynq_system_i/axi_gpio_0/U0/gpio_core_1/Read_Reg_Rst                                                                                     |               12 |             35 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 | zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r_pipe/p_1_in        |                                                                                                                                          |                9 |             47 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 | zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/si_rs_rready                |                                                                                                                                          |                9 |             47 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 |                                                                                                                                          | zynq_system_i/axi_gpio_0/U0/bus2ip_reset                                                                                                 |               19 |             59 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 |                                                                                                                                          | zynq_system_i/processing_system7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/areset_d1                   |               19 |             70 |
|  zynq_system_i/processing_system7_0/inst/FCLK_CLK0 |                                                                                                                                          |                                                                                                                                          |               95 |            195 |
+----------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+


