<registers>
  <register offset="0xf889d000" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMCR">
    <name>ETMCR</name>
    <desc>Main Control Register</desc>
  </register>
  <register offset="0xf889d004" type="ro" uniqueid="ps7_debug_cpu_ptm1_ETMCCR">
    <name>ETMCCR</name>
    <desc>Configuration Code Register</desc>
  </register>
  <register offset="0xf889d008" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMTRIGGER">
    <name>ETMTRIGGER</name>
    <desc>Trigger Event Register</desc>
  </register>
  <register offset="0xf889d010" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMSR">
    <name>ETMSR</name>
    <desc>Status Register</desc>
  </register>
  <register offset="0xf889d014" type="ro" uniqueid="ps7_debug_cpu_ptm1_ETMSCR">
    <name>ETMSCR</name>
    <desc>System Configuration Register</desc>
  </register>
  <register offset="0xf889d018" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMTSSCR">
    <name>ETMTSSCR</name>
    <desc>TraceEnable Start/Stop Control Register</desc>
  </register>
  <register offset="0xf889d024" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMTECR1">
    <name>ETMTECR1</name>
    <desc>TraceEnable Control Register 1</desc>
  </register>
  <register offset="0xf889d040" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMACVR1">
    <name>ETMACVR1</name>
    <desc>Address Comparator Value Register 1</desc>
  </register>
  <register offset="0xf889d044" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMACVR2">
    <name>ETMACVR2</name>
    <desc>Address Comparator Value Register 2</desc>
  </register>
  <register offset="0xf889d048" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMACVR3">
    <name>ETMACVR3</name>
    <desc>Address Comparator Value Register 3</desc>
  </register>
  <register offset="0xf889d04c" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMACVR4">
    <name>ETMACVR4</name>
    <desc>Address Comparator Value Register 4</desc>
  </register>
  <register offset="0xf889d050" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMACVR5">
    <name>ETMACVR5</name>
    <desc>Address Comparator Value Register 5</desc>
  </register>
  <register offset="0xf889d054" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMACVR6">
    <name>ETMACVR6</name>
    <desc>Address Comparator Value Register 6</desc>
  </register>
  <register offset="0xf889d058" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMACVR7">
    <name>ETMACVR7</name>
    <desc>Address Comparator Value Register 7</desc>
  </register>
  <register offset="0xf889d05c" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMACVR8">
    <name>ETMACVR8</name>
    <desc>Address Comparator Value Register 8</desc>
  </register>
  <register offset="0xf889d080" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMACTR1">
    <name>ETMACTR1</name>
    <desc>Address Comparator Access Type Register 1</desc>
  </register>
  <register offset="0xf889d084" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMACTR2">
    <name>ETMACTR2</name>
    <desc>Address Comparator Access Type Register 2</desc>
  </register>
  <register offset="0xf889d088" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMACTR3">
    <name>ETMACTR3</name>
    <desc>Address Comparator Access Type Register 3</desc>
  </register>
  <register offset="0xf889d08c" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMACTR4">
    <name>ETMACTR4</name>
    <desc>Address Comparator Access Type Register 4</desc>
  </register>
  <register offset="0xf889d090" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMACTR5">
    <name>ETMACTR5</name>
    <desc>Address Comparator Access Type Register 5</desc>
  </register>
  <register offset="0xf889d094" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMACTR6">
    <name>ETMACTR6</name>
    <desc>Address Comparator Access Type Register 6</desc>
  </register>
  <register offset="0xf889d098" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMACTR7">
    <name>ETMACTR7</name>
    <desc>Address Comparator Access Type Register 7</desc>
  </register>
  <register offset="0xf889d09c" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMACTR8">
    <name>ETMACTR8</name>
    <desc>Address Comparator Access Type Register 8</desc>
  </register>
  <register offset="0xf889d140" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMCNTRLDVR1">
    <name>ETMCNTRLDVR1</name>
    <desc>Counter Reload Value Register 1</desc>
  </register>
  <register offset="0xf889d144" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMCNTRLDVR2">
    <name>ETMCNTRLDVR2</name>
    <desc>Counter Reload Value Register 2</desc>
  </register>
  <register offset="0xf889d150" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMCNTENR1">
    <name>ETMCNTENR1</name>
    <desc>Counter Enable Event Register 1</desc>
  </register>
  <register offset="0xf889d154" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMCNTENR2">
    <name>ETMCNTENR2</name>
    <desc>Counter Enable Event Register 2</desc>
  </register>
  <register offset="0xf889d160" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMCNTRLDEVR1">
    <name>ETMCNTRLDEVR1</name>
    <desc>Counter Reload Event Register 1</desc>
  </register>
  <register offset="0xf889d164" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMCNTRLDEVR2">
    <name>ETMCNTRLDEVR2</name>
    <desc>Counter Reload Event Register 2</desc>
  </register>
  <register offset="0xf889d170" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMCNTVR1">
    <name>ETMCNTVR1</name>
    <desc>Counter Value Register 1</desc>
  </register>
  <register offset="0xf889d174" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMCNTVR2">
    <name>ETMCNTVR2</name>
    <desc>Counter Value Register 2</desc>
  </register>
  <register offset="0xf889d180" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMSQ12EVR">
    <name>ETMSQ12EVR</name>
    <desc>Sequencer State Transition Event Register 12</desc>
  </register>
  <register offset="0xf889d184" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMSQ21EVR">
    <name>ETMSQ21EVR</name>
    <desc>Sequencer State Transition Event Register 21</desc>
  </register>
  <register offset="0xf889d188" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMSQ23EVR">
    <name>ETMSQ23EVR</name>
    <desc>Sequencer State Transition Event Register 23</desc>
  </register>
  <register offset="0xf889d18c" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMSQ31EVR">
    <name>ETMSQ31EVR</name>
    <desc>Sequencer State Transition Event Register 31</desc>
  </register>
  <register offset="0xf889d190" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMSQ32EVR">
    <name>ETMSQ32EVR</name>
    <desc>Sequencer State Transition Event Register 32</desc>
  </register>
  <register offset="0xf889d194" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMSQ13EVR">
    <name>ETMSQ13EVR</name>
    <desc>Sequencer State Transition Event Register 13</desc>
  </register>
  <register offset="0xf889d19c" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMSQR">
    <name>ETMSQR</name>
    <desc>Current Sequencer State Register</desc>
  </register>
  <register offset="0xf889d1a0" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMEXTOUTEVR1">
    <name>ETMEXTOUTEVR1</name>
    <desc>External Output Event Register 1</desc>
  </register>
  <register offset="0xf889d1a4" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMEXTOUTEVR2">
    <name>ETMEXTOUTEVR2</name>
    <desc>External Output Event Register 2</desc>
  </register>
  <register offset="0xf889d1b0" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMCIDCVR1">
    <name>ETMCIDCVR1</name>
    <desc>Context ID Comparator Value Register</desc>
  </register>
  <register offset="0xf889d1bc" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMCIDCMR">
    <name>ETMCIDCMR</name>
    <desc>Context ID Comparator Mask Register</desc>
  </register>
  <register offset="0xf889d1e0" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMSYNCFR">
    <name>ETMSYNCFR</name>
    <desc>Synchronization Frequency Register</desc>
  </register>
  <register offset="0xf889d1e4" type="ro" uniqueid="ps7_debug_cpu_ptm1_ETMIDR">
    <name>ETMIDR</name>
    <desc>ID Register</desc>
  </register>
  <register offset="0xf889d1e8" type="ro" uniqueid="ps7_debug_cpu_ptm1_ETMCCER">
    <name>ETMCCER</name>
    <desc>Configuration Code Extension Register</desc>
  </register>
  <register offset="0xf889d1ec" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMEXTINSELR">
    <name>ETMEXTINSELR</name>
    <desc>Extended External Input Selection Register</desc>
  </register>
  <register offset="0xf889d1fc" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMAUXCR">
    <name>ETMAUXCR</name>
    <desc>Auxiliary Control Register</desc>
  </register>
  <register offset="0xf889d200" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMTRACEIDR">
    <name>ETMTRACEIDR</name>
    <desc>CoreSight Trace ID Register</desc>
  </register>
  <register offset="0xf889d304" type="ro" uniqueid="ps7_debug_cpu_ptm1_OSLSR">
    <name>OSLSR</name>
    <desc>OS Lock Status Register</desc>
  </register>
  <register offset="0xf889d314" type="ro" uniqueid="ps7_debug_cpu_ptm1_ETMPDSR">
    <name>ETMPDSR</name>
    <desc>Device Power-Down Status Register</desc>
  </register>
  <register offset="0xf889dedc" type="wo" uniqueid="ps7_debug_cpu_ptm1_ITMISCOUT">
    <name>ITMISCOUT</name>
    <desc>Miscellaneous Outputs Register</desc>
  </register>
  <register offset="0xf889dee0" type="ro" uniqueid="ps7_debug_cpu_ptm1_ITMISCIN">
    <name>ITMISCIN</name>
    <desc>Miscellaneous Inputs Register</desc>
  </register>
  <register offset="0xf889dee8" type="wo" uniqueid="ps7_debug_cpu_ptm1_ITTRIGGER">
    <name>ITTRIGGER</name>
    <desc>Trigger Register</desc>
  </register>
  <register offset="0xf889deec" type="wo" uniqueid="ps7_debug_cpu_ptm1_ITATBDATA0">
    <name>ITATBDATA0</name>
    <desc>ATB Data 0 Register</desc>
  </register>
  <register offset="0xf889def0" type="ro" uniqueid="ps7_debug_cpu_ptm1_ITATBCTR2">
    <name>ITATBCTR2</name>
    <desc>ATB Control 2 Register</desc>
  </register>
  <register offset="0xf889def4" type="wo" uniqueid="ps7_debug_cpu_ptm1_ITATBID">
    <name>ITATBID</name>
    <desc>ATB Identification Register</desc>
  </register>
  <register offset="0xf889def8" type="wo" uniqueid="ps7_debug_cpu_ptm1_ITATBCTR0">
    <name>ITATBCTR0</name>
    <desc>ATB Control 0 Register</desc>
  </register>
  <register offset="0xf889df00" type="rw" uniqueid="ps7_debug_cpu_ptm1_ETMITCTRL">
    <name>ETMITCTRL</name>
    <desc>Integration Mode Control Register</desc>
  </register>
  <register offset="0xf889dfa0" type="rw" uniqueid="ps7_debug_cpu_ptm1_CTSR">
    <name>CTSR</name>
    <desc>Claim Tag Set Register</desc>
  </register>
  <register offset="0xf889dfa4" type="rw" uniqueid="ps7_debug_cpu_ptm1_CTCR">
    <name>CTCR</name>
    <desc>Claim Tag Clear Register</desc>
  </register>
  <register offset="0xf889dfb0" type="wo" uniqueid="ps7_debug_cpu_ptm1_LAR">
    <name>LAR</name>
    <desc>Lock Access Register</desc>
  </register>
  <register offset="0xf889dfb4" type="ro" uniqueid="ps7_debug_cpu_ptm1_LSR">
    <name>LSR</name>
    <desc>Lock Status Register</desc>
  </register>
  <register offset="0xf889dfb8" type="ro" uniqueid="ps7_debug_cpu_ptm1_ASR">
    <name>ASR</name>
    <desc>Authentication Status Register</desc>
  </register>
  <register offset="0xf889dfc8" type="ro" uniqueid="ps7_debug_cpu_ptm1_DEVID">
    <name>DEVID</name>
    <desc>Device ID</desc>
  </register>
  <register offset="0xf889dfcc" type="ro" uniqueid="ps7_debug_cpu_ptm1_DTIR">
    <name>DTIR</name>
    <desc>Device Type Identifier Register</desc>
  </register>
  <register offset="0xf889dfd0" type="ro" uniqueid="ps7_debug_cpu_ptm1_PERIPHID4">
    <name>PERIPHID4</name>
    <desc>Peripheral ID4</desc>
  </register>
  <register offset="0xf889dfd4" type="ro" uniqueid="ps7_debug_cpu_ptm1_PERIPHID5">
    <name>PERIPHID5</name>
    <desc>Peripheral ID5</desc>
  </register>
  <register offset="0xf889dfd8" type="ro" uniqueid="ps7_debug_cpu_ptm1_PERIPHID6">
    <name>PERIPHID6</name>
    <desc>Peripheral ID6</desc>
  </register>
  <register offset="0xf889dfdc" type="ro" uniqueid="ps7_debug_cpu_ptm1_PERIPHID7">
    <name>PERIPHID7</name>
    <desc>Peripheral ID7</desc>
  </register>
  <register offset="0xf889dfe0" type="ro" uniqueid="ps7_debug_cpu_ptm1_PERIPHID0">
    <name>PERIPHID0</name>
    <desc>Peripheral ID0</desc>
  </register>
  <register offset="0xf889dfe4" type="ro" uniqueid="ps7_debug_cpu_ptm1_PERIPHID1">
    <name>PERIPHID1</name>
    <desc>Peripheral ID1</desc>
  </register>
  <register offset="0xf889dfe8" type="ro" uniqueid="ps7_debug_cpu_ptm1_PERIPHID2">
    <name>PERIPHID2</name>
    <desc>Peripheral ID2</desc>
  </register>
  <register offset="0xf889dfec" type="ro" uniqueid="ps7_debug_cpu_ptm1_PERIPHID3">
    <name>PERIPHID3</name>
    <desc>Peripheral ID3</desc>
  </register>
  <register offset="0xf889dff0" type="ro" uniqueid="ps7_debug_cpu_ptm1_COMPID0">
    <name>COMPID0</name>
    <desc>Component ID0</desc>
  </register>
  <register offset="0xf889dff4" type="ro" uniqueid="ps7_debug_cpu_ptm1_COMPID1">
    <name>COMPID1</name>
    <desc>Component ID1</desc>
  </register>
  <register offset="0xf889dff8" type="ro" uniqueid="ps7_debug_cpu_ptm1_COMPID2">
    <name>COMPID2</name>
    <desc>Component ID2</desc>
  </register>
  <register offset="0xf889dffc" type="ro" uniqueid="ps7_debug_cpu_ptm1_COMPID3">
    <name>COMPID3</name>
    <desc>Component ID3</desc>
  </register>
  <register offset="0xf889c000" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMCR">
    <name>ETMCR</name>
    <desc>Main Control Register</desc>
  </register>
  <register offset="0xf889c004" type="ro" uniqueid="ps7_debug_cpu_ptm0_ETMCCR">
    <name>ETMCCR</name>
    <desc>Configuration Code Register</desc>
  </register>
  <register offset="0xf889c008" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMTRIGGER">
    <name>ETMTRIGGER</name>
    <desc>Trigger Event Register</desc>
  </register>
  <register offset="0xf889c010" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMSR">
    <name>ETMSR</name>
    <desc>Status Register</desc>
  </register>
  <register offset="0xf889c014" type="ro" uniqueid="ps7_debug_cpu_ptm0_ETMSCR">
    <name>ETMSCR</name>
    <desc>System Configuration Register</desc>
  </register>
  <register offset="0xf889c018" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMTSSCR">
    <name>ETMTSSCR</name>
    <desc>TraceEnable Start/Stop Control Register</desc>
  </register>
  <register offset="0xf889c024" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMTECR1">
    <name>ETMTECR1</name>
    <desc>TraceEnable Control Register 1</desc>
  </register>
  <register offset="0xf889c040" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMACVR1">
    <name>ETMACVR1</name>
    <desc>Address Comparator Value Register 1</desc>
  </register>
  <register offset="0xf889c044" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMACVR2">
    <name>ETMACVR2</name>
    <desc>Address Comparator Value Register 2</desc>
  </register>
  <register offset="0xf889c048" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMACVR3">
    <name>ETMACVR3</name>
    <desc>Address Comparator Value Register 3</desc>
  </register>
  <register offset="0xf889c04c" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMACVR4">
    <name>ETMACVR4</name>
    <desc>Address Comparator Value Register 4</desc>
  </register>
  <register offset="0xf889c050" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMACVR5">
    <name>ETMACVR5</name>
    <desc>Address Comparator Value Register 5</desc>
  </register>
  <register offset="0xf889c054" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMACVR6">
    <name>ETMACVR6</name>
    <desc>Address Comparator Value Register 6</desc>
  </register>
  <register offset="0xf889c058" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMACVR7">
    <name>ETMACVR7</name>
    <desc>Address Comparator Value Register 7</desc>
  </register>
  <register offset="0xf889c05c" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMACVR8">
    <name>ETMACVR8</name>
    <desc>Address Comparator Value Register 8</desc>
  </register>
  <register offset="0xf889c080" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMACTR1">
    <name>ETMACTR1</name>
    <desc>Address Comparator Access Type Register 1</desc>
  </register>
  <register offset="0xf889c084" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMACTR2">
    <name>ETMACTR2</name>
    <desc>Address Comparator Access Type Register 2</desc>
  </register>
  <register offset="0xf889c088" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMACTR3">
    <name>ETMACTR3</name>
    <desc>Address Comparator Access Type Register 3</desc>
  </register>
  <register offset="0xf889c08c" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMACTR4">
    <name>ETMACTR4</name>
    <desc>Address Comparator Access Type Register 4</desc>
  </register>
  <register offset="0xf889c090" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMACTR5">
    <name>ETMACTR5</name>
    <desc>Address Comparator Access Type Register 5</desc>
  </register>
  <register offset="0xf889c094" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMACTR6">
    <name>ETMACTR6</name>
    <desc>Address Comparator Access Type Register 6</desc>
  </register>
  <register offset="0xf889c098" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMACTR7">
    <name>ETMACTR7</name>
    <desc>Address Comparator Access Type Register 7</desc>
  </register>
  <register offset="0xf889c09c" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMACTR8">
    <name>ETMACTR8</name>
    <desc>Address Comparator Access Type Register 8</desc>
  </register>
  <register offset="0xf889c140" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMCNTRLDVR1">
    <name>ETMCNTRLDVR1</name>
    <desc>Counter Reload Value Register 1</desc>
  </register>
  <register offset="0xf889c144" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMCNTRLDVR2">
    <name>ETMCNTRLDVR2</name>
    <desc>Counter Reload Value Register 2</desc>
  </register>
  <register offset="0xf889c150" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMCNTENR1">
    <name>ETMCNTENR1</name>
    <desc>Counter Enable Event Register 1</desc>
  </register>
  <register offset="0xf889c154" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMCNTENR2">
    <name>ETMCNTENR2</name>
    <desc>Counter Enable Event Register 2</desc>
  </register>
  <register offset="0xf889c160" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMCNTRLDEVR1">
    <name>ETMCNTRLDEVR1</name>
    <desc>Counter Reload Event Register 1</desc>
  </register>
  <register offset="0xf889c164" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMCNTRLDEVR2">
    <name>ETMCNTRLDEVR2</name>
    <desc>Counter Reload Event Register 2</desc>
  </register>
  <register offset="0xf889c170" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMCNTVR1">
    <name>ETMCNTVR1</name>
    <desc>Counter Value Register 1</desc>
  </register>
  <register offset="0xf889c174" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMCNTVR2">
    <name>ETMCNTVR2</name>
    <desc>Counter Value Register 2</desc>
  </register>
  <register offset="0xf889c180" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMSQ12EVR">
    <name>ETMSQ12EVR</name>
    <desc>Sequencer State Transition Event Register 12</desc>
  </register>
  <register offset="0xf889c184" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMSQ21EVR">
    <name>ETMSQ21EVR</name>
    <desc>Sequencer State Transition Event Register 21</desc>
  </register>
  <register offset="0xf889c188" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMSQ23EVR">
    <name>ETMSQ23EVR</name>
    <desc>Sequencer State Transition Event Register 23</desc>
  </register>
  <register offset="0xf889c18c" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMSQ31EVR">
    <name>ETMSQ31EVR</name>
    <desc>Sequencer State Transition Event Register 31</desc>
  </register>
  <register offset="0xf889c190" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMSQ32EVR">
    <name>ETMSQ32EVR</name>
    <desc>Sequencer State Transition Event Register 32</desc>
  </register>
  <register offset="0xf889c194" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMSQ13EVR">
    <name>ETMSQ13EVR</name>
    <desc>Sequencer State Transition Event Register 13</desc>
  </register>
  <register offset="0xf889c19c" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMSQR">
    <name>ETMSQR</name>
    <desc>Current Sequencer State Register</desc>
  </register>
  <register offset="0xf889c1a0" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMEXTOUTEVR1">
    <name>ETMEXTOUTEVR1</name>
    <desc>External Output Event Register 1</desc>
  </register>
  <register offset="0xf889c1a4" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMEXTOUTEVR2">
    <name>ETMEXTOUTEVR2</name>
    <desc>External Output Event Register 2</desc>
  </register>
  <register offset="0xf889c1b0" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMCIDCVR1">
    <name>ETMCIDCVR1</name>
    <desc>Context ID Comparator Value Register</desc>
  </register>
  <register offset="0xf889c1bc" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMCIDCMR">
    <name>ETMCIDCMR</name>
    <desc>Context ID Comparator Mask Register</desc>
  </register>
  <register offset="0xf889c1e0" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMSYNCFR">
    <name>ETMSYNCFR</name>
    <desc>Synchronization Frequency Register</desc>
  </register>
  <register offset="0xf889c1e4" type="ro" uniqueid="ps7_debug_cpu_ptm0_ETMIDR">
    <name>ETMIDR</name>
    <desc>ID Register</desc>
  </register>
  <register offset="0xf889c1e8" type="ro" uniqueid="ps7_debug_cpu_ptm0_ETMCCER">
    <name>ETMCCER</name>
    <desc>Configuration Code Extension Register</desc>
  </register>
  <register offset="0xf889c1ec" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMEXTINSELR">
    <name>ETMEXTINSELR</name>
    <desc>Extended External Input Selection Register</desc>
  </register>
  <register offset="0xf889c1fc" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMAUXCR">
    <name>ETMAUXCR</name>
    <desc>Auxiliary Control Register</desc>
  </register>
  <register offset="0xf889c200" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMTRACEIDR">
    <name>ETMTRACEIDR</name>
    <desc>CoreSight Trace ID Register</desc>
  </register>
  <register offset="0xf889c304" type="ro" uniqueid="ps7_debug_cpu_ptm0_OSLSR">
    <name>OSLSR</name>
    <desc>OS Lock Status Register</desc>
  </register>
  <register offset="0xf889c314" type="ro" uniqueid="ps7_debug_cpu_ptm0_ETMPDSR">
    <name>ETMPDSR</name>
    <desc>Device Power-Down Status Register</desc>
  </register>
  <register offset="0xf889cedc" type="wo" uniqueid="ps7_debug_cpu_ptm0_ITMISCOUT">
    <name>ITMISCOUT</name>
    <desc>Miscellaneous Outputs Register</desc>
  </register>
  <register offset="0xf889cee0" type="ro" uniqueid="ps7_debug_cpu_ptm0_ITMISCIN">
    <name>ITMISCIN</name>
    <desc>Miscellaneous Inputs Register</desc>
  </register>
  <register offset="0xf889cee8" type="wo" uniqueid="ps7_debug_cpu_ptm0_ITTRIGGER">
    <name>ITTRIGGER</name>
    <desc>Trigger Register</desc>
  </register>
  <register offset="0xf889ceec" type="wo" uniqueid="ps7_debug_cpu_ptm0_ITATBDATA0">
    <name>ITATBDATA0</name>
    <desc>ATB Data 0 Register</desc>
  </register>
  <register offset="0xf889cef0" type="ro" uniqueid="ps7_debug_cpu_ptm0_ITATBCTR2">
    <name>ITATBCTR2</name>
    <desc>ATB Control 2 Register</desc>
  </register>
  <register offset="0xf889cef4" type="wo" uniqueid="ps7_debug_cpu_ptm0_ITATBID">
    <name>ITATBID</name>
    <desc>ATB Identification Register</desc>
  </register>
  <register offset="0xf889cef8" type="wo" uniqueid="ps7_debug_cpu_ptm0_ITATBCTR0">
    <name>ITATBCTR0</name>
    <desc>ATB Control 0 Register</desc>
  </register>
  <register offset="0xf889cf00" type="rw" uniqueid="ps7_debug_cpu_ptm0_ETMITCTRL">
    <name>ETMITCTRL</name>
    <desc>Integration Mode Control Register</desc>
  </register>
  <register offset="0xf889cfa0" type="rw" uniqueid="ps7_debug_cpu_ptm0_CTSR">
    <name>CTSR</name>
    <desc>Claim Tag Set Register</desc>
  </register>
  <register offset="0xf889cfa4" type="rw" uniqueid="ps7_debug_cpu_ptm0_CTCR">
    <name>CTCR</name>
    <desc>Claim Tag Clear Register</desc>
  </register>
  <register offset="0xf889cfb0" type="wo" uniqueid="ps7_debug_cpu_ptm0_LAR">
    <name>LAR</name>
    <desc>Lock Access Register</desc>
  </register>
  <register offset="0xf889cfb4" type="ro" uniqueid="ps7_debug_cpu_ptm0_LSR">
    <name>LSR</name>
    <desc>Lock Status Register</desc>
  </register>
  <register offset="0xf889cfb8" type="ro" uniqueid="ps7_debug_cpu_ptm0_ASR">
    <name>ASR</name>
    <desc>Authentication Status Register</desc>
  </register>
  <register offset="0xf889cfc8" type="ro" uniqueid="ps7_debug_cpu_ptm0_DEVID">
    <name>DEVID</name>
    <desc>Device ID</desc>
  </register>
  <register offset="0xf889cfcc" type="ro" uniqueid="ps7_debug_cpu_ptm0_DTIR">
    <name>DTIR</name>
    <desc>Device Type Identifier Register</desc>
  </register>
  <register offset="0xf889cfd0" type="ro" uniqueid="ps7_debug_cpu_ptm0_PERIPHID4">
    <name>PERIPHID4</name>
    <desc>Peripheral ID4</desc>
  </register>
  <register offset="0xf889cfd4" type="ro" uniqueid="ps7_debug_cpu_ptm0_PERIPHID5">
    <name>PERIPHID5</name>
    <desc>Peripheral ID5</desc>
  </register>
  <register offset="0xf889cfd8" type="ro" uniqueid="ps7_debug_cpu_ptm0_PERIPHID6">
    <name>PERIPHID6</name>
    <desc>Peripheral ID6</desc>
  </register>
  <register offset="0xf889cfdc" type="ro" uniqueid="ps7_debug_cpu_ptm0_PERIPHID7">
    <name>PERIPHID7</name>
    <desc>Peripheral ID7</desc>
  </register>
  <register offset="0xf889cfe0" type="ro" uniqueid="ps7_debug_cpu_ptm0_PERIPHID0">
    <name>PERIPHID0</name>
    <desc>Peripheral ID0</desc>
  </register>
  <register offset="0xf889cfe4" type="ro" uniqueid="ps7_debug_cpu_ptm0_PERIPHID1">
    <name>PERIPHID1</name>
    <desc>Peripheral ID1</desc>
  </register>
  <register offset="0xf889cfe8" type="ro" uniqueid="ps7_debug_cpu_ptm0_PERIPHID2">
    <name>PERIPHID2</name>
    <desc>Peripheral ID2</desc>
  </register>
  <register offset="0xf889cfec" type="ro" uniqueid="ps7_debug_cpu_ptm0_PERIPHID3">
    <name>PERIPHID3</name>
    <desc>Peripheral ID3</desc>
  </register>
  <register offset="0xf889cff0" type="ro" uniqueid="ps7_debug_cpu_ptm0_COMPID0">
    <name>COMPID0</name>
    <desc>Component ID0</desc>
  </register>
  <register offset="0xf889cff4" type="ro" uniqueid="ps7_debug_cpu_ptm0_COMPID1">
    <name>COMPID1</name>
    <desc>Component ID1</desc>
  </register>
  <register offset="0xf889cff8" type="ro" uniqueid="ps7_debug_cpu_ptm0_COMPID2">
    <name>COMPID2</name>
    <desc>Component ID2</desc>
  </register>
  <register offset="0xf889cffc" type="ro" uniqueid="ps7_debug_cpu_ptm0_COMPID3">
    <name>COMPID3</name>
    <desc>Component ID3</desc>
  </register>
  <register offset="0xe0101000" type="rw" uniqueid="ps7_sd1_SDMA_system_address_register">
    <name>SDMA_system_address_register</name>
    <desc>This register contains the system memory address for a DMA transfer. When the Host Controller (HC) stops a DMA transfer, this register shall point to the system address of the next contiguous data position. It can be accessed only if no transaction is executing (i.e after a transaction has stopped). Read operations during transfer return an invalid value. The Host Driver (HD) shall initialize this register before starting a DMA transaction. After DMA has stopped, the next system address of the next contiguous data position can be read from this register. The DMA transfer waits at every boundary specified by the Host DMA Buffer Size in the Block Size register. The Host Controller generates DMA Interrupt to request to update this register. The HD sets the next system address of the next data position to this register. When most upper byte of this register (003h) is written, the HC restart the DMA transfer. When restarting DMA by the resume command or by setting Continue Request in the Block Gap Control register, the HC shall start at the next contiguous address stored here in the System Address register</desc>
  </register>
  <register offset="0xe0101004" type="rw" uniqueid="ps7_sd1_Block_Size_Block_Count">
    <name>Block_Size_Block_Count</name>
    <desc>Block size register
Block count register</desc>
  </register>
  <register offset="0xe0101008" type="rw" uniqueid="ps7_sd1_Argument">
    <name>Argument</name>
    <desc>Argument register</desc>
  </register>
  <register offset="0xe010100c" type="rw" uniqueid="ps7_sd1_Transfer_Mode_Command">
    <name>Transfer_Mode_Command</name>
    <desc>Transfer mode register
Command register</desc>
  </register>
  <register offset="0xe0101010" type="ro" uniqueid="ps7_sd1_Response0">
    <name>Response</name>
    <desc>Response register</desc>
  </register>
  <register offset="0xe0101014" type="ro" uniqueid="ps7_sd1_Response1">
    <name>Response</name>
    <desc>Response register</desc>
  </register>
  <register offset="0xe0101018" type="ro" uniqueid="ps7_sd1_Response2">
    <name>Response</name>
    <desc>Response register</desc>
  </register>
  <register offset="0xe010101c" type="ro" uniqueid="ps7_sd1_Response3">
    <name>Response</name>
    <desc>Response register</desc>
  </register>
  <register offset="0xe0101020" type="rw" uniqueid="ps7_sd1_Buffer_Data_Port">
    <name>Buffer_Data_Port</name>
    <desc>Buffer data port register</desc>
  </register>
  <register offset="0xe0101024" type="ro" uniqueid="ps7_sd1_Present_State">
    <name>Present_State</name>
    <desc>Present State register</desc>
  </register>
  <register offset="0xe0101028" type="rw" uniqueid="ps7_sd1_Host_control_Power_control_Block_Gap_Control_Wakeup_control">
    <name>Host_control_Power_control_Block_Gap_Control_Wakeup_control</name>
    <desc>Host control register
Power control register
Block gap control register
Wake-up control register</desc>
  </register>
  <register offset="0xe010102c" type="rw" uniqueid="ps7_sd1_Clock_Control_Timeout_control_Software_reset">
    <name>Clock_Control_Timeout_control_Software_reset</name>
    <desc>Clock Control register
Timeout control register
Software reset register</desc>
  </register>
  <register offset="0xe0101030" type="rw" uniqueid="ps7_sd1_Normal_interrupt_status_Error_interrupt_status">
    <name>Normal_interrupt_status_Error_interrupt_status</name>
    <desc>Normal interrupt status register
Error interrupt status register</desc>
  </register>
  <register offset="0xe0101034" type="rw" uniqueid="ps7_sd1_Normal_interrupt_status_enable_Error_interrupt_status_enable">
    <name>Normal_interrupt_status_enable_Error_interrupt_status_enable</name>
    <desc>Normal interrupt status enable register
Error interrupt status enable register</desc>
  </register>
  <register offset="0xe0101038" type="rw" uniqueid="ps7_sd1_Normal_interrupt_signal_enable_Error_interrupt_signal_enable">
    <name>Normal_interrupt_signal_enable_Error_interrupt_signal_enable</name>
    <desc>Normal interrupt signal enable register
Error interrupt signal enable register</desc>
  </register>
  <register offset="0xe010103c" type="ro" uniqueid="ps7_sd1_Auto_CMD12_error_status">
    <name>Auto_CMD12_error_status</name>
    <desc>Auto CMD12 error status register</desc>
  </register>
  <register offset="0xe0101040" type="ro" uniqueid="ps7_sd1_Capabilities">
    <name>Capabilities</name>
    <desc>Capabilities register</desc>
  </register>
  <register offset="0xe0101048" type="ro" uniqueid="ps7_sd1_Maximum_current_capabilities">
    <name>Maximum_current_capabilities</name>
    <desc>Maximum current capabilities register</desc>
  </register>
  <register offset="0xe0101050" type="rw" uniqueid="ps7_sd1_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status">
    <name>Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status</name>
    <desc>Force event register for Auto CMD12 error status register
Force event register for error interrupt status</desc>
  </register>
  <register offset="0xe0101054" type="rw" uniqueid="ps7_sd1_ADMA_error_status">
    <name>ADMA_error_status</name>
    <desc>ADMA error status register</desc>
  </register>
  <register offset="0xe0101058" type="rw" uniqueid="ps7_sd1_ADMA_system_address">
    <name>ADMA_system_address</name>
    <desc>ADMA system address register</desc>
  </register>
  <register offset="0xe0101060" type="rw" uniqueid="ps7_sd1_Boot_Timeout_control">
    <name>Boot_Timeout_control</name>
    <desc>Boot Timeout control register</desc>
  </register>
  <register offset="0xe0101064" type="wo" uniqueid="ps7_sd1_Debug_Selection">
    <name>Debug_Selection</name>
    <desc>Debug Selection Register</desc>
  </register>
  <register offset="0xe01010f0" type="rw" uniqueid="ps7_sd1_SPI_interrupt_support">
    <name>SPI_interrupt_support</name>
    <desc>SPI interrupt support register</desc>
  </register>
  <register offset="0xe01010fc" type="ro" uniqueid="ps7_sd1_Slot_interrupt_status_Host_controller_version">
    <name>Slot_interrupt_status_Host_controller_version</name>
    <desc>Slot interrupt status register and
Host controller version register</desc>
  </register>
  <register offset="0xe0100000" type="rw" uniqueid="ps7_sd0_SDMA_system_address_register">
    <name>SDMA_system_address_register</name>
    <desc>This register contains the system memory address for a DMA transfer. When the Host Controller (HC) stops a DMA transfer, this register shall point to the system address of the next contiguous data position. It can be accessed only if no transaction is executing (i.e after a transaction has stopped). Read operations during transfer return an invalid value. The Host Driver (HD) shall initialize this register before starting a DMA transaction. After DMA has stopped, the next system address of the next contiguous data position can be read from this register. The DMA transfer waits at every boundary specified by the Host DMA Buffer Size in the Block Size register. The Host Controller generates DMA Interrupt to request to update this register. The HD sets the next system address of the next data position to this register. When most upper byte of this register (003h) is written, the HC restart the DMA transfer. When restarting DMA by the resume command or by setting Continue Request in the Block Gap Control register, the HC shall start at the next contiguous address stored here in the System Address register</desc>
  </register>
  <register offset="0xe0100004" type="rw" uniqueid="ps7_sd0_Block_Size_Block_Count">
    <name>Block_Size_Block_Count</name>
    <desc>Block size register
Block count register</desc>
  </register>
  <register offset="0xe0100008" type="rw" uniqueid="ps7_sd0_Argument">
    <name>Argument</name>
    <desc>Argument register</desc>
  </register>
  <register offset="0xe010000c" type="rw" uniqueid="ps7_sd0_Transfer_Mode_Command">
    <name>Transfer_Mode_Command</name>
    <desc>Transfer mode register
Command register</desc>
  </register>
  <register offset="0xe0100010" type="ro" uniqueid="ps7_sd0_Response0">
    <name>Response</name>
    <desc>Response register</desc>
  </register>
  <register offset="0xe0100014" type="ro" uniqueid="ps7_sd0_Response1">
    <name>Response</name>
    <desc>Response register</desc>
  </register>
  <register offset="0xe0100018" type="ro" uniqueid="ps7_sd0_Response2">
    <name>Response</name>
    <desc>Response register</desc>
  </register>
  <register offset="0xe010001c" type="ro" uniqueid="ps7_sd0_Response3">
    <name>Response</name>
    <desc>Response register</desc>
  </register>
  <register offset="0xe0100020" type="rw" uniqueid="ps7_sd0_Buffer_Data_Port">
    <name>Buffer_Data_Port</name>
    <desc>Buffer data port register</desc>
  </register>
  <register offset="0xe0100024" type="ro" uniqueid="ps7_sd0_Present_State">
    <name>Present_State</name>
    <desc>Present State register</desc>
  </register>
  <register offset="0xe0100028" type="rw" uniqueid="ps7_sd0_Host_control_Power_control_Block_Gap_Control_Wakeup_control">
    <name>Host_control_Power_control_Block_Gap_Control_Wakeup_control</name>
    <desc>Host control register
Power control register
Block gap control register
Wake-up control register</desc>
  </register>
  <register offset="0xe010002c" type="rw" uniqueid="ps7_sd0_Clock_Control_Timeout_control_Software_reset">
    <name>Clock_Control_Timeout_control_Software_reset</name>
    <desc>Clock Control register
Timeout control register
Software reset register</desc>
  </register>
  <register offset="0xe0100030" type="rw" uniqueid="ps7_sd0_Normal_interrupt_status_Error_interrupt_status">
    <name>Normal_interrupt_status_Error_interrupt_status</name>
    <desc>Normal interrupt status register
Error interrupt status register</desc>
  </register>
  <register offset="0xe0100034" type="rw" uniqueid="ps7_sd0_Normal_interrupt_status_enable_Error_interrupt_status_enable">
    <name>Normal_interrupt_status_enable_Error_interrupt_status_enable</name>
    <desc>Normal interrupt status enable register
Error interrupt status enable register</desc>
  </register>
  <register offset="0xe0100038" type="rw" uniqueid="ps7_sd0_Normal_interrupt_signal_enable_Error_interrupt_signal_enable">
    <name>Normal_interrupt_signal_enable_Error_interrupt_signal_enable</name>
    <desc>Normal interrupt signal enable register
Error interrupt signal enable register</desc>
  </register>
  <register offset="0xe010003c" type="ro" uniqueid="ps7_sd0_Auto_CMD12_error_status">
    <name>Auto_CMD12_error_status</name>
    <desc>Auto CMD12 error status register</desc>
  </register>
  <register offset="0xe0100040" type="ro" uniqueid="ps7_sd0_Capabilities">
    <name>Capabilities</name>
    <desc>Capabilities register</desc>
  </register>
  <register offset="0xe0100048" type="ro" uniqueid="ps7_sd0_Maximum_current_capabilities">
    <name>Maximum_current_capabilities</name>
    <desc>Maximum current capabilities register</desc>
  </register>
  <register offset="0xe0100050" type="rw" uniqueid="ps7_sd0_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status">
    <name>Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status</name>
    <desc>Force event register for Auto CMD12 error status register
Force event register for error interrupt status</desc>
  </register>
  <register offset="0xe0100054" type="rw" uniqueid="ps7_sd0_ADMA_error_status">
    <name>ADMA_error_status</name>
    <desc>ADMA error status register</desc>
  </register>
  <register offset="0xe0100058" type="rw" uniqueid="ps7_sd0_ADMA_system_address">
    <name>ADMA_system_address</name>
    <desc>ADMA system address register</desc>
  </register>
  <register offset="0xe0100060" type="rw" uniqueid="ps7_sd0_Boot_Timeout_control">
    <name>Boot_Timeout_control</name>
    <desc>Boot Timeout control register</desc>
  </register>
  <register offset="0xe0100064" type="wo" uniqueid="ps7_sd0_Debug_Selection">
    <name>Debug_Selection</name>
    <desc>Debug Selection Register</desc>
  </register>
  <register offset="0xe01000f0" type="rw" uniqueid="ps7_sd0_SPI_interrupt_support">
    <name>SPI_interrupt_support</name>
    <desc>SPI interrupt support register</desc>
  </register>
  <register offset="0xe01000fc" type="ro" uniqueid="ps7_sd0_Slot_interrupt_status_Host_controller_version">
    <name>Slot_interrupt_status_Host_controller_version</name>
    <desc>Slot interrupt status register and
Host controller version register</desc>
  </register>
  <register offset="0xf8803000" type="rw" uniqueid="ps7_debug_tpiu_SuppSize">
    <name>SuppSize</name>
    <desc>Supported Port Size Register</desc>
  </register>
  <register offset="0xf8803004" type="rw" uniqueid="ps7_debug_tpiu_CurrentSize">
    <name>CurrentSize</name>
    <desc>Current Port Size Register</desc>
  </register>
  <register offset="0xf8803100" type="ro" uniqueid="ps7_debug_tpiu_SuppTrigMode">
    <name>SuppTrigMode</name>
    <desc>Supported Trigger Modes Register</desc>
  </register>
  <register offset="0xf8803104" type="rw" uniqueid="ps7_debug_tpiu_TrigCount">
    <name>TrigCount</name>
    <desc>Trigger Counter Register</desc>
  </register>
  <register offset="0xf8803108" type="rw" uniqueid="ps7_debug_tpiu_TrigMult">
    <name>TrigMult</name>
    <desc>Trigger Multiplier Register</desc>
  </register>
  <register offset="0xf8803200" type="ro" uniqueid="ps7_debug_tpiu_SuppTest">
    <name>SuppTest</name>
    <desc>Supported Test Patterns/Modes Register</desc>
  </register>
  <register offset="0xf8803204" type="rw" uniqueid="ps7_debug_tpiu_CurrentTest">
    <name>CurrentTest</name>
    <desc>Current Test Patterns/Modes Register
Only one of the modes can be set using bits 17-16, but a multiple number of bits for the patterns can be set using bits 3-0.</desc>
  </register>
  <register offset="0xf8803208" type="rw" uniqueid="ps7_debug_tpiu_TestRepeatCount">
    <name>TestRepeatCount</name>
    <desc>TPIU Test Pattern Repeat Counter Register</desc>
  </register>
  <register offset="0xf8803300" type="ro" uniqueid="ps7_debug_tpiu_FFSR">
    <name>FFSR</name>
    <desc>Formatter and Flush Status Register</desc>
  </register>
  <register offset="0xf8803304" type="rw" uniqueid="ps7_debug_tpiu_FFCR">
    <name>FFCR</name>
    <desc>Formatter and Flush Control Register</desc>
  </register>
  <register offset="0xf8803308" type="rw" uniqueid="ps7_debug_tpiu_FormatSyncCount">
    <name>FormatSyncCount</name>
    <desc>Formatter Synchronization Counter Register</desc>
  </register>
  <register offset="0xf8803400" type="ro" uniqueid="ps7_debug_tpiu_EXTCTLIn">
    <name>EXTCTLIn</name>
    <desc>EXTCTL In Port</desc>
  </register>
  <register offset="0xf8803404" type="rw" uniqueid="ps7_debug_tpiu_EXTCTLOut">
    <name>EXTCTLOut</name>
    <desc>EXTCTL Out Port</desc>
  </register>
  <register offset="0xf8803ee4" type="wo" uniqueid="ps7_debug_tpiu_ITTRFLINACK">
    <name>ITTRFLINACK</name>
    <desc>Integration Test Trigger In and Flush In Acknowledge Register</desc>
  </register>
  <register offset="0xf8803ee8" type="ro" uniqueid="ps7_debug_tpiu_ITTRFLIN">
    <name>ITTRFLIN</name>
    <desc>Integration Test Trigger In and Flush In Register</desc>
  </register>
  <register offset="0xf8803eec" type="ro" uniqueid="ps7_debug_tpiu_ITATBDATA0">
    <name>ITATBDATA0</name>
    <desc>Integration Test ATB Data Register 0</desc>
  </register>
  <register offset="0xf8803ef0" type="wo" uniqueid="ps7_debug_tpiu_ITATBCTR2">
    <name>ITATBCTR2</name>
    <desc>Integration Test ATB Control Register 2</desc>
  </register>
  <register offset="0xf8803ef4" type="ro" uniqueid="ps7_debug_tpiu_ITATBCTR1">
    <name>ITATBCTR1</name>
    <desc>Integration Test ATB Control Register 1</desc>
  </register>
  <register offset="0xf8803ef8" type="ro" uniqueid="ps7_debug_tpiu_ITATBCTR0">
    <name>ITATBCTR0</name>
    <desc>Integration Test ATB Control Register 0</desc>
  </register>
  <register offset="0xf8803f00" type="rw" uniqueid="ps7_debug_tpiu_IMCR">
    <name>IMCR</name>
    <desc>Integration Mode Control Register</desc>
  </register>
  <register offset="0xf8803fa0" type="rw" uniqueid="ps7_debug_tpiu_CTSR">
    <name>CTSR</name>
    <desc>Claim Tag Set Register</desc>
  </register>
  <register offset="0xf8803fa4" type="rw" uniqueid="ps7_debug_tpiu_CTCR">
    <name>CTCR</name>
    <desc>Claim Tag Clear Register</desc>
  </register>
  <register offset="0xf8803fb0" type="wo" uniqueid="ps7_debug_tpiu_LAR">
    <name>LAR</name>
    <desc>Lock Access Register</desc>
  </register>
  <register offset="0xf8803fb4" type="ro" uniqueid="ps7_debug_tpiu_LSR">
    <name>LSR</name>
    <desc>Lock Status Register</desc>
  </register>
  <register offset="0xf8803fb8" type="ro" uniqueid="ps7_debug_tpiu_ASR">
    <name>ASR</name>
    <desc>Authentication Status Register</desc>
  </register>
  <register offset="0xf8803fc8" type="ro" uniqueid="ps7_debug_tpiu_DEVID">
    <name>DEVID</name>
    <desc>Device ID</desc>
  </register>
  <register offset="0xf8803fcc" type="ro" uniqueid="ps7_debug_tpiu_DTIR">
    <name>DTIR</name>
    <desc>Device Type Identifier Register</desc>
  </register>
  <register offset="0xf8803fd0" type="ro" uniqueid="ps7_debug_tpiu_PERIPHID4">
    <name>PERIPHID4</name>
    <desc>Peripheral ID4</desc>
  </register>
  <register offset="0xf8803fd4" type="ro" uniqueid="ps7_debug_tpiu_PERIPHID5">
    <name>PERIPHID5</name>
    <desc>Peripheral ID5</desc>
  </register>
  <register offset="0xf8803fd8" type="ro" uniqueid="ps7_debug_tpiu_PERIPHID6">
    <name>PERIPHID6</name>
    <desc>Peripheral ID6</desc>
  </register>
  <register offset="0xf8803fdc" type="ro" uniqueid="ps7_debug_tpiu_PERIPHID7">
    <name>PERIPHID7</name>
    <desc>Peripheral ID7</desc>
  </register>
  <register offset="0xf8803fe0" type="ro" uniqueid="ps7_debug_tpiu_PERIPHID0">
    <name>PERIPHID0</name>
    <desc>Peripheral ID0</desc>
  </register>
  <register offset="0xf8803fe4" type="ro" uniqueid="ps7_debug_tpiu_PERIPHID1">
    <name>PERIPHID1</name>
    <desc>Peripheral ID1</desc>
  </register>
  <register offset="0xf8803fe8" type="ro" uniqueid="ps7_debug_tpiu_PERIPHID2">
    <name>PERIPHID2</name>
    <desc>Peripheral ID2</desc>
  </register>
  <register offset="0xf8803fec" type="ro" uniqueid="ps7_debug_tpiu_PERIPHID3">
    <name>PERIPHID3</name>
    <desc>Peripheral ID3</desc>
  </register>
  <register offset="0xf8803ff0" type="ro" uniqueid="ps7_debug_tpiu_COMPID0">
    <name>COMPID0</name>
    <desc>Component ID0</desc>
  </register>
  <register offset="0xf8803ff4" type="ro" uniqueid="ps7_debug_tpiu_COMPID1">
    <name>COMPID1</name>
    <desc>Component ID1</desc>
  </register>
  <register offset="0xf8803ff8" type="ro" uniqueid="ps7_debug_tpiu_COMPID2">
    <name>COMPID2</name>
    <desc>Component ID2</desc>
  </register>
  <register offset="0xf8803ffc" type="ro" uniqueid="ps7_debug_tpiu_COMPID3">
    <name>COMPID3</name>
    <desc>Component ID3</desc>
  </register>
  <register offset="0xf880b000" type="rw" uniqueid="ps7_debug_ftm_FTMGLBCTRL">
    <name>FTMGLBCTRL</name>
    <desc>FTM Global Control Register</desc>
  </register>
  <register offset="0xf880b004" type="ro" uniqueid="ps7_debug_ftm_FTMSTATUS">
    <name>FTMSTATUS</name>
    <desc>FTM Status Register</desc>
  </register>
  <register offset="0xf880b008" type="rw" uniqueid="ps7_debug_ftm_FTMCONTROL">
    <name>FTMCONTROL</name>
    <desc>FTM Configuration</desc>
  </register>
  <register offset="0xf880b00c" type="rw" uniqueid="ps7_debug_ftm_FTMP2FDBG0">
    <name>FTMP2FDBG0</name>
    <desc>FPGA Debug Register P2F0</desc>
  </register>
  <register offset="0xf880b010" type="rw" uniqueid="ps7_debug_ftm_FTMP2FDBG1">
    <name>FTMP2FDBG1</name>
    <desc>FPGA Debug Register P2F1</desc>
  </register>
  <register offset="0xf880b014" type="rw" uniqueid="ps7_debug_ftm_FTMP2FDBG2">
    <name>FTMP2FDBG2</name>
    <desc>FPGA Debug Register P2F2</desc>
  </register>
  <register offset="0xf880b018" type="rw" uniqueid="ps7_debug_ftm_FTMP2FDBG3">
    <name>FTMP2FDBG3</name>
    <desc>FPGA Debug Register P2F3</desc>
  </register>
  <register offset="0xf880b01c" type="ro" uniqueid="ps7_debug_ftm_FTMF2PDBG0">
    <name>FTMF2PDBG0</name>
    <desc>FPGA Debug Register F2P0</desc>
  </register>
  <register offset="0xf880b020" type="ro" uniqueid="ps7_debug_ftm_FTMF2PDBG1">
    <name>FTMF2PDBG1</name>
    <desc>FPGA Debug Register F2P1</desc>
  </register>
  <register offset="0xf880b024" type="ro" uniqueid="ps7_debug_ftm_FTMF2PDBG2">
    <name>FTMF2PDBG2</name>
    <desc>FPGA Debug Register F2P2</desc>
  </register>
  <register offset="0xf880b028" type="ro" uniqueid="ps7_debug_ftm_FTMF2PDBG3">
    <name>FTMF2PDBG3</name>
    <desc>FPGA Debug Register F2P3</desc>
  </register>
  <register offset="0xf880b02c" type="rw" uniqueid="ps7_debug_ftm_CYCOUNTPRE">
    <name>CYCOUNTPRE</name>
    <desc>AXI Cycle Count clock pre-scaler</desc>
  </register>
  <register offset="0xf880b030" type="rw" uniqueid="ps7_debug_ftm_FTMSYNCRELOAD">
    <name>FTMSYNCRELOAD</name>
    <desc>FTM Synchronization Counter reload value</desc>
  </register>
  <register offset="0xf880b034" type="ro" uniqueid="ps7_debug_ftm_FTMSYNCCOUT">
    <name>FTMSYNCCOUT</name>
    <desc>FTM Synchronization Counter value</desc>
  </register>
  <register offset="0xf880b400" type="rw" uniqueid="ps7_debug_ftm_FTMATID">
    <name>FTMATID</name>
    <desc>FTM ATID Value Register</desc>
  </register>
  <register offset="0xf880bed0" type="ro" uniqueid="ps7_debug_ftm_FTMITTRIGOUTACK">
    <name>FTMITTRIGOUTACK</name>
    <desc>Trigger Output Acknowledge Integration Test Register</desc>
  </register>
  <register offset="0xf880bed4" type="wo" uniqueid="ps7_debug_ftm_FTMITTRIGGER">
    <name>FTMITTRIGGER</name>
    <desc>Trigger Output Integration Test Register</desc>
  </register>
  <register offset="0xf880bed8" type="ro" uniqueid="ps7_debug_ftm_FTMITTRACEDIS">
    <name>FTMITTRACEDIS</name>
    <desc>External Trace Disable Integration Test Register</desc>
  </register>
  <register offset="0xf880bedc" type="rw" uniqueid="ps7_debug_ftm_FTMITCYCCOUNT">
    <name>FTMITCYCCOUNT</name>
    <desc>Cycle Counter Test Register</desc>
  </register>
  <register offset="0xf880beec" type="wo" uniqueid="ps7_debug_ftm_FTMITATBDATA0">
    <name>FTMITATBDATA0</name>
    <desc>ATB Data Integration Test Register 0</desc>
  </register>
  <register offset="0xf880bef0" type="ro" uniqueid="ps7_debug_ftm_FTMITATBCTR2">
    <name>FTMITATBCTR2</name>
    <desc>ATB Control Integration Test Register 2</desc>
  </register>
  <register offset="0xf880bef4" type="rw" uniqueid="ps7_debug_ftm_FTMITATBCTR1">
    <name>FTMITATBCTR1</name>
    <desc>ATB Control Integration Test Register 1</desc>
  </register>
  <register offset="0xf880bef8" type="wo" uniqueid="ps7_debug_ftm_FTMITATBCTR0">
    <name>FTMITATBCTR0</name>
    <desc>ATB Control Integration Test Register 0</desc>
  </register>
  <register offset="0xf880bf00" type="rw" uniqueid="ps7_debug_ftm_FTMITCR">
    <name>FTMITCR</name>
    <desc>FTM Test Control Register</desc>
  </register>
  <register offset="0xf880bfa0" type="rw" uniqueid="ps7_debug_ftm_CLAIMTAGSET">
    <name>CLAIMTAGSET</name>
    <desc>Claim Tag Set Register</desc>
  </register>
  <register offset="0xf880bfa4" type="rw" uniqueid="ps7_debug_ftm_CLAIMTAGCLR">
    <name>CLAIMTAGCLR</name>
    <desc>Claim Tag Clear Register</desc>
  </register>
  <register offset="0xf880bfb0" type="wo" uniqueid="ps7_debug_ftm_LOCK_ACCESS">
    <name>LOCK_ACCESS</name>
    <desc>Lock Access Register</desc>
  </register>
  <register offset="0xf880bfb4" type="ro" uniqueid="ps7_debug_ftm_LOCK_STATUS">
    <name>LOCK_STATUS</name>
    <desc>Lock Status Register</desc>
  </register>
  <register offset="0xf880bfb8" type="ro" uniqueid="ps7_debug_ftm_FTMAUTHSTATUS">
    <name>FTMAUTHSTATUS</name>
    <desc>Authentication Status Register</desc>
  </register>
  <register offset="0xf880bfc8" type="ro" uniqueid="ps7_debug_ftm_FTMDEVID">
    <name>FTMDEVID</name>
    <desc>Device Configuration Register</desc>
  </register>
  <register offset="0xf880bfcc" type="ro" uniqueid="ps7_debug_ftm_FTMDEV_TYPE">
    <name>FTMDEV_TYPE</name>
    <desc>Device Type Identification Register</desc>
  </register>
  <register offset="0xf880bfd0" type="ro" uniqueid="ps7_debug_ftm_FTMPERIPHID4">
    <name>FTMPERIPHID4</name>
    <desc>Peripheral ID4</desc>
  </register>
  <register offset="0xf880bfd4" type="ro" uniqueid="ps7_debug_ftm_FTMPERIPHID5">
    <name>FTMPERIPHID5</name>
    <desc>Peripheral ID5</desc>
  </register>
  <register offset="0xf880bfd8" type="ro" uniqueid="ps7_debug_ftm_FTMPERIPHID6">
    <name>FTMPERIPHID6</name>
    <desc>Peripheral ID6</desc>
  </register>
  <register offset="0xf880bfdc" type="ro" uniqueid="ps7_debug_ftm_FTMPERIPHID7">
    <name>FTMPERIPHID7</name>
    <desc>Peripheral ID7</desc>
  </register>
  <register offset="0xf880bfe0" type="ro" uniqueid="ps7_debug_ftm_FTMPERIPHID0">
    <name>FTMPERIPHID0</name>
    <desc>Peripheral ID0</desc>
  </register>
  <register offset="0xf880bfe4" type="ro" uniqueid="ps7_debug_ftm_FTMPERIPHID1">
    <name>FTMPERIPHID1</name>
    <desc>Peripheral ID1</desc>
  </register>
  <register offset="0xf880bfe8" type="ro" uniqueid="ps7_debug_ftm_FTMPERIPHID2">
    <name>FTMPERIPHID2</name>
    <desc>Peripheral ID2</desc>
  </register>
  <register offset="0xf880bfec" type="ro" uniqueid="ps7_debug_ftm_FTMPERIPHID3">
    <name>FTMPERIPHID3</name>
    <desc>Peripheral ID3</desc>
  </register>
  <register offset="0xf880bff0" type="ro" uniqueid="ps7_debug_ftm_FTMCOMPONID0">
    <name>FTMCOMPONID0</name>
    <desc>Component ID0</desc>
  </register>
  <register offset="0xf880bff4" type="ro" uniqueid="ps7_debug_ftm_FTMCOMPONID1">
    <name>FTMCOMPONID1</name>
    <desc>Component ID1</desc>
  </register>
  <register offset="0xf880bff8" type="ro" uniqueid="ps7_debug_ftm_FTMCOMPONID2">
    <name>FTMCOMPONID2</name>
    <desc>Component ID2</desc>
  </register>
  <register offset="0xf880bffc" type="ro" uniqueid="ps7_debug_ftm_FTMCOMPONID3">
    <name>FTMCOMPONID3</name>
    <desc>Component ID3</desc>
  </register>
  <register offset="0xf800a000" type="rw" uniqueid="ps7_afi2_AFI_RDCHAN_CTRL">
    <name>AFI_RDCHAN_CTRL</name>
    <desc>Read Channel Control Register: Control fields for Read Channel operation</desc>
  </register>
  <register offset="0xf800a004" type="rw" uniqueid="ps7_afi2_AFI_RDCHAN_ISSUINGCAP">
    <name>AFI_RDCHAN_ISSUINGCAP</name>
    <desc>Read Issuing Capability Register: Sets the maximum number of Outstanding Read Commands allowed (Issuing Capability). Refers to the commands that can be outstanding from the AFI to the SAM switch and back. Fields are selected by the 'axds_rdissuecap1_en' input.</desc>
  </register>
  <register offset="0xf800a008" type="rw" uniqueid="ps7_afi2_AFI_RDQOS">
    <name>AFI_RDQOS</name>
    <desc>QOS Read Channel Register: Sets the static Qos value to be used for the read channel. If APB register field, 'FabricQosEn' is 0 or ('FabricQosEn' is 1 and 'QosHeadOfCmdQEn' is 1), this static Qos value will be applied to all read commands enqueued into the RdCmdQ. If ('FabricQosEn' is 1 and 'QosHeadOfCmdQEn' is 0), this static Qos field will be ignored.</desc>
  </register>
  <register offset="0xf800a00c" type="rw" uniqueid="ps7_afi2_AFI_RDDATAFIFO_LEVEL">
    <name>AFI_RDDATAFIFO_LEVEL</name>
    <desc>Read Data FIFO Level Register:Returns the Level of the Read Data FIFO in Qwords</desc>
  </register>
  <register offset="0xf800a010" type="rw" uniqueid="ps7_afi2_AFI_RDDEBUG">
    <name>AFI_RDDEBUG</name>
    <desc>Read Channel Debug Register: Miscellaneous debug fields for the Read channel. Not to be used for functional purposes.</desc>
  </register>
  <register offset="0xf800a014" type="rw" uniqueid="ps7_afi2_AFI_WRCHAN_CTRL">
    <name>AFI_WRCHAN_CTRL</name>
    <desc>Write Channel Control Register: Control fields for Write Channel operation</desc>
  </register>
  <register offset="0xf800a018" type="rw" uniqueid="ps7_afi2_AFI_WRCHAN_ISSUINGCAP">
    <name>AFI_WRCHAN_ISSUINGCAP</name>
    <desc>Write Issuing Capability Register: Sets the maximum number of Outstanding Write Commands (Issuing Capability) allowed. Refers to the commands that can be outstanding from the AFI to the SAM switch and back. Fields are selected by the 'axds_wrissuecap1_en' input.</desc>
  </register>
  <register offset="0xf800a01c" type="rw" uniqueid="ps7_afi2_AFI_WRQOS">
    <name>AFI_WRQOS</name>
    <desc>QOS Write Channel Register: Sets the static Qos value to be used for the write channel. If APB register field, 'FabricQosEn' is 0 or ('FabricQosEn' is 1 and 'QosHeadOfCmdQEn' is 1), this static Qos value will be applied to all write commands enqueued into the WrCmdQ. If ('FabricQosEn' is 1 and 'QosHeadOfCmdQEn' is 0), this static Qos field will be ignored.</desc>
  </register>
  <register offset="0xf800a020" type="rw" uniqueid="ps7_afi2_AFI_WRDATAFIFO_LEVEL">
    <name>AFI_WRDATAFIFO_LEVEL</name>
    <desc>Write Data FIFO Level Register: Returns the Level of the Write Data FIFO in Dwords</desc>
  </register>
  <register offset="0xf800a024" type="rw" uniqueid="ps7_afi2_AFI_WRDEBUG">
    <name>AFI_WRDEBUG</name>
    <desc>Write Channel Debug Register</desc>
  </register>
  <register offset="0xf8009000" type="rw" uniqueid="ps7_afi1_AFI_RDCHAN_CTRL">
    <name>AFI_RDCHAN_CTRL</name>
    <desc>Read Channel Control Register: Control fields for Read Channel operation</desc>
  </register>
  <register offset="0xf8009004" type="rw" uniqueid="ps7_afi1_AFI_RDCHAN_ISSUINGCAP">
    <name>AFI_RDCHAN_ISSUINGCAP</name>
    <desc>Read Issuing Capability Register: Sets the maximum number of Outstanding Read Commands allowed (Issuing Capability). Refers to the commands that can be outstanding from the AFI to the SAM switch and back. Fields are selected by the 'axds_rdissuecap1_en' input.</desc>
  </register>
  <register offset="0xf8009008" type="rw" uniqueid="ps7_afi1_AFI_RDQOS">
    <name>AFI_RDQOS</name>
    <desc>QOS Read Channel Register: Sets the static Qos value to be used for the read channel. If APB register field, 'FabricQosEn' is 0 or ('FabricQosEn' is 1 and 'QosHeadOfCmdQEn' is 1), this static Qos value will be applied to all read commands enqueued into the RdCmdQ. If ('FabricQosEn' is 1 and 'QosHeadOfCmdQEn' is 0), this static Qos field will be ignored.</desc>
  </register>
  <register offset="0xf800900c" type="rw" uniqueid="ps7_afi1_AFI_RDDATAFIFO_LEVEL">
    <name>AFI_RDDATAFIFO_LEVEL</name>
    <desc>Read Data FIFO Level Register:Returns the Level of the Read Data FIFO in Qwords</desc>
  </register>
  <register offset="0xf8009010" type="rw" uniqueid="ps7_afi1_AFI_RDDEBUG">
    <name>AFI_RDDEBUG</name>
    <desc>Read Channel Debug Register: Miscellaneous debug fields for the Read channel. Not to be used for functional purposes.</desc>
  </register>
  <register offset="0xf8009014" type="rw" uniqueid="ps7_afi1_AFI_WRCHAN_CTRL">
    <name>AFI_WRCHAN_CTRL</name>
    <desc>Write Channel Control Register: Control fields for Write Channel operation</desc>
  </register>
  <register offset="0xf8009018" type="rw" uniqueid="ps7_afi1_AFI_WRCHAN_ISSUINGCAP">
    <name>AFI_WRCHAN_ISSUINGCAP</name>
    <desc>Write Issuing Capability Register: Sets the maximum number of Outstanding Write Commands (Issuing Capability) allowed. Refers to the commands that can be outstanding from the AFI to the SAM switch and back. Fields are selected by the 'axds_wrissuecap1_en' input.</desc>
  </register>
  <register offset="0xf800901c" type="rw" uniqueid="ps7_afi1_AFI_WRQOS">
    <name>AFI_WRQOS</name>
    <desc>QOS Write Channel Register: Sets the static Qos value to be used for the write channel. If APB register field, 'FabricQosEn' is 0 or ('FabricQosEn' is 1 and 'QosHeadOfCmdQEn' is 1), this static Qos value will be applied to all write commands enqueued into the WrCmdQ. If ('FabricQosEn' is 1 and 'QosHeadOfCmdQEn' is 0), this static Qos field will be ignored.</desc>
  </register>
  <register offset="0xf8009020" type="rw" uniqueid="ps7_afi1_AFI_WRDATAFIFO_LEVEL">
    <name>AFI_WRDATAFIFO_LEVEL</name>
    <desc>Write Data FIFO Level Register: Returns the Level of the Write Data FIFO in Dwords</desc>
  </register>
  <register offset="0xf8009024" type="rw" uniqueid="ps7_afi1_AFI_WRDEBUG">
    <name>AFI_WRDEBUG</name>
    <desc>Write Channel Debug Register</desc>
  </register>
  <register offset="0xf800b000" type="rw" uniqueid="ps7_afi3_AFI_RDCHAN_CTRL">
    <name>AFI_RDCHAN_CTRL</name>
    <desc>Read Channel Control Register: Control fields for Read Channel operation</desc>
  </register>
  <register offset="0xf800b004" type="rw" uniqueid="ps7_afi3_AFI_RDCHAN_ISSUINGCAP">
    <name>AFI_RDCHAN_ISSUINGCAP</name>
    <desc>Read Issuing Capability Register: Sets the maximum number of Outstanding Read Commands allowed (Issuing Capability). Refers to the commands that can be outstanding from the AFI to the SAM switch and back. Fields are selected by the 'axds_rdissuecap1_en' input.</desc>
  </register>
  <register offset="0xf800b008" type="rw" uniqueid="ps7_afi3_AFI_RDQOS">
    <name>AFI_RDQOS</name>
    <desc>QOS Read Channel Register: Sets the static Qos value to be used for the read channel. If APB register field, 'FabricQosEn' is 0 or ('FabricQosEn' is 1 and 'QosHeadOfCmdQEn' is 1), this static Qos value will be applied to all read commands enqueued into the RdCmdQ. If ('FabricQosEn' is 1 and 'QosHeadOfCmdQEn' is 0), this static Qos field will be ignored.</desc>
  </register>
  <register offset="0xf800b00c" type="rw" uniqueid="ps7_afi3_AFI_RDDATAFIFO_LEVEL">
    <name>AFI_RDDATAFIFO_LEVEL</name>
    <desc>Read Data FIFO Level Register:Returns the Level of the Read Data FIFO in Qwords</desc>
  </register>
  <register offset="0xf800b010" type="rw" uniqueid="ps7_afi3_AFI_RDDEBUG">
    <name>AFI_RDDEBUG</name>
    <desc>Read Channel Debug Register: Miscellaneous debug fields for the Read channel. Not to be used for functional purposes.</desc>
  </register>
  <register offset="0xf800b014" type="rw" uniqueid="ps7_afi3_AFI_WRCHAN_CTRL">
    <name>AFI_WRCHAN_CTRL</name>
    <desc>Write Channel Control Register: Control fields for Write Channel operation</desc>
  </register>
  <register offset="0xf800b018" type="rw" uniqueid="ps7_afi3_AFI_WRCHAN_ISSUINGCAP">
    <name>AFI_WRCHAN_ISSUINGCAP</name>
    <desc>Write Issuing Capability Register: Sets the maximum number of Outstanding Write Commands (Issuing Capability) allowed. Refers to the commands that can be outstanding from the AFI to the SAM switch and back. Fields are selected by the 'axds_wrissuecap1_en' input.</desc>
  </register>
  <register offset="0xf800b01c" type="rw" uniqueid="ps7_afi3_AFI_WRQOS">
    <name>AFI_WRQOS</name>
    <desc>QOS Write Channel Register: Sets the static Qos value to be used for the write channel. If APB register field, 'FabricQosEn' is 0 or ('FabricQosEn' is 1 and 'QosHeadOfCmdQEn' is 1), this static Qos value will be applied to all write commands enqueued into the WrCmdQ. If ('FabricQosEn' is 1 and 'QosHeadOfCmdQEn' is 0), this static Qos field will be ignored.</desc>
  </register>
  <register offset="0xf800b020" type="rw" uniqueid="ps7_afi3_AFI_WRDATAFIFO_LEVEL">
    <name>AFI_WRDATAFIFO_LEVEL</name>
    <desc>Write Data FIFO Level Register: Returns the Level of the Write Data FIFO in Dwords</desc>
  </register>
  <register offset="0xf800b024" type="rw" uniqueid="ps7_afi3_AFI_WRDEBUG">
    <name>AFI_WRDEBUG</name>
    <desc>Write Channel Debug Register</desc>
  </register>
  <register offset="0xf8008000" type="rw" uniqueid="ps7_afi0_AFI_RDCHAN_CTRL">
    <name>AFI_RDCHAN_CTRL</name>
    <desc>Read Channel Control Register: Control fields for Read Channel operation</desc>
  </register>
  <register offset="0xf8008004" type="rw" uniqueid="ps7_afi0_AFI_RDCHAN_ISSUINGCAP">
    <name>AFI_RDCHAN_ISSUINGCAP</name>
    <desc>Read Issuing Capability Register: Sets the maximum number of Outstanding Read Commands allowed (Issuing Capability). Refers to the commands that can be outstanding from the AFI to the SAM switch and back. Fields are selected by the 'axds_rdissuecap1_en' input.</desc>
  </register>
  <register offset="0xf8008008" type="rw" uniqueid="ps7_afi0_AFI_RDQOS">
    <name>AFI_RDQOS</name>
    <desc>QOS Read Channel Register: Sets the static Qos value to be used for the read channel. If APB register field, 'FabricQosEn' is 0 or ('FabricQosEn' is 1 and 'QosHeadOfCmdQEn' is 1), this static Qos value will be applied to all read commands enqueued into the RdCmdQ. If ('FabricQosEn' is 1 and 'QosHeadOfCmdQEn' is 0), this static Qos field will be ignored.</desc>
  </register>
  <register offset="0xf800800c" type="rw" uniqueid="ps7_afi0_AFI_RDDATAFIFO_LEVEL">
    <name>AFI_RDDATAFIFO_LEVEL</name>
    <desc>Read Data FIFO Level Register:Returns the Level of the Read Data FIFO in Qwords</desc>
  </register>
  <register offset="0xf8008010" type="rw" uniqueid="ps7_afi0_AFI_RDDEBUG">
    <name>AFI_RDDEBUG</name>
    <desc>Read Channel Debug Register: Miscellaneous debug fields for the Read channel. Not to be used for functional purposes.</desc>
  </register>
  <register offset="0xf8008014" type="rw" uniqueid="ps7_afi0_AFI_WRCHAN_CTRL">
    <name>AFI_WRCHAN_CTRL</name>
    <desc>Write Channel Control Register: Control fields for Write Channel operation</desc>
  </register>
  <register offset="0xf8008018" type="rw" uniqueid="ps7_afi0_AFI_WRCHAN_ISSUINGCAP">
    <name>AFI_WRCHAN_ISSUINGCAP</name>
    <desc>Write Issuing Capability Register: Sets the maximum number of Outstanding Write Commands (Issuing Capability) allowed. Refers to the commands that can be outstanding from the AFI to the SAM switch and back. Fields are selected by the 'axds_wrissuecap1_en' input.</desc>
  </register>
  <register offset="0xf800801c" type="rw" uniqueid="ps7_afi0_AFI_WRQOS">
    <name>AFI_WRQOS</name>
    <desc>QOS Write Channel Register: Sets the static Qos value to be used for the write channel. If APB register field, 'FabricQosEn' is 0 or ('FabricQosEn' is 1 and 'QosHeadOfCmdQEn' is 1), this static Qos value will be applied to all write commands enqueued into the WrCmdQ. If ('FabricQosEn' is 1 and 'QosHeadOfCmdQEn' is 0), this static Qos field will be ignored.</desc>
  </register>
  <register offset="0xf8008020" type="rw" uniqueid="ps7_afi0_AFI_WRDATAFIFO_LEVEL">
    <name>AFI_WRDATAFIFO_LEVEL</name>
    <desc>Write Data FIFO Level Register: Returns the Level of the Write Data FIFO in Dwords</desc>
  </register>
  <register offset="0xf8008024" type="rw" uniqueid="ps7_afi0_AFI_WRDEBUG">
    <name>AFI_WRDEBUG</name>
    <desc>Write Channel Debug Register</desc>
  </register>
  <register offset="0xe0002000" type="ro" uniqueid="ps7_usb0_ID">
    <name>ID</name>
    <desc>The ID register identifies the USB-HS 2.0 core and its revision</desc>
  </register>
  <register offset="0xe0002004" type="ro" uniqueid="ps7_usb0_HWGENERAL">
    <name>HWGENERAL</name>
    <desc>General hardware parameters as defined in configuration file.</desc>
  </register>
  <register offset="0xe0002008" type="ro" uniqueid="ps7_usb0_HWHOST">
    <name>HWHOST</name>
    <desc>Host hardware parameters as defined in configuration file</desc>
  </register>
  <register offset="0xe000200c" type="ro" uniqueid="ps7_usb0_HWDEVICE">
    <name>HWDEVICE</name>
    <desc>Device hardware parameters as defined in configuration file.</desc>
  </register>
  <register offset="0xe0002010" type="ro" uniqueid="ps7_usb0_HWTXBUF">
    <name>HWTXBUF</name>
    <desc>TX buffer hardware parameters as defined in configuration file</desc>
  </register>
  <register offset="0xe0002014" type="ro" uniqueid="ps7_usb0_HWRXBUF">
    <name>HWRXBUF</name>
    <desc>RX buffer hardware parameters as defined in configuration file</desc>
  </register>
  <register offset="0xe0002080" type="rw" uniqueid="ps7_usb0_GPTIMER0LD">
    <name>GPTIMER0LD</name>
    <desc>This register contains the timer duration or load value. See the GPTIMER0CTRL for a description of the
timer functions</desc>
  </register>
  <register offset="0xe0002084" type="rw" uniqueid="ps7_usb0_GPTIMER0CTRL">
    <name>GPTIMER0CTRL</name>
    <desc>This register contains the control for the timer and a data field, which can be queried to determine the running
count value.</desc>
  </register>
  <register offset="0xe0002088" type="rw" uniqueid="ps7_usb0_GPTIMER1LD">
    <name>GPTIMER1LD</name>
    <desc>This register contains the timer duration or load value. See the GPTIMER0CTRL for a description of the
timer functions</desc>
  </register>
  <register offset="0xe000208c" type="rw" uniqueid="ps7_usb0_GPTIMER1CTRL">
    <name>GPTIMER1CTRL</name>
    <desc>This register contains the control for the timer and a data field, which can be queried to determine the running
count value.</desc>
  </register>
  <register offset="0xe0002090" type="rw" uniqueid="ps7_usb0_SBUSCFG">
    <name>SBUSCFG</name>
    <desc>This register contains the control for the system bus interface (such as AMBA / BVCI Master / Slave
interfaces).</desc>
  </register>
  <register offset="0xe0002100" type="ro" uniqueid="ps7_usb0_CAPLENGTH_HCIVERSION">
    <name>CAPLENGTH_HCIVERSION</name>
    <desc>Device/Host Capability registers specify the software limits, restrictions, and capabilities of the host/device
controller implementation.</desc>
  </register>
  <register offset="0xe0002104" type="ro" uniqueid="ps7_usb0_HCSPARAMS">
    <name>HCSPARAMS</name>
    <desc>Port steering logic capabilities are described in this register.</desc>
  </register>
  <register offset="0xe0002108" type="ro" uniqueid="ps7_usb0_HCCPARAMS">
    <name>HCCPARAMS</name>
    <desc>This register identifies multiple mode control (time-base bit functionality) addressing capability</desc>
  </register>
  <register offset="0xe0002120" type="ro" uniqueid="ps7_usb0_DCIVERSION">
    <name>DCIVERSION</name>
    <desc>The device controller interface conforms to the two-byte BCD encoding of the interface version number
contained in this register.</desc>
  </register>
  <register offset="0xe0002124" type="ro" uniqueid="ps7_usb0_DCCPARAMS">
    <name>DCCPARAMS</name>
    <desc>These fields describe the overall host/device capability of the controller</desc>
  </register>
  <register offset="0xe0002140" type="rw" uniqueid="ps7_usb0_USBCMD">
    <name>USBCMD</name>
    <desc>The serial bus host/device controller executes the command indicated in this register</desc>
  </register>
  <register offset="0xe0002144" type="rw" uniqueid="ps7_usb0_USBSTS">
    <name>USBSTS</name>
    <desc>This register indicates various states of the Controller and any pending interrupts. This register does not indicate status resulting from a transaction on the serial bus.</desc>
  </register>
  <register offset="0xe0002148" type="rw" uniqueid="ps7_usb0_USBINTR">
    <name>USBINTR</name>
    <desc>The interrupts to software are enabled with this register. An interrupt is generated when a bit is set and the corresponding interrupt is active. The USB Status register (USBSTS) still shows interrupt sources even if they are disabled by the USBINTR register, allowing polling of interrupt events by the software.</desc>
  </register>
  <register offset="0xe000214c" type="rw" uniqueid="ps7_usb0_FRINDEX">
    <name>FRINDEX</name>
    <desc>This register is used by the host controller to index the periodic frame list. The register updates every 125 us (once each micro-frame).</desc>
  </register>
  <register offset="0xe0002154" type="rw" uniqueid="ps7_usb0_PERIODICLISTBASE_DEVICEADDR">
    <name>PERIODICLISTBASE_DEVICEADDR</name>
    <desc>This register is has two different uses when working in device or host mode.</desc>
  </register>
  <register offset="0xe0002158" type="rw" uniqueid="ps7_usb0_ASYNCLISTADDR_ENDPOINTLISTADDR">
    <name>ASYNCLISTADDR_ENDPOINTLISTADDR</name>
    <desc>This register is has two different uses when working in device or host mode.</desc>
  </register>
  <register offset="0xe000215c" type="rw" uniqueid="ps7_usb0_TTCTRL">
    <name>TTCTRL</name>
    <desc>This register contains parameters needed for internal TT operations.</desc>
  </register>
  <register offset="0xe0002160" type="rw" uniqueid="ps7_usb0_BURSTSIZE">
    <name>BURSTSIZE</name>
    <desc>This register controls the burst size used during data movement on the initiator/master interface.</desc>
  </register>
  <register offset="0xe0002164" type="rw" uniqueid="ps7_usb0_TXFILLTUNING">
    <name>TXFILLTUNING</name>
    <desc>The fields in this register control performance tuning associated with how the Controller posts data to the TX latency FIFO before moving the data onto the USB bus.</desc>
  </register>
  <register offset="0xe0002168" type="rw" uniqueid="ps7_usb0_TXTTFILLTUNING">
    <name>TXTTFILLTUNING</name>
    <desc>This register provides a function similar to TXFILLTUNING except there is no equivalent to TXFIFOTHRES because the TT TX latency FIFO is always loaded in a single burst. Even</desc>
  </register>
  <register offset="0xe000216c" type="rw" uniqueid="ps7_usb0_IC_USB">
    <name>IC_USB</name>
    <desc>This register enable and controls the IC_USB FS/LS transceiver.</desc>
  </register>
  <register offset="0xe0002170" type="rw" uniqueid="ps7_usb0_ULPI_VIEWPORT">
    <name>ULPI_VIEWPORT</name>
    <desc>The register provides indirect access to the ULPI PHY register set. Although the core performs access to the
ULPI PHY register set, there may be extraordinary circumstances where software may need direct access.</desc>
  </register>
  <register offset="0xe0002178" type="rw" uniqueid="ps7_usb0_ENDPTNAK">
    <name>ENDPTNAK</name>
    <desc>Only implemented in device mode.</desc>
  </register>
  <register offset="0xe000217c" type="rw" uniqueid="ps7_usb0_ENDPTNAKEN">
    <name>ENDPTNAKEN</name>
    <desc>Only implemented in device mode.</desc>
  </register>
  <register offset="0xe0002180" type="ro" uniqueid="ps7_usb0_CONFIGFLAG">
    <name>CONFIGFLAG</name>
    <desc>This register is not used in this implementation. A read from this register returns a constant of a 00000001h to indicate that all port routings default to this host controller.</desc>
  </register>
  <register offset="0xe0002184" type="rw" uniqueid="ps7_usb0_PORTSC1">
    <name>PORTSC1</name>
    <desc>The Controller implement one The number of port registers implemented by a particular instantiation is documented in the HCSPARAM register. Software uses this information as an input parameter to determine how many ports need service. This implement contains only 1 host port.</desc>
  </register>
  <register offset="0xe00021a4" type="rw" uniqueid="ps7_usb0_OTGSC">
    <name>OTGSC</name>
    <desc>The Controller implements one On-The-Go (OTG) Status and Control register.
The OTGSC register has four sections:
OTG Interrupt enables (Read/Write)
OTG Interrupt status (Read/Write to Clear)
OTG Status inputs (Read Only)
OTG Controls (Read/Write)</desc>
  </register>
  <register offset="0xe00021a8" type="rw" uniqueid="ps7_usb0_USBMODE">
    <name>USBMODE</name>
    <desc>USB Mode Selection register</desc>
  </register>
  <register offset="0xe00021ac" type="rw" uniqueid="ps7_usb0_ENDPTSETUPSTAT">
    <name>ENDPTSETUPSTAT</name>
    <desc>Only implemented in device mode.</desc>
  </register>
  <register offset="0xe00021b0" type="rw" uniqueid="ps7_usb0_ENDPTPRIME">
    <name>ENDPTPRIME</name>
    <desc>Only implemented in device mode</desc>
  </register>
  <register offset="0xe00021b4" type="rw" uniqueid="ps7_usb0_ENDPTFLUSH">
    <name>ENDPTFLUSH</name>
    <desc>The Flush operation for an endpoint will clear the Ready status of that endpoint and re-align the Latency Buffer pointers, but not clear the actual data that resides in the Latency Buffers.</desc>
  </register>
  <register offset="0xe00021b8" type="ro" uniqueid="ps7_usb0_ENDPTSTAT">
    <name>ENDPTSTAT</name>
    <desc>Only implemented in device mode.</desc>
  </register>
  <register offset="0xe00021bc" type="ro" uniqueid="ps7_usb0_ENDPTCOMPLETE">
    <name>ENDPTCOMPLETE</name>
    <desc>Only implemented in device mode.</desc>
  </register>
  <register offset="0xe00021c0" type="rw" uniqueid="ps7_usb0_ENDPTCTRL0">
    <name>ENDPTCTRL0</name>
    <desc>Every device will implement Endpoint0 as a control endpoint. Only implemented in device mode.</desc>
  </register>
  <register offset="0xe00021c4" type="rw" uniqueid="ps7_usb0_ENDPTCTRL1">
    <name>ENDPTCTRL</name>
    <desc>This is an ENDPTCTRL1 register for the endpoint 1 device. Only implemented in device mode.</desc>
  </register>
  <register offset="0xe00021c8" type="rw" uniqueid="ps7_usb0_ENDPTCTRL2">
    <name>ENDPTCTRL</name>
    <desc>This is an ENDPTCTRL1 register for the endpoint 1 device. Only implemented in device mode.</desc>
  </register>
  <register offset="0xe00021cc" type="rw" uniqueid="ps7_usb0_ENDPTCTRL3">
    <name>ENDPTCTRL</name>
    <desc>This is an ENDPTCTRL1 register for the endpoint 1 device. Only implemented in device mode.</desc>
  </register>
  <register offset="0xe00021d0" type="rw" uniqueid="ps7_usb0_ENDPTCTRL4">
    <name>ENDPTCTRL</name>
    <desc>This is an ENDPTCTRL1 register for the endpoint 1 device. Only implemented in device mode.</desc>
  </register>
  <register offset="0xe00021d4" type="rw" uniqueid="ps7_usb0_ENDPTCTRL5">
    <name>ENDPTCTRL</name>
    <desc>This is an ENDPTCTRL1 register for the endpoint 1 device. Only implemented in device mode.</desc>
  </register>
  <register offset="0xe00021d8" type="rw" uniqueid="ps7_usb0_ENDPTCTRL6">
    <name>ENDPTCTRL</name>
    <desc>This is an ENDPTCTRL1 register for the endpoint 1 device. Only implemented in device mode.</desc>
  </register>
  <register offset="0xe00021dc" type="rw" uniqueid="ps7_usb0_ENDPTCTRL7">
    <name>ENDPTCTRL</name>
    <desc>This is an ENDPTCTRL1 register for the endpoint 1 device. Only implemented in device mode.</desc>
  </register>
  <register offset="0xe00021e0" type="rw" uniqueid="ps7_usb0_ENDPTCTRL8">
    <name>ENDPTCTRL</name>
    <desc>This is an ENDPTCTRL1 register for the endpoint 1 device. Only implemented in device mode.</desc>
  </register>
  <register offset="0xe00021e4" type="rw" uniqueid="ps7_usb0_ENDPTCTRL9">
    <name>ENDPTCTRL</name>
    <desc>This is an ENDPTCTRL1 register for the endpoint 1 device. Only implemented in device mode.</desc>
  </register>
  <register offset="0xe00021e8" type="rw" uniqueid="ps7_usb0_ENDPTCTRL10">
    <name>ENDPTCTRL</name>
    <desc>This is an ENDPTCTRL1 register for the endpoint 1 device. Only implemented in device mode.</desc>
  </register>
  <register offset="0xe00021ec" type="rw" uniqueid="ps7_usb0_ENDPTCTRL11">
    <name>ENDPTCTRL</name>
    <desc>This is an ENDPTCTRL1 register for the endpoint 1 device. Only implemented in device mode.</desc>
  </register>
  <register offset="0xe00021f0" type="rw" uniqueid="ps7_usb0_ENDPTCTRL12">
    <name>ENDPTCTRL</name>
    <desc>This is an ENDPTCTRL1 register for the endpoint 1 device. Only implemented in device mode.</desc>
  </register>
  <register offset="0xe0003000" type="ro" uniqueid="ps7_usb1_ID">
    <name>ID</name>
    <desc>The ID register identifies the USB-HS 2.0 core and its revision</desc>
  </register>
  <register offset="0xe0003004" type="ro" uniqueid="ps7_usb1_HWGENERAL">
    <name>HWGENERAL</name>
    <desc>General hardware parameters as defined in configuration file.</desc>
  </register>
  <register offset="0xe0003008" type="ro" uniqueid="ps7_usb1_HWHOST">
    <name>HWHOST</name>
    <desc>Host hardware parameters as defined in configuration file</desc>
  </register>
  <register offset="0xe000300c" type="ro" uniqueid="ps7_usb1_HWDEVICE">
    <name>HWDEVICE</name>
    <desc>Device hardware parameters as defined in configuration file.</desc>
  </register>
  <register offset="0xe0003010" type="ro" uniqueid="ps7_usb1_HWTXBUF">
    <name>HWTXBUF</name>
    <desc>TX buffer hardware parameters as defined in configuration file</desc>
  </register>
  <register offset="0xe0003014" type="ro" uniqueid="ps7_usb1_HWRXBUF">
    <name>HWRXBUF</name>
    <desc>RX buffer hardware parameters as defined in configuration file</desc>
  </register>
  <register offset="0xe0003080" type="rw" uniqueid="ps7_usb1_GPTIMER0LD">
    <name>GPTIMER0LD</name>
    <desc>This register contains the timer duration or load value. See the GPTIMER0CTRL for a description of the
timer functions</desc>
  </register>
  <register offset="0xe0003084" type="rw" uniqueid="ps7_usb1_GPTIMER0CTRL">
    <name>GPTIMER0CTRL</name>
    <desc>This register contains the control for the timer and a data field, which can be queried to determine the running
count value.</desc>
  </register>
  <register offset="0xe0003088" type="rw" uniqueid="ps7_usb1_GPTIMER1LD">
    <name>GPTIMER1LD</name>
    <desc>This register contains the timer duration or load value. See the GPTIMER0CTRL for a description of the
timer functions</desc>
  </register>
  <register offset="0xe000308c" type="rw" uniqueid="ps7_usb1_GPTIMER1CTRL">
    <name>GPTIMER1CTRL</name>
    <desc>This register contains the control for the timer and a data field, which can be queried to determine the running
count value.</desc>
  </register>
  <register offset="0xe0003090" type="rw" uniqueid="ps7_usb1_SBUSCFG">
    <name>SBUSCFG</name>
    <desc>This register contains the control for the system bus interface (such as AMBA / BVCI Master / Slave
interfaces).</desc>
  </register>
  <register offset="0xe0003100" type="ro" uniqueid="ps7_usb1_CAPLENGTH_HCIVERSION">
    <name>CAPLENGTH_HCIVERSION</name>
    <desc>Device/Host Capability registers specify the software limits, restrictions, and capabilities of the host/device
controller implementation.</desc>
  </register>
  <register offset="0xe0003104" type="ro" uniqueid="ps7_usb1_HCSPARAMS">
    <name>HCSPARAMS</name>
    <desc>Port steering logic capabilities are described in this register.</desc>
  </register>
  <register offset="0xe0003108" type="ro" uniqueid="ps7_usb1_HCCPARAMS">
    <name>HCCPARAMS</name>
    <desc>This register identifies multiple mode control (time-base bit functionality) addressing capability</desc>
  </register>
  <register offset="0xe0003120" type="ro" uniqueid="ps7_usb1_DCIVERSION">
    <name>DCIVERSION</name>
    <desc>The device controller interface conforms to the two-byte BCD encoding of the interface version number
contained in this register.</desc>
  </register>
  <register offset="0xe0003124" type="ro" uniqueid="ps7_usb1_DCCPARAMS">
    <name>DCCPARAMS</name>
    <desc>These fields describe the overall host/device capability of the controller</desc>
  </register>
  <register offset="0xe0003140" type="rw" uniqueid="ps7_usb1_USBCMD">
    <name>USBCMD</name>
    <desc>The serial bus host/device controller executes the command indicated in this register</desc>
  </register>
  <register offset="0xe0003144" type="rw" uniqueid="ps7_usb1_USBSTS">
    <name>USBSTS</name>
    <desc>This register indicates various states of the Controller and any pending interrupts. This register does not indicate status resulting from a transaction on the serial bus.</desc>
  </register>
  <register offset="0xe0003148" type="rw" uniqueid="ps7_usb1_USBINTR">
    <name>USBINTR</name>
    <desc>The interrupts to software are enabled with this register. An interrupt is generated when a bit is set and the corresponding interrupt is active. The USB Status register (USBSTS) still shows interrupt sources even if they are disabled by the USBINTR register, allowing polling of interrupt events by the software.</desc>
  </register>
  <register offset="0xe000314c" type="rw" uniqueid="ps7_usb1_FRINDEX">
    <name>FRINDEX</name>
    <desc>This register is used by the host controller to index the periodic frame list. The register updates every 125 us (once each micro-frame).</desc>
  </register>
  <register offset="0xe0003154" type="rw" uniqueid="ps7_usb1_PERIODICLISTBASE_DEVICEADDR">
    <name>PERIODICLISTBASE_DEVICEADDR</name>
    <desc>This register is has two different uses when working in device or host mode.</desc>
  </register>
  <register offset="0xe0003158" type="rw" uniqueid="ps7_usb1_ASYNCLISTADDR_ENDPOINTLISTADDR">
    <name>ASYNCLISTADDR_ENDPOINTLISTADDR</name>
    <desc>This register is has two different uses when working in device or host mode.</desc>
  </register>
  <register offset="0xe000315c" type="rw" uniqueid="ps7_usb1_TTCTRL">
    <name>TTCTRL</name>
    <desc>This register contains parameters needed for internal TT operations.</desc>
  </register>
  <register offset="0xe0003160" type="rw" uniqueid="ps7_usb1_BURSTSIZE">
    <name>BURSTSIZE</name>
    <desc>This register controls the burst size used during data movement on the initiator/master interface.</desc>
  </register>
  <register offset="0xe0003164" type="rw" uniqueid="ps7_usb1_TXFILLTUNING">
    <name>TXFILLTUNING</name>
    <desc>The fields in this register control performance tuning associated with how the Controller posts data to the TX latency FIFO before moving the data onto the USB bus.</desc>
  </register>
  <register offset="0xe0003168" type="rw" uniqueid="ps7_usb1_TXTTFILLTUNING">
    <name>TXTTFILLTUNING</name>
    <desc>This register provides a function similar to TXFILLTUNING except there is no equivalent to TXFIFOTHRES because the TT TX latency FIFO is always loaded in a single burst. Even</desc>
  </register>
  <register offset="0xe000316c" type="rw" uniqueid="ps7_usb1_IC_USB">
    <name>IC_USB</name>
    <desc>This register enable and controls the IC_USB FS/LS transceiver.</desc>
  </register>
  <register offset="0xe0003170" type="rw" uniqueid="ps7_usb1_ULPI_VIEWPORT">
    <name>ULPI_VIEWPORT</name>
    <desc>The register provides indirect access to the ULPI PHY register set. Although the core performs access to the
ULPI PHY register set, there may be extraordinary circumstances where software may need direct access.</desc>
  </register>
  <register offset="0xe0003178" type="rw" uniqueid="ps7_usb1_ENDPTNAK">
    <name>ENDPTNAK</name>
    <desc>Only implemented in device mode.</desc>
  </register>
  <register offset="0xe000317c" type="rw" uniqueid="ps7_usb1_ENDPTNAKEN">
    <name>ENDPTNAKEN</name>
    <desc>Only implemented in device mode.</desc>
  </register>
  <register offset="0xe0003180" type="ro" uniqueid="ps7_usb1_CONFIGFLAG">
    <name>CONFIGFLAG</name>
    <desc>This register is not used in this implementation. A read from this register returns a constant of a 00000001h to indicate that all port routings default to this host controller.</desc>
  </register>
  <register offset="0xe0003184" type="rw" uniqueid="ps7_usb1_PORTSC1">
    <name>PORTSC1</name>
    <desc>The Controller implement one The number of port registers implemented by a particular instantiation is documented in the HCSPARAM register. Software uses this information as an input parameter to determine how many ports need service. This implement contains only 1 host port.</desc>
  </register>
  <register offset="0xe00031a4" type="rw" uniqueid="ps7_usb1_OTGSC">
    <name>OTGSC</name>
    <desc>The Controller implements one On-The-Go (OTG) Status and Control register.
The OTGSC register has four sections:
OTG Interrupt enables (Read/Write)
OTG Interrupt status (Read/Write to Clear)
OTG Status inputs (Read Only)
OTG Controls (Read/Write)</desc>
  </register>
  <register offset="0xe00031a8" type="rw" uniqueid="ps7_usb1_USBMODE">
    <name>USBMODE</name>
    <desc>USB Mode Selection register</desc>
  </register>
  <register offset="0xe00031ac" type="rw" uniqueid="ps7_usb1_ENDPTSETUPSTAT">
    <name>ENDPTSETUPSTAT</name>
    <desc>Only implemented in device mode.</desc>
  </register>
  <register offset="0xe00031b0" type="rw" uniqueid="ps7_usb1_ENDPTPRIME">
    <name>ENDPTPRIME</name>
    <desc>Only implemented in device mode</desc>
  </register>
  <register offset="0xe00031b4" type="rw" uniqueid="ps7_usb1_ENDPTFLUSH">
    <name>ENDPTFLUSH</name>
    <desc>The Flush operation for an endpoint will clear the Ready status of that endpoint and re-align the Latency Buffer pointers, but not clear the actual data that resides in the Latency Buffers.</desc>
  </register>
  <register offset="0xe00031b8" type="ro" uniqueid="ps7_usb1_ENDPTSTAT">
    <name>ENDPTSTAT</name>
    <desc>Only implemented in device mode.</desc>
  </register>
  <register offset="0xe00031bc" type="ro" uniqueid="ps7_usb1_ENDPTCOMPLETE">
    <name>ENDPTCOMPLETE</name>
    <desc>Only implemented in device mode.</desc>
  </register>
  <register offset="0xe00031c0" type="rw" uniqueid="ps7_usb1_ENDPTCTRL0">
    <name>ENDPTCTRL0</name>
    <desc>Every device will implement Endpoint0 as a control endpoint. Only implemented in device mode.</desc>
  </register>
  <register offset="0xe00031c4" type="rw" uniqueid="ps7_usb1_ENDPTCTRL1">
    <name>ENDPTCTRL</name>
    <desc>This is an ENDPTCTRL1 register for the endpoint 1 device. Only implemented in device mode.</desc>
  </register>
  <register offset="0xe00031c8" type="rw" uniqueid="ps7_usb1_ENDPTCTRL2">
    <name>ENDPTCTRL</name>
    <desc>This is an ENDPTCTRL1 register for the endpoint 1 device. Only implemented in device mode.</desc>
  </register>
  <register offset="0xe00031cc" type="rw" uniqueid="ps7_usb1_ENDPTCTRL3">
    <name>ENDPTCTRL</name>
    <desc>This is an ENDPTCTRL1 register for the endpoint 1 device. Only implemented in device mode.</desc>
  </register>
  <register offset="0xe00031d0" type="rw" uniqueid="ps7_usb1_ENDPTCTRL4">
    <name>ENDPTCTRL</name>
    <desc>This is an ENDPTCTRL1 register for the endpoint 1 device. Only implemented in device mode.</desc>
  </register>
  <register offset="0xe00031d4" type="rw" uniqueid="ps7_usb1_ENDPTCTRL5">
    <name>ENDPTCTRL</name>
    <desc>This is an ENDPTCTRL1 register for the endpoint 1 device. Only implemented in device mode.</desc>
  </register>
  <register offset="0xe00031d8" type="rw" uniqueid="ps7_usb1_ENDPTCTRL6">
    <name>ENDPTCTRL</name>
    <desc>This is an ENDPTCTRL1 register for the endpoint 1 device. Only implemented in device mode.</desc>
  </register>
  <register offset="0xe00031dc" type="rw" uniqueid="ps7_usb1_ENDPTCTRL7">
    <name>ENDPTCTRL</name>
    <desc>This is an ENDPTCTRL1 register for the endpoint 1 device. Only implemented in device mode.</desc>
  </register>
  <register offset="0xe00031e0" type="rw" uniqueid="ps7_usb1_ENDPTCTRL8">
    <name>ENDPTCTRL</name>
    <desc>This is an ENDPTCTRL1 register for the endpoint 1 device. Only implemented in device mode.</desc>
  </register>
  <register offset="0xe00031e4" type="rw" uniqueid="ps7_usb1_ENDPTCTRL9">
    <name>ENDPTCTRL</name>
    <desc>This is an ENDPTCTRL1 register for the endpoint 1 device. Only implemented in device mode.</desc>
  </register>
  <register offset="0xe00031e8" type="rw" uniqueid="ps7_usb1_ENDPTCTRL10">
    <name>ENDPTCTRL</name>
    <desc>This is an ENDPTCTRL1 register for the endpoint 1 device. Only implemented in device mode.</desc>
  </register>
  <register offset="0xe00031ec" type="rw" uniqueid="ps7_usb1_ENDPTCTRL11">
    <name>ENDPTCTRL</name>
    <desc>This is an ENDPTCTRL1 register for the endpoint 1 device. Only implemented in device mode.</desc>
  </register>
  <register offset="0xe00031f0" type="rw" uniqueid="ps7_usb1_ENDPTCTRL12">
    <name>ENDPTCTRL</name>
    <desc>This is an ENDPTCTRL1 register for the endpoint 1 device. Only implemented in device mode.</desc>
  </register>
  <register offset="0xf8805000" type="rw" uniqueid="ps7_debug_itm_StimPort00">
    <name>StimPort00</name>
    <desc>Stimulus Port Register 0</desc>
  </register>
  <register offset="0xf8805004" type="rw" uniqueid="ps7_debug_itm_StimPort01">
    <name>StimPort01</name>
    <desc>Stimulus Port Register 1</desc>
  </register>
  <register offset="0xf8805008" type="rw" uniqueid="ps7_debug_itm_StimPort02">
    <name>StimPort02</name>
    <desc>Stimulus Port Register 2</desc>
  </register>
  <register offset="0xf880500c" type="rw" uniqueid="ps7_debug_itm_StimPort03">
    <name>StimPort03</name>
    <desc>Stimulus Port Register 3</desc>
  </register>
  <register offset="0xf8805010" type="rw" uniqueid="ps7_debug_itm_StimPort04">
    <name>StimPort04</name>
    <desc>Stimulus Port Register 4</desc>
  </register>
  <register offset="0xf8805014" type="rw" uniqueid="ps7_debug_itm_StimPort05">
    <name>StimPort05</name>
    <desc>Stimulus Port Register 5</desc>
  </register>
  <register offset="0xf8805018" type="rw" uniqueid="ps7_debug_itm_StimPort06">
    <name>StimPort06</name>
    <desc>Stimulus Port Register 6</desc>
  </register>
  <register offset="0xf880501c" type="rw" uniqueid="ps7_debug_itm_StimPort07">
    <name>StimPort07</name>
    <desc>Stimulus Port Register 7</desc>
  </register>
  <register offset="0xf8805020" type="rw" uniqueid="ps7_debug_itm_StimPort08">
    <name>StimPort08</name>
    <desc>Stimulus Port Register 8</desc>
  </register>
  <register offset="0xf8805024" type="rw" uniqueid="ps7_debug_itm_StimPort09">
    <name>StimPort09</name>
    <desc>Stimulus Port Register 9</desc>
  </register>
  <register offset="0xf8805028" type="rw" uniqueid="ps7_debug_itm_StimPort10">
    <name>StimPort10</name>
    <desc>Stimulus Port Register 10</desc>
  </register>
  <register offset="0xf880502c" type="rw" uniqueid="ps7_debug_itm_StimPort11">
    <name>StimPort11</name>
    <desc>Stimulus Port Register 11</desc>
  </register>
  <register offset="0xf8805030" type="rw" uniqueid="ps7_debug_itm_StimPort12">
    <name>StimPort12</name>
    <desc>Stimulus Port Register 12</desc>
  </register>
  <register offset="0xf8805034" type="rw" uniqueid="ps7_debug_itm_StimPort13">
    <name>StimPort13</name>
    <desc>Stimulus Port Register 13</desc>
  </register>
  <register offset="0xf8805038" type="rw" uniqueid="ps7_debug_itm_StimPort14">
    <name>StimPort14</name>
    <desc>Stimulus Port Register 14</desc>
  </register>
  <register offset="0xf880503c" type="rw" uniqueid="ps7_debug_itm_StimPort15">
    <name>StimPort15</name>
    <desc>Stimulus Port Register 15</desc>
  </register>
  <register offset="0xf8805040" type="rw" uniqueid="ps7_debug_itm_StimPort16">
    <name>StimPort16</name>
    <desc>Stimulus Port Register 16</desc>
  </register>
  <register offset="0xf8805044" type="rw" uniqueid="ps7_debug_itm_StimPort17">
    <name>StimPort17</name>
    <desc>Stimulus Port Register 17</desc>
  </register>
  <register offset="0xf8805048" type="rw" uniqueid="ps7_debug_itm_StimPort18">
    <name>StimPort18</name>
    <desc>Stimulus Port Register 18</desc>
  </register>
  <register offset="0xf880504c" type="rw" uniqueid="ps7_debug_itm_StimPort19">
    <name>StimPort19</name>
    <desc>Stimulus Port Register 19</desc>
  </register>
  <register offset="0xf8805050" type="rw" uniqueid="ps7_debug_itm_StimPort20">
    <name>StimPort20</name>
    <desc>Stimulus Port Register 20</desc>
  </register>
  <register offset="0xf8805054" type="rw" uniqueid="ps7_debug_itm_StimPort21">
    <name>StimPort21</name>
    <desc>Stimulus Port Register 21</desc>
  </register>
  <register offset="0xf8805058" type="rw" uniqueid="ps7_debug_itm_StimPort22">
    <name>StimPort22</name>
    <desc>Stimulus Port Register 22</desc>
  </register>
  <register offset="0xf880505c" type="rw" uniqueid="ps7_debug_itm_StimPort23">
    <name>StimPort23</name>
    <desc>Stimulus Port Register 23</desc>
  </register>
  <register offset="0xf8805060" type="rw" uniqueid="ps7_debug_itm_StimPort24">
    <name>StimPort24</name>
    <desc>Stimulus Port Register 24</desc>
  </register>
  <register offset="0xf8805064" type="rw" uniqueid="ps7_debug_itm_StimPort25">
    <name>StimPort25</name>
    <desc>Stimulus Port Register 25</desc>
  </register>
  <register offset="0xf8805068" type="rw" uniqueid="ps7_debug_itm_StimPort26">
    <name>StimPort26</name>
    <desc>Stimulus Port Register 26</desc>
  </register>
  <register offset="0xf880506c" type="rw" uniqueid="ps7_debug_itm_StimPort27">
    <name>StimPort27</name>
    <desc>Stimulus Port Register 27</desc>
  </register>
  <register offset="0xf8805070" type="rw" uniqueid="ps7_debug_itm_StimPort28">
    <name>StimPort28</name>
    <desc>Stimulus Port Register 28</desc>
  </register>
  <register offset="0xf8805074" type="rw" uniqueid="ps7_debug_itm_StimPort29">
    <name>StimPort29</name>
    <desc>Stimulus Port Register 29</desc>
  </register>
  <register offset="0xf8805078" type="rw" uniqueid="ps7_debug_itm_StimPort30">
    <name>StimPort30</name>
    <desc>Stimulus Port Register 30</desc>
  </register>
  <register offset="0xf880507c" type="rw" uniqueid="ps7_debug_itm_StimPort31">
    <name>StimPort31</name>
    <desc>Stimulus Port Register 31</desc>
  </register>
  <register offset="0xf8805e00" type="rw" uniqueid="ps7_debug_itm_TER">
    <name>TER</name>
    <desc>Trace Enable Register</desc>
  </register>
  <register offset="0xf8805e20" type="rw" uniqueid="ps7_debug_itm_TTR">
    <name>TTR</name>
    <desc>Trace Trigger Register</desc>
  </register>
  <register offset="0xf8805e80" type="rw" uniqueid="ps7_debug_itm_CR">
    <name>CR</name>
    <desc>Control Register</desc>
  </register>
  <register offset="0xf8805e90" type="rw" uniqueid="ps7_debug_itm_SCR">
    <name>SCR</name>
    <desc>Synchronization Control Register</desc>
  </register>
  <register offset="0xf8805ee4" type="ro" uniqueid="ps7_debug_itm_ITTRIGOUTACK">
    <name>ITTRIGOUTACK</name>
    <desc>Integration Test Trigger Out Acknowledge Register</desc>
  </register>
  <register offset="0xf8805ee8" type="wo" uniqueid="ps7_debug_itm_ITTRIGOUT">
    <name>ITTRIGOUT</name>
    <desc>Integration Test Trigger Out Register</desc>
  </register>
  <register offset="0xf8805eec" type="wo" uniqueid="ps7_debug_itm_ITATBDATA0">
    <name>ITATBDATA0</name>
    <desc>Integration Test ATB Data Register 0</desc>
  </register>
  <register offset="0xf8805ef0" type="ro" uniqueid="ps7_debug_itm_ITATBCTR2">
    <name>ITATBCTR2</name>
    <desc>Integration Test ATB Control Register 2</desc>
  </register>
  <register offset="0xf8805ef4" type="wo" uniqueid="ps7_debug_itm_ITATABCTR1">
    <name>ITATABCTR1</name>
    <desc>Integration Test ATB Control Register 1</desc>
  </register>
  <register offset="0xf8805ef8" type="wo" uniqueid="ps7_debug_itm_ITATBCTR0">
    <name>ITATBCTR0</name>
    <desc>Integration Test ATB Control Register 0</desc>
  </register>
  <register offset="0xf8805f00" type="rw" uniqueid="ps7_debug_itm_IMCR">
    <name>IMCR</name>
    <desc>Integration Mode Control Register</desc>
  </register>
  <register offset="0xf8805fa0" type="rw" uniqueid="ps7_debug_itm_CTSR">
    <name>CTSR</name>
    <desc>Claim Tag Set Register</desc>
  </register>
  <register offset="0xf8805fa4" type="rw" uniqueid="ps7_debug_itm_CTCR">
    <name>CTCR</name>
    <desc>Claim Tag Clear Register</desc>
  </register>
  <register offset="0xf8805fb0" type="wo" uniqueid="ps7_debug_itm_LAR">
    <name>LAR</name>
    <desc>Lock Access Register</desc>
  </register>
  <register offset="0xf8805fb4" type="ro" uniqueid="ps7_debug_itm_LSR">
    <name>LSR</name>
    <desc>Lock Status Register</desc>
  </register>
  <register offset="0xf8805fb8" type="ro" uniqueid="ps7_debug_itm_ASR">
    <name>ASR</name>
    <desc>Authentication Status Register</desc>
  </register>
  <register offset="0xf8805fc8" type="ro" uniqueid="ps7_debug_itm_DEVID">
    <name>DEVID</name>
    <desc>Device ID</desc>
  </register>
  <register offset="0xf8805fcc" type="ro" uniqueid="ps7_debug_itm_DTIR">
    <name>DTIR</name>
    <desc>Device Type Identifier Register</desc>
  </register>
  <register offset="0xf8805fd0" type="ro" uniqueid="ps7_debug_itm_PERIPHID4">
    <name>PERIPHID4</name>
    <desc>Peripheral ID4</desc>
  </register>
  <register offset="0xf8805fd4" type="ro" uniqueid="ps7_debug_itm_PERIPHID5">
    <name>PERIPHID5</name>
    <desc>Peripheral ID5</desc>
  </register>
  <register offset="0xf8805fd8" type="ro" uniqueid="ps7_debug_itm_PERIPHID6">
    <name>PERIPHID6</name>
    <desc>Peripheral ID6</desc>
  </register>
  <register offset="0xf8805fdc" type="ro" uniqueid="ps7_debug_itm_PERIPHID7">
    <name>PERIPHID7</name>
    <desc>Peripheral ID7</desc>
  </register>
  <register offset="0xf8805fe0" type="ro" uniqueid="ps7_debug_itm_PERIPHID0">
    <name>PERIPHID0</name>
    <desc>Peripheral ID0</desc>
  </register>
  <register offset="0xf8805fe4" type="ro" uniqueid="ps7_debug_itm_PERIPHID1">
    <name>PERIPHID1</name>
    <desc>Peripheral ID1</desc>
  </register>
  <register offset="0xf8805fe8" type="ro" uniqueid="ps7_debug_itm_PERIPHID2">
    <name>PERIPHID2</name>
    <desc>Peripheral ID2</desc>
  </register>
  <register offset="0xf8805fec" type="ro" uniqueid="ps7_debug_itm_PERIPHID3">
    <name>PERIPHID3</name>
    <desc>Peripheral ID3</desc>
  </register>
  <register offset="0xf8805ff0" type="ro" uniqueid="ps7_debug_itm_COMPID0">
    <name>COMPID0</name>
    <desc>Component ID0</desc>
  </register>
  <register offset="0xf8805ff4" type="ro" uniqueid="ps7_debug_itm_COMPID1">
    <name>COMPID1</name>
    <desc>Component ID1</desc>
  </register>
  <register offset="0xf8805ff8" type="ro" uniqueid="ps7_debug_itm_COMPID2">
    <name>COMPID2</name>
    <desc>Component ID2</desc>
  </register>
  <register offset="0xf8805ffc" type="ro" uniqueid="ps7_debug_itm_COMPID3">
    <name>COMPID3</name>
    <desc>Component ID3</desc>
  </register>
  <register offset="0xf8800000" type="ro" uniqueid="ps7_debug_dap_rom_ROMENTRY00">
    <name>ROMENTRY00</name>
    <desc>ROM entry 00</desc>
  </register>
  <register offset="0xf8800004" type="ro" uniqueid="ps7_debug_dap_rom_ROMENTRY01">
    <name>ROMENTRY01</name>
    <desc>ROM entry 01</desc>
  </register>
  <register offset="0xf8800008" type="ro" uniqueid="ps7_debug_dap_rom_ROMENTRY02">
    <name>ROMENTRY02</name>
    <desc>ROM entry 02</desc>
  </register>
  <register offset="0xf880000c" type="ro" uniqueid="ps7_debug_dap_rom_ROMENTRY03">
    <name>ROMENTRY03</name>
    <desc>ROM entry 03</desc>
  </register>
  <register offset="0xf8800010" type="ro" uniqueid="ps7_debug_dap_rom_ROMENTRY04">
    <name>ROMENTRY04</name>
    <desc>ROM entry 04</desc>
  </register>
  <register offset="0xf8800014" type="ro" uniqueid="ps7_debug_dap_rom_ROMENTRY05">
    <name>ROMENTRY05</name>
    <desc>ROM entry 05</desc>
  </register>
  <register offset="0xf8800018" type="ro" uniqueid="ps7_debug_dap_rom_ROMENTRY06">
    <name>ROMENTRY06</name>
    <desc>ROM entry 06</desc>
  </register>
  <register offset="0xf880001c" type="ro" uniqueid="ps7_debug_dap_rom_ROMENTRY07">
    <name>ROMENTRY07</name>
    <desc>ROM entry 07</desc>
  </register>
  <register offset="0xf8800020" type="ro" uniqueid="ps7_debug_dap_rom_ROMENTRY08">
    <name>ROMENTRY08</name>
    <desc>ROM entry 08</desc>
  </register>
  <register offset="0xf8800024" type="ro" uniqueid="ps7_debug_dap_rom_ROMENTRY09">
    <name>ROMENTRY09</name>
    <desc>ROM entry 09</desc>
  </register>
  <register offset="0xf8800028" type="rw" uniqueid="ps7_debug_dap_rom_ROMENTRY10">
    <name>ROMENTRY10</name>
    <desc>ROM entry 10</desc>
  </register>
  <register offset="0xf880002c" type="rw" uniqueid="ps7_debug_dap_rom_ROMENTRY11">
    <name>ROMENTRY11</name>
    <desc>ROM entry 11</desc>
  </register>
  <register offset="0xf8800030" type="rw" uniqueid="ps7_debug_dap_rom_ROMENTRY12">
    <name>ROMENTRY12</name>
    <desc>ROM entry 12</desc>
  </register>
  <register offset="0xf8800034" type="rw" uniqueid="ps7_debug_dap_rom_ROMENTRY13">
    <name>ROMENTRY13</name>
    <desc>ROM entry 13</desc>
  </register>
  <register offset="0xf8800038" type="rw" uniqueid="ps7_debug_dap_rom_ROMENTRY14">
    <name>ROMENTRY14</name>
    <desc>ROM entry 14</desc>
  </register>
  <register offset="0xf880003c" type="rw" uniqueid="ps7_debug_dap_rom_ROMENTRY15">
    <name>ROMENTRY15</name>
    <desc>ROM entry 15</desc>
  </register>
  <register offset="0xf8800fd0" type="ro" uniqueid="ps7_debug_dap_rom_PERIPHID4">
    <name>PERIPHID4</name>
    <desc>Peripheral ID4</desc>
  </register>
  <register offset="0xf8800fd4" type="ro" uniqueid="ps7_debug_dap_rom_PERIPHID5">
    <name>PERIPHID5</name>
    <desc>Peripheral ID5</desc>
  </register>
  <register offset="0xf8800fd8" type="ro" uniqueid="ps7_debug_dap_rom_PERIPHID6">
    <name>PERIPHID6</name>
    <desc>Peripheral ID6</desc>
  </register>
  <register offset="0xf8800fdc" type="ro" uniqueid="ps7_debug_dap_rom_PERIPHID7">
    <name>PERIPHID7</name>
    <desc>Peripheral ID7</desc>
  </register>
  <register offset="0xf8800fe0" type="ro" uniqueid="ps7_debug_dap_rom_PERIPHID0">
    <name>PERIPHID0</name>
    <desc>Peripheral ID0</desc>
  </register>
  <register offset="0xf8800fe4" type="ro" uniqueid="ps7_debug_dap_rom_PERIPHID1">
    <name>PERIPHID1</name>
    <desc>Peripheral ID1</desc>
  </register>
  <register offset="0xf8800fe8" type="ro" uniqueid="ps7_debug_dap_rom_PERIPHID2">
    <name>PERIPHID2</name>
    <desc>Peripheral ID2</desc>
  </register>
  <register offset="0xf8800fec" type="ro" uniqueid="ps7_debug_dap_rom_PERIPHID3">
    <name>PERIPHID3</name>
    <desc>Peripheral ID3</desc>
  </register>
  <register offset="0xf8800ff0" type="ro" uniqueid="ps7_debug_dap_rom_COMPID0">
    <name>COMPID0</name>
    <desc>Component ID0</desc>
  </register>
  <register offset="0xf8800ff4" type="ro" uniqueid="ps7_debug_dap_rom_COMPID1">
    <name>COMPID1</name>
    <desc>Component ID1</desc>
  </register>
  <register offset="0xf8800ff8" type="ro" uniqueid="ps7_debug_dap_rom_COMPID2">
    <name>COMPID2</name>
    <desc>Component ID2</desc>
  </register>
  <register offset="0xf8800ffc" type="ro" uniqueid="ps7_debug_dap_rom_COMPID3">
    <name>COMPID3</name>
    <desc>Component ID3</desc>
  </register>
  <register offset="0xf880a000" type="rw" uniqueid="ps7_debug_cti_axim_CTICONTROL">
    <name>CTICONTROL</name>
    <desc>CTI Control Register</desc>
  </register>
  <register offset="0xf880a010" type="wo" uniqueid="ps7_debug_cti_axim_CTIINTACK">
    <name>CTIINTACK</name>
    <desc>CTI Interrupt Acknowledge Register</desc>
  </register>
  <register offset="0xf880a014" type="rw" uniqueid="ps7_debug_cti_axim_CTIAPPSET">
    <name>CTIAPPSET</name>
    <desc>CTI Application Trigger Set Register</desc>
  </register>
  <register offset="0xf880a018" type="wo" uniqueid="ps7_debug_cti_axim_CTIAPPCLEAR">
    <name>CTIAPPCLEAR</name>
    <desc>CTI Application Trigger Clear Register</desc>
  </register>
  <register offset="0xf880a01c" type="wo" uniqueid="ps7_debug_cti_axim_CTIAPPPULSE">
    <name>CTIAPPPULSE</name>
    <desc>CTI Application Pulse Register</desc>
  </register>
  <register offset="0xf880a020" type="rw" uniqueid="ps7_debug_cti_axim_CTIINEN0">
    <name>CTIINEN0</name>
    <desc>CTI Trigger to Channel Enable 0 Register</desc>
  </register>
  <register offset="0xf880a024" type="rw" uniqueid="ps7_debug_cti_axim_CTIINEN1">
    <name>CTIINEN1</name>
    <desc>CTI Trigger to Channel Enable 1 Register</desc>
  </register>
  <register offset="0xf880a028" type="rw" uniqueid="ps7_debug_cti_axim_CTIINEN2">
    <name>CTIINEN2</name>
    <desc>CTI Trigger to Channel Enable 2 Register</desc>
  </register>
  <register offset="0xf880a02c" type="rw" uniqueid="ps7_debug_cti_axim_CTIINEN3">
    <name>CTIINEN3</name>
    <desc>CTI Trigger to Channel Enable 3 Register</desc>
  </register>
  <register offset="0xf880a030" type="rw" uniqueid="ps7_debug_cti_axim_CTIINEN4">
    <name>CTIINEN4</name>
    <desc>CTI Trigger to Channel Enable 4 Register</desc>
  </register>
  <register offset="0xf880a034" type="rw" uniqueid="ps7_debug_cti_axim_CTIINEN5">
    <name>CTIINEN5</name>
    <desc>CTI Trigger to Channel Enable 5 Register</desc>
  </register>
  <register offset="0xf880a038" type="rw" uniqueid="ps7_debug_cti_axim_CTIINEN6">
    <name>CTIINEN6</name>
    <desc>CTI Trigger to Channel Enable 6 Register</desc>
  </register>
  <register offset="0xf880a03c" type="rw" uniqueid="ps7_debug_cti_axim_CTIINEN7">
    <name>CTIINEN7</name>
    <desc>CTI Trigger to Channel Enable 7 Register</desc>
  </register>
  <register offset="0xf880a0a0" type="rw" uniqueid="ps7_debug_cti_axim_CTIOUTEN0">
    <name>CTIOUTEN0</name>
    <desc>CTI Channel to Trigger Enable 0 Register</desc>
  </register>
  <register offset="0xf880a0a4" type="rw" uniqueid="ps7_debug_cti_axim_CTIOUTEN1">
    <name>CTIOUTEN1</name>
    <desc>CTI Channel to Trigger Enable 1 Register</desc>
  </register>
  <register offset="0xf880a0a8" type="rw" uniqueid="ps7_debug_cti_axim_CTIOUTEN2">
    <name>CTIOUTEN2</name>
    <desc>CTI Channel to Trigger Enable 2 Register</desc>
  </register>
  <register offset="0xf880a0ac" type="rw" uniqueid="ps7_debug_cti_axim_CTIOUTEN3">
    <name>CTIOUTEN3</name>
    <desc>CTI Channel to Trigger Enable 3 Register</desc>
  </register>
  <register offset="0xf880a0b0" type="rw" uniqueid="ps7_debug_cti_axim_CTIOUTEN4">
    <name>CTIOUTEN4</name>
    <desc>CTI Channel to Trigger Enable 4 Register</desc>
  </register>
  <register offset="0xf880a0b4" type="rw" uniqueid="ps7_debug_cti_axim_CTIOUTEN5">
    <name>CTIOUTEN5</name>
    <desc>CTI Channel to Trigger Enable 5 Register</desc>
  </register>
  <register offset="0xf880a0b8" type="rw" uniqueid="ps7_debug_cti_axim_CTIOUTEN6">
    <name>CTIOUTEN6</name>
    <desc>CTI Channel to Trigger Enable 6 Register</desc>
  </register>
  <register offset="0xf880a0bc" type="rw" uniqueid="ps7_debug_cti_axim_CTIOUTEN7">
    <name>CTIOUTEN7</name>
    <desc>CTI Channel to Trigger Enable 7 Register</desc>
  </register>
  <register offset="0xf880a130" type="ro" uniqueid="ps7_debug_cti_axim_CTITRIGINSTATUS">
    <name>CTITRIGINSTATUS</name>
    <desc>CTI Trigger In Status Register</desc>
  </register>
  <register offset="0xf880a134" type="ro" uniqueid="ps7_debug_cti_axim_CTITRIGOUTSTATUS">
    <name>CTITRIGOUTSTATUS</name>
    <desc>CTI Trigger Out Status Register</desc>
  </register>
  <register offset="0xf880a138" type="ro" uniqueid="ps7_debug_cti_axim_CTICHINSTATUS">
    <name>CTICHINSTATUS</name>
    <desc>CTI Channel In Status Register</desc>
  </register>
  <register offset="0xf880a13c" type="ro" uniqueid="ps7_debug_cti_axim_CTICHOUTSTATUS">
    <name>CTICHOUTSTATUS</name>
    <desc>CTI Channel Out Status Register</desc>
  </register>
  <register offset="0xf880a140" type="rw" uniqueid="ps7_debug_cti_axim_CTIGATE">
    <name>CTIGATE</name>
    <desc>Enable CTI Channel Gate Register</desc>
  </register>
  <register offset="0xf880a144" type="rw" uniqueid="ps7_debug_cti_axim_ASICCTL">
    <name>ASICCTL</name>
    <desc>External Multiplexor Control Register</desc>
  </register>
  <register offset="0xf880aedc" type="wo" uniqueid="ps7_debug_cti_axim_ITCHINACK">
    <name>ITCHINACK</name>
    <desc>ITCHINACK Register</desc>
  </register>
  <register offset="0xf880aee0" type="wo" uniqueid="ps7_debug_cti_axim_ITTRIGINACK">
    <name>ITTRIGINACK</name>
    <desc>ITTRIGINACK Register</desc>
  </register>
  <register offset="0xf880aee4" type="wo" uniqueid="ps7_debug_cti_axim_ITCHOUT">
    <name>ITCHOUT</name>
    <desc>ITCHOUT Register</desc>
  </register>
  <register offset="0xf880aee8" type="wo" uniqueid="ps7_debug_cti_axim_ITTRIGOUT">
    <name>ITTRIGOUT</name>
    <desc>ITTRIGOUT Register</desc>
  </register>
  <register offset="0xf880aeec" type="ro" uniqueid="ps7_debug_cti_axim_ITCHOUTACK">
    <name>ITCHOUTACK</name>
    <desc>ITCHOUTACK Register</desc>
  </register>
  <register offset="0xf880aef0" type="ro" uniqueid="ps7_debug_cti_axim_ITTRIGOUTACK">
    <name>ITTRIGOUTACK</name>
    <desc>ITTRIGOUTACK Register</desc>
  </register>
  <register offset="0xf880aef4" type="ro" uniqueid="ps7_debug_cti_axim_ITCHIN">
    <name>ITCHIN</name>
    <desc>ITCHIN Register</desc>
  </register>
  <register offset="0xf880aef8" type="ro" uniqueid="ps7_debug_cti_axim_ITTRIGIN">
    <name>ITTRIGIN</name>
    <desc>ITTRIGIN Register</desc>
  </register>
  <register offset="0xf880af00" type="rw" uniqueid="ps7_debug_cti_axim_ITCTRL">
    <name>ITCTRL</name>
    <desc>IT Control Register</desc>
  </register>
  <register offset="0xf880afa0" type="rw" uniqueid="ps7_debug_cti_axim_CTSR">
    <name>CTSR</name>
    <desc>Claim Tag Set Register</desc>
  </register>
  <register offset="0xf880afa4" type="rw" uniqueid="ps7_debug_cti_axim_CTCR">
    <name>CTCR</name>
    <desc>Claim Tag Clear Register</desc>
  </register>
  <register offset="0xf880afb0" type="wo" uniqueid="ps7_debug_cti_axim_LAR">
    <name>LAR</name>
    <desc>Lock Access Register</desc>
  </register>
  <register offset="0xf880afb4" type="ro" uniqueid="ps7_debug_cti_axim_LSR">
    <name>LSR</name>
    <desc>Lock Status Register</desc>
  </register>
  <register offset="0xf880afb8" type="ro" uniqueid="ps7_debug_cti_axim_ASR">
    <name>ASR</name>
    <desc>Authentication Status Register</desc>
  </register>
  <register offset="0xf880afc8" type="ro" uniqueid="ps7_debug_cti_axim_DEVID">
    <name>DEVID</name>
    <desc>Device ID</desc>
  </register>
  <register offset="0xf880afcc" type="ro" uniqueid="ps7_debug_cti_axim_DTIR">
    <name>DTIR</name>
    <desc>Device Type Identifier Register</desc>
  </register>
  <register offset="0xf880afd0" type="ro" uniqueid="ps7_debug_cti_axim_PERIPHID4">
    <name>PERIPHID4</name>
    <desc>Peripheral ID4</desc>
  </register>
  <register offset="0xf880afd4" type="ro" uniqueid="ps7_debug_cti_axim_PERIPHID5">
    <name>PERIPHID5</name>
    <desc>Peripheral ID5</desc>
  </register>
  <register offset="0xf880afd8" type="ro" uniqueid="ps7_debug_cti_axim_PERIPHID6">
    <name>PERIPHID6</name>
    <desc>Peripheral ID6</desc>
  </register>
  <register offset="0xf880afdc" type="ro" uniqueid="ps7_debug_cti_axim_PERIPHID7">
    <name>PERIPHID7</name>
    <desc>Peripheral ID7</desc>
  </register>
  <register offset="0xf880afe0" type="ro" uniqueid="ps7_debug_cti_axim_PERIPHID0">
    <name>PERIPHID0</name>
    <desc>Peripheral ID0</desc>
  </register>
  <register offset="0xf880afe4" type="ro" uniqueid="ps7_debug_cti_axim_PERIPHID1">
    <name>PERIPHID1</name>
    <desc>Peripheral ID1</desc>
  </register>
  <register offset="0xf880afe8" type="ro" uniqueid="ps7_debug_cti_axim_PERIPHID2">
    <name>PERIPHID2</name>
    <desc>Peripheral ID2</desc>
  </register>
  <register offset="0xf880afec" type="ro" uniqueid="ps7_debug_cti_axim_PERIPHID3">
    <name>PERIPHID3</name>
    <desc>Peripheral ID3</desc>
  </register>
  <register offset="0xf880aff0" type="ro" uniqueid="ps7_debug_cti_axim_COMPID0">
    <name>COMPID0</name>
    <desc>Component ID0</desc>
  </register>
  <register offset="0xf880aff4" type="ro" uniqueid="ps7_debug_cti_axim_COMPID1">
    <name>COMPID1</name>
    <desc>Component ID1</desc>
  </register>
  <register offset="0xf880aff8" type="ro" uniqueid="ps7_debug_cti_axim_COMPID2">
    <name>COMPID2</name>
    <desc>Component ID2</desc>
  </register>
  <register offset="0xf880affc" type="ro" uniqueid="ps7_debug_cti_axim_COMPID3">
    <name>COMPID3</name>
    <desc>Component ID3</desc>
  </register>
  <register offset="0xf8899000" type="rw" uniqueid="ps7_debug_cpu_cti1_CTICONTROL">
    <name>CTICONTROL</name>
    <desc>CTI Control Register</desc>
  </register>
  <register offset="0xf8899010" type="wo" uniqueid="ps7_debug_cpu_cti1_CTIINTACK">
    <name>CTIINTACK</name>
    <desc>CTI Interrupt Acknowledge Register</desc>
  </register>
  <register offset="0xf8899014" type="rw" uniqueid="ps7_debug_cpu_cti1_CTIAPPSET">
    <name>CTIAPPSET</name>
    <desc>CTI Application Trigger Set Register</desc>
  </register>
  <register offset="0xf8899018" type="wo" uniqueid="ps7_debug_cpu_cti1_CTIAPPCLEAR">
    <name>CTIAPPCLEAR</name>
    <desc>CTI Application Trigger Clear Register</desc>
  </register>
  <register offset="0xf889901c" type="wo" uniqueid="ps7_debug_cpu_cti1_CTIAPPPULSE">
    <name>CTIAPPPULSE</name>
    <desc>CTI Application Pulse Register</desc>
  </register>
  <register offset="0xf8899020" type="rw" uniqueid="ps7_debug_cpu_cti1_CTIINEN0">
    <name>CTIINEN0</name>
    <desc>CTI Trigger to Channel Enable 0 Register</desc>
  </register>
  <register offset="0xf8899024" type="rw" uniqueid="ps7_debug_cpu_cti1_CTIINEN1">
    <name>CTIINEN1</name>
    <desc>CTI Trigger to Channel Enable 1 Register</desc>
  </register>
  <register offset="0xf8899028" type="rw" uniqueid="ps7_debug_cpu_cti1_CTIINEN2">
    <name>CTIINEN2</name>
    <desc>CTI Trigger to Channel Enable 2 Register</desc>
  </register>
  <register offset="0xf889902c" type="rw" uniqueid="ps7_debug_cpu_cti1_CTIINEN3">
    <name>CTIINEN3</name>
    <desc>CTI Trigger to Channel Enable 3 Register</desc>
  </register>
  <register offset="0xf8899030" type="rw" uniqueid="ps7_debug_cpu_cti1_CTIINEN4">
    <name>CTIINEN4</name>
    <desc>CTI Trigger to Channel Enable 4 Register</desc>
  </register>
  <register offset="0xf8899034" type="rw" uniqueid="ps7_debug_cpu_cti1_CTIINEN5">
    <name>CTIINEN5</name>
    <desc>CTI Trigger to Channel Enable 5 Register</desc>
  </register>
  <register offset="0xf8899038" type="rw" uniqueid="ps7_debug_cpu_cti1_CTIINEN6">
    <name>CTIINEN6</name>
    <desc>CTI Trigger to Channel Enable 6 Register</desc>
  </register>
  <register offset="0xf889903c" type="rw" uniqueid="ps7_debug_cpu_cti1_CTIINEN7">
    <name>CTIINEN7</name>
    <desc>CTI Trigger to Channel Enable 7 Register</desc>
  </register>
  <register offset="0xf88990a0" type="rw" uniqueid="ps7_debug_cpu_cti1_CTIOUTEN0">
    <name>CTIOUTEN0</name>
    <desc>CTI Channel to Trigger Enable 0 Register</desc>
  </register>
  <register offset="0xf88990a4" type="rw" uniqueid="ps7_debug_cpu_cti1_CTIOUTEN1">
    <name>CTIOUTEN1</name>
    <desc>CTI Channel to Trigger Enable 1 Register</desc>
  </register>
  <register offset="0xf88990a8" type="rw" uniqueid="ps7_debug_cpu_cti1_CTIOUTEN2">
    <name>CTIOUTEN2</name>
    <desc>CTI Channel to Trigger Enable 2 Register</desc>
  </register>
  <register offset="0xf88990ac" type="rw" uniqueid="ps7_debug_cpu_cti1_CTIOUTEN3">
    <name>CTIOUTEN3</name>
    <desc>CTI Channel to Trigger Enable 3 Register</desc>
  </register>
  <register offset="0xf88990b0" type="rw" uniqueid="ps7_debug_cpu_cti1_CTIOUTEN4">
    <name>CTIOUTEN4</name>
    <desc>CTI Channel to Trigger Enable 4 Register</desc>
  </register>
  <register offset="0xf88990b4" type="rw" uniqueid="ps7_debug_cpu_cti1_CTIOUTEN5">
    <name>CTIOUTEN5</name>
    <desc>CTI Channel to Trigger Enable 5 Register</desc>
  </register>
  <register offset="0xf88990b8" type="rw" uniqueid="ps7_debug_cpu_cti1_CTIOUTEN6">
    <name>CTIOUTEN6</name>
    <desc>CTI Channel to Trigger Enable 6 Register</desc>
  </register>
  <register offset="0xf88990bc" type="rw" uniqueid="ps7_debug_cpu_cti1_CTIOUTEN7">
    <name>CTIOUTEN7</name>
    <desc>CTI Channel to Trigger Enable 7 Register</desc>
  </register>
  <register offset="0xf8899130" type="ro" uniqueid="ps7_debug_cpu_cti1_CTITRIGINSTATUS">
    <name>CTITRIGINSTATUS</name>
    <desc>CTI Trigger In Status Register</desc>
  </register>
  <register offset="0xf8899134" type="ro" uniqueid="ps7_debug_cpu_cti1_CTITRIGOUTSTATUS">
    <name>CTITRIGOUTSTATUS</name>
    <desc>CTI Trigger Out Status Register</desc>
  </register>
  <register offset="0xf8899138" type="ro" uniqueid="ps7_debug_cpu_cti1_CTICHINSTATUS">
    <name>CTICHINSTATUS</name>
    <desc>CTI Channel In Status Register</desc>
  </register>
  <register offset="0xf889913c" type="ro" uniqueid="ps7_debug_cpu_cti1_CTICHOUTSTATUS">
    <name>CTICHOUTSTATUS</name>
    <desc>CTI Channel Out Status Register</desc>
  </register>
  <register offset="0xf8899140" type="rw" uniqueid="ps7_debug_cpu_cti1_CTIGATE">
    <name>CTIGATE</name>
    <desc>Enable CTI Channel Gate Register</desc>
  </register>
  <register offset="0xf8899144" type="rw" uniqueid="ps7_debug_cpu_cti1_ASICCTL">
    <name>ASICCTL</name>
    <desc>External Multiplexor Control Register</desc>
  </register>
  <register offset="0xf8899edc" type="wo" uniqueid="ps7_debug_cpu_cti1_ITCHINACK">
    <name>ITCHINACK</name>
    <desc>ITCHINACK Register</desc>
  </register>
  <register offset="0xf8899ee0" type="wo" uniqueid="ps7_debug_cpu_cti1_ITTRIGINACK">
    <name>ITTRIGINACK</name>
    <desc>ITTRIGINACK Register</desc>
  </register>
  <register offset="0xf8899ee4" type="wo" uniqueid="ps7_debug_cpu_cti1_ITCHOUT">
    <name>ITCHOUT</name>
    <desc>ITCHOUT Register</desc>
  </register>
  <register offset="0xf8899ee8" type="wo" uniqueid="ps7_debug_cpu_cti1_ITTRIGOUT">
    <name>ITTRIGOUT</name>
    <desc>ITTRIGOUT Register</desc>
  </register>
  <register offset="0xf8899eec" type="ro" uniqueid="ps7_debug_cpu_cti1_ITCHOUTACK">
    <name>ITCHOUTACK</name>
    <desc>ITCHOUTACK Register</desc>
  </register>
  <register offset="0xf8899ef0" type="ro" uniqueid="ps7_debug_cpu_cti1_ITTRIGOUTACK">
    <name>ITTRIGOUTACK</name>
    <desc>ITTRIGOUTACK Register</desc>
  </register>
  <register offset="0xf8899ef4" type="ro" uniqueid="ps7_debug_cpu_cti1_ITCHIN">
    <name>ITCHIN</name>
    <desc>ITCHIN Register</desc>
  </register>
  <register offset="0xf8899ef8" type="ro" uniqueid="ps7_debug_cpu_cti1_ITTRIGIN">
    <name>ITTRIGIN</name>
    <desc>ITTRIGIN Register</desc>
  </register>
  <register offset="0xf8899f00" type="rw" uniqueid="ps7_debug_cpu_cti1_ITCTRL">
    <name>ITCTRL</name>
    <desc>IT Control Register</desc>
  </register>
  <register offset="0xf8899fa0" type="rw" uniqueid="ps7_debug_cpu_cti1_CTSR">
    <name>CTSR</name>
    <desc>Claim Tag Set Register</desc>
  </register>
  <register offset="0xf8899fa4" type="rw" uniqueid="ps7_debug_cpu_cti1_CTCR">
    <name>CTCR</name>
    <desc>Claim Tag Clear Register</desc>
  </register>
  <register offset="0xf8899fb0" type="wo" uniqueid="ps7_debug_cpu_cti1_LAR">
    <name>LAR</name>
    <desc>Lock Access Register</desc>
  </register>
  <register offset="0xf8899fb4" type="ro" uniqueid="ps7_debug_cpu_cti1_LSR">
    <name>LSR</name>
    <desc>Lock Status Register</desc>
  </register>
  <register offset="0xf8899fb8" type="ro" uniqueid="ps7_debug_cpu_cti1_ASR">
    <name>ASR</name>
    <desc>Authentication Status Register</desc>
  </register>
  <register offset="0xf8899fc8" type="ro" uniqueid="ps7_debug_cpu_cti1_DEVID">
    <name>DEVID</name>
    <desc>Device ID</desc>
  </register>
  <register offset="0xf8899fcc" type="ro" uniqueid="ps7_debug_cpu_cti1_DTIR">
    <name>DTIR</name>
    <desc>Device Type Identifier Register</desc>
  </register>
  <register offset="0xf8899fd0" type="ro" uniqueid="ps7_debug_cpu_cti1_PERIPHID4">
    <name>PERIPHID4</name>
    <desc>Peripheral ID4</desc>
  </register>
  <register offset="0xf8899fd4" type="ro" uniqueid="ps7_debug_cpu_cti1_PERIPHID5">
    <name>PERIPHID5</name>
    <desc>Peripheral ID5</desc>
  </register>
  <register offset="0xf8899fd8" type="ro" uniqueid="ps7_debug_cpu_cti1_PERIPHID6">
    <name>PERIPHID6</name>
    <desc>Peripheral ID6</desc>
  </register>
  <register offset="0xf8899fdc" type="ro" uniqueid="ps7_debug_cpu_cti1_PERIPHID7">
    <name>PERIPHID7</name>
    <desc>Peripheral ID7</desc>
  </register>
  <register offset="0xf8899fe0" type="ro" uniqueid="ps7_debug_cpu_cti1_PERIPHID0">
    <name>PERIPHID0</name>
    <desc>Peripheral ID0</desc>
  </register>
  <register offset="0xf8899fe4" type="ro" uniqueid="ps7_debug_cpu_cti1_PERIPHID1">
    <name>PERIPHID1</name>
    <desc>Peripheral ID1</desc>
  </register>
  <register offset="0xf8899fe8" type="ro" uniqueid="ps7_debug_cpu_cti1_PERIPHID2">
    <name>PERIPHID2</name>
    <desc>Peripheral ID2</desc>
  </register>
  <register offset="0xf8899fec" type="ro" uniqueid="ps7_debug_cpu_cti1_PERIPHID3">
    <name>PERIPHID3</name>
    <desc>Peripheral ID3</desc>
  </register>
  <register offset="0xf8899ff0" type="ro" uniqueid="ps7_debug_cpu_cti1_COMPID0">
    <name>COMPID0</name>
    <desc>Component ID0</desc>
  </register>
  <register offset="0xf8899ff4" type="ro" uniqueid="ps7_debug_cpu_cti1_COMPID1">
    <name>COMPID1</name>
    <desc>Component ID1</desc>
  </register>
  <register offset="0xf8899ff8" type="ro" uniqueid="ps7_debug_cpu_cti1_COMPID2">
    <name>COMPID2</name>
    <desc>Component ID2</desc>
  </register>
  <register offset="0xf8899ffc" type="ro" uniqueid="ps7_debug_cpu_cti1_COMPID3">
    <name>COMPID3</name>
    <desc>Component ID3</desc>
  </register>
  <register offset="0xf8898000" type="rw" uniqueid="ps7_debug_cpu_cti0_CTICONTROL">
    <name>CTICONTROL</name>
    <desc>CTI Control Register</desc>
  </register>
  <register offset="0xf8898010" type="wo" uniqueid="ps7_debug_cpu_cti0_CTIINTACK">
    <name>CTIINTACK</name>
    <desc>CTI Interrupt Acknowledge Register</desc>
  </register>
  <register offset="0xf8898014" type="rw" uniqueid="ps7_debug_cpu_cti0_CTIAPPSET">
    <name>CTIAPPSET</name>
    <desc>CTI Application Trigger Set Register</desc>
  </register>
  <register offset="0xf8898018" type="wo" uniqueid="ps7_debug_cpu_cti0_CTIAPPCLEAR">
    <name>CTIAPPCLEAR</name>
    <desc>CTI Application Trigger Clear Register</desc>
  </register>
  <register offset="0xf889801c" type="wo" uniqueid="ps7_debug_cpu_cti0_CTIAPPPULSE">
    <name>CTIAPPPULSE</name>
    <desc>CTI Application Pulse Register</desc>
  </register>
  <register offset="0xf8898020" type="rw" uniqueid="ps7_debug_cpu_cti0_CTIINEN0">
    <name>CTIINEN0</name>
    <desc>CTI Trigger to Channel Enable 0 Register</desc>
  </register>
  <register offset="0xf8898024" type="rw" uniqueid="ps7_debug_cpu_cti0_CTIINEN1">
    <name>CTIINEN1</name>
    <desc>CTI Trigger to Channel Enable 1 Register</desc>
  </register>
  <register offset="0xf8898028" type="rw" uniqueid="ps7_debug_cpu_cti0_CTIINEN2">
    <name>CTIINEN2</name>
    <desc>CTI Trigger to Channel Enable 2 Register</desc>
  </register>
  <register offset="0xf889802c" type="rw" uniqueid="ps7_debug_cpu_cti0_CTIINEN3">
    <name>CTIINEN3</name>
    <desc>CTI Trigger to Channel Enable 3 Register</desc>
  </register>
  <register offset="0xf8898030" type="rw" uniqueid="ps7_debug_cpu_cti0_CTIINEN4">
    <name>CTIINEN4</name>
    <desc>CTI Trigger to Channel Enable 4 Register</desc>
  </register>
  <register offset="0xf8898034" type="rw" uniqueid="ps7_debug_cpu_cti0_CTIINEN5">
    <name>CTIINEN5</name>
    <desc>CTI Trigger to Channel Enable 5 Register</desc>
  </register>
  <register offset="0xf8898038" type="rw" uniqueid="ps7_debug_cpu_cti0_CTIINEN6">
    <name>CTIINEN6</name>
    <desc>CTI Trigger to Channel Enable 6 Register</desc>
  </register>
  <register offset="0xf889803c" type="rw" uniqueid="ps7_debug_cpu_cti0_CTIINEN7">
    <name>CTIINEN7</name>
    <desc>CTI Trigger to Channel Enable 7 Register</desc>
  </register>
  <register offset="0xf88980a0" type="rw" uniqueid="ps7_debug_cpu_cti0_CTIOUTEN0">
    <name>CTIOUTEN0</name>
    <desc>CTI Channel to Trigger Enable 0 Register</desc>
  </register>
  <register offset="0xf88980a4" type="rw" uniqueid="ps7_debug_cpu_cti0_CTIOUTEN1">
    <name>CTIOUTEN1</name>
    <desc>CTI Channel to Trigger Enable 1 Register</desc>
  </register>
  <register offset="0xf88980a8" type="rw" uniqueid="ps7_debug_cpu_cti0_CTIOUTEN2">
    <name>CTIOUTEN2</name>
    <desc>CTI Channel to Trigger Enable 2 Register</desc>
  </register>
  <register offset="0xf88980ac" type="rw" uniqueid="ps7_debug_cpu_cti0_CTIOUTEN3">
    <name>CTIOUTEN3</name>
    <desc>CTI Channel to Trigger Enable 3 Register</desc>
  </register>
  <register offset="0xf88980b0" type="rw" uniqueid="ps7_debug_cpu_cti0_CTIOUTEN4">
    <name>CTIOUTEN4</name>
    <desc>CTI Channel to Trigger Enable 4 Register</desc>
  </register>
  <register offset="0xf88980b4" type="rw" uniqueid="ps7_debug_cpu_cti0_CTIOUTEN5">
    <name>CTIOUTEN5</name>
    <desc>CTI Channel to Trigger Enable 5 Register</desc>
  </register>
  <register offset="0xf88980b8" type="rw" uniqueid="ps7_debug_cpu_cti0_CTIOUTEN6">
    <name>CTIOUTEN6</name>
    <desc>CTI Channel to Trigger Enable 6 Register</desc>
  </register>
  <register offset="0xf88980bc" type="rw" uniqueid="ps7_debug_cpu_cti0_CTIOUTEN7">
    <name>CTIOUTEN7</name>
    <desc>CTI Channel to Trigger Enable 7 Register</desc>
  </register>
  <register offset="0xf8898130" type="ro" uniqueid="ps7_debug_cpu_cti0_CTITRIGINSTATUS">
    <name>CTITRIGINSTATUS</name>
    <desc>CTI Trigger In Status Register</desc>
  </register>
  <register offset="0xf8898134" type="ro" uniqueid="ps7_debug_cpu_cti0_CTITRIGOUTSTATUS">
    <name>CTITRIGOUTSTATUS</name>
    <desc>CTI Trigger Out Status Register</desc>
  </register>
  <register offset="0xf8898138" type="ro" uniqueid="ps7_debug_cpu_cti0_CTICHINSTATUS">
    <name>CTICHINSTATUS</name>
    <desc>CTI Channel In Status Register</desc>
  </register>
  <register offset="0xf889813c" type="ro" uniqueid="ps7_debug_cpu_cti0_CTICHOUTSTATUS">
    <name>CTICHOUTSTATUS</name>
    <desc>CTI Channel Out Status Register</desc>
  </register>
  <register offset="0xf8898140" type="rw" uniqueid="ps7_debug_cpu_cti0_CTIGATE">
    <name>CTIGATE</name>
    <desc>Enable CTI Channel Gate Register</desc>
  </register>
  <register offset="0xf8898144" type="rw" uniqueid="ps7_debug_cpu_cti0_ASICCTL">
    <name>ASICCTL</name>
    <desc>External Multiplexor Control Register</desc>
  </register>
  <register offset="0xf8898edc" type="wo" uniqueid="ps7_debug_cpu_cti0_ITCHINACK">
    <name>ITCHINACK</name>
    <desc>ITCHINACK Register</desc>
  </register>
  <register offset="0xf8898ee0" type="wo" uniqueid="ps7_debug_cpu_cti0_ITTRIGINACK">
    <name>ITTRIGINACK</name>
    <desc>ITTRIGINACK Register</desc>
  </register>
  <register offset="0xf8898ee4" type="wo" uniqueid="ps7_debug_cpu_cti0_ITCHOUT">
    <name>ITCHOUT</name>
    <desc>ITCHOUT Register</desc>
  </register>
  <register offset="0xf8898ee8" type="wo" uniqueid="ps7_debug_cpu_cti0_ITTRIGOUT">
    <name>ITTRIGOUT</name>
    <desc>ITTRIGOUT Register</desc>
  </register>
  <register offset="0xf8898eec" type="ro" uniqueid="ps7_debug_cpu_cti0_ITCHOUTACK">
    <name>ITCHOUTACK</name>
    <desc>ITCHOUTACK Register</desc>
  </register>
  <register offset="0xf8898ef0" type="ro" uniqueid="ps7_debug_cpu_cti0_ITTRIGOUTACK">
    <name>ITTRIGOUTACK</name>
    <desc>ITTRIGOUTACK Register</desc>
  </register>
  <register offset="0xf8898ef4" type="ro" uniqueid="ps7_debug_cpu_cti0_ITCHIN">
    <name>ITCHIN</name>
    <desc>ITCHIN Register</desc>
  </register>
  <register offset="0xf8898ef8" type="ro" uniqueid="ps7_debug_cpu_cti0_ITTRIGIN">
    <name>ITTRIGIN</name>
    <desc>ITTRIGIN Register</desc>
  </register>
  <register offset="0xf8898f00" type="rw" uniqueid="ps7_debug_cpu_cti0_ITCTRL">
    <name>ITCTRL</name>
    <desc>IT Control Register</desc>
  </register>
  <register offset="0xf8898fa0" type="rw" uniqueid="ps7_debug_cpu_cti0_CTSR">
    <name>CTSR</name>
    <desc>Claim Tag Set Register</desc>
  </register>
  <register offset="0xf8898fa4" type="rw" uniqueid="ps7_debug_cpu_cti0_CTCR">
    <name>CTCR</name>
    <desc>Claim Tag Clear Register</desc>
  </register>
  <register offset="0xf8898fb0" type="wo" uniqueid="ps7_debug_cpu_cti0_LAR">
    <name>LAR</name>
    <desc>Lock Access Register</desc>
  </register>
  <register offset="0xf8898fb4" type="ro" uniqueid="ps7_debug_cpu_cti0_LSR">
    <name>LSR</name>
    <desc>Lock Status Register</desc>
  </register>
  <register offset="0xf8898fb8" type="ro" uniqueid="ps7_debug_cpu_cti0_ASR">
    <name>ASR</name>
    <desc>Authentication Status Register</desc>
  </register>
  <register offset="0xf8898fc8" type="ro" uniqueid="ps7_debug_cpu_cti0_DEVID">
    <name>DEVID</name>
    <desc>Device ID</desc>
  </register>
  <register offset="0xf8898fcc" type="ro" uniqueid="ps7_debug_cpu_cti0_DTIR">
    <name>DTIR</name>
    <desc>Device Type Identifier Register</desc>
  </register>
  <register offset="0xf8898fd0" type="ro" uniqueid="ps7_debug_cpu_cti0_PERIPHID4">
    <name>PERIPHID4</name>
    <desc>Peripheral ID4</desc>
  </register>
  <register offset="0xf8898fd4" type="ro" uniqueid="ps7_debug_cpu_cti0_PERIPHID5">
    <name>PERIPHID5</name>
    <desc>Peripheral ID5</desc>
  </register>
  <register offset="0xf8898fd8" type="ro" uniqueid="ps7_debug_cpu_cti0_PERIPHID6">
    <name>PERIPHID6</name>
    <desc>Peripheral ID6</desc>
  </register>
  <register offset="0xf8898fdc" type="ro" uniqueid="ps7_debug_cpu_cti0_PERIPHID7">
    <name>PERIPHID7</name>
    <desc>Peripheral ID7</desc>
  </register>
  <register offset="0xf8898fe0" type="ro" uniqueid="ps7_debug_cpu_cti0_PERIPHID0">
    <name>PERIPHID0</name>
    <desc>Peripheral ID0</desc>
  </register>
  <register offset="0xf8898fe4" type="ro" uniqueid="ps7_debug_cpu_cti0_PERIPHID1">
    <name>PERIPHID1</name>
    <desc>Peripheral ID1</desc>
  </register>
  <register offset="0xf8898fe8" type="ro" uniqueid="ps7_debug_cpu_cti0_PERIPHID2">
    <name>PERIPHID2</name>
    <desc>Peripheral ID2</desc>
  </register>
  <register offset="0xf8898fec" type="ro" uniqueid="ps7_debug_cpu_cti0_PERIPHID3">
    <name>PERIPHID3</name>
    <desc>Peripheral ID3</desc>
  </register>
  <register offset="0xf8898ff0" type="ro" uniqueid="ps7_debug_cpu_cti0_COMPID0">
    <name>COMPID0</name>
    <desc>Component ID0</desc>
  </register>
  <register offset="0xf8898ff4" type="ro" uniqueid="ps7_debug_cpu_cti0_COMPID1">
    <name>COMPID1</name>
    <desc>Component ID1</desc>
  </register>
  <register offset="0xf8898ff8" type="ro" uniqueid="ps7_debug_cpu_cti0_COMPID2">
    <name>COMPID2</name>
    <desc>Component ID2</desc>
  </register>
  <register offset="0xf8898ffc" type="ro" uniqueid="ps7_debug_cpu_cti0_COMPID3">
    <name>COMPID3</name>
    <desc>Component ID3</desc>
  </register>
  <register offset="0xf8809000" type="rw" uniqueid="ps7_debug_cti_ftm_CTICONTROL">
    <name>CTICONTROL</name>
    <desc>CTI Control Register</desc>
  </register>
  <register offset="0xf8809010" type="wo" uniqueid="ps7_debug_cti_ftm_CTIINTACK">
    <name>CTIINTACK</name>
    <desc>CTI Interrupt Acknowledge Register</desc>
  </register>
  <register offset="0xf8809014" type="rw" uniqueid="ps7_debug_cti_ftm_CTIAPPSET">
    <name>CTIAPPSET</name>
    <desc>CTI Application Trigger Set Register</desc>
  </register>
  <register offset="0xf8809018" type="wo" uniqueid="ps7_debug_cti_ftm_CTIAPPCLEAR">
    <name>CTIAPPCLEAR</name>
    <desc>CTI Application Trigger Clear Register</desc>
  </register>
  <register offset="0xf880901c" type="wo" uniqueid="ps7_debug_cti_ftm_CTIAPPPULSE">
    <name>CTIAPPPULSE</name>
    <desc>CTI Application Pulse Register</desc>
  </register>
  <register offset="0xf8809020" type="rw" uniqueid="ps7_debug_cti_ftm_CTIINEN0">
    <name>CTIINEN0</name>
    <desc>CTI Trigger to Channel Enable 0 Register</desc>
  </register>
  <register offset="0xf8809024" type="rw" uniqueid="ps7_debug_cti_ftm_CTIINEN1">
    <name>CTIINEN1</name>
    <desc>CTI Trigger to Channel Enable 1 Register</desc>
  </register>
  <register offset="0xf8809028" type="rw" uniqueid="ps7_debug_cti_ftm_CTIINEN2">
    <name>CTIINEN2</name>
    <desc>CTI Trigger to Channel Enable 2 Register</desc>
  </register>
  <register offset="0xf880902c" type="rw" uniqueid="ps7_debug_cti_ftm_CTIINEN3">
    <name>CTIINEN3</name>
    <desc>CTI Trigger to Channel Enable 3 Register</desc>
  </register>
  <register offset="0xf8809030" type="rw" uniqueid="ps7_debug_cti_ftm_CTIINEN4">
    <name>CTIINEN4</name>
    <desc>CTI Trigger to Channel Enable 4 Register</desc>
  </register>
  <register offset="0xf8809034" type="rw" uniqueid="ps7_debug_cti_ftm_CTIINEN5">
    <name>CTIINEN5</name>
    <desc>CTI Trigger to Channel Enable 5 Register</desc>
  </register>
  <register offset="0xf8809038" type="rw" uniqueid="ps7_debug_cti_ftm_CTIINEN6">
    <name>CTIINEN6</name>
    <desc>CTI Trigger to Channel Enable 6 Register</desc>
  </register>
  <register offset="0xf880903c" type="rw" uniqueid="ps7_debug_cti_ftm_CTIINEN7">
    <name>CTIINEN7</name>
    <desc>CTI Trigger to Channel Enable 7 Register</desc>
  </register>
  <register offset="0xf88090a0" type="rw" uniqueid="ps7_debug_cti_ftm_CTIOUTEN0">
    <name>CTIOUTEN0</name>
    <desc>CTI Channel to Trigger Enable 0 Register</desc>
  </register>
  <register offset="0xf88090a4" type="rw" uniqueid="ps7_debug_cti_ftm_CTIOUTEN1">
    <name>CTIOUTEN1</name>
    <desc>CTI Channel to Trigger Enable 1 Register</desc>
  </register>
  <register offset="0xf88090a8" type="rw" uniqueid="ps7_debug_cti_ftm_CTIOUTEN2">
    <name>CTIOUTEN2</name>
    <desc>CTI Channel to Trigger Enable 2 Register</desc>
  </register>
  <register offset="0xf88090ac" type="rw" uniqueid="ps7_debug_cti_ftm_CTIOUTEN3">
    <name>CTIOUTEN3</name>
    <desc>CTI Channel to Trigger Enable 3 Register</desc>
  </register>
  <register offset="0xf88090b0" type="rw" uniqueid="ps7_debug_cti_ftm_CTIOUTEN4">
    <name>CTIOUTEN4</name>
    <desc>CTI Channel to Trigger Enable 4 Register</desc>
  </register>
  <register offset="0xf88090b4" type="rw" uniqueid="ps7_debug_cti_ftm_CTIOUTEN5">
    <name>CTIOUTEN5</name>
    <desc>CTI Channel to Trigger Enable 5 Register</desc>
  </register>
  <register offset="0xf88090b8" type="rw" uniqueid="ps7_debug_cti_ftm_CTIOUTEN6">
    <name>CTIOUTEN6</name>
    <desc>CTI Channel to Trigger Enable 6 Register</desc>
  </register>
  <register offset="0xf88090bc" type="rw" uniqueid="ps7_debug_cti_ftm_CTIOUTEN7">
    <name>CTIOUTEN7</name>
    <desc>CTI Channel to Trigger Enable 7 Register</desc>
  </register>
  <register offset="0xf8809130" type="ro" uniqueid="ps7_debug_cti_ftm_CTITRIGINSTATUS">
    <name>CTITRIGINSTATUS</name>
    <desc>CTI Trigger In Status Register</desc>
  </register>
  <register offset="0xf8809134" type="ro" uniqueid="ps7_debug_cti_ftm_CTITRIGOUTSTATUS">
    <name>CTITRIGOUTSTATUS</name>
    <desc>CTI Trigger Out Status Register</desc>
  </register>
  <register offset="0xf8809138" type="ro" uniqueid="ps7_debug_cti_ftm_CTICHINSTATUS">
    <name>CTICHINSTATUS</name>
    <desc>CTI Channel In Status Register</desc>
  </register>
  <register offset="0xf880913c" type="ro" uniqueid="ps7_debug_cti_ftm_CTICHOUTSTATUS">
    <name>CTICHOUTSTATUS</name>
    <desc>CTI Channel Out Status Register</desc>
  </register>
  <register offset="0xf8809140" type="rw" uniqueid="ps7_debug_cti_ftm_CTIGATE">
    <name>CTIGATE</name>
    <desc>Enable CTI Channel Gate Register</desc>
  </register>
  <register offset="0xf8809144" type="rw" uniqueid="ps7_debug_cti_ftm_ASICCTL">
    <name>ASICCTL</name>
    <desc>External Multiplexor Control Register</desc>
  </register>
  <register offset="0xf8809edc" type="wo" uniqueid="ps7_debug_cti_ftm_ITCHINACK">
    <name>ITCHINACK</name>
    <desc>ITCHINACK Register</desc>
  </register>
  <register offset="0xf8809ee0" type="wo" uniqueid="ps7_debug_cti_ftm_ITTRIGINACK">
    <name>ITTRIGINACK</name>
    <desc>ITTRIGINACK Register</desc>
  </register>
  <register offset="0xf8809ee4" type="wo" uniqueid="ps7_debug_cti_ftm_ITCHOUT">
    <name>ITCHOUT</name>
    <desc>ITCHOUT Register</desc>
  </register>
  <register offset="0xf8809ee8" type="wo" uniqueid="ps7_debug_cti_ftm_ITTRIGOUT">
    <name>ITTRIGOUT</name>
    <desc>ITTRIGOUT Register</desc>
  </register>
  <register offset="0xf8809eec" type="ro" uniqueid="ps7_debug_cti_ftm_ITCHOUTACK">
    <name>ITCHOUTACK</name>
    <desc>ITCHOUTACK Register</desc>
  </register>
  <register offset="0xf8809ef0" type="ro" uniqueid="ps7_debug_cti_ftm_ITTRIGOUTACK">
    <name>ITTRIGOUTACK</name>
    <desc>ITTRIGOUTACK Register</desc>
  </register>
  <register offset="0xf8809ef4" type="ro" uniqueid="ps7_debug_cti_ftm_ITCHIN">
    <name>ITCHIN</name>
    <desc>ITCHIN Register</desc>
  </register>
  <register offset="0xf8809ef8" type="ro" uniqueid="ps7_debug_cti_ftm_ITTRIGIN">
    <name>ITTRIGIN</name>
    <desc>ITTRIGIN Register</desc>
  </register>
  <register offset="0xf8809f00" type="rw" uniqueid="ps7_debug_cti_ftm_ITCTRL">
    <name>ITCTRL</name>
    <desc>IT Control Register</desc>
  </register>
  <register offset="0xf8809fa0" type="rw" uniqueid="ps7_debug_cti_ftm_CTSR">
    <name>CTSR</name>
    <desc>Claim Tag Set Register</desc>
  </register>
  <register offset="0xf8809fa4" type="rw" uniqueid="ps7_debug_cti_ftm_CTCR">
    <name>CTCR</name>
    <desc>Claim Tag Clear Register</desc>
  </register>
  <register offset="0xf8809fb0" type="wo" uniqueid="ps7_debug_cti_ftm_LAR">
    <name>LAR</name>
    <desc>Lock Access Register</desc>
  </register>
  <register offset="0xf8809fb4" type="ro" uniqueid="ps7_debug_cti_ftm_LSR">
    <name>LSR</name>
    <desc>Lock Status Register</desc>
  </register>
  <register offset="0xf8809fb8" type="ro" uniqueid="ps7_debug_cti_ftm_ASR">
    <name>ASR</name>
    <desc>Authentication Status Register</desc>
  </register>
  <register offset="0xf8809fc8" type="ro" uniqueid="ps7_debug_cti_ftm_DEVID">
    <name>DEVID</name>
    <desc>Device ID</desc>
  </register>
  <register offset="0xf8809fcc" type="ro" uniqueid="ps7_debug_cti_ftm_DTIR">
    <name>DTIR</name>
    <desc>Device Type Identifier Register</desc>
  </register>
  <register offset="0xf8809fd0" type="ro" uniqueid="ps7_debug_cti_ftm_PERIPHID4">
    <name>PERIPHID4</name>
    <desc>Peripheral ID4</desc>
  </register>
  <register offset="0xf8809fd4" type="ro" uniqueid="ps7_debug_cti_ftm_PERIPHID5">
    <name>PERIPHID5</name>
    <desc>Peripheral ID5</desc>
  </register>
  <register offset="0xf8809fd8" type="ro" uniqueid="ps7_debug_cti_ftm_PERIPHID6">
    <name>PERIPHID6</name>
    <desc>Peripheral ID6</desc>
  </register>
  <register offset="0xf8809fdc" type="ro" uniqueid="ps7_debug_cti_ftm_PERIPHID7">
    <name>PERIPHID7</name>
    <desc>Peripheral ID7</desc>
  </register>
  <register offset="0xf8809fe0" type="ro" uniqueid="ps7_debug_cti_ftm_PERIPHID0">
    <name>PERIPHID0</name>
    <desc>Peripheral ID0</desc>
  </register>
  <register offset="0xf8809fe4" type="ro" uniqueid="ps7_debug_cti_ftm_PERIPHID1">
    <name>PERIPHID1</name>
    <desc>Peripheral ID1</desc>
  </register>
  <register offset="0xf8809fe8" type="ro" uniqueid="ps7_debug_cti_ftm_PERIPHID2">
    <name>PERIPHID2</name>
    <desc>Peripheral ID2</desc>
  </register>
  <register offset="0xf8809fec" type="ro" uniqueid="ps7_debug_cti_ftm_PERIPHID3">
    <name>PERIPHID3</name>
    <desc>Peripheral ID3</desc>
  </register>
  <register offset="0xf8809ff0" type="ro" uniqueid="ps7_debug_cti_ftm_COMPID0">
    <name>COMPID0</name>
    <desc>Component ID0</desc>
  </register>
  <register offset="0xf8809ff4" type="ro" uniqueid="ps7_debug_cti_ftm_COMPID1">
    <name>COMPID1</name>
    <desc>Component ID1</desc>
  </register>
  <register offset="0xf8809ff8" type="ro" uniqueid="ps7_debug_cti_ftm_COMPID2">
    <name>COMPID2</name>
    <desc>Component ID2</desc>
  </register>
  <register offset="0xf8809ffc" type="ro" uniqueid="ps7_debug_cti_ftm_COMPID3">
    <name>COMPID3</name>
    <desc>Component ID3</desc>
  </register>
  <register offset="0xf8802000" type="rw" uniqueid="ps7_debug_cti_etb_tpiu_CTICONTROL">
    <name>CTICONTROL</name>
    <desc>CTI Control Register</desc>
  </register>
  <register offset="0xf8802010" type="wo" uniqueid="ps7_debug_cti_etb_tpiu_CTIINTACK">
    <name>CTIINTACK</name>
    <desc>CTI Interrupt Acknowledge Register</desc>
  </register>
  <register offset="0xf8802014" type="rw" uniqueid="ps7_debug_cti_etb_tpiu_CTIAPPSET">
    <name>CTIAPPSET</name>
    <desc>CTI Application Trigger Set Register</desc>
  </register>
  <register offset="0xf8802018" type="wo" uniqueid="ps7_debug_cti_etb_tpiu_CTIAPPCLEAR">
    <name>CTIAPPCLEAR</name>
    <desc>CTI Application Trigger Clear Register</desc>
  </register>
  <register offset="0xf880201c" type="wo" uniqueid="ps7_debug_cti_etb_tpiu_CTIAPPPULSE">
    <name>CTIAPPPULSE</name>
    <desc>CTI Application Pulse Register</desc>
  </register>
  <register offset="0xf8802020" type="rw" uniqueid="ps7_debug_cti_etb_tpiu_CTIINEN0">
    <name>CTIINEN0</name>
    <desc>CTI Trigger to Channel Enable 0 Register</desc>
  </register>
  <register offset="0xf8802024" type="rw" uniqueid="ps7_debug_cti_etb_tpiu_CTIINEN1">
    <name>CTIINEN1</name>
    <desc>CTI Trigger to Channel Enable 1 Register</desc>
  </register>
  <register offset="0xf8802028" type="rw" uniqueid="ps7_debug_cti_etb_tpiu_CTIINEN2">
    <name>CTIINEN2</name>
    <desc>CTI Trigger to Channel Enable 2 Register</desc>
  </register>
  <register offset="0xf880202c" type="rw" uniqueid="ps7_debug_cti_etb_tpiu_CTIINEN3">
    <name>CTIINEN3</name>
    <desc>CTI Trigger to Channel Enable 3 Register</desc>
  </register>
  <register offset="0xf8802030" type="rw" uniqueid="ps7_debug_cti_etb_tpiu_CTIINEN4">
    <name>CTIINEN4</name>
    <desc>CTI Trigger to Channel Enable 4 Register</desc>
  </register>
  <register offset="0xf8802034" type="rw" uniqueid="ps7_debug_cti_etb_tpiu_CTIINEN5">
    <name>CTIINEN5</name>
    <desc>CTI Trigger to Channel Enable 5 Register</desc>
  </register>
  <register offset="0xf8802038" type="rw" uniqueid="ps7_debug_cti_etb_tpiu_CTIINEN6">
    <name>CTIINEN6</name>
    <desc>CTI Trigger to Channel Enable 6 Register</desc>
  </register>
  <register offset="0xf880203c" type="rw" uniqueid="ps7_debug_cti_etb_tpiu_CTIINEN7">
    <name>CTIINEN7</name>
    <desc>CTI Trigger to Channel Enable 7 Register</desc>
  </register>
  <register offset="0xf88020a0" type="rw" uniqueid="ps7_debug_cti_etb_tpiu_CTIOUTEN0">
    <name>CTIOUTEN0</name>
    <desc>CTI Channel to Trigger Enable 0 Register</desc>
  </register>
  <register offset="0xf88020a4" type="rw" uniqueid="ps7_debug_cti_etb_tpiu_CTIOUTEN1">
    <name>CTIOUTEN1</name>
    <desc>CTI Channel to Trigger Enable 1 Register</desc>
  </register>
  <register offset="0xf88020a8" type="rw" uniqueid="ps7_debug_cti_etb_tpiu_CTIOUTEN2">
    <name>CTIOUTEN2</name>
    <desc>CTI Channel to Trigger Enable 2 Register</desc>
  </register>
  <register offset="0xf88020ac" type="rw" uniqueid="ps7_debug_cti_etb_tpiu_CTIOUTEN3">
    <name>CTIOUTEN3</name>
    <desc>CTI Channel to Trigger Enable 3 Register</desc>
  </register>
  <register offset="0xf88020b0" type="rw" uniqueid="ps7_debug_cti_etb_tpiu_CTIOUTEN4">
    <name>CTIOUTEN4</name>
    <desc>CTI Channel to Trigger Enable 4 Register</desc>
  </register>
  <register offset="0xf88020b4" type="rw" uniqueid="ps7_debug_cti_etb_tpiu_CTIOUTEN5">
    <name>CTIOUTEN5</name>
    <desc>CTI Channel to Trigger Enable 5 Register</desc>
  </register>
  <register offset="0xf88020b8" type="rw" uniqueid="ps7_debug_cti_etb_tpiu_CTIOUTEN6">
    <name>CTIOUTEN6</name>
    <desc>CTI Channel to Trigger Enable 6 Register</desc>
  </register>
  <register offset="0xf88020bc" type="rw" uniqueid="ps7_debug_cti_etb_tpiu_CTIOUTEN7">
    <name>CTIOUTEN7</name>
    <desc>CTI Channel to Trigger Enable 7 Register</desc>
  </register>
  <register offset="0xf8802130" type="ro" uniqueid="ps7_debug_cti_etb_tpiu_CTITRIGINSTATUS">
    <name>CTITRIGINSTATUS</name>
    <desc>CTI Trigger In Status Register</desc>
  </register>
  <register offset="0xf8802134" type="ro" uniqueid="ps7_debug_cti_etb_tpiu_CTITRIGOUTSTATUS">
    <name>CTITRIGOUTSTATUS</name>
    <desc>CTI Trigger Out Status Register</desc>
  </register>
  <register offset="0xf8802138" type="ro" uniqueid="ps7_debug_cti_etb_tpiu_CTICHINSTATUS">
    <name>CTICHINSTATUS</name>
    <desc>CTI Channel In Status Register</desc>
  </register>
  <register offset="0xf880213c" type="ro" uniqueid="ps7_debug_cti_etb_tpiu_CTICHOUTSTATUS">
    <name>CTICHOUTSTATUS</name>
    <desc>CTI Channel Out Status Register</desc>
  </register>
  <register offset="0xf8802140" type="rw" uniqueid="ps7_debug_cti_etb_tpiu_CTIGATE">
    <name>CTIGATE</name>
    <desc>Enable CTI Channel Gate Register</desc>
  </register>
  <register offset="0xf8802144" type="rw" uniqueid="ps7_debug_cti_etb_tpiu_ASICCTL">
    <name>ASICCTL</name>
    <desc>External Multiplexor Control Register</desc>
  </register>
  <register offset="0xf8802edc" type="wo" uniqueid="ps7_debug_cti_etb_tpiu_ITCHINACK">
    <name>ITCHINACK</name>
    <desc>ITCHINACK Register</desc>
  </register>
  <register offset="0xf8802ee0" type="wo" uniqueid="ps7_debug_cti_etb_tpiu_ITTRIGINACK">
    <name>ITTRIGINACK</name>
    <desc>ITTRIGINACK Register</desc>
  </register>
  <register offset="0xf8802ee4" type="wo" uniqueid="ps7_debug_cti_etb_tpiu_ITCHOUT">
    <name>ITCHOUT</name>
    <desc>ITCHOUT Register</desc>
  </register>
  <register offset="0xf8802ee8" type="wo" uniqueid="ps7_debug_cti_etb_tpiu_ITTRIGOUT">
    <name>ITTRIGOUT</name>
    <desc>ITTRIGOUT Register</desc>
  </register>
  <register offset="0xf8802eec" type="ro" uniqueid="ps7_debug_cti_etb_tpiu_ITCHOUTACK">
    <name>ITCHOUTACK</name>
    <desc>ITCHOUTACK Register</desc>
  </register>
  <register offset="0xf8802ef0" type="ro" uniqueid="ps7_debug_cti_etb_tpiu_ITTRIGOUTACK">
    <name>ITTRIGOUTACK</name>
    <desc>ITTRIGOUTACK Register</desc>
  </register>
  <register offset="0xf8802ef4" type="ro" uniqueid="ps7_debug_cti_etb_tpiu_ITCHIN">
    <name>ITCHIN</name>
    <desc>ITCHIN Register</desc>
  </register>
  <register offset="0xf8802ef8" type="ro" uniqueid="ps7_debug_cti_etb_tpiu_ITTRIGIN">
    <name>ITTRIGIN</name>
    <desc>ITTRIGIN Register</desc>
  </register>
  <register offset="0xf8802f00" type="rw" uniqueid="ps7_debug_cti_etb_tpiu_ITCTRL">
    <name>ITCTRL</name>
    <desc>IT Control Register</desc>
  </register>
  <register offset="0xf8802fa0" type="rw" uniqueid="ps7_debug_cti_etb_tpiu_CTSR">
    <name>CTSR</name>
    <desc>Claim Tag Set Register</desc>
  </register>
  <register offset="0xf8802fa4" type="rw" uniqueid="ps7_debug_cti_etb_tpiu_CTCR">
    <name>CTCR</name>
    <desc>Claim Tag Clear Register</desc>
  </register>
  <register offset="0xf8802fb0" type="wo" uniqueid="ps7_debug_cti_etb_tpiu_LAR">
    <name>LAR</name>
    <desc>Lock Access Register</desc>
  </register>
  <register offset="0xf8802fb4" type="ro" uniqueid="ps7_debug_cti_etb_tpiu_LSR">
    <name>LSR</name>
    <desc>Lock Status Register</desc>
  </register>
  <register offset="0xf8802fb8" type="ro" uniqueid="ps7_debug_cti_etb_tpiu_ASR">
    <name>ASR</name>
    <desc>Authentication Status Register</desc>
  </register>
  <register offset="0xf8802fc8" type="ro" uniqueid="ps7_debug_cti_etb_tpiu_DEVID">
    <name>DEVID</name>
    <desc>Device ID</desc>
  </register>
  <register offset="0xf8802fcc" type="ro" uniqueid="ps7_debug_cti_etb_tpiu_DTIR">
    <name>DTIR</name>
    <desc>Device Type Identifier Register</desc>
  </register>
  <register offset="0xf8802fd0" type="ro" uniqueid="ps7_debug_cti_etb_tpiu_PERIPHID4">
    <name>PERIPHID4</name>
    <desc>Peripheral ID4</desc>
  </register>
  <register offset="0xf8802fd4" type="ro" uniqueid="ps7_debug_cti_etb_tpiu_PERIPHID5">
    <name>PERIPHID5</name>
    <desc>Peripheral ID5</desc>
  </register>
  <register offset="0xf8802fd8" type="ro" uniqueid="ps7_debug_cti_etb_tpiu_PERIPHID6">
    <name>PERIPHID6</name>
    <desc>Peripheral ID6</desc>
  </register>
  <register offset="0xf8802fdc" type="ro" uniqueid="ps7_debug_cti_etb_tpiu_PERIPHID7">
    <name>PERIPHID7</name>
    <desc>Peripheral ID7</desc>
  </register>
  <register offset="0xf8802fe0" type="ro" uniqueid="ps7_debug_cti_etb_tpiu_PERIPHID0">
    <name>PERIPHID0</name>
    <desc>Peripheral ID0</desc>
  </register>
  <register offset="0xf8802fe4" type="ro" uniqueid="ps7_debug_cti_etb_tpiu_PERIPHID1">
    <name>PERIPHID1</name>
    <desc>Peripheral ID1</desc>
  </register>
  <register offset="0xf8802fe8" type="ro" uniqueid="ps7_debug_cti_etb_tpiu_PERIPHID2">
    <name>PERIPHID2</name>
    <desc>Peripheral ID2</desc>
  </register>
  <register offset="0xf8802fec" type="ro" uniqueid="ps7_debug_cti_etb_tpiu_PERIPHID3">
    <name>PERIPHID3</name>
    <desc>Peripheral ID3</desc>
  </register>
  <register offset="0xf8802ff0" type="ro" uniqueid="ps7_debug_cti_etb_tpiu_COMPID0">
    <name>COMPID0</name>
    <desc>Component ID0</desc>
  </register>
  <register offset="0xf8802ff4" type="ro" uniqueid="ps7_debug_cti_etb_tpiu_COMPID1">
    <name>COMPID1</name>
    <desc>Component ID1</desc>
  </register>
  <register offset="0xf8802ff8" type="ro" uniqueid="ps7_debug_cti_etb_tpiu_COMPID2">
    <name>COMPID2</name>
    <desc>Component ID2</desc>
  </register>
  <register offset="0xf8802ffc" type="ro" uniqueid="ps7_debug_cti_etb_tpiu_COMPID3">
    <name>COMPID3</name>
    <desc>Component ID3</desc>
  </register>
  <register offset="0xe0001000" type="rw" uniqueid="ps7_uart1_Control_reg0">
    <name>Control_reg0</name>
    <desc>UART Control register</desc>
  </register>
  <register offset="0xe0001004" type="rw" uniqueid="ps7_uart1_mode_reg0">
    <name>mode_reg0</name>
    <desc>UART Mode register</desc>
  </register>
  <register offset="0xe0001008" type="rw" uniqueid="ps7_uart1_Intrpt_en_reg0">
    <name>Intrpt_en_reg0</name>
    <desc>Interrupt Enable register</desc>
  </register>
  <register offset="0xe000100c" type="rw" uniqueid="ps7_uart1_Intrpt_dis_reg0">
    <name>Intrpt_dis_reg0</name>
    <desc>Interrupt disable register</desc>
  </register>
  <register offset="0xe0001010" type="ro" uniqueid="ps7_uart1_Intrpt_mask_reg0">
    <name>Intrpt_mask_reg0</name>
    <desc>Interrupt mask register</desc>
  </register>
  <register offset="0xe0001014" type="rw" uniqueid="ps7_uart1_Chnl_int_sts_reg0">
    <name>Chnl_int_sts_reg0</name>
    <desc>Channel interrupt Status register</desc>
  </register>
  <register offset="0xe0001018" type="rw" uniqueid="ps7_uart1_Baud_rate_gen_reg0">
    <name>Baud_rate_gen_reg0</name>
    <desc>Baud rate divider register</desc>
  </register>
  <register offset="0xe000101c" type="rw" uniqueid="ps7_uart1_Rcvr_timeout_reg0">
    <name>Rcvr_timeout_reg0</name>
    <desc>Receiver timeout register</desc>
  </register>
  <register offset="0xe0001020" type="rw" uniqueid="ps7_uart1_Rcvr_FIFO_trigger_level0">
    <name>Rcvr_FIFO_trigger_level0</name>
    <desc>Receiver FIFO trigger level register</desc>
  </register>
  <register offset="0xe0001024" type="rw" uniqueid="ps7_uart1_Modem_ctrl_reg0">
    <name>Modem_ctrl_reg0</name>
    <desc>Modem control register</desc>
  </register>
  <register offset="0xe0001028" type="ro" uniqueid="ps7_uart1_Modem_sts_reg0">
    <name>Modem_sts_reg0</name>
    <desc>Modem status register</desc>
  </register>
  <register offset="0xe000102c" type="ro" uniqueid="ps7_uart1_Channel_sts_reg0">
    <name>Channel_sts_reg0</name>
    <desc>Channel Status register</desc>
  </register>
  <register offset="0xe0001030" type="rw" uniqueid="ps7_uart1_TX_RX_FIFO0">
    <name>TX_RX_FIFO0</name>
    <desc>Transmit and Receive FIFO</desc>
  </register>
  <register offset="0xe0001034" type="rw" uniqueid="ps7_uart1_Baud_rate_divider_reg0">
    <name>Baud_rate_divider_reg0</name>
    <desc>baud rate divider register</desc>
  </register>
  <register offset="0xe0001038" type="rw" uniqueid="ps7_uart1_Flow_delay_reg0">
    <name>Flow_delay_reg0</name>
    <desc>Flow Control Delay Register</desc>
  </register>
  <register offset="0xe000103c" type="rw" uniqueid="ps7_uart1_IR_min_rcv_pulse_wdth0">
    <name>IR_min_rcv_pulse_wdth0</name>
    <desc>IR Minimum Received Pulse Width Register</desc>
  </register>
  <register offset="0xe0001040" type="rw" uniqueid="ps7_uart1_IR_transmitted_pulse_wdth0">
    <name>IR_transmitted_pulse_wdth0</name>
    <desc>IR Transmitted Pulse Width Register</desc>
  </register>
  <register offset="0xe0001044" type="rw" uniqueid="ps7_uart1_Tx_FIFO_trigger_level0">
    <name>Tx_FIFO_trigger_level0</name>
    <desc>Transmitter FIFO Trigger Level Register</desc>
  </register>
  <register offset="0xe0000000" type="rw" uniqueid="ps7_uart0_Control_reg0">
    <name>Control_reg0</name>
    <desc>UART Control register</desc>
  </register>
  <register offset="0xe0000004" type="rw" uniqueid="ps7_uart0_mode_reg0">
    <name>mode_reg0</name>
    <desc>UART Mode register</desc>
  </register>
  <register offset="0xe0000008" type="rw" uniqueid="ps7_uart0_Intrpt_en_reg0">
    <name>Intrpt_en_reg0</name>
    <desc>Interrupt Enable register</desc>
  </register>
  <register offset="0xe000000c" type="rw" uniqueid="ps7_uart0_Intrpt_dis_reg0">
    <name>Intrpt_dis_reg0</name>
    <desc>Interrupt disable register</desc>
  </register>
  <register offset="0xe0000010" type="ro" uniqueid="ps7_uart0_Intrpt_mask_reg0">
    <name>Intrpt_mask_reg0</name>
    <desc>Interrupt mask register</desc>
  </register>
  <register offset="0xe0000014" type="rw" uniqueid="ps7_uart0_Chnl_int_sts_reg0">
    <name>Chnl_int_sts_reg0</name>
    <desc>Channel interrupt Status register</desc>
  </register>
  <register offset="0xe0000018" type="rw" uniqueid="ps7_uart0_Baud_rate_gen_reg0">
    <name>Baud_rate_gen_reg0</name>
    <desc>Baud rate divider register</desc>
  </register>
  <register offset="0xe000001c" type="rw" uniqueid="ps7_uart0_Rcvr_timeout_reg0">
    <name>Rcvr_timeout_reg0</name>
    <desc>Receiver timeout register</desc>
  </register>
  <register offset="0xe0000020" type="rw" uniqueid="ps7_uart0_Rcvr_FIFO_trigger_level0">
    <name>Rcvr_FIFO_trigger_level0</name>
    <desc>Receiver FIFO trigger level register</desc>
  </register>
  <register offset="0xe0000024" type="rw" uniqueid="ps7_uart0_Modem_ctrl_reg0">
    <name>Modem_ctrl_reg0</name>
    <desc>Modem control register</desc>
  </register>
  <register offset="0xe0000028" type="ro" uniqueid="ps7_uart0_Modem_sts_reg0">
    <name>Modem_sts_reg0</name>
    <desc>Modem status register</desc>
  </register>
  <register offset="0xe000002c" type="ro" uniqueid="ps7_uart0_Channel_sts_reg0">
    <name>Channel_sts_reg0</name>
    <desc>Channel Status register</desc>
  </register>
  <register offset="0xe0000030" type="rw" uniqueid="ps7_uart0_TX_RX_FIFO0">
    <name>TX_RX_FIFO0</name>
    <desc>Transmit and Receive FIFO</desc>
  </register>
  <register offset="0xe0000034" type="rw" uniqueid="ps7_uart0_Baud_rate_divider_reg0">
    <name>Baud_rate_divider_reg0</name>
    <desc>baud rate divider register</desc>
  </register>
  <register offset="0xe0000038" type="rw" uniqueid="ps7_uart0_Flow_delay_reg0">
    <name>Flow_delay_reg0</name>
    <desc>Flow Control Delay Register</desc>
  </register>
  <register offset="0xe000003c" type="rw" uniqueid="ps7_uart0_IR_min_rcv_pulse_wdth0">
    <name>IR_min_rcv_pulse_wdth0</name>
    <desc>IR Minimum Received Pulse Width Register</desc>
  </register>
  <register offset="0xe0000040" type="rw" uniqueid="ps7_uart0_IR_transmitted_pulse_wdth0">
    <name>IR_transmitted_pulse_wdth0</name>
    <desc>IR Transmitted Pulse Width Register</desc>
  </register>
  <register offset="0xe0000044" type="rw" uniqueid="ps7_uart0_Tx_FIFO_trigger_level0">
    <name>Tx_FIFO_trigger_level0</name>
    <desc>Transmitter FIFO Trigger Level Register</desc>
  </register>
  <register offset="0xe000c000" type="rw" uniqueid="ps7_gem1_net_ctrl">
    <name>net_ctrl</name>
    <desc>The network control register contains general MAC control functions for both receiver and transmitter.</desc>
  </register>
  <register offset="0xe000c004" type="rw" uniqueid="ps7_gem1_net_cfg">
    <name>net_cfg</name>
    <desc>The network configuration register contains functions for setting the mode of operation for the Gigabit Ethernet MAC</desc>
  </register>
  <register offset="0xe000c008" type="ro" uniqueid="ps7_gem1_net_status">
    <name>net_status</name>
    <desc>The network status register returns status information with respect to the PHY management
interface.</desc>
  </register>
  <register offset="0xe000c00c" type="rw" uniqueid="ps7_gem1_user_io">
    <name>user_io</name>
    <desc>User Input/Output.
The GEM design provides up to 16 inputs and 16 outputs so that the I/O may be read or set under the control of the processor interface.
If the user I/O is disabled as a configuration option, this address space is defined as reserved, and hence will be a read-only register of the value 0x0.
If enabled, the number of inputs and outputs can be configured separately. The first output will be represented in bit 0 of the user I/O register, the second output will use bit 1 and so on.
The first input will be represented in bit 16 of the user I/O register, the second input will use bit 17 and so on.</desc>
  </register>
  <register offset="0xe000c010" type="rw" uniqueid="ps7_gem1_dma_cfg">
    <name>dma_cfg</name>
    <desc>DMA Configuration Register</desc>
  </register>
  <register offset="0xe000c014" type="rw" uniqueid="ps7_gem1_tx_status">
    <name>tx_status</name>
    <desc>Transmit Status Register. This register, when read, provides details of the status of a transmit. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the
register.</desc>
  </register>
  <register offset="0xe000c018" type="rw" uniqueid="ps7_gem1_rx_qbar">
    <name>rx_qbar</name>
    <desc>Receive Buffer Queue Base Address.
This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the 'used' bits.
In terms of AMBA AHB operation, the descriptors are read from memory using a single 32bit AHB access. When the datapath is configured at 64bit, the descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is written to using a single AHB access.
For 32bit datapaths, the descriptors should be aligned at 32-bit boundaries and the descriptors are written to using two individual non sequential accesses.</desc>
  </register>
  <register offset="0xe000c01c" type="rw" uniqueid="ps7_gem1_tx_qbar">
    <name>tx_qbar</name>
    <desc>Transmit Buffer Queue Base Address.
This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored.
Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results.
Reading this register returns the location of the descriptor currently being accessed. Since the DMA handles two frames at once, this may not necessarily be pointing to the current frame being transmitted.
In terms of AMBA AHB operation, the descriptors are written to memory using a single 32bit AHB access. When the datapath is configured at 64bit, the descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AHB access. For 32bit datapaths, the descriptors should be aligned at 32-bit boundaries and the descriptors are read from memory using two individual non sequential accesses.</desc>
  </register>
  <register offset="0xe000c020" type="rw" uniqueid="ps7_gem1_rx_status">
    <name>rx_status</name>
    <desc>When read provides details of the status of a receive. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.</desc>
  </register>
  <register offset="0xe000c024" type="ro" uniqueid="ps7_gem1_intr_status">
    <name>intr_status</name>
    <desc>If not configured for priority queueing, the GEM generates a single interrupt; Pele does not support priority queueing. This register indicates the source of this interrupt. The corresponding bit in the mask register must be clear for a bit to be set. If any bit is set in this register the ethernet_int signal will be asserted.
For test purposes each bit can be set or reset by writing to the interrupt mask register.
The `gem_irq_read_clear define determines if a one must be written to the appropriate bit in order to clear it; in this mode reading has no affect on the status of the bit.
Pele leaves gem_irq_read_clear undefined, so that this register is write-one-to-clear instead of clear on read.</desc>
  </register>
  <register offset="0xe000c028" type="wo" uniqueid="ps7_gem1_intr_en">
    <name>intr_en</name>
    <desc>Interrupt Enable Register. At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero.</desc>
  </register>
  <register offset="0xe000c02c" type="wo" uniqueid="ps7_gem1_intr_dis">
    <name>intr_dis</name>
    <desc>Interrupt Disable Register.
Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero</desc>
  </register>
  <register offset="0xe000c030" type="rw" uniqueid="ps7_gem1_intr_mask">
    <name>intr_mask</name>
    <desc>Interrupt Mask Register.
The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register.
For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register.</desc>
  </register>
  <register offset="0xe000c034" type="rw" uniqueid="ps7_gem1_phy_maint">
    <name>phy_maint</name>
    <desc>PHY Maintenance Register
The PHY maintenance register is implemented as a shift register. Writing to the register starts a shift operation which is signalled as complete when bit-2 is set in the network status register. It takes about 2000 pclk cycles to complete, when MDC is set for pclk divide by 32 in the network configuration register. An interrupt is generated upon completion.
During this time, the MSB of the register is output on the MDIO pin and the LSB updated from the MDIO pin with each MDC cycle. This causes transmission of a PHY management frame on MDIO. See Section 22.2.4.5 of the IEEE 802.3 standard.
Reading during the shift operation will return the current contents of the shift register. At the end of management operation, the bits will have shifted back to their original locations. For a read operation, the data bits will be updated with data read from the PHY. It is important to write the correct values to the register to ensure a valid PHY management frame is produced.
The MDIO interface can read IEEE 802.3 clause 45 PHYs as well as clause 22 PHYs. To read clause 45 PHYs, bit 30 should be written with a 0 rather than a 1.
For a description of MDC generation, see Network Configuration Register</desc>
  </register>
  <register offset="0xe000c038" type="ro" uniqueid="ps7_gem1_rx_pauseq">
    <name>rx_pauseq</name>
    <desc>Received Pause Quantum Register</desc>
  </register>
  <register offset="0xe000c03c" type="rw" uniqueid="ps7_gem1_tx_pauseq">
    <name>tx_pauseq</name>
    <desc>Transmit Pause Quantum Register</desc>
  </register>
  <register offset="0xe000c080" type="rw" uniqueid="ps7_gem1_hash_bot">
    <name>hash_bot</name>
    <desc>Hash Register Bottom [31:0]. The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames.</desc>
  </register>
  <register offset="0xe000c084" type="rw" uniqueid="ps7_gem1_hash_top">
    <name>hash_top</name>
    <desc>Hash Register Top [63:32]. The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames.</desc>
  </register>
  <register offset="0xe000c088" type="rw" uniqueid="ps7_gem1_spec_addr1_bot">
    <name>spec_addr1_bot</name>
    <desc>Specific Address 1 Bottom [31:0]</desc>
  </register>
  <register offset="0xe000c08c" type="rw" uniqueid="ps7_gem1_spec_addr1_top">
    <name>spec_addr1_top</name>
    <desc>Specific Address 1 Top [47:32]</desc>
  </register>
  <register offset="0xe000c090" type="rw" uniqueid="ps7_gem1_spec_addr2_bot">
    <name>spec_addr2_bot</name>
    <desc>Specific Address 2 Bottom [31:0]</desc>
  </register>
  <register offset="0xe000c094" type="rw" uniqueid="ps7_gem1_spec_addr2_top">
    <name>spec_addr2_top</name>
    <desc>Specific Address 2 Top [47:32]</desc>
  </register>
  <register offset="0xe000c098" type="rw" uniqueid="ps7_gem1_spec_addr3_bot">
    <name>spec_addr3_bot</name>
    <desc>Specific Address 3 Bottom [31:0]</desc>
  </register>
  <register offset="0xe000c09c" type="rw" uniqueid="ps7_gem1_spec_addr3_top">
    <name>spec_addr3_top</name>
    <desc>Specific Address 3 Top [47:32]</desc>
  </register>
  <register offset="0xe000c0a0" type="rw" uniqueid="ps7_gem1_spec_addr4_bot">
    <name>spec_addr4_bot</name>
    <desc>Specific Address 4 Bottom [31:0]</desc>
  </register>
  <register offset="0xe000c0a4" type="rw" uniqueid="ps7_gem1_spec_addr4_top">
    <name>spec_addr4_top</name>
    <desc>Specific Address 4 Top [47:32]</desc>
  </register>
  <register offset="0xe000c0a8" type="rw" uniqueid="ps7_gem1_type_id_match1">
    <name>type_id_match1</name>
    <desc>Type ID Match 1</desc>
  </register>
  <register offset="0xe000c0ac" type="rw" uniqueid="ps7_gem1_type_id_match2">
    <name>type_id_match2</name>
    <desc>Type ID Match 2</desc>
  </register>
  <register offset="0xe000c0b0" type="rw" uniqueid="ps7_gem1_type_id_match3">
    <name>type_id_match3</name>
    <desc>Type ID Match 3</desc>
  </register>
  <register offset="0xe000c0b4" type="rw" uniqueid="ps7_gem1_type_id_match4">
    <name>type_id_match4</name>
    <desc>Type ID Match 4</desc>
  </register>
  <register offset="0xe000c0b8" type="rw" uniqueid="ps7_gem1_wake_on_lan">
    <name>wake_on_lan</name>
    <desc>Wake on LAN Register</desc>
  </register>
  <register offset="0xe000c0bc" type="rw" uniqueid="ps7_gem1_ipg_stretch">
    <name>ipg_stretch</name>
    <desc>IPG stretch register</desc>
  </register>
  <register offset="0xe000c0c0" type="rw" uniqueid="ps7_gem1_stacked_vlan">
    <name>stacked_vlan</name>
    <desc>Stacked VLAN Register</desc>
  </register>
  <register offset="0xe000c0c4" type="rw" uniqueid="ps7_gem1_tx_pfc_pause">
    <name>tx_pfc_pause</name>
    <desc>Transmit PFC Pause Register</desc>
  </register>
  <register offset="0xe000c0c8" type="rw" uniqueid="ps7_gem1_spec_addr1_mask_bot">
    <name>spec_addr1_mask_bot</name>
    <desc>Specific Address Mask 1 Bottom [31:0]</desc>
  </register>
  <register offset="0xe000c0cc" type="rw" uniqueid="ps7_gem1_spec_addr1_mask_top">
    <name>spec_addr1_mask_top</name>
    <desc>Specific Address Mask 1 Top [47:32]</desc>
  </register>
  <register offset="0xe000c0fc" type="ro" uniqueid="ps7_gem1_module_id">
    <name>module_id</name>
    <desc>Module ID Register. This register indicates a Cadence module identification number and module revision. The value of this register is read only as defined by `gem_revision_reg_value. In Pele with GEM p23, it is 0x00020118.</desc>
  </register>
  <register offset="0xe000c100" type="ro" uniqueid="ps7_gem1_octets_tx_bot">
    <name>octets_tx_bot</name>
    <desc>Octets transmitted [31:0] (in frames without error). Bits 31:0 should be read prior to bits 47:32 to ensure reliable operation. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000c104" type="ro" uniqueid="ps7_gem1_octets_tx_top">
    <name>octets_tx_top</name>
    <desc>Octets transmitted [47:32] (in frames without error). Bits 31:0 should be read prior to bits 47:32 to ensure reliable operation. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000c108" type="ro" uniqueid="ps7_gem1_frames_tx">
    <name>frames_tx</name>
    <desc>Frames transmitted without error, excluding pause
frames. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000c10c" type="ro" uniqueid="ps7_gem1_broadcast_frames_tx">
    <name>broadcast_frames_tx</name>
    <desc>Broadcast frames transmitted without error,
excluding pause frames. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000c110" type="ro" uniqueid="ps7_gem1_multi_frames_tx">
    <name>multi_frames_tx</name>
    <desc>Multicast frames transmitted without error,
excluding pause frames. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000c114" type="ro" uniqueid="ps7_gem1_pause_frames_tx">
    <name>pause_frames_tx</name>
    <desc>Transmitted pause frames (unless sent through
external FIFO interface). In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000c118" type="ro" uniqueid="ps7_gem1_frames_64b_tx">
    <name>frames_64b_tx</name>
    <desc>64 byte frames transmitted without error, excluding
pause frames. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000c11c" type="ro" uniqueid="ps7_gem1_frames_65to127b_tx">
    <name>frames_65to127b_tx</name>
    <desc>65 to 127 byte frames transmitted without error. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000c120" type="ro" uniqueid="ps7_gem1_frames_128to255b_tx">
    <name>frames_128to255b_tx</name>
    <desc>128 to 255 byte frames transmitted without error. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000c124" type="ro" uniqueid="ps7_gem1_frames_256to511b_tx">
    <name>frames_256to511b_tx</name>
    <desc>256 to 511 byte frames transmitted without error. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000c128" type="ro" uniqueid="ps7_gem1_frames_512to1023b_tx">
    <name>frames_512to1023b_tx</name>
    <desc>512 to 1023 byte frames transmitted without error. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000c12c" type="ro" uniqueid="ps7_gem1_frames_1024to1518b_tx">
    <name>frames_1024to1518b_tx</name>
    <desc>1024 to 1518 byte frames transmitted without error. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000c134" type="ro" uniqueid="ps7_gem1_tx_under_runs">
    <name>tx_under_runs</name>
    <desc>Transmit under runs. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000c138" type="ro" uniqueid="ps7_gem1_single_collisn_frames">
    <name>single_collisn_frames</name>
    <desc>Single Collision Frames. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000c13c" type="ro" uniqueid="ps7_gem1_multi_collisn_frames">
    <name>multi_collisn_frames</name>
    <desc>Multiple Collision Frames. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000c140" type="ro" uniqueid="ps7_gem1_excessive_collisns">
    <name>excessive_collisns</name>
    <desc>Excessive Collisions. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000c144" type="ro" uniqueid="ps7_gem1_late_collisns">
    <name>late_collisns</name>
    <desc>Late Collisions. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000c148" type="ro" uniqueid="ps7_gem1_deferred_tx_frames">
    <name>deferred_tx_frames</name>
    <desc>Deferred Transmission Frames. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000c14c" type="ro" uniqueid="ps7_gem1_carrier_sense_errs">
    <name>carrier_sense_errs</name>
    <desc>Carrier Sense Errors. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000c150" type="ro" uniqueid="ps7_gem1_octets_rx_bot">
    <name>octets_rx_bot</name>
    <desc>Octets Received [31:0]. Bits 31:0 should be read prior to bits 47:32 to ensure reliable operation. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000c154" type="ro" uniqueid="ps7_gem1_octets_rx_top">
    <name>octets_rx_top</name>
    <desc>Octets Received [47:32]. Bits 31:0 should be read prior to bits 47:32 to ensure reliable operation. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000c158" type="ro" uniqueid="ps7_gem1_frames_rx">
    <name>frames_rx</name>
    <desc>Frames received without error, excluding pause frames. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000c15c" type="ro" uniqueid="ps7_gem1_bdcast_fames_rx">
    <name>bdcast_fames_rx</name>
    <desc>Broadcast frames received without error, excluding pause frames. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000c160" type="ro" uniqueid="ps7_gem1_multi_frames_rx">
    <name>multi_frames_rx</name>
    <desc>Multicast frames received without error, excluding pause frames. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000c164" type="ro" uniqueid="ps7_gem1_pause_rx">
    <name>pause_rx</name>
    <desc>Pause frames received. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000c168" type="ro" uniqueid="ps7_gem1_frames_64b_rx">
    <name>frames_64b_rx</name>
    <desc>64 byte frames received without error, excluding
pause frames. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000c16c" type="ro" uniqueid="ps7_gem1_frames_65to127b_rx">
    <name>frames_65to127b_rx</name>
    <desc>65 to 127 byte frames received without error. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000c170" type="ro" uniqueid="ps7_gem1_frames_128to255b_rx">
    <name>frames_128to255b_rx</name>
    <desc>128 to 255 byte frames received without error. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000c174" type="ro" uniqueid="ps7_gem1_frames_256to511b_rx">
    <name>frames_256to511b_rx</name>
    <desc>256 to 511 byte frames received without error. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000c178" type="ro" uniqueid="ps7_gem1_frames_512to1023b_rx">
    <name>frames_512to1023b_rx</name>
    <desc>512 to 1023 byte frames received without error. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000c17c" type="ro" uniqueid="ps7_gem1_frames_1024to1518b_rx">
    <name>frames_1024to1518b_rx</name>
    <desc>1024 to 1518 byte frames received without error. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000c184" type="ro" uniqueid="ps7_gem1_undersz_rx">
    <name>undersz_rx</name>
    <desc>Undersize frames received</desc>
  </register>
  <register offset="0xe000c190" type="ro" uniqueid="ps7_gem1_fcs_errors">
    <name>fcs_errors</name>
    <desc>Frame check sequence errors</desc>
  </register>
  <register offset="0xe000c194" type="ro" uniqueid="ps7_gem1_length_field_errors">
    <name>length_field_errors</name>
    <desc>Length field frame errors</desc>
  </register>
  <register offset="0xe000c198" type="ro" uniqueid="ps7_gem1_rx_symbol_errors">
    <name>rx_symbol_errors</name>
    <desc>Receive symbol errors</desc>
  </register>
  <register offset="0xe000c19c" type="ro" uniqueid="ps7_gem1_align_errors">
    <name>align_errors</name>
    <desc>Alignment errors</desc>
  </register>
  <register offset="0xe000c1a0" type="ro" uniqueid="ps7_gem1_rx_resource_errors">
    <name>rx_resource_errors</name>
    <desc>Receive resource errors</desc>
  </register>
  <register offset="0xe000c1a4" type="ro" uniqueid="ps7_gem1_rx_overrun_errors">
    <name>rx_overrun_errors</name>
    <desc>Receive overrun errors</desc>
  </register>
  <register offset="0xe000c1a8" type="ro" uniqueid="ps7_gem1_ip_hdr_csum_errors">
    <name>ip_hdr_csum_errors</name>
    <desc>IP header checksum errors</desc>
  </register>
  <register offset="0xe000c1ac" type="ro" uniqueid="ps7_gem1_tcp_csum_errors">
    <name>tcp_csum_errors</name>
    <desc>TCP checksum errors</desc>
  </register>
  <register offset="0xe000c1b0" type="ro" uniqueid="ps7_gem1_udp_csum_errors">
    <name>udp_csum_errors</name>
    <desc>UDP checksum error</desc>
  </register>
  <register offset="0xe000c1c8" type="rw" uniqueid="ps7_gem1_timer_strobe_s">
    <name>timer_strobe_s</name>
    <desc>1588 timer sync strobe seconds</desc>
  </register>
  <register offset="0xe000c1cc" type="rw" uniqueid="ps7_gem1_timer_strobe_ns">
    <name>timer_strobe_ns</name>
    <desc>1588 timer sync strobe nanoseconds</desc>
  </register>
  <register offset="0xe000c1d0" type="rw" uniqueid="ps7_gem1_timer_s">
    <name>timer_s</name>
    <desc>1588 timer seconds</desc>
  </register>
  <register offset="0xe000c1d4" type="rw" uniqueid="ps7_gem1_timer_ns">
    <name>timer_ns</name>
    <desc>1588 timer nanoseconds</desc>
  </register>
  <register offset="0xe000c1d8" type="rw" uniqueid="ps7_gem1_timer_adjust">
    <name>timer_adjust</name>
    <desc>1588 timer adjust</desc>
  </register>
  <register offset="0xe000c1dc" type="rw" uniqueid="ps7_gem1_timer_incr">
    <name>timer_incr</name>
    <desc>1588 timer increment</desc>
  </register>
  <register offset="0xe000c1e0" type="ro" uniqueid="ps7_gem1_ptp_tx_s">
    <name>ptp_tx_s</name>
    <desc>PTP event frame transmitted seconds</desc>
  </register>
  <register offset="0xe000c1e4" type="ro" uniqueid="ps7_gem1_ptp_tx_ns">
    <name>ptp_tx_ns</name>
    <desc>PTP event frame transmitted nanoseconds</desc>
  </register>
  <register offset="0xe000c1e8" type="ro" uniqueid="ps7_gem1_ptp_rx_s">
    <name>ptp_rx_s</name>
    <desc>PTP event frame received seconds</desc>
  </register>
  <register offset="0xe000c1ec" type="ro" uniqueid="ps7_gem1_ptp_rx_ns">
    <name>ptp_rx_ns</name>
    <desc>PTP event frame received nanoseconds</desc>
  </register>
  <register offset="0xe000c1f0" type="ro" uniqueid="ps7_gem1_ptp_peer_tx_s">
    <name>ptp_peer_tx_s</name>
    <desc>PTP peer event frame transmitted seconds</desc>
  </register>
  <register offset="0xe000c1f4" type="ro" uniqueid="ps7_gem1_ptp_peer_tx_ns">
    <name>ptp_peer_tx_ns</name>
    <desc>PTP peer event frame transmitted nanoseconds</desc>
  </register>
  <register offset="0xe000c1f8" type="ro" uniqueid="ps7_gem1_ptp_peer_rx_s">
    <name>ptp_peer_rx_s</name>
    <desc>PTP peer event frame received seconds</desc>
  </register>
  <register offset="0xe000c1fc" type="ro" uniqueid="ps7_gem1_ptp_peer_rx_ns">
    <name>ptp_peer_rx_ns</name>
    <desc>PTP peer event frame received nanoseconds</desc>
  </register>
  <register offset="0xe000c280" type="ro" uniqueid="ps7_gem1_design_cfg1">
    <name>design_cfg1</name>
    <desc>Design Configuration Register 1</desc>
  </register>
  <register offset="0xe000c284" type="ro" uniqueid="ps7_gem1_design_cfg2">
    <name>design_cfg2</name>
    <desc>Design Configuration Register 2</desc>
  </register>
  <register offset="0xe000c288" type="ro" uniqueid="ps7_gem1_design_cfg3">
    <name>design_cfg3</name>
    <desc>Design Configuration Register 3</desc>
  </register>
  <register offset="0xe000c28c" type="ro" uniqueid="ps7_gem1_design_cfg4">
    <name>design_cfg4</name>
    <desc>Design Configuration Register 4</desc>
  </register>
  <register offset="0xe000c290" type="ro" uniqueid="ps7_gem1_design_cfg5">
    <name>design_cfg5</name>
    <desc>Design Configuration Register 5</desc>
  </register>
  <register offset="0xe000c294" type="ro" uniqueid="ps7_gem1_design_cfg6">
    <name>design_cfg6</name>
    <desc>Design Configuration Register 6</desc>
  </register>
  <register offset="0xe000c298" type="ro" uniqueid="ps7_gem1_design_cfg7">
    <name>design_cfg7</name>
    <desc>Design Configuration Register 7</desc>
  </register>
  <register offset="0xe000b000" type="rw" uniqueid="ps7_gem0_net_ctrl">
    <name>net_ctrl</name>
    <desc>The network control register contains general MAC control functions for both receiver and transmitter.</desc>
  </register>
  <register offset="0xe000b004" type="rw" uniqueid="ps7_gem0_net_cfg">
    <name>net_cfg</name>
    <desc>The network configuration register contains functions for setting the mode of operation for the Gigabit Ethernet MAC</desc>
  </register>
  <register offset="0xe000b008" type="ro" uniqueid="ps7_gem0_net_status">
    <name>net_status</name>
    <desc>The network status register returns status information with respect to the PHY management
interface.</desc>
  </register>
  <register offset="0xe000b00c" type="rw" uniqueid="ps7_gem0_user_io">
    <name>user_io</name>
    <desc>User Input/Output.
The GEM design provides up to 16 inputs and 16 outputs so that the I/O may be read or set under the control of the processor interface.
If the user I/O is disabled as a configuration option, this address space is defined as reserved, and hence will be a read-only register of the value 0x0.
If enabled, the number of inputs and outputs can be configured separately. The first output will be represented in bit 0 of the user I/O register, the second output will use bit 1 and so on.
The first input will be represented in bit 16 of the user I/O register, the second input will use bit 17 and so on.</desc>
  </register>
  <register offset="0xe000b010" type="rw" uniqueid="ps7_gem0_dma_cfg">
    <name>dma_cfg</name>
    <desc>DMA Configuration Register</desc>
  </register>
  <register offset="0xe000b014" type="rw" uniqueid="ps7_gem0_tx_status">
    <name>tx_status</name>
    <desc>Transmit Status Register. This register, when read, provides details of the status of a transmit. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the
register.</desc>
  </register>
  <register offset="0xe000b018" type="rw" uniqueid="ps7_gem0_rx_qbar">
    <name>rx_qbar</name>
    <desc>Receive Buffer Queue Base Address.
This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the 'used' bits.
In terms of AMBA AHB operation, the descriptors are read from memory using a single 32bit AHB access. When the datapath is configured at 64bit, the descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is written to using a single AHB access.
For 32bit datapaths, the descriptors should be aligned at 32-bit boundaries and the descriptors are written to using two individual non sequential accesses.</desc>
  </register>
  <register offset="0xe000b01c" type="rw" uniqueid="ps7_gem0_tx_qbar">
    <name>tx_qbar</name>
    <desc>Transmit Buffer Queue Base Address.
This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored.
Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results.
Reading this register returns the location of the descriptor currently being accessed. Since the DMA handles two frames at once, this may not necessarily be pointing to the current frame being transmitted.
In terms of AMBA AHB operation, the descriptors are written to memory using a single 32bit AHB access. When the datapath is configured at 64bit, the descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AHB access. For 32bit datapaths, the descriptors should be aligned at 32-bit boundaries and the descriptors are read from memory using two individual non sequential accesses.</desc>
  </register>
  <register offset="0xe000b020" type="rw" uniqueid="ps7_gem0_rx_status">
    <name>rx_status</name>
    <desc>When read provides details of the status of a receive. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.</desc>
  </register>
  <register offset="0xe000b024" type="ro" uniqueid="ps7_gem0_intr_status">
    <name>intr_status</name>
    <desc>If not configured for priority queueing, the GEM generates a single interrupt; Pele does not support priority queueing. This register indicates the source of this interrupt. The corresponding bit in the mask register must be clear for a bit to be set. If any bit is set in this register the ethernet_int signal will be asserted.
For test purposes each bit can be set or reset by writing to the interrupt mask register.
The `gem_irq_read_clear define determines if a one must be written to the appropriate bit in order to clear it; in this mode reading has no affect on the status of the bit.
Pele leaves gem_irq_read_clear undefined, so that this register is write-one-to-clear instead of clear on read.</desc>
  </register>
  <register offset="0xe000b028" type="wo" uniqueid="ps7_gem0_intr_en">
    <name>intr_en</name>
    <desc>Interrupt Enable Register. At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero.</desc>
  </register>
  <register offset="0xe000b02c" type="wo" uniqueid="ps7_gem0_intr_dis">
    <name>intr_dis</name>
    <desc>Interrupt Disable Register.
Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero</desc>
  </register>
  <register offset="0xe000b030" type="rw" uniqueid="ps7_gem0_intr_mask">
    <name>intr_mask</name>
    <desc>Interrupt Mask Register.
The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register.
For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register.</desc>
  </register>
  <register offset="0xe000b034" type="rw" uniqueid="ps7_gem0_phy_maint">
    <name>phy_maint</name>
    <desc>PHY Maintenance Register
The PHY maintenance register is implemented as a shift register. Writing to the register starts a shift operation which is signalled as complete when bit-2 is set in the network status register. It takes about 2000 pclk cycles to complete, when MDC is set for pclk divide by 32 in the network configuration register. An interrupt is generated upon completion.
During this time, the MSB of the register is output on the MDIO pin and the LSB updated from the MDIO pin with each MDC cycle. This causes transmission of a PHY management frame on MDIO. See Section 22.2.4.5 of the IEEE 802.3 standard.
Reading during the shift operation will return the current contents of the shift register. At the end of management operation, the bits will have shifted back to their original locations. For a read operation, the data bits will be updated with data read from the PHY. It is important to write the correct values to the register to ensure a valid PHY management frame is produced.
The MDIO interface can read IEEE 802.3 clause 45 PHYs as well as clause 22 PHYs. To read clause 45 PHYs, bit 30 should be written with a 0 rather than a 1.
For a description of MDC generation, see Network Configuration Register</desc>
  </register>
  <register offset="0xe000b038" type="ro" uniqueid="ps7_gem0_rx_pauseq">
    <name>rx_pauseq</name>
    <desc>Received Pause Quantum Register</desc>
  </register>
  <register offset="0xe000b03c" type="rw" uniqueid="ps7_gem0_tx_pauseq">
    <name>tx_pauseq</name>
    <desc>Transmit Pause Quantum Register</desc>
  </register>
  <register offset="0xe000b080" type="rw" uniqueid="ps7_gem0_hash_bot">
    <name>hash_bot</name>
    <desc>Hash Register Bottom [31:0]. The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames.</desc>
  </register>
  <register offset="0xe000b084" type="rw" uniqueid="ps7_gem0_hash_top">
    <name>hash_top</name>
    <desc>Hash Register Top [63:32]. The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames.</desc>
  </register>
  <register offset="0xe000b088" type="rw" uniqueid="ps7_gem0_spec_addr1_bot">
    <name>spec_addr1_bot</name>
    <desc>Specific Address 1 Bottom [31:0]</desc>
  </register>
  <register offset="0xe000b08c" type="rw" uniqueid="ps7_gem0_spec_addr1_top">
    <name>spec_addr1_top</name>
    <desc>Specific Address 1 Top [47:32]</desc>
  </register>
  <register offset="0xe000b090" type="rw" uniqueid="ps7_gem0_spec_addr2_bot">
    <name>spec_addr2_bot</name>
    <desc>Specific Address 2 Bottom [31:0]</desc>
  </register>
  <register offset="0xe000b094" type="rw" uniqueid="ps7_gem0_spec_addr2_top">
    <name>spec_addr2_top</name>
    <desc>Specific Address 2 Top [47:32]</desc>
  </register>
  <register offset="0xe000b098" type="rw" uniqueid="ps7_gem0_spec_addr3_bot">
    <name>spec_addr3_bot</name>
    <desc>Specific Address 3 Bottom [31:0]</desc>
  </register>
  <register offset="0xe000b09c" type="rw" uniqueid="ps7_gem0_spec_addr3_top">
    <name>spec_addr3_top</name>
    <desc>Specific Address 3 Top [47:32]</desc>
  </register>
  <register offset="0xe000b0a0" type="rw" uniqueid="ps7_gem0_spec_addr4_bot">
    <name>spec_addr4_bot</name>
    <desc>Specific Address 4 Bottom [31:0]</desc>
  </register>
  <register offset="0xe000b0a4" type="rw" uniqueid="ps7_gem0_spec_addr4_top">
    <name>spec_addr4_top</name>
    <desc>Specific Address 4 Top [47:32]</desc>
  </register>
  <register offset="0xe000b0a8" type="rw" uniqueid="ps7_gem0_type_id_match1">
    <name>type_id_match1</name>
    <desc>Type ID Match 1</desc>
  </register>
  <register offset="0xe000b0ac" type="rw" uniqueid="ps7_gem0_type_id_match2">
    <name>type_id_match2</name>
    <desc>Type ID Match 2</desc>
  </register>
  <register offset="0xe000b0b0" type="rw" uniqueid="ps7_gem0_type_id_match3">
    <name>type_id_match3</name>
    <desc>Type ID Match 3</desc>
  </register>
  <register offset="0xe000b0b4" type="rw" uniqueid="ps7_gem0_type_id_match4">
    <name>type_id_match4</name>
    <desc>Type ID Match 4</desc>
  </register>
  <register offset="0xe000b0b8" type="rw" uniqueid="ps7_gem0_wake_on_lan">
    <name>wake_on_lan</name>
    <desc>Wake on LAN Register</desc>
  </register>
  <register offset="0xe000b0bc" type="rw" uniqueid="ps7_gem0_ipg_stretch">
    <name>ipg_stretch</name>
    <desc>IPG stretch register</desc>
  </register>
  <register offset="0xe000b0c0" type="rw" uniqueid="ps7_gem0_stacked_vlan">
    <name>stacked_vlan</name>
    <desc>Stacked VLAN Register</desc>
  </register>
  <register offset="0xe000b0c4" type="rw" uniqueid="ps7_gem0_tx_pfc_pause">
    <name>tx_pfc_pause</name>
    <desc>Transmit PFC Pause Register</desc>
  </register>
  <register offset="0xe000b0c8" type="rw" uniqueid="ps7_gem0_spec_addr1_mask_bot">
    <name>spec_addr1_mask_bot</name>
    <desc>Specific Address Mask 1 Bottom [31:0]</desc>
  </register>
  <register offset="0xe000b0cc" type="rw" uniqueid="ps7_gem0_spec_addr1_mask_top">
    <name>spec_addr1_mask_top</name>
    <desc>Specific Address Mask 1 Top [47:32]</desc>
  </register>
  <register offset="0xe000b0fc" type="ro" uniqueid="ps7_gem0_module_id">
    <name>module_id</name>
    <desc>Module ID Register. This register indicates a Cadence module identification number and module revision. The value of this register is read only as defined by `gem_revision_reg_value. In Pele with GEM p23, it is 0x00020118.</desc>
  </register>
  <register offset="0xe000b100" type="ro" uniqueid="ps7_gem0_octets_tx_bot">
    <name>octets_tx_bot</name>
    <desc>Octets transmitted [31:0] (in frames without error). Bits 31:0 should be read prior to bits 47:32 to ensure reliable operation. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000b104" type="ro" uniqueid="ps7_gem0_octets_tx_top">
    <name>octets_tx_top</name>
    <desc>Octets transmitted [47:32] (in frames without error). Bits 31:0 should be read prior to bits 47:32 to ensure reliable operation. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000b108" type="ro" uniqueid="ps7_gem0_frames_tx">
    <name>frames_tx</name>
    <desc>Frames transmitted without error, excluding pause
frames. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000b10c" type="ro" uniqueid="ps7_gem0_broadcast_frames_tx">
    <name>broadcast_frames_tx</name>
    <desc>Broadcast frames transmitted without error,
excluding pause frames. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000b110" type="ro" uniqueid="ps7_gem0_multi_frames_tx">
    <name>multi_frames_tx</name>
    <desc>Multicast frames transmitted without error,
excluding pause frames. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000b114" type="ro" uniqueid="ps7_gem0_pause_frames_tx">
    <name>pause_frames_tx</name>
    <desc>Transmitted pause frames (unless sent through
external FIFO interface). In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000b118" type="ro" uniqueid="ps7_gem0_frames_64b_tx">
    <name>frames_64b_tx</name>
    <desc>64 byte frames transmitted without error, excluding
pause frames. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000b11c" type="ro" uniqueid="ps7_gem0_frames_65to127b_tx">
    <name>frames_65to127b_tx</name>
    <desc>65 to 127 byte frames transmitted without error. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000b120" type="ro" uniqueid="ps7_gem0_frames_128to255b_tx">
    <name>frames_128to255b_tx</name>
    <desc>128 to 255 byte frames transmitted without error. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000b124" type="ro" uniqueid="ps7_gem0_frames_256to511b_tx">
    <name>frames_256to511b_tx</name>
    <desc>256 to 511 byte frames transmitted without error. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000b128" type="ro" uniqueid="ps7_gem0_frames_512to1023b_tx">
    <name>frames_512to1023b_tx</name>
    <desc>512 to 1023 byte frames transmitted without error. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000b12c" type="ro" uniqueid="ps7_gem0_frames_1024to1518b_tx">
    <name>frames_1024to1518b_tx</name>
    <desc>1024 to 1518 byte frames transmitted without error. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000b134" type="ro" uniqueid="ps7_gem0_tx_under_runs">
    <name>tx_under_runs</name>
    <desc>Transmit under runs. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000b138" type="ro" uniqueid="ps7_gem0_single_collisn_frames">
    <name>single_collisn_frames</name>
    <desc>Single Collision Frames. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000b13c" type="ro" uniqueid="ps7_gem0_multi_collisn_frames">
    <name>multi_collisn_frames</name>
    <desc>Multiple Collision Frames. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000b140" type="ro" uniqueid="ps7_gem0_excessive_collisns">
    <name>excessive_collisns</name>
    <desc>Excessive Collisions. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000b144" type="ro" uniqueid="ps7_gem0_late_collisns">
    <name>late_collisns</name>
    <desc>Late Collisions. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000b148" type="ro" uniqueid="ps7_gem0_deferred_tx_frames">
    <name>deferred_tx_frames</name>
    <desc>Deferred Transmission Frames. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000b14c" type="ro" uniqueid="ps7_gem0_carrier_sense_errs">
    <name>carrier_sense_errs</name>
    <desc>Carrier Sense Errors. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000b150" type="ro" uniqueid="ps7_gem0_octets_rx_bot">
    <name>octets_rx_bot</name>
    <desc>Octets Received [31:0]. Bits 31:0 should be read prior to bits 47:32 to ensure reliable operation. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000b154" type="ro" uniqueid="ps7_gem0_octets_rx_top">
    <name>octets_rx_top</name>
    <desc>Octets Received [47:32]. Bits 31:0 should be read prior to bits 47:32 to ensure reliable operation. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000b158" type="ro" uniqueid="ps7_gem0_frames_rx">
    <name>frames_rx</name>
    <desc>Frames received without error, excluding pause frames. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000b15c" type="ro" uniqueid="ps7_gem0_bdcast_fames_rx">
    <name>bdcast_fames_rx</name>
    <desc>Broadcast frames received without error, excluding pause frames. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000b160" type="ro" uniqueid="ps7_gem0_multi_frames_rx">
    <name>multi_frames_rx</name>
    <desc>Multicast frames received without error, excluding pause frames. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000b164" type="ro" uniqueid="ps7_gem0_pause_rx">
    <name>pause_rx</name>
    <desc>Pause frames received. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000b168" type="ro" uniqueid="ps7_gem0_frames_64b_rx">
    <name>frames_64b_rx</name>
    <desc>64 byte frames received without error, excluding
pause frames. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000b16c" type="ro" uniqueid="ps7_gem0_frames_65to127b_rx">
    <name>frames_65to127b_rx</name>
    <desc>65 to 127 byte frames received without error. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000b170" type="ro" uniqueid="ps7_gem0_frames_128to255b_rx">
    <name>frames_128to255b_rx</name>
    <desc>128 to 255 byte frames received without error. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000b174" type="ro" uniqueid="ps7_gem0_frames_256to511b_rx">
    <name>frames_256to511b_rx</name>
    <desc>256 to 511 byte frames received without error. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000b178" type="ro" uniqueid="ps7_gem0_frames_512to1023b_rx">
    <name>frames_512to1023b_rx</name>
    <desc>512 to 1023 byte frames received without error. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000b17c" type="ro" uniqueid="ps7_gem0_frames_1024to1518b_rx">
    <name>frames_1024to1518b_rx</name>
    <desc>1024 to 1518 byte frames received without error. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
For test purposes it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.
Once a statistics register has been read, it is automatically cleared.</desc>
  </register>
  <register offset="0xe000b184" type="ro" uniqueid="ps7_gem0_undersz_rx">
    <name>undersz_rx</name>
    <desc>Undersize frames received</desc>
  </register>
  <register offset="0xe000b190" type="ro" uniqueid="ps7_gem0_fcs_errors">
    <name>fcs_errors</name>
    <desc>Frame check sequence errors</desc>
  </register>
  <register offset="0xe000b194" type="ro" uniqueid="ps7_gem0_length_field_errors">
    <name>length_field_errors</name>
    <desc>Length field frame errors</desc>
  </register>
  <register offset="0xe000b198" type="ro" uniqueid="ps7_gem0_rx_symbol_errors">
    <name>rx_symbol_errors</name>
    <desc>Receive symbol errors</desc>
  </register>
  <register offset="0xe000b19c" type="ro" uniqueid="ps7_gem0_align_errors">
    <name>align_errors</name>
    <desc>Alignment errors</desc>
  </register>
  <register offset="0xe000b1a0" type="ro" uniqueid="ps7_gem0_rx_resource_errors">
    <name>rx_resource_errors</name>
    <desc>Receive resource errors</desc>
  </register>
  <register offset="0xe000b1a4" type="ro" uniqueid="ps7_gem0_rx_overrun_errors">
    <name>rx_overrun_errors</name>
    <desc>Receive overrun errors</desc>
  </register>
  <register offset="0xe000b1a8" type="ro" uniqueid="ps7_gem0_ip_hdr_csum_errors">
    <name>ip_hdr_csum_errors</name>
    <desc>IP header checksum errors</desc>
  </register>
  <register offset="0xe000b1ac" type="ro" uniqueid="ps7_gem0_tcp_csum_errors">
    <name>tcp_csum_errors</name>
    <desc>TCP checksum errors</desc>
  </register>
  <register offset="0xe000b1b0" type="ro" uniqueid="ps7_gem0_udp_csum_errors">
    <name>udp_csum_errors</name>
    <desc>UDP checksum error</desc>
  </register>
  <register offset="0xe000b1c8" type="rw" uniqueid="ps7_gem0_timer_strobe_s">
    <name>timer_strobe_s</name>
    <desc>1588 timer sync strobe seconds</desc>
  </register>
  <register offset="0xe000b1cc" type="rw" uniqueid="ps7_gem0_timer_strobe_ns">
    <name>timer_strobe_ns</name>
    <desc>1588 timer sync strobe nanoseconds</desc>
  </register>
  <register offset="0xe000b1d0" type="rw" uniqueid="ps7_gem0_timer_s">
    <name>timer_s</name>
    <desc>1588 timer seconds</desc>
  </register>
  <register offset="0xe000b1d4" type="rw" uniqueid="ps7_gem0_timer_ns">
    <name>timer_ns</name>
    <desc>1588 timer nanoseconds</desc>
  </register>
  <register offset="0xe000b1d8" type="rw" uniqueid="ps7_gem0_timer_adjust">
    <name>timer_adjust</name>
    <desc>1588 timer adjust</desc>
  </register>
  <register offset="0xe000b1dc" type="rw" uniqueid="ps7_gem0_timer_incr">
    <name>timer_incr</name>
    <desc>1588 timer increment</desc>
  </register>
  <register offset="0xe000b1e0" type="ro" uniqueid="ps7_gem0_ptp_tx_s">
    <name>ptp_tx_s</name>
    <desc>PTP event frame transmitted seconds</desc>
  </register>
  <register offset="0xe000b1e4" type="ro" uniqueid="ps7_gem0_ptp_tx_ns">
    <name>ptp_tx_ns</name>
    <desc>PTP event frame transmitted nanoseconds</desc>
  </register>
  <register offset="0xe000b1e8" type="ro" uniqueid="ps7_gem0_ptp_rx_s">
    <name>ptp_rx_s</name>
    <desc>PTP event frame received seconds</desc>
  </register>
  <register offset="0xe000b1ec" type="ro" uniqueid="ps7_gem0_ptp_rx_ns">
    <name>ptp_rx_ns</name>
    <desc>PTP event frame received nanoseconds</desc>
  </register>
  <register offset="0xe000b1f0" type="ro" uniqueid="ps7_gem0_ptp_peer_tx_s">
    <name>ptp_peer_tx_s</name>
    <desc>PTP peer event frame transmitted seconds</desc>
  </register>
  <register offset="0xe000b1f4" type="ro" uniqueid="ps7_gem0_ptp_peer_tx_ns">
    <name>ptp_peer_tx_ns</name>
    <desc>PTP peer event frame transmitted nanoseconds</desc>
  </register>
  <register offset="0xe000b1f8" type="ro" uniqueid="ps7_gem0_ptp_peer_rx_s">
    <name>ptp_peer_rx_s</name>
    <desc>PTP peer event frame received seconds</desc>
  </register>
  <register offset="0xe000b1fc" type="ro" uniqueid="ps7_gem0_ptp_peer_rx_ns">
    <name>ptp_peer_rx_ns</name>
    <desc>PTP peer event frame received nanoseconds</desc>
  </register>
  <register offset="0xe000b280" type="ro" uniqueid="ps7_gem0_design_cfg1">
    <name>design_cfg1</name>
    <desc>Design Configuration Register 1</desc>
  </register>
  <register offset="0xe000b284" type="ro" uniqueid="ps7_gem0_design_cfg2">
    <name>design_cfg2</name>
    <desc>Design Configuration Register 2</desc>
  </register>
  <register offset="0xe000b288" type="ro" uniqueid="ps7_gem0_design_cfg3">
    <name>design_cfg3</name>
    <desc>Design Configuration Register 3</desc>
  </register>
  <register offset="0xe000b28c" type="ro" uniqueid="ps7_gem0_design_cfg4">
    <name>design_cfg4</name>
    <desc>Design Configuration Register 4</desc>
  </register>
  <register offset="0xe000b290" type="ro" uniqueid="ps7_gem0_design_cfg5">
    <name>design_cfg5</name>
    <desc>Design Configuration Register 5</desc>
  </register>
  <register offset="0xe000b294" type="ro" uniqueid="ps7_gem0_design_cfg6">
    <name>design_cfg6</name>
    <desc>Design Configuration Register 6</desc>
  </register>
  <register offset="0xe000b298" type="ro" uniqueid="ps7_gem0_design_cfg7">
    <name>design_cfg7</name>
    <desc>Design Configuration Register 7</desc>
  </register>
  <register offset="0xe000d000" type="rw" uniqueid="ps7_qspi_Config_reg">
    <name>Config_reg</name>
    <desc>SPI configuration register</desc>
  </register>
  <register offset="0xe000d004" type="ro" uniqueid="ps7_qspi_Intr_status_REG">
    <name>Intr_status_REG</name>
    <desc>SPI interrupt status register</desc>
  </register>
  <register offset="0xe000d008" type="rw" uniqueid="ps7_qspi_Intrpt_en_REG">
    <name>Intrpt_en_REG</name>
    <desc>Interrupt Enable register</desc>
  </register>
  <register offset="0xe000d00c" type="rw" uniqueid="ps7_qspi_Intrpt_dis_REG">
    <name>Intrpt_dis_REG</name>
    <desc>Interrupt disable register</desc>
  </register>
  <register offset="0xe000d010" type="ro" uniqueid="ps7_qspi_Intrpt_mask_REG">
    <name>Intrpt_mask_REG</name>
    <desc>Interrupt mask register</desc>
  </register>
  <register offset="0xe000d014" type="rw" uniqueid="ps7_qspi_En_REG">
    <name>En_REG</name>
    <desc>SPI_Enable Register</desc>
  </register>
  <register offset="0xe000d018" type="rw" uniqueid="ps7_qspi_Delay_REG">
    <name>Delay_REG</name>
    <desc>Delay Register</desc>
  </register>
  <register offset="0xe000d01c" type="wo" uniqueid="ps7_qspi_TXD0">
    <name>TXD0</name>
    <desc>Transmit Data Register. Keyhole addresses for the Transmit data FIFO. See also TXD1-3.</desc>
  </register>
  <register offset="0xe000d020" type="ro" uniqueid="ps7_qspi_Rx_data_REG">
    <name>Rx_data_REG</name>
    <desc>Receive Data Register</desc>
  </register>
  <register offset="0xe000d024" type="rw" uniqueid="ps7_qspi_Slave_Idle_count_REG">
    <name>Slave_Idle_count_REG</name>
    <desc>Slave Idle Count Register</desc>
  </register>
  <register offset="0xe000d028" type="rw" uniqueid="ps7_qspi_TX_thres_REG">
    <name>TX_thres_REG</name>
    <desc>TX_FIFO Threshold Register</desc>
  </register>
  <register offset="0xe000d02c" type="rw" uniqueid="ps7_qspi_RX_thres_REG">
    <name>RX_thres_REG</name>
    <desc>RX FIFO Threshold Register</desc>
  </register>
  <register offset="0xe000d030" type="rw" uniqueid="ps7_qspi_GPIO">
    <name>GPIO</name>
    <desc>General Purpose Inputs and Outputs Register for the Quad-SPI Controller core</desc>
  </register>
  <register offset="0xe000d038" type="rw" uniqueid="ps7_qspi_LPBK_DLY_ADJ">
    <name>LPBK_DLY_ADJ</name>
    <desc>Loopback Master Clock Delay Adjustment Register</desc>
  </register>
  <register offset="0xe000d080" type="wo" uniqueid="ps7_qspi_TXD1">
    <name>TXD1</name>
    <desc>Transmit Data Register. Keyhole addresses for the Transmit data FIFO.</desc>
  </register>
  <register offset="0xe000d084" type="wo" uniqueid="ps7_qspi_TXD2">
    <name>TXD2</name>
    <desc>Transmit Data Register. Keyhole addresses for the Transmit data FIFO.</desc>
  </register>
  <register offset="0xe000d088" type="wo" uniqueid="ps7_qspi_TXD3">
    <name>TXD3</name>
    <desc>Transmit Data Register. Keyhole addresses for the Transmit data FIFO.</desc>
  </register>
  <register offset="0xe000d0a0" type="rw" uniqueid="ps7_qspi_LQSPI_CFG">
    <name>LQSPI_CFG</name>
    <desc>Configuration Register specifically for the Linear Quad-SPI Controller</desc>
  </register>
  <register offset="0xe000d0a4" type="rw" uniqueid="ps7_qspi_LQSPI_STS">
    <name>LQSPI_STS</name>
    <desc>Status Register specifically for the Linear Quad-SPI Controller</desc>
  </register>
  <register offset="0xe000d0fc" type="rw" uniqueid="ps7_qspi_MOD_ID">
    <name>MOD_ID</name>
    <desc>Module Identification register</desc>
  </register>
  <register offset="0xe0009000" type="rw" uniqueid="ps7_can1_SRR">
    <name>SRR</name>
    <desc>Software Reset Register</desc>
  </register>
  <register offset="0xe0009004" type="rw" uniqueid="ps7_can1_MSR">
    <name>MSR</name>
    <desc>Mode Select Register</desc>
  </register>
  <register offset="0xe0009008" type="rw" uniqueid="ps7_can1_BRPR">
    <name>BRPR</name>
    <desc>Baud Rate Prescaler Register</desc>
  </register>
  <register offset="0xe000900c" type="rw" uniqueid="ps7_can1_BTR">
    <name>BTR</name>
    <desc>Bit Timing Register</desc>
  </register>
  <register offset="0xe0009010" type="ro" uniqueid="ps7_can1_ECR">
    <name>ECR</name>
    <desc>Error Counter Register</desc>
  </register>
  <register offset="0xe0009014" type="rw" uniqueid="ps7_can1_ESR">
    <name>ESR</name>
    <desc>Error Status Register</desc>
  </register>
  <register offset="0xe0009018" type="rw" uniqueid="ps7_can1_SR">
    <name>SR</name>
    <desc>Status Register</desc>
  </register>
  <register offset="0xe000901c" type="rw" uniqueid="ps7_can1_ISR">
    <name>ISR</name>
    <desc>Interrupt Status Register</desc>
  </register>
  <register offset="0xe0009020" type="rw" uniqueid="ps7_can1_IER">
    <name>IER</name>
    <desc>Interrupt Enable Register</desc>
  </register>
  <register offset="0xe0009024" type="rw" uniqueid="ps7_can1_ICR">
    <name>ICR</name>
    <desc>Interrupt Clear Register</desc>
  </register>
  <register offset="0xe0009028" type="rw" uniqueid="ps7_can1_TCR">
    <name>TCR</name>
    <desc>Timestamp Control Register</desc>
  </register>
  <register offset="0xe000902c" type="rw" uniqueid="ps7_can1_WIR">
    <name>WIR</name>
    <desc>Watermark Interrupt Register</desc>
  </register>
  <register offset="0xe0009030" type="wo" uniqueid="ps7_can1_TXFIFO_ID">
    <name>TXFIFO_ID</name>
    <desc>transmit message fifo message identifier</desc>
  </register>
  <register offset="0xe0009034" type="rw" uniqueid="ps7_can1_TXFIFO_DLC">
    <name>TXFIFO_DLC</name>
    <desc>transmit message fifo data length code</desc>
  </register>
  <register offset="0xe0009038" type="rw" uniqueid="ps7_can1_TXFIFO_DATA1">
    <name>TXFIFO_DATA1</name>
    <desc>transmit message fifo data word 1</desc>
  </register>
  <register offset="0xe000903c" type="rw" uniqueid="ps7_can1_TXFIFO_DATA2">
    <name>TXFIFO_DATA2</name>
    <desc>transmit message fifo data word 2</desc>
  </register>
  <register offset="0xe0009040" type="wo" uniqueid="ps7_can1_TXHPB_ID">
    <name>TXHPB_ID</name>
    <desc>transmit high priority buffer message identifier</desc>
  </register>
  <register offset="0xe0009044" type="rw" uniqueid="ps7_can1_TXHPB_DLC">
    <name>TXHPB_DLC</name>
    <desc>transmit high priority buffer data length code</desc>
  </register>
  <register offset="0xe0009048" type="rw" uniqueid="ps7_can1_TXHPB_DATA1">
    <name>TXHPB_DATA1</name>
    <desc>transmit high priority buffer data word 1</desc>
  </register>
  <register offset="0xe000904c" type="rw" uniqueid="ps7_can1_TXHPB_DATA2">
    <name>TXHPB_DATA2</name>
    <desc>transmit high priority buffer data word 2</desc>
  </register>
  <register offset="0xe0009050" type="ro" uniqueid="ps7_can1_RXFIFO_ID">
    <name>RXFIFO_ID</name>
    <desc>receive message fifo message identifier</desc>
  </register>
  <register offset="0xe0009054" type="rw" uniqueid="ps7_can1_RXFIFO_DLC">
    <name>RXFIFO_DLC</name>
    <desc>receive message fifo data length code</desc>
  </register>
  <register offset="0xe0009058" type="rw" uniqueid="ps7_can1_RXFIFO_DATA1">
    <name>RXFIFO_DATA1</name>
    <desc>receive message fifo data word 1</desc>
  </register>
  <register offset="0xe000905c" type="rw" uniqueid="ps7_can1_RXFIFO_DATA2">
    <name>RXFIFO_DATA2</name>
    <desc>receive message fifo data word 2</desc>
  </register>
  <register offset="0xe0009060" type="rw" uniqueid="ps7_can1_AFR">
    <name>AFR</name>
    <desc>Acceptance Filter Register</desc>
  </register>
  <register offset="0xe0009064" type="rw" uniqueid="ps7_can1_AFMR1">
    <name>AFMR1</name>
    <desc>Acceptance Filter Mask Register 1</desc>
  </register>
  <register offset="0xe0009068" type="rw" uniqueid="ps7_can1_AFIR1">
    <name>AFIR1</name>
    <desc>Acceptance Filter ID Register 1</desc>
  </register>
  <register offset="0xe000906c" type="rw" uniqueid="ps7_can1_AFMR2">
    <name>AFMR2</name>
    <desc>Acceptance Filter Mask Register 2</desc>
  </register>
  <register offset="0xe0009070" type="rw" uniqueid="ps7_can1_AFIR2">
    <name>AFIR2</name>
    <desc>Acceptance Filter ID Register 2</desc>
  </register>
  <register offset="0xe0009074" type="rw" uniqueid="ps7_can1_AFMR3">
    <name>AFMR3</name>
    <desc>Acceptance Filter Mask Register 3</desc>
  </register>
  <register offset="0xe0009078" type="rw" uniqueid="ps7_can1_AFIR3">
    <name>AFIR3</name>
    <desc>Acceptance Filter ID Register 3</desc>
  </register>
  <register offset="0xe000907c" type="rw" uniqueid="ps7_can1_AFMR4">
    <name>AFMR4</name>
    <desc>Acceptance Filter Mask Register 4</desc>
  </register>
  <register offset="0xe0009080" type="rw" uniqueid="ps7_can1_AFIR4">
    <name>AFIR4</name>
    <desc>Acceptance Filter ID Register 4</desc>
  </register>
  <register offset="0xe0008000" type="rw" uniqueid="ps7_can0_SRR">
    <name>SRR</name>
    <desc>Software Reset Register</desc>
  </register>
  <register offset="0xe0008004" type="rw" uniqueid="ps7_can0_MSR">
    <name>MSR</name>
    <desc>Mode Select Register</desc>
  </register>
  <register offset="0xe0008008" type="rw" uniqueid="ps7_can0_BRPR">
    <name>BRPR</name>
    <desc>Baud Rate Prescaler Register</desc>
  </register>
  <register offset="0xe000800c" type="rw" uniqueid="ps7_can0_BTR">
    <name>BTR</name>
    <desc>Bit Timing Register</desc>
  </register>
  <register offset="0xe0008010" type="ro" uniqueid="ps7_can0_ECR">
    <name>ECR</name>
    <desc>Error Counter Register</desc>
  </register>
  <register offset="0xe0008014" type="rw" uniqueid="ps7_can0_ESR">
    <name>ESR</name>
    <desc>Error Status Register</desc>
  </register>
  <register offset="0xe0008018" type="rw" uniqueid="ps7_can0_SR">
    <name>SR</name>
    <desc>Status Register</desc>
  </register>
  <register offset="0xe000801c" type="rw" uniqueid="ps7_can0_ISR">
    <name>ISR</name>
    <desc>Interrupt Status Register</desc>
  </register>
  <register offset="0xe0008020" type="rw" uniqueid="ps7_can0_IER">
    <name>IER</name>
    <desc>Interrupt Enable Register</desc>
  </register>
  <register offset="0xe0008024" type="rw" uniqueid="ps7_can0_ICR">
    <name>ICR</name>
    <desc>Interrupt Clear Register</desc>
  </register>
  <register offset="0xe0008028" type="rw" uniqueid="ps7_can0_TCR">
    <name>TCR</name>
    <desc>Timestamp Control Register</desc>
  </register>
  <register offset="0xe000802c" type="rw" uniqueid="ps7_can0_WIR">
    <name>WIR</name>
    <desc>Watermark Interrupt Register</desc>
  </register>
  <register offset="0xe0008030" type="wo" uniqueid="ps7_can0_TXFIFO_ID">
    <name>TXFIFO_ID</name>
    <desc>transmit message fifo message identifier</desc>
  </register>
  <register offset="0xe0008034" type="rw" uniqueid="ps7_can0_TXFIFO_DLC">
    <name>TXFIFO_DLC</name>
    <desc>transmit message fifo data length code</desc>
  </register>
  <register offset="0xe0008038" type="rw" uniqueid="ps7_can0_TXFIFO_DATA1">
    <name>TXFIFO_DATA1</name>
    <desc>transmit message fifo data word 1</desc>
  </register>
  <register offset="0xe000803c" type="rw" uniqueid="ps7_can0_TXFIFO_DATA2">
    <name>TXFIFO_DATA2</name>
    <desc>transmit message fifo data word 2</desc>
  </register>
  <register offset="0xe0008040" type="wo" uniqueid="ps7_can0_TXHPB_ID">
    <name>TXHPB_ID</name>
    <desc>transmit high priority buffer message identifier</desc>
  </register>
  <register offset="0xe0008044" type="rw" uniqueid="ps7_can0_TXHPB_DLC">
    <name>TXHPB_DLC</name>
    <desc>transmit high priority buffer data length code</desc>
  </register>
  <register offset="0xe0008048" type="rw" uniqueid="ps7_can0_TXHPB_DATA1">
    <name>TXHPB_DATA1</name>
    <desc>transmit high priority buffer data word 1</desc>
  </register>
  <register offset="0xe000804c" type="rw" uniqueid="ps7_can0_TXHPB_DATA2">
    <name>TXHPB_DATA2</name>
    <desc>transmit high priority buffer data word 2</desc>
  </register>
  <register offset="0xe0008050" type="ro" uniqueid="ps7_can0_RXFIFO_ID">
    <name>RXFIFO_ID</name>
    <desc>receive message fifo message identifier</desc>
  </register>
  <register offset="0xe0008054" type="rw" uniqueid="ps7_can0_RXFIFO_DLC">
    <name>RXFIFO_DLC</name>
    <desc>receive message fifo data length code</desc>
  </register>
  <register offset="0xe0008058" type="rw" uniqueid="ps7_can0_RXFIFO_DATA1">
    <name>RXFIFO_DATA1</name>
    <desc>receive message fifo data word 1</desc>
  </register>
  <register offset="0xe000805c" type="rw" uniqueid="ps7_can0_RXFIFO_DATA2">
    <name>RXFIFO_DATA2</name>
    <desc>receive message fifo data word 2</desc>
  </register>
  <register offset="0xe0008060" type="rw" uniqueid="ps7_can0_AFR">
    <name>AFR</name>
    <desc>Acceptance Filter Register</desc>
  </register>
  <register offset="0xe0008064" type="rw" uniqueid="ps7_can0_AFMR1">
    <name>AFMR1</name>
    <desc>Acceptance Filter Mask Register 1</desc>
  </register>
  <register offset="0xe0008068" type="rw" uniqueid="ps7_can0_AFIR1">
    <name>AFIR1</name>
    <desc>Acceptance Filter ID Register 1</desc>
  </register>
  <register offset="0xe000806c" type="rw" uniqueid="ps7_can0_AFMR2">
    <name>AFMR2</name>
    <desc>Acceptance Filter Mask Register 2</desc>
  </register>
  <register offset="0xe0008070" type="rw" uniqueid="ps7_can0_AFIR2">
    <name>AFIR2</name>
    <desc>Acceptance Filter ID Register 2</desc>
  </register>
  <register offset="0xe0008074" type="rw" uniqueid="ps7_can0_AFMR3">
    <name>AFMR3</name>
    <desc>Acceptance Filter Mask Register 3</desc>
  </register>
  <register offset="0xe0008078" type="rw" uniqueid="ps7_can0_AFIR3">
    <name>AFIR3</name>
    <desc>Acceptance Filter ID Register 3</desc>
  </register>
  <register offset="0xe000807c" type="rw" uniqueid="ps7_can0_AFMR4">
    <name>AFMR4</name>
    <desc>Acceptance Filter Mask Register 4</desc>
  </register>
  <register offset="0xe0008080" type="rw" uniqueid="ps7_can0_AFIR4">
    <name>AFIR4</name>
    <desc>Acceptance Filter ID Register 4</desc>
  </register>
  <register offset="0xf894610c" type="rw" uniqueid="ps7_gpv_qos301_cpu_qos_cntl">
    <name>qos_cntl</name>
    <desc>The QoS control register contains the enable bits for all the regulators.</desc>
  </register>
  <register offset="0xf8946110" type="rw" uniqueid="ps7_gpv_qos301_cpu_max_ot">
    <name>max_ot</name>
    <desc>Maximum number of outstanding transactions</desc>
  </register>
  <register offset="0xf8946114" type="rw" uniqueid="ps7_gpv_qos301_cpu_max_comb_ot">
    <name>max_comb_ot</name>
    <desc>Maximum number of combined outstanding transactions</desc>
  </register>
  <register offset="0xf8946118" type="rw" uniqueid="ps7_gpv_qos301_cpu_aw_p">
    <name>aw_p</name>
    <desc>AW channel peak rate</desc>
  </register>
  <register offset="0xf894611c" type="rw" uniqueid="ps7_gpv_qos301_cpu_aw_b">
    <name>aw_b</name>
    <desc>AW channel burstiness allowance</desc>
  </register>
  <register offset="0xf8946120" type="rw" uniqueid="ps7_gpv_qos301_cpu_aw_r">
    <name>aw_r</name>
    <desc>AW channel average rate</desc>
  </register>
  <register offset="0xf8946124" type="rw" uniqueid="ps7_gpv_qos301_cpu_ar_p">
    <name>ar_p</name>
    <desc>AR channel peak rate</desc>
  </register>
  <register offset="0xf8946128" type="rw" uniqueid="ps7_gpv_qos301_cpu_ar_b">
    <name>ar_b</name>
    <desc>AR channel burstiness allowance</desc>
  </register>
  <register offset="0xf894612c" type="rw" uniqueid="ps7_gpv_qos301_cpu_ar_r">
    <name>ar_r</name>
    <desc>AR channel average rate</desc>
  </register>
  <register offset="0xf894810c" type="rw" uniqueid="ps7_gpv_qos301_iou_qos_cntl">
    <name>qos_cntl</name>
    <desc>The QoS control register contains the enable bits for all the regulators.</desc>
  </register>
  <register offset="0xf8948110" type="rw" uniqueid="ps7_gpv_qos301_iou_max_ot">
    <name>max_ot</name>
    <desc>Maximum number of outstanding transactions</desc>
  </register>
  <register offset="0xf8948114" type="rw" uniqueid="ps7_gpv_qos301_iou_max_comb_ot">
    <name>max_comb_ot</name>
    <desc>Maximum number of combined outstanding transactions</desc>
  </register>
  <register offset="0xf8948118" type="rw" uniqueid="ps7_gpv_qos301_iou_aw_p">
    <name>aw_p</name>
    <desc>AW channel peak rate</desc>
  </register>
  <register offset="0xf894811c" type="rw" uniqueid="ps7_gpv_qos301_iou_aw_b">
    <name>aw_b</name>
    <desc>AW channel burstiness allowance</desc>
  </register>
  <register offset="0xf8948120" type="rw" uniqueid="ps7_gpv_qos301_iou_aw_r">
    <name>aw_r</name>
    <desc>AW channel average rate</desc>
  </register>
  <register offset="0xf8948124" type="rw" uniqueid="ps7_gpv_qos301_iou_ar_p">
    <name>ar_p</name>
    <desc>AR channel peak rate</desc>
  </register>
  <register offset="0xf8948128" type="rw" uniqueid="ps7_gpv_qos301_iou_ar_b">
    <name>ar_b</name>
    <desc>AR channel burstiness allowance</desc>
  </register>
  <register offset="0xf894812c" type="rw" uniqueid="ps7_gpv_qos301_iou_ar_r">
    <name>ar_r</name>
    <desc>AR channel average rate</desc>
  </register>
  <register offset="0xf894710c" type="rw" uniqueid="ps7_gpv_qos301_dmac_qos_cntl">
    <name>qos_cntl</name>
    <desc>The QoS control register contains the enable bits for all the regulators.</desc>
  </register>
  <register offset="0xf8947110" type="rw" uniqueid="ps7_gpv_qos301_dmac_max_ot">
    <name>max_ot</name>
    <desc>Maximum number of outstanding transactions</desc>
  </register>
  <register offset="0xf8947114" type="rw" uniqueid="ps7_gpv_qos301_dmac_max_comb_ot">
    <name>max_comb_ot</name>
    <desc>Maximum number of combined outstanding transactions</desc>
  </register>
  <register offset="0xf8947118" type="rw" uniqueid="ps7_gpv_qos301_dmac_aw_p">
    <name>aw_p</name>
    <desc>AW channel peak rate</desc>
  </register>
  <register offset="0xf894711c" type="rw" uniqueid="ps7_gpv_qos301_dmac_aw_b">
    <name>aw_b</name>
    <desc>AW channel burstiness allowance</desc>
  </register>
  <register offset="0xf8947120" type="rw" uniqueid="ps7_gpv_qos301_dmac_aw_r">
    <name>aw_r</name>
    <desc>AW channel average rate</desc>
  </register>
  <register offset="0xf8947124" type="rw" uniqueid="ps7_gpv_qos301_dmac_ar_p">
    <name>ar_p</name>
    <desc>AR channel peak rate</desc>
  </register>
  <register offset="0xf8947128" type="rw" uniqueid="ps7_gpv_qos301_dmac_ar_b">
    <name>ar_b</name>
    <desc>AR channel burstiness allowance</desc>
  </register>
  <register offset="0xf894712c" type="rw" uniqueid="ps7_gpv_qos301_dmac_ar_r">
    <name>ar_r</name>
    <desc>AR channel average rate</desc>
  </register>
  <register offset="0xf8804000" type="rw" uniqueid="ps7_debug_funnel_Control">
    <name>Control</name>
    <desc>CSTF Control Register</desc>
  </register>
  <register offset="0xf8804004" type="rw" uniqueid="ps7_debug_funnel_PriControl">
    <name>PriControl</name>
    <desc>CSTF Priority Control Register</desc>
  </register>
  <register offset="0xf8804eec" type="rw" uniqueid="ps7_debug_funnel_ITATBDATA0">
    <name>ITATBDATA0</name>
    <desc>Integration Test ATB Data 0 Register</desc>
  </register>
  <register offset="0xf8804ef0" type="rw" uniqueid="ps7_debug_funnel_ITATBCTR2">
    <name>ITATBCTR2</name>
    <desc>Integration Test ATB Control 2 Register</desc>
  </register>
  <register offset="0xf8804ef4" type="rw" uniqueid="ps7_debug_funnel_ITATBCTR1">
    <name>ITATBCTR1</name>
    <desc>Integration Test ATB Control 1 Register</desc>
  </register>
  <register offset="0xf8804ef8" type="rw" uniqueid="ps7_debug_funnel_ITATBCTR0">
    <name>ITATBCTR0</name>
    <desc>Integration Test ATB Control 0 Register</desc>
  </register>
  <register offset="0xf8804f00" type="rw" uniqueid="ps7_debug_funnel_IMCR">
    <name>IMCR</name>
    <desc>Integration Mode Control Register</desc>
  </register>
  <register offset="0xf8804fa0" type="rw" uniqueid="ps7_debug_funnel_CTSR">
    <name>CTSR</name>
    <desc>Claim Tag Set Register</desc>
  </register>
  <register offset="0xf8804fa4" type="rw" uniqueid="ps7_debug_funnel_CTCR">
    <name>CTCR</name>
    <desc>Claim Tag Clear Register</desc>
  </register>
  <register offset="0xf8804fb0" type="wo" uniqueid="ps7_debug_funnel_LAR">
    <name>LAR</name>
    <desc>Lock Access Register</desc>
  </register>
  <register offset="0xf8804fb4" type="ro" uniqueid="ps7_debug_funnel_LSR">
    <name>LSR</name>
    <desc>Lock Status Register</desc>
  </register>
  <register offset="0xf8804fb8" type="ro" uniqueid="ps7_debug_funnel_ASR">
    <name>ASR</name>
    <desc>Authentication Status Register</desc>
  </register>
  <register offset="0xf8804fc8" type="ro" uniqueid="ps7_debug_funnel_DEVID">
    <name>DEVID</name>
    <desc>Device ID</desc>
  </register>
  <register offset="0xf8804fcc" type="ro" uniqueid="ps7_debug_funnel_DTIR">
    <name>DTIR</name>
    <desc>Device Type Identifier Register</desc>
  </register>
  <register offset="0xf8804fd0" type="ro" uniqueid="ps7_debug_funnel_PERIPHID4">
    <name>PERIPHID4</name>
    <desc>Peripheral ID4</desc>
  </register>
  <register offset="0xf8804fd4" type="ro" uniqueid="ps7_debug_funnel_PERIPHID5">
    <name>PERIPHID5</name>
    <desc>Peripheral ID5</desc>
  </register>
  <register offset="0xf8804fd8" type="ro" uniqueid="ps7_debug_funnel_PERIPHID6">
    <name>PERIPHID6</name>
    <desc>Peripheral ID6</desc>
  </register>
  <register offset="0xf8804fdc" type="ro" uniqueid="ps7_debug_funnel_PERIPHID7">
    <name>PERIPHID7</name>
    <desc>Peripheral ID7</desc>
  </register>
  <register offset="0xf8804fe0" type="ro" uniqueid="ps7_debug_funnel_PERIPHID0">
    <name>PERIPHID0</name>
    <desc>Peripheral ID0</desc>
  </register>
  <register offset="0xf8804fe4" type="ro" uniqueid="ps7_debug_funnel_PERIPHID1">
    <name>PERIPHID1</name>
    <desc>Peripheral ID1</desc>
  </register>
  <register offset="0xf8804fe8" type="ro" uniqueid="ps7_debug_funnel_PERIPHID2">
    <name>PERIPHID2</name>
    <desc>Peripheral ID2</desc>
  </register>
  <register offset="0xf8804fec" type="ro" uniqueid="ps7_debug_funnel_PERIPHID3">
    <name>PERIPHID3</name>
    <desc>Peripheral ID3</desc>
  </register>
  <register offset="0xf8804ff0" type="ro" uniqueid="ps7_debug_funnel_COMPID0">
    <name>COMPID0</name>
    <desc>Component ID0</desc>
  </register>
  <register offset="0xf8804ff4" type="ro" uniqueid="ps7_debug_funnel_COMPID1">
    <name>COMPID1</name>
    <desc>Component ID1</desc>
  </register>
  <register offset="0xf8804ff8" type="ro" uniqueid="ps7_debug_funnel_COMPID2">
    <name>COMPID2</name>
    <desc>Component ID2</desc>
  </register>
  <register offset="0xf8804ffc" type="ro" uniqueid="ps7_debug_funnel_COMPID3">
    <name>COMPID3</name>
    <desc>Component ID3</desc>
  </register>
  <register offset="0xe0005000" type="rw" uniqueid="ps7_i2c1_Control_reg0">
    <name>Control_reg0</name>
    <desc>Control Register</desc>
  </register>
  <register offset="0xe0005004" type="ro" uniqueid="ps7_i2c1_Status_reg0">
    <name>Status_reg0</name>
    <desc>Stauts register</desc>
  </register>
  <register offset="0xe0005008" type="rw" uniqueid="ps7_i2c1_I2C_address_reg0">
    <name>I2C_address_reg0</name>
    <desc>IIC Address register</desc>
  </register>
  <register offset="0xe000500c" type="rw" uniqueid="ps7_i2c1_I2C_data_reg0">
    <name>I2C_data_reg0</name>
    <desc>IIC data register</desc>
  </register>
  <register offset="0xe0005010" type="rw" uniqueid="ps7_i2c1_Interrupt_status_reg0">
    <name>Interrupt_status_reg0</name>
    <desc>IIC interrupt status register</desc>
  </register>
  <register offset="0xe0005014" type="rw" uniqueid="ps7_i2c1_Transfer_size_reg0">
    <name>Transfer_size_reg0</name>
    <desc>Transfer Size Register</desc>
  </register>
  <register offset="0xe0005018" type="rw" uniqueid="ps7_i2c1_Slave_mon_pause_reg0">
    <name>Slave_mon_pause_reg0</name>
    <desc>Slave Monitor Pause Register</desc>
  </register>
  <register offset="0xe000501c" type="rw" uniqueid="ps7_i2c1_Time_out_reg0">
    <name>Time_out_reg0</name>
    <desc>Time out register</desc>
  </register>
  <register offset="0xe0005020" type="ro" uniqueid="ps7_i2c1_Intrpt_mask_reg0">
    <name>Intrpt_mask_reg0</name>
    <desc>Interrupt mask register</desc>
  </register>
  <register offset="0xe0005024" type="rw" uniqueid="ps7_i2c1_Intrpt_enable_reg0">
    <name>Intrpt_enable_reg0</name>
    <desc>Interrupt Enable Register</desc>
  </register>
  <register offset="0xe0005028" type="rw" uniqueid="ps7_i2c1_Intrpt_disable_reg0">
    <name>Intrpt_disable_reg0</name>
    <desc>Interrupt Disable Register</desc>
  </register>
  <register offset="0xe0004000" type="rw" uniqueid="ps7_i2c0_Control_reg0">
    <name>Control_reg0</name>
    <desc>Control Register</desc>
  </register>
  <register offset="0xe0004004" type="ro" uniqueid="ps7_i2c0_Status_reg0">
    <name>Status_reg0</name>
    <desc>Stauts register</desc>
  </register>
  <register offset="0xe0004008" type="rw" uniqueid="ps7_i2c0_I2C_address_reg0">
    <name>I2C_address_reg0</name>
    <desc>IIC Address register</desc>
  </register>
  <register offset="0xe000400c" type="rw" uniqueid="ps7_i2c0_I2C_data_reg0">
    <name>I2C_data_reg0</name>
    <desc>IIC data register</desc>
  </register>
  <register offset="0xe0004010" type="rw" uniqueid="ps7_i2c0_Interrupt_status_reg0">
    <name>Interrupt_status_reg0</name>
    <desc>IIC interrupt status register</desc>
  </register>
  <register offset="0xe0004014" type="rw" uniqueid="ps7_i2c0_Transfer_size_reg0">
    <name>Transfer_size_reg0</name>
    <desc>Transfer Size Register</desc>
  </register>
  <register offset="0xe0004018" type="rw" uniqueid="ps7_i2c0_Slave_mon_pause_reg0">
    <name>Slave_mon_pause_reg0</name>
    <desc>Slave Monitor Pause Register</desc>
  </register>
  <register offset="0xe000401c" type="rw" uniqueid="ps7_i2c0_Time_out_reg0">
    <name>Time_out_reg0</name>
    <desc>Time out register</desc>
  </register>
  <register offset="0xe0004020" type="ro" uniqueid="ps7_i2c0_Intrpt_mask_reg0">
    <name>Intrpt_mask_reg0</name>
    <desc>Interrupt mask register</desc>
  </register>
  <register offset="0xe0004024" type="rw" uniqueid="ps7_i2c0_Intrpt_enable_reg0">
    <name>Intrpt_enable_reg0</name>
    <desc>Interrupt Enable Register</desc>
  </register>
  <register offset="0xe0004028" type="rw" uniqueid="ps7_i2c0_Intrpt_disable_reg0">
    <name>Intrpt_disable_reg0</name>
    <desc>Interrupt Disable Register</desc>
  </register>
  <register offset="0xf8f02000" type="rw" uniqueid="ps7_l2cache_reg0_cache_id">
    <name>reg0_cache_id</name>
    <desc>cache ID register, Returns the 32-bit device ID code it reads off the CACHEID input bus.
The value is specified by the system integrator. Reset value: 0x410000c8</desc>
  </register>
  <register offset="0xf8f02004" type="rw" uniqueid="ps7_l2cache_reg0_cache_type">
    <name>reg0_cache_type</name>
    <desc>cache type register, Returns the 32-bit cache type. Reset value: 0x1c100100</desc>
  </register>
  <register offset="0xf8f02100" type="rw" uniqueid="ps7_l2cache_reg1_control">
    <name>reg1_control</name>
    <desc>control register, reset value: 0x0</desc>
  </register>
  <register offset="0xf8f02104" type="rw" uniqueid="ps7_l2cache_reg1_aux_control">
    <name>reg1_aux_control</name>
    <desc>auxilary control register, reset value: 0x02020000+H273</desc>
  </register>
  <register offset="0xf8f02108" type="rw" uniqueid="ps7_l2cache_reg1_tag_ram_control">
    <name>reg1_tag_ram_control</name>
    <desc>Configures Tag RAM latencies</desc>
  </register>
  <register offset="0xf8f0210c" type="rw" uniqueid="ps7_l2cache_reg1_data_ram_control">
    <name>reg1_data_ram_control</name>
    <desc>configures data RAM latencies</desc>
  </register>
  <register offset="0xf8f02200" type="rw" uniqueid="ps7_l2cache_reg2_ev_counter_ctrl">
    <name>reg2_ev_counter_ctrl</name>
    <desc>Permits the event counters to be enabled and reset.</desc>
  </register>
  <register offset="0xf8f02204" type="rw" uniqueid="ps7_l2cache_reg2_ev_counter1_cfg">
    <name>reg2_ev_counter1_cfg</name>
    <desc>Enables event counter 1 to be driven by a specific event. Counter 1
increments when the event occurs.</desc>
  </register>
  <register offset="0xf8f02208" type="rw" uniqueid="ps7_l2cache_reg2_ev_counter0_cfg">
    <name>reg2_ev_counter0_cfg</name>
    <desc>Enables event counter 0 to be driven by a specific event. Counter 0 increments when the event occurs.</desc>
  </register>
  <register offset="0xf8f0220c" type="rw" uniqueid="ps7_l2cache_reg2_ev_counter1">
    <name>reg2_ev_counter1</name>
    <desc>Enable the programmer to read off the counter value. The counter counts
an event as specified by the Counter Configuration Registers. The counter
can be preloaded if counting is disabled and reset by the Event Counter
Control Register.</desc>
  </register>
  <register offset="0xf8f02210" type="rw" uniqueid="ps7_l2cache_reg2_ev_counter0">
    <name>reg2_ev_counter0</name>
    <desc>Enable the programmer to read off the counter value. The counter counts
an event as specified by the Counter Configuration Registers. The counter
can be preloaded if counting is disabled and reset by the Event Counter
Control Register.</desc>
  </register>
  <register offset="0xf8f02214" type="rw" uniqueid="ps7_l2cache_reg2_int_mask">
    <name>reg2_int_mask</name>
    <desc>This register enables or masks interrupts from being triggered on the
external pins of the cache controller. Figure 3-8 on page 3-17 shows the
register bit assignments. The bit assignments enables the masking of the
interrupts on both their individual outputs and the combined L2CCINTR
line. Clearing a bit by writing a 0, disables the interrupt triggering on that
pin. All bits are cleared by a reset. You must write to the register bits with a 1 to enable the generation of interrupts.
1 = Enabled.
0 = Masked. This is the default.</desc>
  </register>
  <register offset="0xf8f02218" type="rw" uniqueid="ps7_l2cache_reg2_int_mask_status">
    <name>reg2_int_mask_status</name>
    <desc>This register is a read-only.It returns the masked interrupt status. This
register can be accessed by secure and non-secure operations. The register
gives an AND function of the raw interrupt status with the values of the
interrupt mask register. All the bits are cleared by a reset. A write to this register is ignored. Bits read can be HIGH or LOW:
HIGH If the bits read HIGH, they reflect the status of the input lines triggering an interrupt.
LOW If the bits read LOW, either no interrupt has been
generated, or the interrupt is masked.</desc>
  </register>
  <register offset="0xf8f0221c" type="rw" uniqueid="ps7_l2cache_reg2_int_raw_status">
    <name>reg2_int_raw_status</name>
    <desc>The Raw Interrupt Status Register enables the interrupt status that excludes the masking logic.
Bits read can be HIGH or LOW:
HIGH If the bits read HIGH, they reflect the status of the input lines triggering an interrupt.
LOW If the bits read LOW, no interrupt has been generated.</desc>
  </register>
  <register offset="0xf8f02220" type="rw" uniqueid="ps7_l2cache_reg2_int_clear">
    <name>reg2_int_clear</name>
    <desc>Clears the Raw Interrupt Status Register bits.
When a bit is written as 1, it clears the corresponding bit in the Raw Interrupt Status Register. When a bit is written as 0, it has no effect</desc>
  </register>
  <register offset="0xf8f02730" type="rw" uniqueid="ps7_l2cache_reg7_cache_sync">
    <name>reg7_cache_sync</name>
    <desc>Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and EB, are empty</desc>
  </register>
  <register offset="0xf8f02770" type="rw" uniqueid="ps7_l2cache_reg7_inv_pa">
    <name>reg7_inv_pa</name>
    <desc>Invalidate Line by PA: Specific L2 cache line is marked as not valid</desc>
  </register>
  <register offset="0xf8f0277c" type="rw" uniqueid="ps7_l2cache_reg7_inv_way">
    <name>reg7_inv_way</name>
    <desc>Invalidate by Way Invalidate all data in specified ways, including dirty data. An Invalidate by way while
selecting all cache ways is equivalent to invalidating all cache entries. Completes as a
background task with the way, or ways, locked, preventing allocation.</desc>
  </register>
  <register offset="0xf8f027b0" type="rw" uniqueid="ps7_l2cache_reg7_clean_pa">
    <name>reg7_clean_pa</name>
    <desc>Clean Line by PA Write the specific L2 cache line to L3 main memory if the line is marked as valid and dirty.
The line is marked as not dirty. The valid bit is unchanged</desc>
  </register>
  <register offset="0xf8f027b8" type="rw" uniqueid="ps7_l2cache_reg7_clean_index">
    <name>reg7_clean_index</name>
    <desc>Clean Line by Set/Way Write the specific L2 cache line within the specified way to L3 main memory if the line is
marked as valid and dirty. The line is marked as not dirty. The valid bit is unchanged</desc>
  </register>
  <register offset="0xf8f027bc" type="rw" uniqueid="ps7_l2cache_reg7_clean_way">
    <name>reg7_clean_way</name>
    <desc>Clean by Way Writes each line of the specified L2 cache ways to L3 main memory if the line is marked
as valid and dirty. The lines are marked as not dirty. The valid bits are unchanged.
Completes as a background task with the way, or ways, locked, preventing allocation.</desc>
  </register>
  <register offset="0xf8f027f0" type="rw" uniqueid="ps7_l2cache_reg7_clean_inv_pa">
    <name>reg7_clean_inv_pa</name>
    <desc>Clean and Invalidate Line by PA Write the specific L2 cache line to L3 main memory if the line is marked as valid and dirty.
The line is marked as not valid</desc>
  </register>
  <register offset="0xf8f027f8" type="rw" uniqueid="ps7_l2cache_reg7_clean_inv_index">
    <name>reg7_clean_inv_index</name>
    <desc>Clean and Invalidate Line by Set/Way Write the specific L2 cache line within the specified way to L3 main memory if the line is
marked as valid and dirty. The line is marked as not valid</desc>
  </register>
  <register offset="0xf8f027fc" type="rw" uniqueid="ps7_l2cache_reg7_clean_inv_way">
    <name>reg7_clean_inv_way</name>
    <desc>Clean and Invalidate by Way Writes each line of the specified L2 cache ways to L3 main memory if the line is marked
as valid and dirty. The lines are marked as not valid. Completes as a background task with
the way, or ways, locked, preventing allocation.</desc>
  </register>
  <register offset="0xf8f02900" type="rw" uniqueid="ps7_l2cache_reg9_d_lockdown0">
    <name>reg9_d_lockdown0</name>
    <desc>These registers can prevent new addresses from being allocated and can also prevent data from
being evicted out of the L2 cache. Such behavior can distinguish instructions from data
transactions.
To control the cache lockdown by way and the cache lockdown by master mechanisms see the
tables from Table 3-20 to Table 3-35 on page 3-31. For these tables each bit has the following
meaning:
0 allocation can occur in the corresponding way.
1 there is no allocation in the corresponding way.</desc>
  </register>
  <register offset="0xf8f02904" type="rw" uniqueid="ps7_l2cache_reg9_i_lockdown0">
    <name>reg9_i_lockdown0</name>
    <desc>instruction lock down 0</desc>
  </register>
  <register offset="0xf8f02908" type="rw" uniqueid="ps7_l2cache_reg9_d_lockdown1">
    <name>reg9_d_lockdown1</name>
    <desc>data lock down 1</desc>
  </register>
  <register offset="0xf8f0290c" type="rw" uniqueid="ps7_l2cache_reg9_i_lockdown1">
    <name>reg9_i_lockdown1</name>
    <desc>instruction lock down 1</desc>
  </register>
  <register offset="0xf8f02910" type="rw" uniqueid="ps7_l2cache_reg9_d_lockdown2">
    <name>reg9_d_lockdown2</name>
    <desc>data lock down 2</desc>
  </register>
  <register offset="0xf8f02914" type="rw" uniqueid="ps7_l2cache_reg9_i_lockdown2">
    <name>reg9_i_lockdown2</name>
    <desc>instruction lock down 2</desc>
  </register>
  <register offset="0xf8f02918" type="rw" uniqueid="ps7_l2cache_reg9_d_lockdown3">
    <name>reg9_d_lockdown3</name>
    <desc>data lock down 3</desc>
  </register>
  <register offset="0xf8f0291c" type="rw" uniqueid="ps7_l2cache_reg9_i_lockdown3">
    <name>reg9_i_lockdown3</name>
    <desc>instruction lock down 3</desc>
  </register>
  <register offset="0xf8f02920" type="rw" uniqueid="ps7_l2cache_reg9_d_lockdown4">
    <name>reg9_d_lockdown4</name>
    <desc>data lock down 4</desc>
  </register>
  <register offset="0xf8f02924" type="rw" uniqueid="ps7_l2cache_reg9_i_lockdown4">
    <name>reg9_i_lockdown4</name>
    <desc>instruction lock down 4</desc>
  </register>
  <register offset="0xf8f02928" type="rw" uniqueid="ps7_l2cache_reg9_d_lockdown5">
    <name>reg9_d_lockdown5</name>
    <desc>data lock down 5</desc>
  </register>
  <register offset="0xf8f0292c" type="rw" uniqueid="ps7_l2cache_reg9_i_lockdown5">
    <name>reg9_i_lockdown5</name>
    <desc>instruction lock down 5</desc>
  </register>
  <register offset="0xf8f02930" type="rw" uniqueid="ps7_l2cache_reg9_d_lockdown6">
    <name>reg9_d_lockdown6</name>
    <desc>data lock down 6</desc>
  </register>
  <register offset="0xf8f02934" type="rw" uniqueid="ps7_l2cache_reg9_i_lockdown6">
    <name>reg9_i_lockdown6</name>
    <desc>instruction lock down 6</desc>
  </register>
  <register offset="0xf8f02938" type="rw" uniqueid="ps7_l2cache_reg9_d_lockdown7">
    <name>reg9_d_lockdown7</name>
    <desc>data lock down 7</desc>
  </register>
  <register offset="0xf8f0293c" type="rw" uniqueid="ps7_l2cache_reg9_i_lockdown7">
    <name>reg9_i_lockdown7</name>
    <desc>instruction lock down 7</desc>
  </register>
  <register offset="0xf8f02950" type="rw" uniqueid="ps7_l2cache_reg9_lock_line_en">
    <name>reg9_lock_line_en</name>
    <desc>Lockdown by Line Enable Register.</desc>
  </register>
  <register offset="0xf8f02954" type="rw" uniqueid="ps7_l2cache_reg9_unlock_way">
    <name>reg9_unlock_way</name>
    <desc>Cache lockdown by way
To control the cache lockdown by way and the cache lockdown by master mechanisms see the
tables from Table 3-20 to Table 3-35 on page 3-31. For these tables each bit has the following
meaning:
0 allocation can occur in the corresponding way.
1 there is no allocation in the corresponding way.</desc>
  </register>
  <register offset="0xf8f02c00" type="rw" uniqueid="ps7_l2cache_reg12_addr_filtering_start">
    <name>reg12_addr_filtering_start</name>
    <desc>When two masters are implemented, you can redirect a whole address range to master 1 (M1).
When address_filtering_enable is set, all accesses with address &gt;= address_filtering_start and &lt;address_filtering_end are automatically directed to M1. All other accesses are directed to M0.
This feature is programmed using two registers.</desc>
  </register>
  <register offset="0xf8f02c04" type="rw" uniqueid="ps7_l2cache_reg12_addr_filtering_end">
    <name>reg12_addr_filtering_end</name>
    <desc>When two masters are implemented, you can redirect a whole address range to master 1 (M1).
When address_filtering_enable is set, all accesses with address &gt;= address_filtering_start and &lt;address_filtering_end are automatically directed to M1. All other accesses are directed to M0.
This feature is programmed using two registers.</desc>
  </register>
  <register offset="0xf8f02f40" type="rw" uniqueid="ps7_l2cache_reg15_debug_ctrl">
    <name>reg15_debug_ctrl</name>
    <desc>The Debug Control Register forces specific cache behavior required for debug. This register has
read-only, non-secure, or read and write, secure, permission. Any secure access and non-secure
access can read this register. Only a secure access can write to this register. If a non-secure
access tries to write to this register the register issues a DECERR response and does not update.</desc>
  </register>
  <register offset="0xf8f02f60" type="rw" uniqueid="ps7_l2cache_reg15_prefetch_ctrl">
    <name>reg15_prefetch_ctrl</name>
    <desc>Purpose Enables prefetch-related features that can improve system performance.
Usage constraints This register has both read-only, non-secure, and read and write, secure,
permissions. Any secure or non-secure access can read this register. Only
a secure access can write to this register. If a non-secure access attempts
to write to this register, the register</desc>
  </register>
  <register offset="0xf8f02f80" type="rw" uniqueid="ps7_l2cache_reg15_power_ctrl">
    <name>reg15_power_ctrl</name>
    <desc>Purpose Controls the operating mode clock and power modes.
Usage constraints There are no usage constraints.</desc>
  </register>
  <register offset="0xf800c000" type="rw" uniqueid="ps7_ocm_OCM_PARITY_CTRL">
    <name>OCM_PARITY_CTRL</name>
    <desc>Control fields for RAM parity operation</desc>
  </register>
  <register offset="0xf800c004" type="rw" uniqueid="ps7_ocm_OCM_PARITY_ERRADDRESS">
    <name>OCM_PARITY_ERRADDRESS</name>
    <desc>Stores the first parity error access address. This register is sticky and will retain its value unless explicitly cleared (written with 1's) with an APB write access. The physical RAM address is logged.</desc>
  </register>
  <register offset="0xf800c008" type="rw" uniqueid="ps7_ocm_OCM_IRQ_STS">
    <name>OCM_IRQ_STS</name>
    <desc>Status of OCM Interrupt</desc>
  </register>
  <register offset="0xf800c00c" type="rw" uniqueid="ps7_ocm_OCM_CONTROL">
    <name>OCM_CONTROL</name>
    <desc>Control fields for OCM</desc>
  </register>
  <register offset="0xf8891000" type="rw" uniqueid="ps7_debug_cpu_pmu0_PMXEVCNTR0">
    <name>PMXEVCNTR0</name>
    <desc>PMU event counter 0</desc>
  </register>
  <register offset="0xf8891004" type="rw" uniqueid="ps7_debug_cpu_pmu0_PMXEVCNTR1">
    <name>PMXEVCNTR1</name>
    <desc>PMU event counter 1</desc>
  </register>
  <register offset="0xf8891008" type="rw" uniqueid="ps7_debug_cpu_pmu0_PMXEVCNTR2">
    <name>PMXEVCNTR2</name>
    <desc>PMU event counter 2</desc>
  </register>
  <register offset="0xf889100c" type="rw" uniqueid="ps7_debug_cpu_pmu0_PMXEVCNTR3">
    <name>PMXEVCNTR3</name>
    <desc>PMU event counter 3</desc>
  </register>
  <register offset="0xf8891010" type="rw" uniqueid="ps7_debug_cpu_pmu0_PMXEVCNTR4">
    <name>PMXEVCNTR4</name>
    <desc>PMU event counter 4</desc>
  </register>
  <register offset="0xf8891014" type="rw" uniqueid="ps7_debug_cpu_pmu0_PMXEVCNTR5">
    <name>PMXEVCNTR5</name>
    <desc>PMU event counter 5</desc>
  </register>
  <register offset="0xf889107c" type="rw" uniqueid="ps7_debug_cpu_pmu0_PMCCNTR">
    <name>PMCCNTR</name>
    <desc>pmccntr</desc>
  </register>
  <register offset="0xf8891400" type="rw" uniqueid="ps7_debug_cpu_pmu0_PMXEVTYPER0">
    <name>PMXEVTYPER0</name>
    <desc>pmevtyper0</desc>
  </register>
  <register offset="0xf8891404" type="rw" uniqueid="ps7_debug_cpu_pmu0_PMXEVTYPER1">
    <name>PMXEVTYPER1</name>
    <desc>pmevtyper1</desc>
  </register>
  <register offset="0xf8891408" type="rw" uniqueid="ps7_debug_cpu_pmu0_PMXEVTYPER2">
    <name>PMXEVTYPER2</name>
    <desc>pmevtyper2</desc>
  </register>
  <register offset="0xf889140c" type="rw" uniqueid="ps7_debug_cpu_pmu0_PMXEVTYPER3">
    <name>PMXEVTYPER3</name>
    <desc>pmevtyper3</desc>
  </register>
  <register offset="0xf8891410" type="rw" uniqueid="ps7_debug_cpu_pmu0_PMXEVTYPER4">
    <name>PMXEVTYPER4</name>
    <desc>pmevtyper4</desc>
  </register>
  <register offset="0xf8891414" type="rw" uniqueid="ps7_debug_cpu_pmu0_PMXEVTYPER5">
    <name>PMXEVTYPER5</name>
    <desc>pmevtyper5</desc>
  </register>
  <register offset="0xf8891c00" type="rw" uniqueid="ps7_debug_cpu_pmu0_PMCNTENSET">
    <name>PMCNTENSET</name>
    <desc>pmcntenset</desc>
  </register>
  <register offset="0xf8891c20" type="rw" uniqueid="ps7_debug_cpu_pmu0_PMCNTENCLR">
    <name>PMCNTENCLR</name>
    <desc>pmcntenclr</desc>
  </register>
  <register offset="0xf8891c40" type="rw" uniqueid="ps7_debug_cpu_pmu0_PMINTENSET">
    <name>PMINTENSET</name>
    <desc>pmintenset</desc>
  </register>
  <register offset="0xf8891c60" type="rw" uniqueid="ps7_debug_cpu_pmu0_PMINTENCLR">
    <name>PMINTENCLR</name>
    <desc>pmintenclr</desc>
  </register>
  <register offset="0xf8891c80" type="rw" uniqueid="ps7_debug_cpu_pmu0_PMOVSR">
    <name>PMOVSR</name>
    <desc>pmovsr</desc>
  </register>
  <register offset="0xf8891ca0" type="wo" uniqueid="ps7_debug_cpu_pmu0_PMSWINC">
    <name>PMSWINC</name>
    <desc>pmswinc</desc>
  </register>
  <register offset="0xf8891e04" type="rw" uniqueid="ps7_debug_cpu_pmu0_PMCR">
    <name>PMCR</name>
    <desc>pmcr</desc>
  </register>
  <register offset="0xf8891e08" type="rw" uniqueid="ps7_debug_cpu_pmu0_PMUSERENR">
    <name>PMUSERENR</name>
    <desc>pmuserenr</desc>
  </register>
  <register offset="0xf8893000" type="rw" uniqueid="ps7_debug_cpu_pmu1_PMXEVCNTR0">
    <name>PMXEVCNTR0</name>
    <desc>PMU event counter 0</desc>
  </register>
  <register offset="0xf8893004" type="rw" uniqueid="ps7_debug_cpu_pmu1_PMXEVCNTR1">
    <name>PMXEVCNTR1</name>
    <desc>PMU event counter 1</desc>
  </register>
  <register offset="0xf8893008" type="rw" uniqueid="ps7_debug_cpu_pmu1_PMXEVCNTR2">
    <name>PMXEVCNTR2</name>
    <desc>PMU event counter 2</desc>
  </register>
  <register offset="0xf889300c" type="rw" uniqueid="ps7_debug_cpu_pmu1_PMXEVCNTR3">
    <name>PMXEVCNTR3</name>
    <desc>PMU event counter 3</desc>
  </register>
  <register offset="0xf8893010" type="rw" uniqueid="ps7_debug_cpu_pmu1_PMXEVCNTR4">
    <name>PMXEVCNTR4</name>
    <desc>PMU event counter 4</desc>
  </register>
  <register offset="0xf8893014" type="rw" uniqueid="ps7_debug_cpu_pmu1_PMXEVCNTR5">
    <name>PMXEVCNTR5</name>
    <desc>PMU event counter 5</desc>
  </register>
  <register offset="0xf889307c" type="rw" uniqueid="ps7_debug_cpu_pmu1_PMCCNTR">
    <name>PMCCNTR</name>
    <desc>pmccntr</desc>
  </register>
  <register offset="0xf8893400" type="rw" uniqueid="ps7_debug_cpu_pmu1_PMXEVTYPER0">
    <name>PMXEVTYPER0</name>
    <desc>pmevtyper0</desc>
  </register>
  <register offset="0xf8893404" type="rw" uniqueid="ps7_debug_cpu_pmu1_PMXEVTYPER1">
    <name>PMXEVTYPER1</name>
    <desc>pmevtyper1</desc>
  </register>
  <register offset="0xf8893408" type="rw" uniqueid="ps7_debug_cpu_pmu1_PMXEVTYPER2">
    <name>PMXEVTYPER2</name>
    <desc>pmevtyper2</desc>
  </register>
  <register offset="0xf889340c" type="rw" uniqueid="ps7_debug_cpu_pmu1_PMXEVTYPER3">
    <name>PMXEVTYPER3</name>
    <desc>pmevtyper3</desc>
  </register>
  <register offset="0xf8893410" type="rw" uniqueid="ps7_debug_cpu_pmu1_PMXEVTYPER4">
    <name>PMXEVTYPER4</name>
    <desc>pmevtyper4</desc>
  </register>
  <register offset="0xf8893414" type="rw" uniqueid="ps7_debug_cpu_pmu1_PMXEVTYPER5">
    <name>PMXEVTYPER5</name>
    <desc>pmevtyper5</desc>
  </register>
  <register offset="0xf8893c00" type="rw" uniqueid="ps7_debug_cpu_pmu1_PMCNTENSET">
    <name>PMCNTENSET</name>
    <desc>pmcntenset</desc>
  </register>
  <register offset="0xf8893c20" type="rw" uniqueid="ps7_debug_cpu_pmu1_PMCNTENCLR">
    <name>PMCNTENCLR</name>
    <desc>pmcntenclr</desc>
  </register>
  <register offset="0xf8893c40" type="rw" uniqueid="ps7_debug_cpu_pmu1_PMINTENSET">
    <name>PMINTENSET</name>
    <desc>pmintenset</desc>
  </register>
  <register offset="0xf8893c60" type="rw" uniqueid="ps7_debug_cpu_pmu1_PMINTENCLR">
    <name>PMINTENCLR</name>
    <desc>pmintenclr</desc>
  </register>
  <register offset="0xf8893c80" type="rw" uniqueid="ps7_debug_cpu_pmu1_PMOVSR">
    <name>PMOVSR</name>
    <desc>pmovsr</desc>
  </register>
  <register offset="0xf8893ca0" type="wo" uniqueid="ps7_debug_cpu_pmu1_PMSWINC">
    <name>PMSWINC</name>
    <desc>pmswinc</desc>
  </register>
  <register offset="0xf8893e04" type="rw" uniqueid="ps7_debug_cpu_pmu1_PMCR">
    <name>PMCR</name>
    <desc>pmcr</desc>
  </register>
  <register offset="0xf8893e08" type="rw" uniqueid="ps7_debug_cpu_pmu1_PMUSERENR">
    <name>PMUSERENR</name>
    <desc>pmuserenr</desc>
  </register>
  <register offset="0xf8000000" type="rw" uniqueid="ps7_slcr_SCL">
    <name>SCL</name>
    <desc>Secure Configuration Lock</desc>
  </register>
  <register offset="0xf8000004" type="wo" uniqueid="ps7_slcr_SLCR_LOCK">
    <name>SLCR_LOCK</name>
    <desc>SLCR Write Protection Lock</desc>
  </register>
  <register offset="0xf8000008" type="wo" uniqueid="ps7_slcr_SLCR_UNLOCK">
    <name>SLCR_UNLOCK</name>
    <desc>SLCR Write Protection Unlock</desc>
  </register>
  <register offset="0xf800000c" type="ro" uniqueid="ps7_slcr_SLCR_LOCKSTA">
    <name>SLCR_LOCKSTA</name>
    <desc>SLCR Write Protection Status</desc>
  </register>
  <register offset="0xf8000100" type="rw" uniqueid="ps7_slcr_ARM_PLL_CTRL">
    <name>ARM_PLL_CTRL</name>
    <desc>ARM PLL Control</desc>
  </register>
  <register offset="0xf8000104" type="rw" uniqueid="ps7_slcr_DDR_PLL_CTRL">
    <name>DDR_PLL_CTRL</name>
    <desc>DDR PLL Control</desc>
  </register>
  <register offset="0xf8000108" type="rw" uniqueid="ps7_slcr_IO_PLL_CTRL">
    <name>IO_PLL_CTRL</name>
    <desc>IO PLL Control</desc>
  </register>
  <register offset="0xf800010c" type="ro" uniqueid="ps7_slcr_PLL_STATUS">
    <name>PLL_STATUS</name>
    <desc>PLL Status</desc>
  </register>
  <register offset="0xf8000110" type="rw" uniqueid="ps7_slcr_ARM_PLL_CFG">
    <name>ARM_PLL_CFG</name>
    <desc>ARM PLL Configuration</desc>
  </register>
  <register offset="0xf8000114" type="rw" uniqueid="ps7_slcr_DDR_PLL_CFG">
    <name>DDR_PLL_CFG</name>
    <desc>DDR PLL Configuration</desc>
  </register>
  <register offset="0xf8000118" type="rw" uniqueid="ps7_slcr_IO_PLL_CFG">
    <name>IO_PLL_CFG</name>
    <desc>IO PLL Configuration</desc>
  </register>
  <register offset="0xf800011c" type="rw" uniqueid="ps7_slcr_PLL_BG_CTRL">
    <name>PLL_BG_CTRL</name>
    <desc>PLL Bandgap control</desc>
  </register>
  <register offset="0xf8000120" type="rw" uniqueid="ps7_slcr_ARM_CLK_CTRL">
    <name>ARM_CLK_CTRL</name>
    <desc>CORTEX A9 Clock Control</desc>
  </register>
  <register offset="0xf8000124" type="rw" uniqueid="ps7_slcr_DDR_CLK_CTRL">
    <name>DDR_CLK_CTRL</name>
    <desc>DDR Clock Control</desc>
  </register>
  <register offset="0xf8000128" type="rw" uniqueid="ps7_slcr_DCI_CLK_CTRL">
    <name>DCI_CLK_CTRL</name>
    <desc>DCI clock control</desc>
  </register>
  <register offset="0xf800012c" type="rw" uniqueid="ps7_slcr_APER_CLK_CTRL">
    <name>APER_CLK_CTRL</name>
    <desc>AMBA Peripheral Clock Control</desc>
  </register>
  <register offset="0xf8000130" type="rw" uniqueid="ps7_slcr_USB0_CLK_CTRL">
    <name>USB0_CLK_CTRL</name>
    <desc>USB 0 ULPI Clock Control</desc>
  </register>
  <register offset="0xf8000134" type="rw" uniqueid="ps7_slcr_USB1_CLK_CTRL">
    <name>USB1_CLK_CTRL</name>
    <desc>USB 1 ULPI Clock Control</desc>
  </register>
  <register offset="0xf8000138" type="rw" uniqueid="ps7_slcr_GEM0_RCLK_CTRL">
    <name>GEM0_RCLK_CTRL</name>
    <desc>Gigabit Ethernet MAC 0 RX Clock Control</desc>
  </register>
  <register offset="0xf800013c" type="rw" uniqueid="ps7_slcr_GEM1_RCLK_CTRL">
    <name>GEM1_RCLK_CTRL</name>
    <desc>Gigabit Ethernet MAC 1 RX Clock Control</desc>
  </register>
  <register offset="0xf8000140" type="rw" uniqueid="ps7_slcr_GEM0_CLK_CTRL">
    <name>GEM0_CLK_CTRL</name>
    <desc>Gigabit Ethernet MAC 0 Ref Clock Control</desc>
  </register>
  <register offset="0xf8000144" type="rw" uniqueid="ps7_slcr_GEM1_CLK_CTRL">
    <name>GEM1_CLK_CTRL</name>
    <desc>Gigabit Ethernet MAC 1 Ref Clock Control</desc>
  </register>
  <register offset="0xf8000148" type="rw" uniqueid="ps7_slcr_SMC_CLK_CTRL">
    <name>SMC_CLK_CTRL</name>
    <desc>SMC Reference Clock Control</desc>
  </register>
  <register offset="0xf800014c" type="rw" uniqueid="ps7_slcr_LQSPI_CLK_CTRL">
    <name>LQSPI_CLK_CTRL</name>
    <desc>Linear Quad-SPI Reference Clock Control</desc>
  </register>
  <register offset="0xf8000150" type="rw" uniqueid="ps7_slcr_SDIO_CLK_CTRL">
    <name>SDIO_CLK_CTRL</name>
    <desc>SDIO Reference Clock Control</desc>
  </register>
  <register offset="0xf8000154" type="rw" uniqueid="ps7_slcr_UART_CLK_CTRL">
    <name>UART_CLK_CTRL</name>
    <desc>UART Reference Clock Control</desc>
  </register>
  <register offset="0xf8000158" type="rw" uniqueid="ps7_slcr_SPI_CLK_CTRL">
    <name>SPI_CLK_CTRL</name>
    <desc>SPI Reference Clock Control</desc>
  </register>
  <register offset="0xf800015c" type="rw" uniqueid="ps7_slcr_CAN_CLK_CTRL">
    <name>CAN_CLK_CTRL</name>
    <desc>CAN Reference Clock Control</desc>
  </register>
  <register offset="0xf8000160" type="rw" uniqueid="ps7_slcr_CAN_MIOCLK_CTRL">
    <name>CAN_MIOCLK_CTRL</name>
    <desc>CAN MIO Clock Control</desc>
  </register>
  <register offset="0xf8000164" type="rw" uniqueid="ps7_slcr_DBG_CLK_CTRL">
    <name>DBG_CLK_CTRL</name>
    <desc>SoC Debug Clock Control</desc>
  </register>
  <register offset="0xf8000168" type="rw" uniqueid="ps7_slcr_PCAP_CLK_CTRL">
    <name>PCAP_CLK_CTRL</name>
    <desc>PCAP 2X Clock Contol</desc>
  </register>
  <register offset="0xf800016c" type="rw" uniqueid="ps7_slcr_TOPSW_CLK_CTRL">
    <name>TOPSW_CLK_CTRL</name>
    <desc>Top-Level Switch Clock Control</desc>
  </register>
  <register offset="0xf8000170" type="rw" uniqueid="ps7_slcr_FPGA0_CLK_CTRL">
    <name>FPGA0_CLK_CTRL</name>
    <desc>FPGA 0 Output Clock Control</desc>
  </register>
  <register offset="0xf8000174" type="rw" uniqueid="ps7_slcr_FPGA0_THR_CTRL">
    <name>FPGA0_THR_CTRL</name>
    <desc>FPGA 0 Clock Throttle Control</desc>
  </register>
  <register offset="0xf8000178" type="rw" uniqueid="ps7_slcr_FPGA0_THR_CNT">
    <name>FPGA0_THR_CNT</name>
    <desc>FPGA 0 Clock Throttle Count</desc>
  </register>
  <register offset="0xf800017c" type="rw" uniqueid="ps7_slcr_FPGA0_THR_STA">
    <name>FPGA0_THR_STA</name>
    <desc>FPGA 0 Clock Throttle Status</desc>
  </register>
  <register offset="0xf8000180" type="rw" uniqueid="ps7_slcr_FPGA1_CLK_CTRL">
    <name>FPGA1_CLK_CTRL</name>
    <desc>FPGA 1 Output Clock Control</desc>
  </register>
  <register offset="0xf8000184" type="rw" uniqueid="ps7_slcr_FPGA1_THR_CTRL">
    <name>FPGA1_THR_CTRL</name>
    <desc>FPGA 1 Clock Throttle Control</desc>
  </register>
  <register offset="0xf8000188" type="rw" uniqueid="ps7_slcr_FPGA1_THR_CNT">
    <name>FPGA1_THR_CNT</name>
    <desc>FPGA 1 Clock Throttle Count</desc>
  </register>
  <register offset="0xf800018c" type="rw" uniqueid="ps7_slcr_FPGA1_THR_STA">
    <name>FPGA1_THR_STA</name>
    <desc>FPGA 1 Clock Throttle Status</desc>
  </register>
  <register offset="0xf8000190" type="rw" uniqueid="ps7_slcr_FPGA2_CLK_CTRL">
    <name>FPGA2_CLK_CTRL</name>
    <desc>FPGA 2 Output Clock Control</desc>
  </register>
  <register offset="0xf8000194" type="rw" uniqueid="ps7_slcr_FPGA2_THR_CTRL">
    <name>FPGA2_THR_CTRL</name>
    <desc>FPGA 2 Clock Throttle Control</desc>
  </register>
  <register offset="0xf8000198" type="rw" uniqueid="ps7_slcr_FPGA2_THR_CNT">
    <name>FPGA2_THR_CNT</name>
    <desc>FPGA 2 Clock Throttle Count</desc>
  </register>
  <register offset="0xf800019c" type="rw" uniqueid="ps7_slcr_FPGA2_THR_STA">
    <name>FPGA2_THR_STA</name>
    <desc>FPGA 2 Clock Throttle Status</desc>
  </register>
  <register offset="0xf80001a0" type="rw" uniqueid="ps7_slcr_FPGA3_CLK_CTRL">
    <name>FPGA3_CLK_CTRL</name>
    <desc>FPGA 3 Output Clock Control</desc>
  </register>
  <register offset="0xf80001a4" type="rw" uniqueid="ps7_slcr_FPGA3_THR_CTRL">
    <name>FPGA3_THR_CTRL</name>
    <desc>FPGA 3 Clock Throttle Control</desc>
  </register>
  <register offset="0xf80001a8" type="rw" uniqueid="ps7_slcr_FPGA3_THR_CNT">
    <name>FPGA3_THR_CNT</name>
    <desc>FPGA 3 Clock Throttle Count</desc>
  </register>
  <register offset="0xf80001ac" type="rw" uniqueid="ps7_slcr_FPGA3_THR_STA">
    <name>FPGA3_THR_STA</name>
    <desc>FPGA 3 Clock Throttle Status</desc>
  </register>
  <register offset="0xf80001b0" type="rw" uniqueid="ps7_slcr_SYNC_CTRL">
    <name>SYNC_CTRL</name>
    <desc>Clock Synchronisation Mode Control</desc>
  </register>
  <register offset="0xf80001b8" type="rw" uniqueid="ps7_slcr_BANDGAP_TRIM">
    <name>BANDGAP_TRIM</name>
    <desc>Band gap trim register</desc>
  </register>
  <register offset="0xf80001bc" type="rw" uniqueid="ps7_slcr_CC_TEST">
    <name>CC_TEST</name>
    <desc>Test register</desc>
  </register>
  <register offset="0xf80001c0" type="rw" uniqueid="ps7_slcr_PLL_PREDIVISOR">
    <name>PLL_PREDIVISOR</name>
    <desc>Divider on the input clock</desc>
  </register>
  <register offset="0xf80001c4" type="rw" uniqueid="ps7_slcr_CLK_621_TRUE">
    <name>CLK_621_TRUE</name>
    <desc>6:2:1 ratio clock, if set</desc>
  </register>
  <register offset="0xf80001d0" type="rw" uniqueid="ps7_slcr_PICTURE_DBG">
    <name>PICTURE_DBG</name>
    <desc>Picture debug configuartion register</desc>
  </register>
  <register offset="0xf80001d4" type="rw" uniqueid="ps7_slcr_PICTURE_DBG_UCNT">
    <name>PICTURE_DBG_UCNT</name>
    <desc>Picture debug count register, upper 32-bit</desc>
  </register>
  <register offset="0xf80001d8" type="rw" uniqueid="ps7_slcr_PICTURE_DBG_LCNT">
    <name>PICTURE_DBG_LCNT</name>
    <desc>Picture debug count register, lower 32-bit</desc>
  </register>
  <register offset="0xf8000200" type="rw" uniqueid="ps7_slcr_PSS_RST_CTRL">
    <name>PSS_RST_CTRL</name>
    <desc>PSS Software Reset Control</desc>
  </register>
  <register offset="0xf8000204" type="rw" uniqueid="ps7_slcr_DDR_RST_CTRL">
    <name>DDR_RST_CTRL</name>
    <desc>DDR Software Reset Control</desc>
  </register>
  <register offset="0xf800020c" type="rw" uniqueid="ps7_slcr_DMAC_RST_CTRL">
    <name>DMAC_RST_CTRL</name>
    <desc>DMAC Software Reset Control</desc>
  </register>
  <register offset="0xf8000210" type="rw" uniqueid="ps7_slcr_USB_RST_CTRL">
    <name>USB_RST_CTRL</name>
    <desc>USB Software Reset Control</desc>
  </register>
  <register offset="0xf8000214" type="rw" uniqueid="ps7_slcr_GEM_RST_CTRL">
    <name>GEM_RST_CTRL</name>
    <desc>Gigabit Ethernet MAC Software Reset Control</desc>
  </register>
  <register offset="0xf8000218" type="rw" uniqueid="ps7_slcr_SDIO_RST_CTRL">
    <name>SDIO_RST_CTRL</name>
    <desc>SDIO Software Reset Control</desc>
  </register>
  <register offset="0xf800021c" type="rw" uniqueid="ps7_slcr_SPI_RST_CTRL">
    <name>SPI_RST_CTRL</name>
    <desc>SPI Software Reset Control</desc>
  </register>
  <register offset="0xf8000220" type="rw" uniqueid="ps7_slcr_CAN_RST_CTRL">
    <name>CAN_RST_CTRL</name>
    <desc>CAN Software Reset Control</desc>
  </register>
  <register offset="0xf8000224" type="rw" uniqueid="ps7_slcr_I2C_RST_CTRL">
    <name>I2C_RST_CTRL</name>
    <desc>I2C Software Reset Control</desc>
  </register>
  <register offset="0xf8000228" type="rw" uniqueid="ps7_slcr_UART_RST_CTRL">
    <name>UART_RST_CTRL</name>
    <desc>UART Software Reset Control</desc>
  </register>
  <register offset="0xf800022c" type="rw" uniqueid="ps7_slcr_GPIO_RST_CTRL">
    <name>GPIO_RST_CTRL</name>
    <desc>GPIO Software Reset Control</desc>
  </register>
  <register offset="0xf8000230" type="rw" uniqueid="ps7_slcr_LQSPI_RST_CTRL">
    <name>LQSPI_RST_CTRL</name>
    <desc>Linear Quad-SpI Software Reset Control</desc>
  </register>
  <register offset="0xf8000234" type="rw" uniqueid="ps7_slcr_SMC_RST_CTRL">
    <name>SMC_RST_CTRL</name>
    <desc>SMC Software Reset Control</desc>
  </register>
  <register offset="0xf8000238" type="rw" uniqueid="ps7_slcr_OCM_RST_CTRL">
    <name>OCM_RST_CTRL</name>
    <desc>OCM Software Reset Control</desc>
  </register>
  <register offset="0xf800023c" type="rw" uniqueid="ps7_slcr_DEVCI_RST_CTRL">
    <name>DEVCI_RST_CTRL</name>
    <desc>Device Config Interface Software Reset Control</desc>
  </register>
  <register offset="0xf8000240" type="rw" uniqueid="ps7_slcr_FPGA_RST_CTRL">
    <name>FPGA_RST_CTRL</name>
    <desc>FPGA Software Reset Control</desc>
  </register>
  <register offset="0xf8000244" type="rw" uniqueid="ps7_slcr_A9_CPU_RST_CTRL">
    <name>A9_CPU_RST_CTRL</name>
    <desc>A9 CPU software Reset Control</desc>
  </register>
  <register offset="0xf800024c" type="rw" uniqueid="ps7_slcr_RS_AWDT_CTRL">
    <name>RS_AWDT_CTRL</name>
    <desc>Watchdog Timer Reset Control</desc>
  </register>
  <register offset="0xf8000250" type="ro" uniqueid="ps7_slcr_RST_REASON">
    <name>RST_REASON</name>
    <desc>Reset Reason</desc>
  </register>
  <register offset="0xf8000254" type="rw" uniqueid="ps7_slcr_RST_REASON_CLR">
    <name>RST_REASON_CLR</name>
    <desc>Reset Reason Clear</desc>
  </register>
  <register offset="0xf8000258" type="rw" uniqueid="ps7_slcr_REBOOT_STATUS">
    <name>REBOOT_STATUS</name>
    <desc>Reboot Status (persistent through all resets except Power-on reset)</desc>
  </register>
  <register offset="0xf800025c" type="rw" uniqueid="ps7_slcr_BOOT_MODE">
    <name>BOOT_MODE</name>
    <desc>Boot Mode bootstrap register</desc>
  </register>
  <register offset="0xf8000300" type="rw" uniqueid="ps7_slcr_APU_CTRL">
    <name>APU_CTRL</name>
    <desc>APU Control</desc>
  </register>
  <register offset="0xf8000304" type="rw" uniqueid="ps7_slcr_WDT_CLK_SEL">
    <name>WDT_CLK_SEL</name>
    <desc>APU watchdog timer clock select</desc>
  </register>
  <register offset="0xf8000400" type="rw" uniqueid="ps7_slcr_TZ_OCM_RAM0">
    <name>TZ_OCM_RAM0</name>
    <desc>OCM RAM TrustZone Configuration Register 0</desc>
  </register>
  <register offset="0xf8000404" type="rw" uniqueid="ps7_slcr_TZ_OCM_RAM1">
    <name>TZ_OCM_RAM1</name>
    <desc>OCM RAM TrustZone Configuration Register 1</desc>
  </register>
  <register offset="0xf8000408" type="rw" uniqueid="ps7_slcr_TZ_OCM_ROM">
    <name>TZ_OCM_ROM</name>
    <desc>OCM ROM TrustZone Configuration Register</desc>
  </register>
  <register offset="0xf8000430" type="rw" uniqueid="ps7_slcr_TZ_DDR_RAM">
    <name>TZ_DDR_RAM</name>
    <desc>DDR RAM TrustZone Configuration Register</desc>
  </register>
  <register offset="0xf8000440" type="rw" uniqueid="ps7_slcr_TZ_DMA_NS">
    <name>TZ_DMA_NS</name>
    <desc>DMAC TrustZone Configuration Register</desc>
  </register>
  <register offset="0xf8000444" type="rw" uniqueid="ps7_slcr_TZ_DMA_IRQ_NS">
    <name>TZ_DMA_IRQ_NS</name>
    <desc>DMAC TrustZone Configuration Register for Interrupts</desc>
  </register>
  <register offset="0xf8000448" type="rw" uniqueid="ps7_slcr_TZ_DMA_PERIPH_NS">
    <name>TZ_DMA_PERIPH_NS</name>
    <desc>DMAC TrustZone Configuration Register for Peripherals</desc>
  </register>
  <register offset="0xf8000450" type="rw" uniqueid="ps7_slcr_TZ_GEM">
    <name>TZ_GEM</name>
    <desc>GEM TrustZone Configuration Register</desc>
  </register>
  <register offset="0xf8000454" type="rw" uniqueid="ps7_slcr_TZ_SDIO">
    <name>TZ_SDIO</name>
    <desc>SDIO TrustZone Configuration Register</desc>
  </register>
  <register offset="0xf8000458" type="rw" uniqueid="ps7_slcr_TZ_USB">
    <name>TZ_USB</name>
    <desc>USB TrustZone Configuration Register</desc>
  </register>
  <register offset="0xf8000484" type="rw" uniqueid="ps7_slcr_TZ_FPGA_M">
    <name>TZ_FPGA_M</name>
    <desc>FPGA master ports TrustZone Disable Register</desc>
  </register>
  <register offset="0xf8000488" type="rw" uniqueid="ps7_slcr_TZ_FPGA_AFI">
    <name>TZ_FPGA_AFI</name>
    <desc>FPGA AFI AXI ports TrustZone Disable Register</desc>
  </register>
  <register offset="0xf8000500" type="rw" uniqueid="ps7_slcr_DBG_CTRL">
    <name>DBG_CTRL</name>
    <desc>SoC Debug Control</desc>
  </register>
  <register offset="0xf8000530" type="rw" uniqueid="ps7_slcr_PSS_IDCODE">
    <name>PSS_IDCODE</name>
    <desc>PSS IDCODE</desc>
  </register>
  <register offset="0xf8000600" type="rw" uniqueid="ps7_slcr_DDR_URGENT">
    <name>DDR_URGENT</name>
    <desc>DDR Urgent Control</desc>
  </register>
  <register offset="0xf800060c" type="rw" uniqueid="ps7_slcr_DDR_CAL_START">
    <name>DDR_CAL_START</name>
    <desc>DDR Calibration Start Triggers</desc>
  </register>
  <register offset="0xf8000614" type="rw" uniqueid="ps7_slcr_DDR_REF_START">
    <name>DDR_REF_START</name>
    <desc>DDR Refresh Start Triggers</desc>
  </register>
  <register offset="0xf8000618" type="rw" uniqueid="ps7_slcr_DDR_CMD_STA">
    <name>DDR_CMD_STA</name>
    <desc>DDR Command Store Status</desc>
  </register>
  <register offset="0xf800061c" type="rw" uniqueid="ps7_slcr_DDR_URGENT_SEL">
    <name>DDR_URGENT_SEL</name>
    <desc>DDR Urgent Select</desc>
  </register>
  <register offset="0xf8000620" type="rw" uniqueid="ps7_slcr_DDR_DFI_STATUS">
    <name>DDR_DFI_STATUS</name>
    <desc>DDR DFI status</desc>
  </register>
  <register offset="0xf8000700" type="rw" uniqueid="ps7_slcr_MIO_PIN_00">
    <name>MIO_PIN_00</name>
    <desc>MIO Control for Pin 0</desc>
  </register>
  <register offset="0xf8000704" type="rw" uniqueid="ps7_slcr_MIO_PIN_01">
    <name>MIO_PIN_01</name>
    <desc>MIO Control for Pin 1</desc>
  </register>
  <register offset="0xf8000708" type="rw" uniqueid="ps7_slcr_MIO_PIN_02">
    <name>MIO_PIN_02</name>
    <desc>MIO Control for Pin 2</desc>
  </register>
  <register offset="0xf800070c" type="rw" uniqueid="ps7_slcr_MIO_PIN_03">
    <name>MIO_PIN_03</name>
    <desc>MIO Control for Pin 3</desc>
  </register>
  <register offset="0xf8000710" type="rw" uniqueid="ps7_slcr_MIO_PIN_04">
    <name>MIO_PIN_04</name>
    <desc>MIO Control for Pin 4</desc>
  </register>
  <register offset="0xf8000714" type="rw" uniqueid="ps7_slcr_MIO_PIN_05">
    <name>MIO_PIN_05</name>
    <desc>MIO Control for Pin 5</desc>
  </register>
  <register offset="0xf8000718" type="rw" uniqueid="ps7_slcr_MIO_PIN_06">
    <name>MIO_PIN_06</name>
    <desc>MIO Control for Pin 6</desc>
  </register>
  <register offset="0xf800071c" type="rw" uniqueid="ps7_slcr_MIO_PIN_07">
    <name>MIO_PIN_07</name>
    <desc>MIO Control for Pin 7</desc>
  </register>
  <register offset="0xf8000720" type="rw" uniqueid="ps7_slcr_MIO_PIN_08">
    <name>MIO_PIN_08</name>
    <desc>MIO Control for Pin 8</desc>
  </register>
  <register offset="0xf8000724" type="rw" uniqueid="ps7_slcr_MIO_PIN_09">
    <name>MIO_PIN_09</name>
    <desc>MIO Control for Pin 9</desc>
  </register>
  <register offset="0xf8000728" type="rw" uniqueid="ps7_slcr_MIO_PIN_10">
    <name>MIO_PIN_10</name>
    <desc>MIO Control for Pin 10</desc>
  </register>
  <register offset="0xf800072c" type="rw" uniqueid="ps7_slcr_MIO_PIN_11">
    <name>MIO_PIN_11</name>
    <desc>MIO Control for Pin 11</desc>
  </register>
  <register offset="0xf8000730" type="rw" uniqueid="ps7_slcr_MIO_PIN_12">
    <name>MIO_PIN_12</name>
    <desc>MIO Control for Pin 12</desc>
  </register>
  <register offset="0xf8000734" type="rw" uniqueid="ps7_slcr_MIO_PIN_13">
    <name>MIO_PIN_13</name>
    <desc>MIO Control for Pin 13</desc>
  </register>
  <register offset="0xf8000738" type="rw" uniqueid="ps7_slcr_MIO_PIN_14">
    <name>MIO_PIN_14</name>
    <desc>MIO Control for Pin 14</desc>
  </register>
  <register offset="0xf800073c" type="rw" uniqueid="ps7_slcr_MIO_PIN_15">
    <name>MIO_PIN_15</name>
    <desc>MIO Control for Pin 15</desc>
  </register>
  <register offset="0xf8000740" type="rw" uniqueid="ps7_slcr_MIO_PIN_16">
    <name>MIO_PIN_16</name>
    <desc>MIO Control for Pin 16</desc>
  </register>
  <register offset="0xf8000744" type="rw" uniqueid="ps7_slcr_MIO_PIN_17">
    <name>MIO_PIN_17</name>
    <desc>MIO Control for Pin 17</desc>
  </register>
  <register offset="0xf8000748" type="rw" uniqueid="ps7_slcr_MIO_PIN_18">
    <name>MIO_PIN_18</name>
    <desc>MIO Control for Pin 18</desc>
  </register>
  <register offset="0xf800074c" type="rw" uniqueid="ps7_slcr_MIO_PIN_19">
    <name>MIO_PIN_19</name>
    <desc>MIO Control for Pin 19</desc>
  </register>
  <register offset="0xf8000750" type="rw" uniqueid="ps7_slcr_MIO_PIN_20">
    <name>MIO_PIN_20</name>
    <desc>MIO Control for Pin 20</desc>
  </register>
  <register offset="0xf8000754" type="rw" uniqueid="ps7_slcr_MIO_PIN_21">
    <name>MIO_PIN_21</name>
    <desc>MIO Control for Pin 21</desc>
  </register>
  <register offset="0xf8000758" type="rw" uniqueid="ps7_slcr_MIO_PIN_22">
    <name>MIO_PIN_22</name>
    <desc>MIO Control for Pin 22</desc>
  </register>
  <register offset="0xf800075c" type="rw" uniqueid="ps7_slcr_MIO_PIN_23">
    <name>MIO_PIN_23</name>
    <desc>MIO Control for Pin 23</desc>
  </register>
  <register offset="0xf8000760" type="rw" uniqueid="ps7_slcr_MIO_PIN_24">
    <name>MIO_PIN_24</name>
    <desc>MIO Control for Pin 24</desc>
  </register>
  <register offset="0xf8000764" type="rw" uniqueid="ps7_slcr_MIO_PIN_25">
    <name>MIO_PIN_25</name>
    <desc>MIO Control for Pin 25</desc>
  </register>
  <register offset="0xf8000768" type="rw" uniqueid="ps7_slcr_MIO_PIN_26">
    <name>MIO_PIN_26</name>
    <desc>MIO Control for Pin 26</desc>
  </register>
  <register offset="0xf800076c" type="rw" uniqueid="ps7_slcr_MIO_PIN_27">
    <name>MIO_PIN_27</name>
    <desc>MIO Control for Pin 27</desc>
  </register>
  <register offset="0xf8000770" type="rw" uniqueid="ps7_slcr_MIO_PIN_28">
    <name>MIO_PIN_28</name>
    <desc>MIO Control for Pin 28</desc>
  </register>
  <register offset="0xf8000774" type="rw" uniqueid="ps7_slcr_MIO_PIN_29">
    <name>MIO_PIN_29</name>
    <desc>MIO Control for Pin 29</desc>
  </register>
  <register offset="0xf8000778" type="rw" uniqueid="ps7_slcr_MIO_PIN_30">
    <name>MIO_PIN_30</name>
    <desc>MIO Control for Pin 30</desc>
  </register>
  <register offset="0xf800077c" type="rw" uniqueid="ps7_slcr_MIO_PIN_31">
    <name>MIO_PIN_31</name>
    <desc>MIO Control for Pin 31</desc>
  </register>
  <register offset="0xf8000780" type="rw" uniqueid="ps7_slcr_MIO_PIN_32">
    <name>MIO_PIN_32</name>
    <desc>MIO Control for Pin 32</desc>
  </register>
  <register offset="0xf8000784" type="rw" uniqueid="ps7_slcr_MIO_PIN_33">
    <name>MIO_PIN_33</name>
    <desc>MIO Control for Pin 33</desc>
  </register>
  <register offset="0xf8000788" type="rw" uniqueid="ps7_slcr_MIO_PIN_34">
    <name>MIO_PIN_34</name>
    <desc>MIO Control for Pin 34</desc>
  </register>
  <register offset="0xf800078c" type="rw" uniqueid="ps7_slcr_MIO_PIN_35">
    <name>MIO_PIN_35</name>
    <desc>MIO Control for Pin 35</desc>
  </register>
  <register offset="0xf8000790" type="rw" uniqueid="ps7_slcr_MIO_PIN_36">
    <name>MIO_PIN_36</name>
    <desc>MIO Control for Pin 36</desc>
  </register>
  <register offset="0xf8000794" type="rw" uniqueid="ps7_slcr_MIO_PIN_37">
    <name>MIO_PIN_37</name>
    <desc>MIO Control for Pin 37</desc>
  </register>
  <register offset="0xf8000798" type="rw" uniqueid="ps7_slcr_MIO_PIN_38">
    <name>MIO_PIN_38</name>
    <desc>MIO Control for Pin 38</desc>
  </register>
  <register offset="0xf800079c" type="rw" uniqueid="ps7_slcr_MIO_PIN_39">
    <name>MIO_PIN_39</name>
    <desc>MIO Control for Pin 39</desc>
  </register>
  <register offset="0xf80007a0" type="rw" uniqueid="ps7_slcr_MIO_PIN_40">
    <name>MIO_PIN_40</name>
    <desc>MIO Control for Pin 40</desc>
  </register>
  <register offset="0xf80007a4" type="rw" uniqueid="ps7_slcr_MIO_PIN_41">
    <name>MIO_PIN_41</name>
    <desc>MIO Control for Pin 41</desc>
  </register>
  <register offset="0xf80007a8" type="rw" uniqueid="ps7_slcr_MIO_PIN_42">
    <name>MIO_PIN_42</name>
    <desc>MIO Control for Pin 42</desc>
  </register>
  <register offset="0xf80007ac" type="rw" uniqueid="ps7_slcr_MIO_PIN_43">
    <name>MIO_PIN_43</name>
    <desc>MIO Control for Pin 43</desc>
  </register>
  <register offset="0xf80007b0" type="rw" uniqueid="ps7_slcr_MIO_PIN_44">
    <name>MIO_PIN_44</name>
    <desc>MIO Control for Pin 44</desc>
  </register>
  <register offset="0xf80007b4" type="rw" uniqueid="ps7_slcr_MIO_PIN_45">
    <name>MIO_PIN_45</name>
    <desc>MIO Control for Pin 45</desc>
  </register>
  <register offset="0xf80007b8" type="rw" uniqueid="ps7_slcr_MIO_PIN_46">
    <name>MIO_PIN_46</name>
    <desc>MIO Control for Pin 46</desc>
  </register>
  <register offset="0xf80007bc" type="rw" uniqueid="ps7_slcr_MIO_PIN_47">
    <name>MIO_PIN_47</name>
    <desc>MIO Control for Pin 47</desc>
  </register>
  <register offset="0xf80007c0" type="rw" uniqueid="ps7_slcr_MIO_PIN_48">
    <name>MIO_PIN_48</name>
    <desc>MIO Control for Pin 48</desc>
  </register>
  <register offset="0xf80007c4" type="rw" uniqueid="ps7_slcr_MIO_PIN_49">
    <name>MIO_PIN_49</name>
    <desc>MIO Control for Pin 49</desc>
  </register>
  <register offset="0xf80007c8" type="rw" uniqueid="ps7_slcr_MIO_PIN_50">
    <name>MIO_PIN_50</name>
    <desc>MIO Control for Pin 50</desc>
  </register>
  <register offset="0xf80007cc" type="rw" uniqueid="ps7_slcr_MIO_PIN_51">
    <name>MIO_PIN_51</name>
    <desc>MIO Control for Pin 51</desc>
  </register>
  <register offset="0xf80007d0" type="rw" uniqueid="ps7_slcr_MIO_PIN_52">
    <name>MIO_PIN_52</name>
    <desc>MIO Control for Pin 52</desc>
  </register>
  <register offset="0xf80007d4" type="rw" uniqueid="ps7_slcr_MIO_PIN_53">
    <name>MIO_PIN_53</name>
    <desc>MIO Control for Pin 53</desc>
  </register>
  <register offset="0xf8000800" type="rw" uniqueid="ps7_slcr_MIO_FMIO_GEM_SEL">
    <name>MIO_FMIO_GEM_SEL</name>
    <desc>Select function to be routed via MIO or FMIO</desc>
  </register>
  <register offset="0xf8000804" type="rw" uniqueid="ps7_slcr_MIO_LOOPBACK">
    <name>MIO_LOOPBACK</name>
    <desc>Loopback function within MIO</desc>
  </register>
  <register offset="0xf800080c" type="rw" uniqueid="ps7_slcr_MIO_MST_TRI0">
    <name>MIO_MST_TRI0</name>
    <desc>Parallel access to the master tri-state enables for all pins, least significant word</desc>
  </register>
  <register offset="0xf8000810" type="rw" uniqueid="ps7_slcr_MIO_MST_TR11">
    <name>MIO_MST_TR11</name>
    <desc>Parallel access to the master tri-state enables for all pins, most significant word</desc>
  </register>
  <register offset="0xf8000830" type="rw" uniqueid="ps7_slcr_SD0_WP_CD_SEL">
    <name>SD0_WP_CD_SEL</name>
    <desc>SDIO 0 WP CD select register</desc>
  </register>
  <register offset="0xf8000834" type="rw" uniqueid="ps7_slcr_SD1_WP_CD_SEL">
    <name>SD1_WP_CD_SEL</name>
    <desc>SDIO 1 WP CD select register</desc>
  </register>
  <register offset="0xf8000900" type="rw" uniqueid="ps7_slcr_LVL_SHFTR_EN">
    <name>LVL_SHFTR_EN</name>
    <desc>Level Shifters Enable</desc>
  </register>
  <register offset="0xf8000910" type="rw" uniqueid="ps7_slcr_OCM_CFG">
    <name>OCM_CFG</name>
    <desc>OCM configuration</desc>
  </register>
  <register offset="0xf8000a00" type="rw" uniqueid="ps7_slcr_CPU0_RAM0">
    <name>CPU0_RAM0</name>
    <desc>CPU#0: dcache outer, dcache tag, dcache data (3 RAM controls)</desc>
  </register>
  <register offset="0xf8000a04" type="rw" uniqueid="ps7_slcr_CPU0_RAM1">
    <name>CPU0_RAM1</name>
    <desc>CPU#0: global history buffer, icache tag, icache data (3 RAM controls)</desc>
  </register>
  <register offset="0xf8000a08" type="rw" uniqueid="ps7_slcr_CPU0_RAM2">
    <name>CPU0_RAM2</name>
    <desc>CPU#0: TLB hi, TLB lo, btac_target, btac_control (4 RAM controls)</desc>
  </register>
  <register offset="0xf8000a0c" type="rw" uniqueid="ps7_slcr_CPU1_RAM0">
    <name>CPU1_RAM0</name>
    <desc>CPU#1: dcache outer, dcache tag, dcache data (3 RAM controls)</desc>
  </register>
  <register offset="0xf8000a10" type="rw" uniqueid="ps7_slcr_CPU1_RAM1">
    <name>CPU1_RAM1</name>
    <desc>CPU#1: global history buffer, icache tag, icache data (3 RAM controls)</desc>
  </register>
  <register offset="0xf8000a14" type="rw" uniqueid="ps7_slcr_CPU1_RAM2">
    <name>CPU1_RAM2</name>
    <desc>CPU#1: TLB hi, TLB lo, btac_target, btac_control (4 RAM controls)</desc>
  </register>
  <register offset="0xf8000a18" type="rw" uniqueid="ps7_slcr_SCU_RAM">
    <name>SCU_RAM</name>
    <desc>SCU: tag (1 RAM control)</desc>
  </register>
  <register offset="0xf8000a1c" type="rw" uniqueid="ps7_slcr_L2C_RAM">
    <name>L2C_RAM</name>
    <desc>L2 Cache: tag, parity, data (3 RAM controls)</desc>
  </register>
  <register offset="0xf8000a30" type="rw" uniqueid="ps7_slcr_IOU_RAM_GEM01">
    <name>IOU_RAM_GEM01</name>
    <desc>IOU: GEM 0/1, 4 RAM controls</desc>
  </register>
  <register offset="0xf8000a34" type="rw" uniqueid="ps7_slcr_IOU_RAM_USB01">
    <name>IOU_RAM_USB01</name>
    <desc>IOU: USB 0/1, 4 RAM controls</desc>
  </register>
  <register offset="0xf8000a38" type="rw" uniqueid="ps7_slcr_IOU_RAM_SDIO0">
    <name>IOU_RAM_SDIO0</name>
    <desc>IOU: SDIO 0, 4 RAM controls</desc>
  </register>
  <register offset="0xf8000a3c" type="rw" uniqueid="ps7_slcr_IOU_RAM_SDIO1">
    <name>IOU_RAM_SDIO1</name>
    <desc>IOU: SDIO 1, 4 RAM controls</desc>
  </register>
  <register offset="0xf8000a40" type="rw" uniqueid="ps7_slcr_IOU_RAM_CAN0">
    <name>IOU_RAM_CAN0</name>
    <desc>IOU: CAN 0, 3 RAM controls</desc>
  </register>
  <register offset="0xf8000a44" type="rw" uniqueid="ps7_slcr_IOU_RAM_CAN1">
    <name>IOU_RAM_CAN1</name>
    <desc>IOU: CAN 1, 3 RAM controls</desc>
  </register>
  <register offset="0xf8000a48" type="rw" uniqueid="ps7_slcr_IOU_RAM_LQSPI">
    <name>IOU_RAM_LQSPI</name>
    <desc>IOU: LQSPI, 2 RAM controls</desc>
  </register>
  <register offset="0xf8000a50" type="rw" uniqueid="ps7_slcr_DMAC_RAM">
    <name>DMAC_RAM</name>
    <desc>DMA Controller: 1 RAM control</desc>
  </register>
  <register offset="0xf8000a60" type="rw" uniqueid="ps7_slcr_AFI0_RAM0">
    <name>AFI0_RAM0</name>
    <desc>AFI0: RAM 3 to RAM 0 controls</desc>
  </register>
  <register offset="0xf8000a64" type="rw" uniqueid="ps7_slcr_AFI0_RAM1">
    <name>AFI0_RAM1</name>
    <desc>AFI0: RAM 7 to RAM 4controls</desc>
  </register>
  <register offset="0xf8000a68" type="rw" uniqueid="ps7_slcr_AFI0_RAM2">
    <name>AFI0_RAM2</name>
    <desc>AFI0: RAM 9 to RAM 8 controls</desc>
  </register>
  <register offset="0xf8000a6c" type="rw" uniqueid="ps7_slcr_AFI1_RAM0">
    <name>AFI1_RAM0</name>
    <desc>AFI1: RAM 3 to RAM 0 controls</desc>
  </register>
  <register offset="0xf8000a70" type="rw" uniqueid="ps7_slcr_AFI1_RAM1">
    <name>AFI1_RAM1</name>
    <desc>AFI1: RAM 7 to RAM 4controls</desc>
  </register>
  <register offset="0xf8000a74" type="rw" uniqueid="ps7_slcr_AFI1_RAM2">
    <name>AFI1_RAM2</name>
    <desc>AFI1: RAM 9 to RAM 8 controls</desc>
  </register>
  <register offset="0xf8000a78" type="rw" uniqueid="ps7_slcr_AFI2_RAM0">
    <name>AFI2_RAM0</name>
    <desc>AFI2: RAM 3 to RAM 0 controls</desc>
  </register>
  <register offset="0xf8000a7c" type="rw" uniqueid="ps7_slcr_AFI2_RAM1">
    <name>AFI2_RAM1</name>
    <desc>AFI2: RAM 7 to RAM 4controls</desc>
  </register>
  <register offset="0xf8000a80" type="rw" uniqueid="ps7_slcr_AFI2_RAM2">
    <name>AFI2_RAM2</name>
    <desc>AFI2: RAM 9 to RAM 8 controls</desc>
  </register>
  <register offset="0xf8000a84" type="rw" uniqueid="ps7_slcr_AFI3_RAM0">
    <name>AFI3_RAM0</name>
    <desc>AFI3: RAM 3 to RAM 0 controls</desc>
  </register>
  <register offset="0xf8000a88" type="rw" uniqueid="ps7_slcr_AFI3_RAM1">
    <name>AFI3_RAM1</name>
    <desc>AFI3: RAM 7 to RAM 4controls</desc>
  </register>
  <register offset="0xf8000a8c" type="rw" uniqueid="ps7_slcr_AFI3_RAM2">
    <name>AFI3_RAM2</name>
    <desc>AFI3: RAM 9 to RAM 8 controls</desc>
  </register>
  <register offset="0xf8000a90" type="rw" uniqueid="ps7_slcr_OCM_RAM">
    <name>OCM_RAM</name>
    <desc>OCM: 4 RAM controls</desc>
  </register>
  <register offset="0xf8000a94" type="ro" uniqueid="ps7_slcr_OCM_ROM0">
    <name>OCM_ROM0</name>
    <desc>OCM: 4 ROM controls</desc>
  </register>
  <register offset="0xf8000a98" type="ro" uniqueid="ps7_slcr_OCM_ROM1">
    <name>OCM_ROM1</name>
    <desc>OCM: 4 ROM controls</desc>
  </register>
  <register offset="0xf8000aa0" type="rw" uniqueid="ps7_slcr_DEVCI_RAM">
    <name>DEVCI_RAM</name>
    <desc>DEVCI: Tx and Rx FIFOs (2 RAM controls)</desc>
  </register>
  <register offset="0xf8000ab0" type="rw" uniqueid="ps7_slcr_CSG_RAM">
    <name>CSG_RAM</name>
    <desc>Coresight: embedded trace buffer</desc>
  </register>
  <register offset="0xf8000b00" type="rw" uniqueid="ps7_slcr_GPIOB_CTRL">
    <name>GPIOB_CTRL</name>
    <desc>GPIOB control</desc>
  </register>
  <register offset="0xf8000b04" type="rw" uniqueid="ps7_slcr_GPIOB_CFG_CMOS18">
    <name>GPIOB_CFG_CMOS18</name>
    <desc>GPIOB CMOS 1.8V IO configuration</desc>
  </register>
  <register offset="0xf8000b08" type="rw" uniqueid="ps7_slcr_GPIOB_CFG_CMOS25">
    <name>GPIOB_CFG_CMOS25</name>
    <desc>GPIOB CMOS 2.5V IO configuration</desc>
  </register>
  <register offset="0xf8000b0c" type="rw" uniqueid="ps7_slcr_GPIOB_CFG_CMOS33">
    <name>GPIOB_CFG_CMOS33</name>
    <desc>GPIOB CMOS 3.3V IO configuration</desc>
  </register>
  <register offset="0xf8000b10" type="rw" uniqueid="ps7_slcr_GPIOB_CFG_LVTTL">
    <name>GPIOB_CFG_LVTTL</name>
    <desc>GPIOB LVTTL IO configuration</desc>
  </register>
  <register offset="0xf8000b14" type="rw" uniqueid="ps7_slcr_GPIOB_CFG_HSTL">
    <name>GPIOB_CFG_HSTL</name>
    <desc>GPIOB HSTL configuration</desc>
  </register>
  <register offset="0xf8000b18" type="rw" uniqueid="ps7_slcr_GPIOB_DRVR_BIAS_CTRL">
    <name>GPIOB_DRVR_BIAS_CTRL</name>
    <desc>GPIOB Driver Bias Control [31:0]</desc>
  </register>
  <register offset="0xf8000b40" type="rw" uniqueid="ps7_slcr_DDRIOB_ADDR0">
    <name>DDRIOB_ADDR0</name>
    <desc>DDRIOB Address 0 Configuartion Register</desc>
  </register>
  <register offset="0xf8000b44" type="rw" uniqueid="ps7_slcr_DDRIOB_ADDR1">
    <name>DDRIOB_ADDR1</name>
    <desc>DDRIOB Address 1 Configuration Register</desc>
  </register>
  <register offset="0xf8000b48" type="rw" uniqueid="ps7_slcr_DDRIOB_DATA0">
    <name>DDRIOB_DATA0</name>
    <desc>DDRIOB Data 0 Configuration Register</desc>
  </register>
  <register offset="0xf8000b4c" type="rw" uniqueid="ps7_slcr_DDRIOB_DATA1">
    <name>DDRIOB_DATA1</name>
    <desc>DDRIOB Data 1 Configuration Register</desc>
  </register>
  <register offset="0xf8000b50" type="rw" uniqueid="ps7_slcr_DDRIOB_DIFF0">
    <name>DDRIOB_DIFF0</name>
    <desc>DDRIOB Differential DQS 0 Configuration Register</desc>
  </register>
  <register offset="0xf8000b54" type="rw" uniqueid="ps7_slcr_DDRIOB_DIFF1">
    <name>DDRIOB_DIFF1</name>
    <desc>DDRIOB Differential DQS 1 Configuration Register</desc>
  </register>
  <register offset="0xf8000b58" type="rw" uniqueid="ps7_slcr_DDRIOB_CLOCK">
    <name>DDRIOB_CLOCK</name>
    <desc>DDRIOB Differential Clock Configuration Register</desc>
  </register>
  <register offset="0xf8000b5c" type="rw" uniqueid="ps7_slcr_DDRIOB_DRIVE_SLEW_ADDR">
    <name>DDRIOB_DRIVE_SLEW_ADDR</name>
    <desc>DDRIOB Drive Slew Address Register</desc>
  </register>
  <register offset="0xf8000b60" type="rw" uniqueid="ps7_slcr_DDRIOB_DRIVE_SLEW_DATA">
    <name>DDRIOB_DRIVE_SLEW_DATA</name>
    <desc>DDRIOB Drive Slew Data Register</desc>
  </register>
  <register offset="0xf8000b64" type="rw" uniqueid="ps7_slcr_DDRIOB_DRIVE_SLEW_DIFF">
    <name>DDRIOB_DRIVE_SLEW_DIFF</name>
    <desc>DDRIOB Drive Slew Differential Strobe Register</desc>
  </register>
  <register offset="0xf8000b68" type="rw" uniqueid="ps7_slcr_DDRIOB_DRIVE_SLEW_CLOCK">
    <name>DDRIOB_DRIVE_SLEW_CLOCK</name>
    <desc>DDRIOB Drive Slew Clcok Register</desc>
  </register>
  <register offset="0xf8000b6c" type="rw" uniqueid="ps7_slcr_DDRIOB_DDR_CTRL">
    <name>DDRIOB_DDR_CTRL</name>
    <desc>DDRIOB DDR Control Register</desc>
  </register>
  <register offset="0xf8000b70" type="rw" uniqueid="ps7_slcr_DDRIOB_DCI_CTRL">
    <name>DDRIOB_DCI_CTRL</name>
    <desc>DDRIOB DCI configuration</desc>
  </register>
  <register offset="0xf8000b74" type="rw" uniqueid="ps7_slcr_DDRIOB_DCI_STATUS">
    <name>DDRIOB_DCI_STATUS</name>
    <desc>DDRIOB digital control impedance status</desc>
  </register>
  <register offset="0xe0007000" type="rw" uniqueid="ps7_spi1_Config_reg0">
    <name>Config_reg0</name>
    <desc>SPI configuration register</desc>
  </register>
  <register offset="0xe0007004" type="ro" uniqueid="ps7_spi1_Intr_status_reg0">
    <name>Intr_status_reg0</name>
    <desc>SPI interrupt status register</desc>
  </register>
  <register offset="0xe0007008" type="rw" uniqueid="ps7_spi1_Intrpt_en_reg0">
    <name>Intrpt_en_reg0</name>
    <desc>Interrupt Enable register</desc>
  </register>
  <register offset="0xe000700c" type="rw" uniqueid="ps7_spi1_Intrpt_dis_reg0">
    <name>Intrpt_dis_reg0</name>
    <desc>Interrupt disable register</desc>
  </register>
  <register offset="0xe0007010" type="ro" uniqueid="ps7_spi1_Intrpt_mask_reg0">
    <name>Intrpt_mask_reg0</name>
    <desc>Interrupt mask register</desc>
  </register>
  <register offset="0xe0007014" type="rw" uniqueid="ps7_spi1_En_reg0">
    <name>En_reg0</name>
    <desc>SPI_Enable Register</desc>
  </register>
  <register offset="0xe0007018" type="rw" uniqueid="ps7_spi1_Delay_reg0">
    <name>Delay_reg0</name>
    <desc>Delay Register</desc>
  </register>
  <register offset="0xe000701c" type="wo" uniqueid="ps7_spi1_Tx_data_reg0">
    <name>Tx_data_reg0</name>
    <desc>Transmit Data Register</desc>
  </register>
  <register offset="0xe0007020" type="ro" uniqueid="ps7_spi1_Rx_data_reg0">
    <name>Rx_data_reg0</name>
    <desc>Receive Data Register</desc>
  </register>
  <register offset="0xe0007024" type="rw" uniqueid="ps7_spi1_Slave_Idle_count_reg0">
    <name>Slave_Idle_count_reg0</name>
    <desc>Slave Idle Count Register</desc>
  </register>
  <register offset="0xe0007028" type="rw" uniqueid="ps7_spi1_TX_thres_reg0">
    <name>TX_thres_reg0</name>
    <desc>TX_FIFO Threshold Register</desc>
  </register>
  <register offset="0xe000702c" type="rw" uniqueid="ps7_spi1_RX_thres_reg0">
    <name>RX_thres_reg0</name>
    <desc>RX FIFO Threshold Register</desc>
  </register>
  <register offset="0xe00070fc" type="ro" uniqueid="ps7_spi1_Mod_id_reg0">
    <name>Mod_id_reg0</name>
    <desc>Module ID register</desc>
  </register>
  <register offset="0xe0006000" type="rw" uniqueid="ps7_spi0_Config_reg0">
    <name>Config_reg0</name>
    <desc>SPI configuration register</desc>
  </register>
  <register offset="0xe0006004" type="ro" uniqueid="ps7_spi0_Intr_status_reg0">
    <name>Intr_status_reg0</name>
    <desc>SPI interrupt status register</desc>
  </register>
  <register offset="0xe0006008" type="rw" uniqueid="ps7_spi0_Intrpt_en_reg0">
    <name>Intrpt_en_reg0</name>
    <desc>Interrupt Enable register</desc>
  </register>
  <register offset="0xe000600c" type="rw" uniqueid="ps7_spi0_Intrpt_dis_reg0">
    <name>Intrpt_dis_reg0</name>
    <desc>Interrupt disable register</desc>
  </register>
  <register offset="0xe0006010" type="ro" uniqueid="ps7_spi0_Intrpt_mask_reg0">
    <name>Intrpt_mask_reg0</name>
    <desc>Interrupt mask register</desc>
  </register>
  <register offset="0xe0006014" type="rw" uniqueid="ps7_spi0_En_reg0">
    <name>En_reg0</name>
    <desc>SPI_Enable Register</desc>
  </register>
  <register offset="0xe0006018" type="rw" uniqueid="ps7_spi0_Delay_reg0">
    <name>Delay_reg0</name>
    <desc>Delay Register</desc>
  </register>
  <register offset="0xe000601c" type="wo" uniqueid="ps7_spi0_Tx_data_reg0">
    <name>Tx_data_reg0</name>
    <desc>Transmit Data Register</desc>
  </register>
  <register offset="0xe0006020" type="ro" uniqueid="ps7_spi0_Rx_data_reg0">
    <name>Rx_data_reg0</name>
    <desc>Receive Data Register</desc>
  </register>
  <register offset="0xe0006024" type="rw" uniqueid="ps7_spi0_Slave_Idle_count_reg0">
    <name>Slave_Idle_count_reg0</name>
    <desc>Slave Idle Count Register</desc>
  </register>
  <register offset="0xe0006028" type="rw" uniqueid="ps7_spi0_TX_thres_reg0">
    <name>TX_thres_reg0</name>
    <desc>TX_FIFO Threshold Register</desc>
  </register>
  <register offset="0xe000602c" type="rw" uniqueid="ps7_spi0_RX_thres_reg0">
    <name>RX_thres_reg0</name>
    <desc>RX FIFO Threshold Register</desc>
  </register>
  <register offset="0xe00060fc" type="ro" uniqueid="ps7_spi0_Mod_id_reg0">
    <name>Mod_id_reg0</name>
    <desc>Module ID register</desc>
  </register>
  <register offset="0xf8005000" type="rw" uniqueid="ps7_swdt_MODE">
    <name>MODE</name>
    <desc>WD zero mode register</desc>
  </register>
  <register offset="0xf8005004" type="rw" uniqueid="ps7_swdt_CONTROL">
    <name>CONTROL</name>
    <desc>Counter Control Register</desc>
  </register>
  <register offset="0xf8005008" type="wo" uniqueid="ps7_swdt_RESTART">
    <name>RESTART</name>
    <desc>Restart key register - this not a real register as no data is stored</desc>
  </register>
  <register offset="0xf800500c" type="ro" uniqueid="ps7_swdt_STATUS">
    <name>STATUS</name>
    <desc>Status Register</desc>
  </register>
  <register offset="0xf8004000" type="rw" uniqueid="ps7_dmac0_ns_DSR">
    <name>DSR</name>
    <desc>DMA manager status register</desc>
  </register>
  <register offset="0xf8004004" type="rw" uniqueid="ps7_dmac0_ns_DPC">
    <name>DPC</name>
    <desc>DMA Program Counter Register</desc>
  </register>
  <register offset="0xf8004020" type="rw" uniqueid="ps7_dmac0_ns_INTEN">
    <name>INTEN</name>
    <desc>Interrupt enable register</desc>
  </register>
  <register offset="0xf8004024" type="rw" uniqueid="ps7_dmac0_ns_INT_EVENT_RIS">
    <name>INT_EVENT_RIS</name>
    <desc>Event interrupt raw status register</desc>
  </register>
  <register offset="0xf8004028" type="rw" uniqueid="ps7_dmac0_ns_INTMIS">
    <name>INTMIS</name>
    <desc>Interrupt Status Register</desc>
  </register>
  <register offset="0xf800402c" type="rw" uniqueid="ps7_dmac0_ns_INTCLR">
    <name>INTCLR</name>
    <desc>Interrupt Clear Register</desc>
  </register>
  <register offset="0xf8004030" type="rw" uniqueid="ps7_dmac0_ns_FSRD">
    <name>FSRD</name>
    <desc>Fault Status DMA Manager Register</desc>
  </register>
  <register offset="0xf8004034" type="rw" uniqueid="ps7_dmac0_ns_FSRC">
    <name>FSRC</name>
    <desc>Fault Status DMA Channel Register</desc>
  </register>
  <register offset="0xf8004038" type="rw" uniqueid="ps7_dmac0_ns_FTRD">
    <name>FTRD</name>
    <desc>Fault Type DMA Manager Register</desc>
  </register>
  <register offset="0xf8004040" type="rw" uniqueid="ps7_dmac0_ns_FTR0">
    <name>FTR0</name>
    <desc>Default type for DMA channel 0</desc>
  </register>
  <register offset="0xf8004044" type="rw" uniqueid="ps7_dmac0_ns_FTR1">
    <name>FTR1</name>
    <desc>Default type for DMA channel 1</desc>
  </register>
  <register offset="0xf8004048" type="rw" uniqueid="ps7_dmac0_ns_FTR2">
    <name>FTR2</name>
    <desc>Default type for DMA channel 2</desc>
  </register>
  <register offset="0xf800404c" type="rw" uniqueid="ps7_dmac0_ns_FTR3">
    <name>FTR3</name>
    <desc>Default type for DMA channel 3</desc>
  </register>
  <register offset="0xf8004050" type="rw" uniqueid="ps7_dmac0_ns_FTR4">
    <name>FTR4</name>
    <desc>Default type for DMA channel 4</desc>
  </register>
  <register offset="0xf8004054" type="rw" uniqueid="ps7_dmac0_ns_FTR5">
    <name>FTR5</name>
    <desc>Default type for DMA channel 5</desc>
  </register>
  <register offset="0xf8004058" type="rw" uniqueid="ps7_dmac0_ns_FTR6">
    <name>FTR6</name>
    <desc>Default type for DMA channel 6</desc>
  </register>
  <register offset="0xf800405c" type="rw" uniqueid="ps7_dmac0_ns_FTR7">
    <name>FTR7</name>
    <desc>Default type for DMA channel 7</desc>
  </register>
  <register offset="0xf8004100" type="rw" uniqueid="ps7_dmac0_ns_CSR0">
    <name>CSR0</name>
    <desc>Channel status for DMA channel 0</desc>
  </register>
  <register offset="0xf8004104" type="rw" uniqueid="ps7_dmac0_ns_CPC0">
    <name>CPC0</name>
    <desc>Channel PC for DMA channel 0</desc>
  </register>
  <register offset="0xf8004108" type="rw" uniqueid="ps7_dmac0_ns_CSR1">
    <name>CSR1</name>
    <desc>Channel status for DMA channel 1</desc>
  </register>
  <register offset="0xf800410c" type="rw" uniqueid="ps7_dmac0_ns_CPC1">
    <name>CPC1</name>
    <desc>Channel PC for DMA channel 1</desc>
  </register>
  <register offset="0xf8004110" type="rw" uniqueid="ps7_dmac0_ns_CSR2">
    <name>CSR2</name>
    <desc>Channel status for DMA channel 2</desc>
  </register>
  <register offset="0xf8004114" type="rw" uniqueid="ps7_dmac0_ns_CPC2">
    <name>CPC2</name>
    <desc>Channel PC for DMA channel 2</desc>
  </register>
  <register offset="0xf8004118" type="rw" uniqueid="ps7_dmac0_ns_CSR3">
    <name>CSR3</name>
    <desc>Channel status for DMA channel 3</desc>
  </register>
  <register offset="0xf800411c" type="rw" uniqueid="ps7_dmac0_ns_CPC3">
    <name>CPC3</name>
    <desc>Channel PC for DMA channel 3</desc>
  </register>
  <register offset="0xf8004120" type="rw" uniqueid="ps7_dmac0_ns_CSR4">
    <name>CSR4</name>
    <desc>Channel status for DMA channel 4</desc>
  </register>
  <register offset="0xf8004124" type="rw" uniqueid="ps7_dmac0_ns_CPC4">
    <name>CPC4</name>
    <desc>Channel PC for DMA channel 4</desc>
  </register>
  <register offset="0xf8004128" type="rw" uniqueid="ps7_dmac0_ns_CSR5">
    <name>CSR5</name>
    <desc>Channel status for DMA channel 5</desc>
  </register>
  <register offset="0xf800412c" type="rw" uniqueid="ps7_dmac0_ns_CPC5">
    <name>CPC5</name>
    <desc>Channel PC for DMA channel 5</desc>
  </register>
  <register offset="0xf8004130" type="rw" uniqueid="ps7_dmac0_ns_CSR6">
    <name>CSR6</name>
    <desc>Channel status for DMA channel 6</desc>
  </register>
  <register offset="0xf8004134" type="rw" uniqueid="ps7_dmac0_ns_CPC6">
    <name>CPC6</name>
    <desc>Channel PC for DMA channel 6</desc>
  </register>
  <register offset="0xf8004138" type="rw" uniqueid="ps7_dmac0_ns_CSR7">
    <name>CSR7</name>
    <desc>Channel status for DMA channel 7</desc>
  </register>
  <register offset="0xf800413c" type="rw" uniqueid="ps7_dmac0_ns_CPC7">
    <name>CPC7</name>
    <desc>Channel PC for DMA channel 7</desc>
  </register>
  <register offset="0xf8004400" type="rw" uniqueid="ps7_dmac0_ns_SAR0">
    <name>SAR0</name>
    <desc>source address for DMA channel 0</desc>
  </register>
  <register offset="0xf8004404" type="rw" uniqueid="ps7_dmac0_ns_DAR0">
    <name>DAR0</name>
    <desc>destination address for DMA channel 0</desc>
  </register>
  <register offset="0xf8004408" type="rw" uniqueid="ps7_dmac0_ns_CCR0">
    <name>CCR0</name>
    <desc>channel control for DMA channel 0</desc>
  </register>
  <register offset="0xf800440c" type="rw" uniqueid="ps7_dmac0_ns_LC0_0">
    <name>LC0_0</name>
    <desc>loop counter 0 for DMA channel 0</desc>
  </register>
  <register offset="0xf8004410" type="rw" uniqueid="ps7_dmac0_ns_LC1_0">
    <name>LC1_0</name>
    <desc>loop counter 1 for DMA channel 0</desc>
  </register>
  <register offset="0xf8004420" type="rw" uniqueid="ps7_dmac0_ns_SAR1">
    <name>SAR1</name>
    <desc>source address for DMA channel 1</desc>
  </register>
  <register offset="0xf8004424" type="rw" uniqueid="ps7_dmac0_ns_DAR1">
    <name>DAR1</name>
    <desc>destination address for DMA channel 1</desc>
  </register>
  <register offset="0xf8004428" type="rw" uniqueid="ps7_dmac0_ns_CCR1">
    <name>CCR1</name>
    <desc>channel control for DMA channel 1</desc>
  </register>
  <register offset="0xf800442c" type="rw" uniqueid="ps7_dmac0_ns_LC0_1">
    <name>LC0_1</name>
    <desc>loop counter 0 for DMA channel 1</desc>
  </register>
  <register offset="0xf8004430" type="rw" uniqueid="ps7_dmac0_ns_LC1_1">
    <name>LC1_1</name>
    <desc>loop counter 1 for DMA channel 1</desc>
  </register>
  <register offset="0xf8004440" type="rw" uniqueid="ps7_dmac0_ns_SAR2">
    <name>SAR2</name>
    <desc>source address for DMA channel 2</desc>
  </register>
  <register offset="0xf8004444" type="rw" uniqueid="ps7_dmac0_ns_DAR2">
    <name>DAR2</name>
    <desc>destination address for DMA channel 2</desc>
  </register>
  <register offset="0xf8004448" type="rw" uniqueid="ps7_dmac0_ns_CCR2">
    <name>CCR2</name>
    <desc>channel control for DMA channel 2</desc>
  </register>
  <register offset="0xf800444c" type="rw" uniqueid="ps7_dmac0_ns_LC0_2">
    <name>LC0_2</name>
    <desc>loop counter 0 for DMA channel 2</desc>
  </register>
  <register offset="0xf8004450" type="rw" uniqueid="ps7_dmac0_ns_LC1_2">
    <name>LC1_2</name>
    <desc>loop counter 1 for DMA channel 2</desc>
  </register>
  <register offset="0xf8004460" type="rw" uniqueid="ps7_dmac0_ns_SAR3">
    <name>SAR3</name>
    <desc>source address for DMA channel 3</desc>
  </register>
  <register offset="0xf8004464" type="rw" uniqueid="ps7_dmac0_ns_DAR3">
    <name>DAR3</name>
    <desc>destination address for DMA channel 3</desc>
  </register>
  <register offset="0xf8004468" type="rw" uniqueid="ps7_dmac0_ns_CCR3">
    <name>CCR3</name>
    <desc>channel control for DMA channel 3</desc>
  </register>
  <register offset="0xf800446c" type="rw" uniqueid="ps7_dmac0_ns_LC0_3">
    <name>LC0_3</name>
    <desc>loop counter 0 for DMA channel 3</desc>
  </register>
  <register offset="0xf8004470" type="rw" uniqueid="ps7_dmac0_ns_LC1_3">
    <name>LC1_3</name>
    <desc>loop counter 1 for DMA channel 3</desc>
  </register>
  <register offset="0xf8004480" type="rw" uniqueid="ps7_dmac0_ns_SAR4">
    <name>SAR4</name>
    <desc>source address for DMA channel 4</desc>
  </register>
  <register offset="0xf8004484" type="rw" uniqueid="ps7_dmac0_ns_DAR4">
    <name>DAR4</name>
    <desc>destination address for DMA channel 4</desc>
  </register>
  <register offset="0xf8004488" type="rw" uniqueid="ps7_dmac0_ns_CCR4">
    <name>CCR4</name>
    <desc>channel control for DMA channel 4</desc>
  </register>
  <register offset="0xf800448c" type="rw" uniqueid="ps7_dmac0_ns_LC0_4">
    <name>LC0_4</name>
    <desc>loop counter 0 for DMA channel 4</desc>
  </register>
  <register offset="0xf8004490" type="rw" uniqueid="ps7_dmac0_ns_LC1_4">
    <name>LC1_4</name>
    <desc>loop counter 1 for DMA channel 4</desc>
  </register>
  <register offset="0xf80044a0" type="rw" uniqueid="ps7_dmac0_ns_SAR5">
    <name>SAR5</name>
    <desc>source address for DMA channel 5</desc>
  </register>
  <register offset="0xf80044a4" type="rw" uniqueid="ps7_dmac0_ns_DAR5">
    <name>DAR5</name>
    <desc>destination address for DMA channel 5</desc>
  </register>
  <register offset="0xf80044a8" type="rw" uniqueid="ps7_dmac0_ns_CCR5">
    <name>CCR5</name>
    <desc>channel control for DMA channel 5</desc>
  </register>
  <register offset="0xf80044ac" type="rw" uniqueid="ps7_dmac0_ns_LC0_5">
    <name>LC0_5</name>
    <desc>loop counter 0 for DMA channel 5</desc>
  </register>
  <register offset="0xf80044b0" type="rw" uniqueid="ps7_dmac0_ns_LC1_5">
    <name>LC1_5</name>
    <desc>loop counter 1 for DMA channel 5</desc>
  </register>
  <register offset="0xf80044c0" type="rw" uniqueid="ps7_dmac0_ns_SAR6">
    <name>SAR6</name>
    <desc>source address for DMA channel 6</desc>
  </register>
  <register offset="0xf80044c4" type="rw" uniqueid="ps7_dmac0_ns_DAR6">
    <name>DAR6</name>
    <desc>destination address for DMA channel 6</desc>
  </register>
  <register offset="0xf80044c8" type="rw" uniqueid="ps7_dmac0_ns_CCR6">
    <name>CCR6</name>
    <desc>channel control for DMA channel 6</desc>
  </register>
  <register offset="0xf80044cc" type="rw" uniqueid="ps7_dmac0_ns_LC0_6">
    <name>LC0_6</name>
    <desc>loop counter 0 for DMA channel 6</desc>
  </register>
  <register offset="0xf80044d0" type="rw" uniqueid="ps7_dmac0_ns_LC1_6">
    <name>LC1_6</name>
    <desc>loop counter 1 for DMA channel 6</desc>
  </register>
  <register offset="0xf80044e0" type="rw" uniqueid="ps7_dmac0_ns_SAR7">
    <name>SAR7</name>
    <desc>source address for DMA channel 7</desc>
  </register>
  <register offset="0xf80044e4" type="rw" uniqueid="ps7_dmac0_ns_DAR7">
    <name>DAR7</name>
    <desc>destination address for DMA channel 7</desc>
  </register>
  <register offset="0xf80044e8" type="rw" uniqueid="ps7_dmac0_ns_CCR7">
    <name>CCR7</name>
    <desc>channel control for DMA channel 7</desc>
  </register>
  <register offset="0xf80044ec" type="rw" uniqueid="ps7_dmac0_ns_LC0_7">
    <name>LC0_7</name>
    <desc>loop counter 0 for DMA channel 7</desc>
  </register>
  <register offset="0xf80044f0" type="rw" uniqueid="ps7_dmac0_ns_LC1_7">
    <name>LC1_7</name>
    <desc>loop counter 1 for DMA channel 7</desc>
  </register>
  <register offset="0xf8004d00" type="rw" uniqueid="ps7_dmac0_ns_DBGSTATUS">
    <name>DBGSTATUS</name>
    <desc>Debug Status Register</desc>
  </register>
  <register offset="0xf8004d04" type="rw" uniqueid="ps7_dmac0_ns_DBGCMD">
    <name>DBGCMD</name>
    <desc>Debug Command Register</desc>
  </register>
  <register offset="0xf8004d08" type="rw" uniqueid="ps7_dmac0_ns_DBGINST0">
    <name>DBGINST0</name>
    <desc>debug instruction 0 register, Controls the debug instruction, channel, and thread information for the
DMAC.</desc>
  </register>
  <register offset="0xf8004d0c" type="rw" uniqueid="ps7_dmac0_ns_DBGINST1">
    <name>DBGINST1</name>
    <desc>debug instruction 0 register, Controls the upper bytes of the debug instruction for the DMAC</desc>
  </register>
  <register offset="0xf8004e00" type="rw" uniqueid="ps7_dmac0_ns_CR0">
    <name>CR0</name>
    <desc>Configuration Register 0, Provides the status of the tie-off control signals.</desc>
  </register>
  <register offset="0xf8004e04" type="rw" uniqueid="ps7_dmac0_ns_CR1">
    <name>CR1</name>
    <desc>Configuration Register 1, Provides information about the instruction cache configuration.</desc>
  </register>
  <register offset="0xf8004e08" type="rw" uniqueid="ps7_dmac0_ns_CR2">
    <name>CR2</name>
    <desc>Configuration Register 2, Provides the value of the boot address that boot_addr[31:0] configures.</desc>
  </register>
  <register offset="0xf8004e0c" type="rw" uniqueid="ps7_dmac0_ns_CR3">
    <name>CR3</name>
    <desc>Configuration Register 3, Provides the security state of the event-interrupt resources that are
initialized when the DMAC exits from reset.</desc>
  </register>
  <register offset="0xf8004e10" type="rw" uniqueid="ps7_dmac0_ns_CR4">
    <name>CR4</name>
    <desc>Configuration Register 4, Provides the security state of the peripheral request interfaces that is
initialized when the DMAC exits from reset.</desc>
  </register>
  <register offset="0xf8004e14" type="rw" uniqueid="ps7_dmac0_ns_CRD">
    <name>CRD</name>
    <desc>DMA configuration register, Provides information about the configuration of the data buffer, data
width, and read and write issuing capability of the DMAC.</desc>
  </register>
  <register offset="0xf8004e80" type="rw" uniqueid="ps7_dmac0_ns_WD">
    <name>WD</name>
    <desc>watch dog register, control the watch dog behavior</desc>
  </register>
  <register offset="0xf8004fe0" type="rw" uniqueid="ps7_dmac0_ns_periph_id_0">
    <name>periph_id_0</name>
    <desc>peripheral idenfication register 0, Provides information about the configuration and version of the peripheral</desc>
  </register>
  <register offset="0xf8004fe4" type="rw" uniqueid="ps7_dmac0_ns_periph_id_1">
    <name>periph_id_1</name>
    <desc>peripheral idenfication register 1, The periph_id_1 Register is hard-coded and the fields in the register control the reset value.</desc>
  </register>
  <register offset="0xf8004fe8" type="rw" uniqueid="ps7_dmac0_ns_periph_id_2">
    <name>periph_id_2</name>
    <desc>peripheral idenfication register 2, The periph_id_2 Register is hard-coded and the fields in the register control the reset value.</desc>
  </register>
  <register offset="0xf8004fec" type="rw" uniqueid="ps7_dmac0_ns_periph_id_3">
    <name>periph_id_3</name>
    <desc>peripheral idenfication register 3, Provides information about the configuration and version of the peripheral</desc>
  </register>
  <register offset="0xf8004ff0" type="rw" uniqueid="ps7_dmac0_ns_pcell_id_0">
    <name>pcell_id_0</name>
    <desc>component idenfication register 0, When concatenated, these four registers return 0xB105F00D.</desc>
  </register>
  <register offset="0xf8004ff4" type="rw" uniqueid="ps7_dmac0_ns_pcell_id_1">
    <name>pcell_id_1</name>
    <desc>component idenfication register 0, When concatenated, these four registers return 0xB105F00D.</desc>
  </register>
  <register offset="0xf8004ff8" type="rw" uniqueid="ps7_dmac0_ns_pcell_id_2">
    <name>pcell_id_2</name>
    <desc>component idenfication register 0, When concatenated, these four registers return 0xB105F00D.</desc>
  </register>
  <register offset="0xf8004ffc" type="rw" uniqueid="ps7_dmac0_ns_pcell_id_3">
    <name>pcell_id_3</name>
    <desc>component idenfication register 0, When concatenated, these four registers return 0xB105F00D.</desc>
  </register>
  <register offset="0xf8003000" type="rw" uniqueid="ps7_dmac0_s_DSR">
    <name>DSR</name>
    <desc>DMA manager status register</desc>
  </register>
  <register offset="0xf8003004" type="rw" uniqueid="ps7_dmac0_s_DPC">
    <name>DPC</name>
    <desc>DMA Program Counter Register</desc>
  </register>
  <register offset="0xf8003020" type="rw" uniqueid="ps7_dmac0_s_INTEN">
    <name>INTEN</name>
    <desc>Interrupt enable register</desc>
  </register>
  <register offset="0xf8003024" type="rw" uniqueid="ps7_dmac0_s_INT_EVENT_RIS">
    <name>INT_EVENT_RIS</name>
    <desc>Event interrupt raw status register</desc>
  </register>
  <register offset="0xf8003028" type="rw" uniqueid="ps7_dmac0_s_INTMIS">
    <name>INTMIS</name>
    <desc>Interrupt Status Register</desc>
  </register>
  <register offset="0xf800302c" type="rw" uniqueid="ps7_dmac0_s_INTCLR">
    <name>INTCLR</name>
    <desc>Interrupt Clear Register</desc>
  </register>
  <register offset="0xf8003030" type="rw" uniqueid="ps7_dmac0_s_FSRD">
    <name>FSRD</name>
    <desc>Fault Status DMA Manager Register</desc>
  </register>
  <register offset="0xf8003034" type="rw" uniqueid="ps7_dmac0_s_FSRC">
    <name>FSRC</name>
    <desc>Fault Status DMA Channel Register</desc>
  </register>
  <register offset="0xf8003038" type="rw" uniqueid="ps7_dmac0_s_FTRD">
    <name>FTRD</name>
    <desc>Fault Type DMA Manager Register</desc>
  </register>
  <register offset="0xf8003040" type="rw" uniqueid="ps7_dmac0_s_FTR0">
    <name>FTR0</name>
    <desc>Default type for DMA channel 0</desc>
  </register>
  <register offset="0xf8003044" type="rw" uniqueid="ps7_dmac0_s_FTR1">
    <name>FTR1</name>
    <desc>Default type for DMA channel 1</desc>
  </register>
  <register offset="0xf8003048" type="rw" uniqueid="ps7_dmac0_s_FTR2">
    <name>FTR2</name>
    <desc>Default type for DMA channel 2</desc>
  </register>
  <register offset="0xf800304c" type="rw" uniqueid="ps7_dmac0_s_FTR3">
    <name>FTR3</name>
    <desc>Default type for DMA channel 3</desc>
  </register>
  <register offset="0xf8003050" type="rw" uniqueid="ps7_dmac0_s_FTR4">
    <name>FTR4</name>
    <desc>Default type for DMA channel 4</desc>
  </register>
  <register offset="0xf8003054" type="rw" uniqueid="ps7_dmac0_s_FTR5">
    <name>FTR5</name>
    <desc>Default type for DMA channel 5</desc>
  </register>
  <register offset="0xf8003058" type="rw" uniqueid="ps7_dmac0_s_FTR6">
    <name>FTR6</name>
    <desc>Default type for DMA channel 6</desc>
  </register>
  <register offset="0xf800305c" type="rw" uniqueid="ps7_dmac0_s_FTR7">
    <name>FTR7</name>
    <desc>Default type for DMA channel 7</desc>
  </register>
  <register offset="0xf8003100" type="rw" uniqueid="ps7_dmac0_s_CSR0">
    <name>CSR0</name>
    <desc>Channel status for DMA channel 0</desc>
  </register>
  <register offset="0xf8003104" type="rw" uniqueid="ps7_dmac0_s_CPC0">
    <name>CPC0</name>
    <desc>Channel PC for DMA channel 0</desc>
  </register>
  <register offset="0xf8003108" type="rw" uniqueid="ps7_dmac0_s_CSR1">
    <name>CSR1</name>
    <desc>Channel status for DMA channel 1</desc>
  </register>
  <register offset="0xf800310c" type="rw" uniqueid="ps7_dmac0_s_CPC1">
    <name>CPC1</name>
    <desc>Channel PC for DMA channel 1</desc>
  </register>
  <register offset="0xf8003110" type="rw" uniqueid="ps7_dmac0_s_CSR2">
    <name>CSR2</name>
    <desc>Channel status for DMA channel 2</desc>
  </register>
  <register offset="0xf8003114" type="rw" uniqueid="ps7_dmac0_s_CPC2">
    <name>CPC2</name>
    <desc>Channel PC for DMA channel 2</desc>
  </register>
  <register offset="0xf8003118" type="rw" uniqueid="ps7_dmac0_s_CSR3">
    <name>CSR3</name>
    <desc>Channel status for DMA channel 3</desc>
  </register>
  <register offset="0xf800311c" type="rw" uniqueid="ps7_dmac0_s_CPC3">
    <name>CPC3</name>
    <desc>Channel PC for DMA channel 3</desc>
  </register>
  <register offset="0xf8003120" type="rw" uniqueid="ps7_dmac0_s_CSR4">
    <name>CSR4</name>
    <desc>Channel status for DMA channel 4</desc>
  </register>
  <register offset="0xf8003124" type="rw" uniqueid="ps7_dmac0_s_CPC4">
    <name>CPC4</name>
    <desc>Channel PC for DMA channel 4</desc>
  </register>
  <register offset="0xf8003128" type="rw" uniqueid="ps7_dmac0_s_CSR5">
    <name>CSR5</name>
    <desc>Channel status for DMA channel 5</desc>
  </register>
  <register offset="0xf800312c" type="rw" uniqueid="ps7_dmac0_s_CPC5">
    <name>CPC5</name>
    <desc>Channel PC for DMA channel 5</desc>
  </register>
  <register offset="0xf8003130" type="rw" uniqueid="ps7_dmac0_s_CSR6">
    <name>CSR6</name>
    <desc>Channel status for DMA channel 6</desc>
  </register>
  <register offset="0xf8003134" type="rw" uniqueid="ps7_dmac0_s_CPC6">
    <name>CPC6</name>
    <desc>Channel PC for DMA channel 6</desc>
  </register>
  <register offset="0xf8003138" type="rw" uniqueid="ps7_dmac0_s_CSR7">
    <name>CSR7</name>
    <desc>Channel status for DMA channel 7</desc>
  </register>
  <register offset="0xf800313c" type="rw" uniqueid="ps7_dmac0_s_CPC7">
    <name>CPC7</name>
    <desc>Channel PC for DMA channel 7</desc>
  </register>
  <register offset="0xf8003400" type="rw" uniqueid="ps7_dmac0_s_SAR0">
    <name>SAR0</name>
    <desc>source address for DMA channel 0</desc>
  </register>
  <register offset="0xf8003404" type="rw" uniqueid="ps7_dmac0_s_DAR0">
    <name>DAR0</name>
    <desc>destination address for DMA channel 0</desc>
  </register>
  <register offset="0xf8003408" type="rw" uniqueid="ps7_dmac0_s_CCR0">
    <name>CCR0</name>
    <desc>channel control for DMA channel 0</desc>
  </register>
  <register offset="0xf800340c" type="rw" uniqueid="ps7_dmac0_s_LC0_0">
    <name>LC0_0</name>
    <desc>loop counter 0 for DMA channel 0</desc>
  </register>
  <register offset="0xf8003410" type="rw" uniqueid="ps7_dmac0_s_LC1_0">
    <name>LC1_0</name>
    <desc>loop counter 1 for DMA channel 0</desc>
  </register>
  <register offset="0xf8003420" type="rw" uniqueid="ps7_dmac0_s_SAR1">
    <name>SAR1</name>
    <desc>source address for DMA channel 1</desc>
  </register>
  <register offset="0xf8003424" type="rw" uniqueid="ps7_dmac0_s_DAR1">
    <name>DAR1</name>
    <desc>destination address for DMA channel 1</desc>
  </register>
  <register offset="0xf8003428" type="rw" uniqueid="ps7_dmac0_s_CCR1">
    <name>CCR1</name>
    <desc>channel control for DMA channel 1</desc>
  </register>
  <register offset="0xf800342c" type="rw" uniqueid="ps7_dmac0_s_LC0_1">
    <name>LC0_1</name>
    <desc>loop counter 0 for DMA channel 1</desc>
  </register>
  <register offset="0xf8003430" type="rw" uniqueid="ps7_dmac0_s_LC1_1">
    <name>LC1_1</name>
    <desc>loop counter 1 for DMA channel 1</desc>
  </register>
  <register offset="0xf8003440" type="rw" uniqueid="ps7_dmac0_s_SAR2">
    <name>SAR2</name>
    <desc>source address for DMA channel 2</desc>
  </register>
  <register offset="0xf8003444" type="rw" uniqueid="ps7_dmac0_s_DAR2">
    <name>DAR2</name>
    <desc>destination address for DMA channel 2</desc>
  </register>
  <register offset="0xf8003448" type="rw" uniqueid="ps7_dmac0_s_CCR2">
    <name>CCR2</name>
    <desc>channel control for DMA channel 2</desc>
  </register>
  <register offset="0xf800344c" type="rw" uniqueid="ps7_dmac0_s_LC0_2">
    <name>LC0_2</name>
    <desc>loop counter 0 for DMA channel 2</desc>
  </register>
  <register offset="0xf8003450" type="rw" uniqueid="ps7_dmac0_s_LC1_2">
    <name>LC1_2</name>
    <desc>loop counter 1 for DMA channel 2</desc>
  </register>
  <register offset="0xf8003460" type="rw" uniqueid="ps7_dmac0_s_SAR3">
    <name>SAR3</name>
    <desc>source address for DMA channel 3</desc>
  </register>
  <register offset="0xf8003464" type="rw" uniqueid="ps7_dmac0_s_DAR3">
    <name>DAR3</name>
    <desc>destination address for DMA channel 3</desc>
  </register>
  <register offset="0xf8003468" type="rw" uniqueid="ps7_dmac0_s_CCR3">
    <name>CCR3</name>
    <desc>channel control for DMA channel 3</desc>
  </register>
  <register offset="0xf800346c" type="rw" uniqueid="ps7_dmac0_s_LC0_3">
    <name>LC0_3</name>
    <desc>loop counter 0 for DMA channel 3</desc>
  </register>
  <register offset="0xf8003470" type="rw" uniqueid="ps7_dmac0_s_LC1_3">
    <name>LC1_3</name>
    <desc>loop counter 1 for DMA channel 3</desc>
  </register>
  <register offset="0xf8003480" type="rw" uniqueid="ps7_dmac0_s_SAR4">
    <name>SAR4</name>
    <desc>source address for DMA channel 4</desc>
  </register>
  <register offset="0xf8003484" type="rw" uniqueid="ps7_dmac0_s_DAR4">
    <name>DAR4</name>
    <desc>destination address for DMA channel 4</desc>
  </register>
  <register offset="0xf8003488" type="rw" uniqueid="ps7_dmac0_s_CCR4">
    <name>CCR4</name>
    <desc>channel control for DMA channel 4</desc>
  </register>
  <register offset="0xf800348c" type="rw" uniqueid="ps7_dmac0_s_LC0_4">
    <name>LC0_4</name>
    <desc>loop counter 0 for DMA channel 4</desc>
  </register>
  <register offset="0xf8003490" type="rw" uniqueid="ps7_dmac0_s_LC1_4">
    <name>LC1_4</name>
    <desc>loop counter 1 for DMA channel 4</desc>
  </register>
  <register offset="0xf80034a0" type="rw" uniqueid="ps7_dmac0_s_SAR5">
    <name>SAR5</name>
    <desc>source address for DMA channel 5</desc>
  </register>
  <register offset="0xf80034a4" type="rw" uniqueid="ps7_dmac0_s_DAR5">
    <name>DAR5</name>
    <desc>destination address for DMA channel 5</desc>
  </register>
  <register offset="0xf80034a8" type="rw" uniqueid="ps7_dmac0_s_CCR5">
    <name>CCR5</name>
    <desc>channel control for DMA channel 5</desc>
  </register>
  <register offset="0xf80034ac" type="rw" uniqueid="ps7_dmac0_s_LC0_5">
    <name>LC0_5</name>
    <desc>loop counter 0 for DMA channel 5</desc>
  </register>
  <register offset="0xf80034b0" type="rw" uniqueid="ps7_dmac0_s_LC1_5">
    <name>LC1_5</name>
    <desc>loop counter 1 for DMA channel 5</desc>
  </register>
  <register offset="0xf80034c0" type="rw" uniqueid="ps7_dmac0_s_SAR6">
    <name>SAR6</name>
    <desc>source address for DMA channel 6</desc>
  </register>
  <register offset="0xf80034c4" type="rw" uniqueid="ps7_dmac0_s_DAR6">
    <name>DAR6</name>
    <desc>destination address for DMA channel 6</desc>
  </register>
  <register offset="0xf80034c8" type="rw" uniqueid="ps7_dmac0_s_CCR6">
    <name>CCR6</name>
    <desc>channel control for DMA channel 6</desc>
  </register>
  <register offset="0xf80034cc" type="rw" uniqueid="ps7_dmac0_s_LC0_6">
    <name>LC0_6</name>
    <desc>loop counter 0 for DMA channel 6</desc>
  </register>
  <register offset="0xf80034d0" type="rw" uniqueid="ps7_dmac0_s_LC1_6">
    <name>LC1_6</name>
    <desc>loop counter 1 for DMA channel 6</desc>
  </register>
  <register offset="0xf80034e0" type="rw" uniqueid="ps7_dmac0_s_SAR7">
    <name>SAR7</name>
    <desc>source address for DMA channel 7</desc>
  </register>
  <register offset="0xf80034e4" type="rw" uniqueid="ps7_dmac0_s_DAR7">
    <name>DAR7</name>
    <desc>destination address for DMA channel 7</desc>
  </register>
  <register offset="0xf80034e8" type="rw" uniqueid="ps7_dmac0_s_CCR7">
    <name>CCR7</name>
    <desc>channel control for DMA channel 7</desc>
  </register>
  <register offset="0xf80034ec" type="rw" uniqueid="ps7_dmac0_s_LC0_7">
    <name>LC0_7</name>
    <desc>loop counter 0 for DMA channel 7</desc>
  </register>
  <register offset="0xf80034f0" type="rw" uniqueid="ps7_dmac0_s_LC1_7">
    <name>LC1_7</name>
    <desc>loop counter 1 for DMA channel 7</desc>
  </register>
  <register offset="0xf8003d00" type="rw" uniqueid="ps7_dmac0_s_DBGSTATUS">
    <name>DBGSTATUS</name>
    <desc>Debug Status Register</desc>
  </register>
  <register offset="0xf8003d04" type="rw" uniqueid="ps7_dmac0_s_DBGCMD">
    <name>DBGCMD</name>
    <desc>Debug Command Register</desc>
  </register>
  <register offset="0xf8003d08" type="rw" uniqueid="ps7_dmac0_s_DBGINST0">
    <name>DBGINST0</name>
    <desc>debug instruction 0 register, Controls the debug instruction, channel, and thread information for the
DMAC.</desc>
  </register>
  <register offset="0xf8003d0c" type="rw" uniqueid="ps7_dmac0_s_DBGINST1">
    <name>DBGINST1</name>
    <desc>debug instruction 0 register, Controls the upper bytes of the debug instruction for the DMAC</desc>
  </register>
  <register offset="0xf8003e00" type="rw" uniqueid="ps7_dmac0_s_CR0">
    <name>CR0</name>
    <desc>Configuration Register 0, Provides the status of the tie-off control signals.</desc>
  </register>
  <register offset="0xf8003e04" type="rw" uniqueid="ps7_dmac0_s_CR1">
    <name>CR1</name>
    <desc>Configuration Register 1, Provides information about the instruction cache configuration.</desc>
  </register>
  <register offset="0xf8003e08" type="rw" uniqueid="ps7_dmac0_s_CR2">
    <name>CR2</name>
    <desc>Configuration Register 2, Provides the value of the boot address that boot_addr[31:0] configures.</desc>
  </register>
  <register offset="0xf8003e0c" type="rw" uniqueid="ps7_dmac0_s_CR3">
    <name>CR3</name>
    <desc>Configuration Register 3, Provides the security state of the event-interrupt resources that are
initialized when the DMAC exits from reset.</desc>
  </register>
  <register offset="0xf8003e10" type="rw" uniqueid="ps7_dmac0_s_CR4">
    <name>CR4</name>
    <desc>Configuration Register 4, Provides the security state of the peripheral request interfaces that is
initialized when the DMAC exits from reset.</desc>
  </register>
  <register offset="0xf8003e14" type="rw" uniqueid="ps7_dmac0_s_CRD">
    <name>CRD</name>
    <desc>DMA configuration register, Provides information about the configuration of the data buffer, data
width, and read and write issuing capability of the DMAC.</desc>
  </register>
  <register offset="0xf8003e80" type="rw" uniqueid="ps7_dmac0_s_WD">
    <name>WD</name>
    <desc>watch dog register, control the watch dog behavior</desc>
  </register>
  <register offset="0xf8003fe0" type="rw" uniqueid="ps7_dmac0_s_periph_id_0">
    <name>periph_id_0</name>
    <desc>peripheral idenfication register 0, Provides information about the configuration and version of the peripheral</desc>
  </register>
  <register offset="0xf8003fe4" type="rw" uniqueid="ps7_dmac0_s_periph_id_1">
    <name>periph_id_1</name>
    <desc>peripheral idenfication register 1, The periph_id_1 Register is hard-coded and the fields in the register control the reset value.</desc>
  </register>
  <register offset="0xf8003fe8" type="rw" uniqueid="ps7_dmac0_s_periph_id_2">
    <name>periph_id_2</name>
    <desc>peripheral idenfication register 2, The periph_id_2 Register is hard-coded and the fields in the register control the reset value.</desc>
  </register>
  <register offset="0xf8003fec" type="rw" uniqueid="ps7_dmac0_s_periph_id_3">
    <name>periph_id_3</name>
    <desc>peripheral idenfication register 3, Provides information about the configuration and version of the peripheral</desc>
  </register>
  <register offset="0xf8003ff0" type="rw" uniqueid="ps7_dmac0_s_pcell_id_0">
    <name>pcell_id_0</name>
    <desc>component idenfication register 0, When concatenated, these four registers return 0xB105F00D.</desc>
  </register>
  <register offset="0xf8003ff4" type="rw" uniqueid="ps7_dmac0_s_pcell_id_1">
    <name>pcell_id_1</name>
    <desc>component idenfication register 0, When concatenated, these four registers return 0xB105F00D.</desc>
  </register>
  <register offset="0xf8003ff8" type="rw" uniqueid="ps7_dmac0_s_pcell_id_2">
    <name>pcell_id_2</name>
    <desc>component idenfication register 0, When concatenated, these four registers return 0xB105F00D.</desc>
  </register>
  <register offset="0xf8003ffc" type="rw" uniqueid="ps7_dmac0_s_pcell_id_3">
    <name>pcell_id_3</name>
    <desc>component idenfication register 0, When concatenated, these four registers return 0xB105F00D.</desc>
  </register>
  <register offset="0xf8002000" type="rw" uniqueid="ps7_ttc1_Clock_Control_1">
    <name>Clock_Control_1</name>
    <desc>Clock Control register</desc>
  </register>
  <register offset="0xf8002004" type="rw" uniqueid="ps7_ttc1_Clock_Control_2">
    <name>Clock_Control_2</name>
    <desc>Clock Control register</desc>
  </register>
  <register offset="0xf8002008" type="rw" uniqueid="ps7_ttc1_Clock_Control_3">
    <name>Clock_Control_3</name>
    <desc>Clock Control register</desc>
  </register>
  <register offset="0xf800200c" type="rw" uniqueid="ps7_ttc1_Counter_Control_1">
    <name>Counter_Control_1</name>
    <desc>Operational mode and reset</desc>
  </register>
  <register offset="0xf8002010" type="rw" uniqueid="ps7_ttc1_Counter_Control_2">
    <name>Counter_Control_2</name>
    <desc>Operational mode and reset</desc>
  </register>
  <register offset="0xf8002014" type="rw" uniqueid="ps7_ttc1_Counter_Control_3">
    <name>Counter_Control_3</name>
    <desc>Operational mode and reset</desc>
  </register>
  <register offset="0xf8002018" type="ro" uniqueid="ps7_ttc1_Counter_Value_1">
    <name>Counter_Value_1</name>
    <desc>Current counter value</desc>
  </register>
  <register offset="0xf800201c" type="ro" uniqueid="ps7_ttc1_Counter_Value_2">
    <name>Counter_Value_2</name>
    <desc>Current counter value</desc>
  </register>
  <register offset="0xf8002020" type="ro" uniqueid="ps7_ttc1_Counter_Value_3">
    <name>Counter_Value_3</name>
    <desc>Current counter value</desc>
  </register>
  <register offset="0xf8002024" type="rw" uniqueid="ps7_ttc1_Interval_Counter_1">
    <name>Interval_Counter_1</name>
    <desc>Interval value</desc>
  </register>
  <register offset="0xf8002028" type="rw" uniqueid="ps7_ttc1_Interval_Counter_2">
    <name>Interval_Counter_2</name>
    <desc>Interval value</desc>
  </register>
  <register offset="0xf800202c" type="rw" uniqueid="ps7_ttc1_Interval_Counter_3">
    <name>Interval_Counter_3</name>
    <desc>Interval value</desc>
  </register>
  <register offset="0xf8002030" type="rw" uniqueid="ps7_ttc1_Match_1_Counter_1">
    <name>Match_1_Counter_1</name>
    <desc>Match value</desc>
  </register>
  <register offset="0xf8002034" type="rw" uniqueid="ps7_ttc1_Match_1_Counter_2">
    <name>Match_1_Counter_2</name>
    <desc>Match value</desc>
  </register>
  <register offset="0xf8002038" type="rw" uniqueid="ps7_ttc1_Match_1_Counter_3">
    <name>Match_1_Counter_3</name>
    <desc>Match value</desc>
  </register>
  <register offset="0xf800203c" type="rw" uniqueid="ps7_ttc1_Match_2_Counter_1">
    <name>Match_2_Counter_1</name>
    <desc>Match value</desc>
  </register>
  <register offset="0xf8002040" type="rw" uniqueid="ps7_ttc1_Match_2_Counter_2">
    <name>Match_2_Counter_2</name>
    <desc>Match value</desc>
  </register>
  <register offset="0xf8002044" type="rw" uniqueid="ps7_ttc1_Match_2_Counter_3">
    <name>Match_2_Counter_3</name>
    <desc>Match value</desc>
  </register>
  <register offset="0xf8002048" type="rw" uniqueid="ps7_ttc1_Match_3_Counter_1">
    <name>Match_3_Counter_1</name>
    <desc>Match value</desc>
  </register>
  <register offset="0xf800204c" type="rw" uniqueid="ps7_ttc1_Match_3_Counter_2">
    <name>Match_3_Counter_2</name>
    <desc>Match value</desc>
  </register>
  <register offset="0xf8002050" type="rw" uniqueid="ps7_ttc1_Match_3_Counter_3">
    <name>Match_3_Counter_3</name>
    <desc>Match value</desc>
  </register>
  <register offset="0xf8002054" type="ro" uniqueid="ps7_ttc1_Interrupt_Register_1">
    <name>Interrupt_Register_1</name>
    <desc>Counter 1 Interval, Match, Overflow
and Event interrupts</desc>
  </register>
  <register offset="0xf8002058" type="ro" uniqueid="ps7_ttc1_Interrupt_Register_2">
    <name>Interrupt_Register_2</name>
    <desc>Counter 2 Interval, Match, Overflow and Event interrupts</desc>
  </register>
  <register offset="0xf800205c" type="ro" uniqueid="ps7_ttc1_Interrupt_Register_3">
    <name>Interrupt_Register_3</name>
    <desc>Counter 3 Interval, Match, Overflow and Event interrupts</desc>
  </register>
  <register offset="0xf8002060" type="rw" uniqueid="ps7_ttc1_Interrupt_Enable_1">
    <name>Interrupt_Enable_1</name>
    <desc>ANDed with corresponding Interrupt
Register</desc>
  </register>
  <register offset="0xf8002064" type="rw" uniqueid="ps7_ttc1_Interrupt_Enable_2">
    <name>Interrupt_Enable_2</name>
    <desc>ANDed with corresponding Interrupt
Register</desc>
  </register>
  <register offset="0xf8002068" type="rw" uniqueid="ps7_ttc1_Interrupt_Enable_3">
    <name>Interrupt_Enable_3</name>
    <desc>ANDed with corresponding Interrupt
Register</desc>
  </register>
  <register offset="0xf800206c" type="rw" uniqueid="ps7_ttc1_Event_Control_Timer_1">
    <name>Event_Control_Timer_1</name>
    <desc>Enable, pulse and overflow</desc>
  </register>
  <register offset="0xf8002070" type="rw" uniqueid="ps7_ttc1_Event_Control_Timer_2">
    <name>Event_Control_Timer_2</name>
    <desc>Enable, pulse and overflow</desc>
  </register>
  <register offset="0xf8002074" type="rw" uniqueid="ps7_ttc1_Event_Control_Timer_3">
    <name>Event_Control_Timer_3</name>
    <desc>Enable, pulse and overflow</desc>
  </register>
  <register offset="0xf8002078" type="ro" uniqueid="ps7_ttc1_Event_Register_1">
    <name>Event_Register_1</name>
    <desc>pclk cycle count for event</desc>
  </register>
  <register offset="0xf800207c" type="ro" uniqueid="ps7_ttc1_Event_Register_2">
    <name>Event_Register_2</name>
    <desc>pclk cycle count for event</desc>
  </register>
  <register offset="0xf8002080" type="ro" uniqueid="ps7_ttc1_Event_Register_3">
    <name>Event_Register_3</name>
    <desc>pclk cycle count for event</desc>
  </register>
  <register offset="0xf8001000" type="rw" uniqueid="ps7_ttc0_Clock_Control_1">
    <name>Clock_Control_1</name>
    <desc>Clock Control register</desc>
  </register>
  <register offset="0xf8001004" type="rw" uniqueid="ps7_ttc0_Clock_Control_2">
    <name>Clock_Control_2</name>
    <desc>Clock Control register</desc>
  </register>
  <register offset="0xf8001008" type="rw" uniqueid="ps7_ttc0_Clock_Control_3">
    <name>Clock_Control_3</name>
    <desc>Clock Control register</desc>
  </register>
  <register offset="0xf800100c" type="rw" uniqueid="ps7_ttc0_Counter_Control_1">
    <name>Counter_Control_1</name>
    <desc>Operational mode and reset</desc>
  </register>
  <register offset="0xf8001010" type="rw" uniqueid="ps7_ttc0_Counter_Control_2">
    <name>Counter_Control_2</name>
    <desc>Operational mode and reset</desc>
  </register>
  <register offset="0xf8001014" type="rw" uniqueid="ps7_ttc0_Counter_Control_3">
    <name>Counter_Control_3</name>
    <desc>Operational mode and reset</desc>
  </register>
  <register offset="0xf8001018" type="ro" uniqueid="ps7_ttc0_Counter_Value_1">
    <name>Counter_Value_1</name>
    <desc>Current counter value</desc>
  </register>
  <register offset="0xf800101c" type="ro" uniqueid="ps7_ttc0_Counter_Value_2">
    <name>Counter_Value_2</name>
    <desc>Current counter value</desc>
  </register>
  <register offset="0xf8001020" type="ro" uniqueid="ps7_ttc0_Counter_Value_3">
    <name>Counter_Value_3</name>
    <desc>Current counter value</desc>
  </register>
  <register offset="0xf8001024" type="rw" uniqueid="ps7_ttc0_Interval_Counter_1">
    <name>Interval_Counter_1</name>
    <desc>Interval value</desc>
  </register>
  <register offset="0xf8001028" type="rw" uniqueid="ps7_ttc0_Interval_Counter_2">
    <name>Interval_Counter_2</name>
    <desc>Interval value</desc>
  </register>
  <register offset="0xf800102c" type="rw" uniqueid="ps7_ttc0_Interval_Counter_3">
    <name>Interval_Counter_3</name>
    <desc>Interval value</desc>
  </register>
  <register offset="0xf8001030" type="rw" uniqueid="ps7_ttc0_Match_1_Counter_1">
    <name>Match_1_Counter_1</name>
    <desc>Match value</desc>
  </register>
  <register offset="0xf8001034" type="rw" uniqueid="ps7_ttc0_Match_1_Counter_2">
    <name>Match_1_Counter_2</name>
    <desc>Match value</desc>
  </register>
  <register offset="0xf8001038" type="rw" uniqueid="ps7_ttc0_Match_1_Counter_3">
    <name>Match_1_Counter_3</name>
    <desc>Match value</desc>
  </register>
  <register offset="0xf800103c" type="rw" uniqueid="ps7_ttc0_Match_2_Counter_1">
    <name>Match_2_Counter_1</name>
    <desc>Match value</desc>
  </register>
  <register offset="0xf8001040" type="rw" uniqueid="ps7_ttc0_Match_2_Counter_2">
    <name>Match_2_Counter_2</name>
    <desc>Match value</desc>
  </register>
  <register offset="0xf8001044" type="rw" uniqueid="ps7_ttc0_Match_2_Counter_3">
    <name>Match_2_Counter_3</name>
    <desc>Match value</desc>
  </register>
  <register offset="0xf8001048" type="rw" uniqueid="ps7_ttc0_Match_3_Counter_1">
    <name>Match_3_Counter_1</name>
    <desc>Match value</desc>
  </register>
  <register offset="0xf800104c" type="rw" uniqueid="ps7_ttc0_Match_3_Counter_2">
    <name>Match_3_Counter_2</name>
    <desc>Match value</desc>
  </register>
  <register offset="0xf8001050" type="rw" uniqueid="ps7_ttc0_Match_3_Counter_3">
    <name>Match_3_Counter_3</name>
    <desc>Match value</desc>
  </register>
  <register offset="0xf8001054" type="ro" uniqueid="ps7_ttc0_Interrupt_Register_1">
    <name>Interrupt_Register_1</name>
    <desc>Counter 1 Interval, Match, Overflow
and Event interrupts</desc>
  </register>
  <register offset="0xf8001058" type="ro" uniqueid="ps7_ttc0_Interrupt_Register_2">
    <name>Interrupt_Register_2</name>
    <desc>Counter 2 Interval, Match, Overflow and Event interrupts</desc>
  </register>
  <register offset="0xf800105c" type="ro" uniqueid="ps7_ttc0_Interrupt_Register_3">
    <name>Interrupt_Register_3</name>
    <desc>Counter 3 Interval, Match, Overflow and Event interrupts</desc>
  </register>
  <register offset="0xf8001060" type="rw" uniqueid="ps7_ttc0_Interrupt_Enable_1">
    <name>Interrupt_Enable_1</name>
    <desc>ANDed with corresponding Interrupt
Register</desc>
  </register>
  <register offset="0xf8001064" type="rw" uniqueid="ps7_ttc0_Interrupt_Enable_2">
    <name>Interrupt_Enable_2</name>
    <desc>ANDed with corresponding Interrupt
Register</desc>
  </register>
  <register offset="0xf8001068" type="rw" uniqueid="ps7_ttc0_Interrupt_Enable_3">
    <name>Interrupt_Enable_3</name>
    <desc>ANDed with corresponding Interrupt
Register</desc>
  </register>
  <register offset="0xf800106c" type="rw" uniqueid="ps7_ttc0_Event_Control_Timer_1">
    <name>Event_Control_Timer_1</name>
    <desc>Enable, pulse and overflow</desc>
  </register>
  <register offset="0xf8001070" type="rw" uniqueid="ps7_ttc0_Event_Control_Timer_2">
    <name>Event_Control_Timer_2</name>
    <desc>Enable, pulse and overflow</desc>
  </register>
  <register offset="0xf8001074" type="rw" uniqueid="ps7_ttc0_Event_Control_Timer_3">
    <name>Event_Control_Timer_3</name>
    <desc>Enable, pulse and overflow</desc>
  </register>
  <register offset="0xf8001078" type="ro" uniqueid="ps7_ttc0_Event_Register_1">
    <name>Event_Register_1</name>
    <desc>pclk cycle count for event</desc>
  </register>
  <register offset="0xf800107c" type="ro" uniqueid="ps7_ttc0_Event_Register_2">
    <name>Event_Register_2</name>
    <desc>pclk cycle count for event</desc>
  </register>
  <register offset="0xf8001080" type="ro" uniqueid="ps7_ttc0_Event_Register_3">
    <name>Event_Register_3</name>
    <desc>pclk cycle count for event</desc>
  </register>
  <register offset="0xf8006000" type="rw" uniqueid="ps7_ddrc_ddrc_ctrl">
    <name>ddrc_ctrl</name>
    <desc>DDRC Control Register</desc>
  </register>
  <register offset="0xf8006004" type="rw" uniqueid="ps7_ddrc_Two_rank_cfg">
    <name>Two_rank_cfg</name>
    <desc>Two rank configuration register</desc>
  </register>
  <register offset="0xf8006008" type="rw" uniqueid="ps7_ddrc_HPR_reg">
    <name>HPR_reg</name>
    <desc>HPR Queue control register</desc>
  </register>
  <register offset="0xf800600c" type="rw" uniqueid="ps7_ddrc_LPR_reg">
    <name>LPR_reg</name>
    <desc>LPR Queue control register</desc>
  </register>
  <register offset="0xf8006010" type="rw" uniqueid="ps7_ddrc_WR_reg">
    <name>WR_reg</name>
    <desc>WR Queue control register</desc>
  </register>
  <register offset="0xf8006014" type="rw" uniqueid="ps7_ddrc_DRAM_param_reg0">
    <name>DRAM_param_reg0</name>
    <desc>DRAM Parameters register 0</desc>
  </register>
  <register offset="0xf8006018" type="rw" uniqueid="ps7_ddrc_DRAM_param_reg1">
    <name>DRAM_param_reg1</name>
    <desc>DRAM Parameters register 1</desc>
  </register>
  <register offset="0xf800601c" type="rw" uniqueid="ps7_ddrc_DRAM_param_reg2">
    <name>DRAM_param_reg2</name>
    <desc>DRAM Parameters register 2</desc>
  </register>
  <register offset="0xf8006020" type="rw" uniqueid="ps7_ddrc_DRAM_param_reg3">
    <name>DRAM_param_reg3</name>
    <desc>DRAM Parameters register 3</desc>
  </register>
  <register offset="0xf8006024" type="rw" uniqueid="ps7_ddrc_DRAM_param_reg4">
    <name>DRAM_param_reg4</name>
    <desc>DRAM Parameters register 4</desc>
  </register>
  <register offset="0xf8006028" type="rw" uniqueid="ps7_ddrc_DRAM_init_param">
    <name>DRAM_init_param</name>
    <desc>DRAM initialization parameters register</desc>
  </register>
  <register offset="0xf800602c" type="rw" uniqueid="ps7_ddrc_DRAM_EMR_reg">
    <name>DRAM_EMR_reg</name>
    <desc>DRAM EMR2, EMR3 access register</desc>
  </register>
  <register offset="0xf8006030" type="rw" uniqueid="ps7_ddrc_DRAM_EMR_MR_reg">
    <name>DRAM_EMR_MR_reg</name>
    <desc>DRAM EMR, MR access register</desc>
  </register>
  <register offset="0xf8006034" type="rw" uniqueid="ps7_ddrc_DRAM_burst8_rdwr">
    <name>DRAM_burst8_rdwr</name>
    <desc>DRAM burst 8 read/write register</desc>
  </register>
  <register offset="0xf8006038" type="rw" uniqueid="ps7_ddrc_DRAM_disable_DQ">
    <name>DRAM_disable_DQ</name>
    <desc>DRAM Disable DQ register</desc>
  </register>
  <register offset="0xf800603c" type="rw" uniqueid="ps7_ddrc_DRAM_addr_map_bank">
    <name>DRAM_addr_map_bank</name>
    <desc>Selects the address bits used as DRAM bank address bits</desc>
  </register>
  <register offset="0xf8006040" type="rw" uniqueid="ps7_ddrc_DRAM_addr_map_col">
    <name>DRAM_addr_map_col</name>
    <desc>Selects the address bits used as DRAM column address bits</desc>
  </register>
  <register offset="0xf8006044" type="rw" uniqueid="ps7_ddrc_DRAM_addr_map_row">
    <name>DRAM_addr_map_row</name>
    <desc>Selects the address bits used as DRAM row address bits</desc>
  </register>
  <register offset="0xf8006048" type="rw" uniqueid="ps7_ddrc_DRAM_ODT_reg">
    <name>DRAM_ODT_reg</name>
    <desc>DRAM ODT register</desc>
  </register>
  <register offset="0xf800604c" type="ro" uniqueid="ps7_ddrc_phy_dbg_reg">
    <name>phy_dbg_reg</name>
    <desc>PHY debug register</desc>
  </register>
  <register offset="0xf8006050" type="rw" uniqueid="ps7_ddrc_phy_cmd_timeout_rddata_cpt">
    <name>phy_cmd_timeout_rddata_cpt</name>
    <desc>PHY command time out and read data capture FIFO register</desc>
  </register>
  <register offset="0xf8006054" type="ro" uniqueid="ps7_ddrc_mode_sts_reg">
    <name>mode_sts_reg</name>
    <desc>Controller operation mode status registers</desc>
  </register>
  <register offset="0xf8006058" type="rw" uniqueid="ps7_ddrc_DLL_calib">
    <name>DLL_calib</name>
    <desc>DLL calibration register</desc>
  </register>
  <register offset="0xf800605c" type="rw" uniqueid="ps7_ddrc_ODT_delay_hold">
    <name>ODT_delay_hold</name>
    <desc>ODT delay and ODT hold register</desc>
  </register>
  <register offset="0xf8006060" type="rw" uniqueid="ps7_ddrc_ctrl_reg1">
    <name>ctrl_reg1</name>
    <desc>Controller register 1</desc>
  </register>
  <register offset="0xf8006064" type="rw" uniqueid="ps7_ddrc_ctrl_reg2">
    <name>ctrl_reg2</name>
    <desc>Controller register 2</desc>
  </register>
  <register offset="0xf8006068" type="rw" uniqueid="ps7_ddrc_ctrl_reg3">
    <name>ctrl_reg3</name>
    <desc>Controller register 3</desc>
  </register>
  <register offset="0xf800606c" type="rw" uniqueid="ps7_ddrc_ctrl_reg4">
    <name>ctrl_reg4</name>
    <desc>Controller register 4</desc>
  </register>
  <register offset="0xf80060a0" type="rw" uniqueid="ps7_ddrc_CHE_REFRESH_TIMER01">
    <name>CHE_REFRESH_TIMER01</name>
    <desc>CHE_REFRESH_TIMER01</desc>
  </register>
  <register offset="0xf80060a4" type="rw" uniqueid="ps7_ddrc_CHE_T_ZQ">
    <name>CHE_T_ZQ</name>
    <desc>ZQ parameters register</desc>
  </register>
  <register offset="0xf80060a8" type="rw" uniqueid="ps7_ddrc_CHE_T_ZQ_Short_Interval_Reg">
    <name>CHE_T_ZQ_Short_Interval_Reg</name>
    <desc>Misc parameters register</desc>
  </register>
  <register offset="0xf80060ac" type="rw" uniqueid="ps7_ddrc_deep_pwrdwn_reg">
    <name>deep_pwrdwn_reg</name>
    <desc>Deep powerdown register</desc>
  </register>
  <register offset="0xf80060b0" type="rw" uniqueid="ps7_ddrc_reg_2c">
    <name>reg_2c</name>
    <desc>Training control register</desc>
  </register>
  <register offset="0xf80060b4" type="rw" uniqueid="ps7_ddrc_reg_2d">
    <name>reg_2d</name>
    <desc>Misc Debug register</desc>
  </register>
  <register offset="0xf80060b8" type="rw" uniqueid="ps7_ddrc_dfi_timing">
    <name>dfi_timing</name>
    <desc>DFI timing register</desc>
  </register>
  <register offset="0xf80060bc" type="rw" uniqueid="ps7_ddrc_refresh_timer_2">
    <name>refresh_timer_2</name>
    <desc>refresh parameters register</desc>
  </register>
  <register offset="0xf80060c0" type="rw" uniqueid="ps7_ddrc_nc_timing">
    <name>nc_timing</name>
    <desc>Unused register</desc>
  </register>
  <register offset="0xf80060c4" type="rw" uniqueid="ps7_ddrc_CHE_ECC_CONTROL_REG_OFFSET">
    <name>CHE_ECC_CONTROL_REG_OFFSET</name>
    <desc>ECC error clear register</desc>
  </register>
  <register offset="0xf80060c8" type="rw" uniqueid="ps7_ddrc_CHE_CORR_ECC_LOG_REG_OFFSET">
    <name>CHE_CORR_ECC_LOG_REG_OFFSET</name>
    <desc>ECC error correction register</desc>
  </register>
  <register offset="0xf80060cc" type="ro" uniqueid="ps7_ddrc_CHE_CORR_ECC_ADDR_REG_OFFSET">
    <name>CHE_CORR_ECC_ADDR_REG_OFFSET</name>
    <desc>ECC error correction address log register</desc>
  </register>
  <register offset="0xf80060d0" type="ro" uniqueid="ps7_ddrc_CHE_CORR_ECC_DATA_31_0_REG_OFFSET">
    <name>CHE_CORR_ECC_DATA_31_0_REG_OFFSET</name>
    <desc>ECC error correction data log low register</desc>
  </register>
  <register offset="0xf80060d4" type="ro" uniqueid="ps7_ddrc_CHE_CORR_ECC_DATA_63_32_REG_OFFSET">
    <name>CHE_CORR_ECC_DATA_63_32_REG_OFFSET</name>
    <desc>ECC error correction data log mid register</desc>
  </register>
  <register offset="0xf80060d8" type="ro" uniqueid="ps7_ddrc_CHE_CORR_ECC_DATA_71_64_REG_OFFSET">
    <name>CHE_CORR_ECC_DATA_71_64_REG_OFFSET</name>
    <desc>ECC error correction data log hi register</desc>
  </register>
  <register offset="0xf80060dc" type="rw" uniqueid="ps7_ddrc_CHE_UNCORR_ECC_LOG_REG_OFFSET">
    <name>CHE_UNCORR_ECC_LOG_REG_OFFSET</name>
    <desc>ECC unrecoverable error status register</desc>
  </register>
  <register offset="0xf80060e0" type="ro" uniqueid="ps7_ddrc_CHE_UNCORR_ECC_ADDR_REG_OFFSET">
    <name>CHE_UNCORR_ECC_ADDR_REG_OFFSET</name>
    <desc>ECC unrecoverable error address register</desc>
  </register>
  <register offset="0xf80060e4" type="ro" uniqueid="ps7_ddrc_CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET">
    <name>CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET</name>
    <desc>ECC unrecoverable error data low register</desc>
  </register>
  <register offset="0xf80060e8" type="ro" uniqueid="ps7_ddrc_CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET">
    <name>CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET</name>
    <desc>ECC unrecoverable error data middle register</desc>
  </register>
  <register offset="0xf80060ec" type="ro" uniqueid="ps7_ddrc_CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET">
    <name>CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET</name>
    <desc>ECC unrecoverable error data hi register</desc>
  </register>
  <register offset="0xf80060f0" type="rw" uniqueid="ps7_ddrc_CHE_ECC_STATS_REG_OFFSET">
    <name>CHE_ECC_STATS_REG_OFFSET</name>
    <desc>ECC error count register</desc>
  </register>
  <register offset="0xf80060f4" type="rw" uniqueid="ps7_ddrc_ECC_scrub">
    <name>ECC_scrub</name>
    <desc>ECC mode/scrub register</desc>
  </register>
  <register offset="0xf80060f8" type="ro" uniqueid="ps7_ddrc_CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET">
    <name>CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET</name>
    <desc>ECC data mask low register</desc>
  </register>
  <register offset="0xf80060fc" type="ro" uniqueid="ps7_ddrc_CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET">
    <name>CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET</name>
    <desc>ECC data mask hi register</desc>
  </register>
  <register offset="0xf8006114" type="rw" uniqueid="ps7_ddrc_phy_rcvr_enable">
    <name>phy_rcvr_enable</name>
    <desc>Phy receiver enable register</desc>
  </register>
  <register offset="0xf8006118" type="rw" uniqueid="ps7_ddrc_PHY_Config0">
    <name>PHY_Config</name>
    <desc>PHY configuration register for data slice 0.</desc>
  </register>
  <register offset="0xf800611c" type="rw" uniqueid="ps7_ddrc_PHY_Config1">
    <name>PHY_Config</name>
    <desc>PHY configuration register for data slice 0.</desc>
  </register>
  <register offset="0xf8006120" type="rw" uniqueid="ps7_ddrc_PHY_Config2">
    <name>PHY_Config</name>
    <desc>PHY configuration register for data slice 0.</desc>
  </register>
  <register offset="0xf8006124" type="rw" uniqueid="ps7_ddrc_PHY_Config3">
    <name>PHY_Config</name>
    <desc>PHY configuration register for data slice 0.</desc>
  </register>
  <register offset="0xf800612c" type="rw" uniqueid="ps7_ddrc_phy_init_ratio0">
    <name>phy_init_ratio</name>
    <desc>PHY init ratio register for data slice 0.</desc>
  </register>
  <register offset="0xf8006130" type="rw" uniqueid="ps7_ddrc_phy_init_ratio1">
    <name>phy_init_ratio</name>
    <desc>PHY init ratio register for data slice 0.</desc>
  </register>
  <register offset="0xf8006134" type="rw" uniqueid="ps7_ddrc_phy_init_ratio2">
    <name>phy_init_ratio</name>
    <desc>PHY init ratio register for data slice 0.</desc>
  </register>
  <register offset="0xf8006138" type="rw" uniqueid="ps7_ddrc_phy_init_ratio3">
    <name>phy_init_ratio</name>
    <desc>PHY init ratio register for data slice 0.</desc>
  </register>
  <register offset="0xf8006140" type="rw" uniqueid="ps7_ddrc_phy_rd_dqs_cfg0">
    <name>phy_rd_dqs_cfg</name>
    <desc>PHY read DQS configuration register for data slice 0.</desc>
  </register>
  <register offset="0xf8006144" type="rw" uniqueid="ps7_ddrc_phy_rd_dqs_cfg1">
    <name>phy_rd_dqs_cfg</name>
    <desc>PHY read DQS configuration register for data slice 0.</desc>
  </register>
  <register offset="0xf8006148" type="rw" uniqueid="ps7_ddrc_phy_rd_dqs_cfg2">
    <name>phy_rd_dqs_cfg</name>
    <desc>PHY read DQS configuration register for data slice 0.</desc>
  </register>
  <register offset="0xf800614c" type="rw" uniqueid="ps7_ddrc_phy_rd_dqs_cfg3">
    <name>phy_rd_dqs_cfg</name>
    <desc>PHY read DQS configuration register for data slice 0.</desc>
  </register>
  <register offset="0xf8006154" type="rw" uniqueid="ps7_ddrc_phy_wr_dqs_cfg0">
    <name>phy_wr_dqs_cfg</name>
    <desc>PHY write DQS configuration register for data slice 0.</desc>
  </register>
  <register offset="0xf8006158" type="rw" uniqueid="ps7_ddrc_phy_wr_dqs_cfg1">
    <name>phy_wr_dqs_cfg</name>
    <desc>PHY write DQS configuration register for data slice 0.</desc>
  </register>
  <register offset="0xf800615c" type="rw" uniqueid="ps7_ddrc_phy_wr_dqs_cfg2">
    <name>phy_wr_dqs_cfg</name>
    <desc>PHY write DQS configuration register for data slice 0.</desc>
  </register>
  <register offset="0xf8006160" type="rw" uniqueid="ps7_ddrc_phy_wr_dqs_cfg3">
    <name>phy_wr_dqs_cfg</name>
    <desc>PHY write DQS configuration register for data slice 0.</desc>
  </register>
  <register offset="0xf8006168" type="rw" uniqueid="ps7_ddrc_phy_we_cfg0">
    <name>phy_we_cfg</name>
    <desc>PHY fifo write enable configuration register for data slice 0.</desc>
  </register>
  <register offset="0xf800616c" type="rw" uniqueid="ps7_ddrc_phy_we_cfg1">
    <name>phy_we_cfg</name>
    <desc>PHY fifo write enable configuration register for data slice 0.</desc>
  </register>
  <register offset="0xf8006170" type="rw" uniqueid="ps7_ddrc_phy_we_cfg2">
    <name>phy_we_cfg</name>
    <desc>PHY fifo write enable configuration register for data slice 0.</desc>
  </register>
  <register offset="0xf8006174" type="rw" uniqueid="ps7_ddrc_phy_we_cfg3">
    <name>phy_we_cfg</name>
    <desc>PHY fifo write enable configuration register for data slice 0.</desc>
  </register>
  <register offset="0xf800617c" type="rw" uniqueid="ps7_ddrc_wr_data_slv0">
    <name>wr_data_slv</name>
    <desc>PHY write data slave ratio configuration register for data slice 0.</desc>
  </register>
  <register offset="0xf8006180" type="rw" uniqueid="ps7_ddrc_wr_data_slv1">
    <name>wr_data_slv</name>
    <desc>PHY write data slave ratio configuration register for data slice 0.</desc>
  </register>
  <register offset="0xf8006184" type="rw" uniqueid="ps7_ddrc_wr_data_slv2">
    <name>wr_data_slv</name>
    <desc>PHY write data slave ratio configuration register for data slice 0.</desc>
  </register>
  <register offset="0xf8006188" type="rw" uniqueid="ps7_ddrc_wr_data_slv3">
    <name>wr_data_slv</name>
    <desc>PHY write data slave ratio configuration register for data slice 0.</desc>
  </register>
  <register offset="0xf8006190" type="rw" uniqueid="ps7_ddrc_reg_64">
    <name>reg_64</name>
    <desc>Training control register (2)</desc>
  </register>
  <register offset="0xf8006194" type="rw" uniqueid="ps7_ddrc_reg_65">
    <name>reg_65</name>
    <desc>Training control register (3)</desc>
  </register>
  <register offset="0xf80061a4" type="ro" uniqueid="ps7_ddrc_reg69_6c0">
    <name>reg69_6c</name>
    <desc>Training results for data slice 0.</desc>
  </register>
  <register offset="0xf80061a8" type="ro" uniqueid="ps7_ddrc_reg69_6c1">
    <name>reg69_6c</name>
    <desc>Training results for data slice 0.</desc>
  </register>
  <register offset="0xf80061ac" type="ro" uniqueid="ps7_ddrc_reg69_6c2">
    <name>reg69_6c</name>
    <desc>Training results for data slice 0.</desc>
  </register>
  <register offset="0xf80061b0" type="ro" uniqueid="ps7_ddrc_reg69_6c3">
    <name>reg69_6c</name>
    <desc>Training results for data slice 0.</desc>
  </register>
  <register offset="0xf80061b8" type="ro" uniqueid="ps7_ddrc_reg6e_710">
    <name>reg6e_71</name>
    <desc>Training results (2) for data slice 0.</desc>
  </register>
  <register offset="0xf80061bc" type="ro" uniqueid="ps7_ddrc_reg6e_711">
    <name>reg6e_71</name>
    <desc>Training results (2) for data slice 0.</desc>
  </register>
  <register offset="0xf80061c0" type="ro" uniqueid="ps7_ddrc_reg6e_712">
    <name>reg6e_71</name>
    <desc>Training results (2) for data slice 0.</desc>
  </register>
  <register offset="0xf80061c4" type="ro" uniqueid="ps7_ddrc_reg6e_713">
    <name>reg6e_71</name>
    <desc>Training results (2) for data slice 0.</desc>
  </register>
  <register offset="0xf80061cc" type="ro" uniqueid="ps7_ddrc_phy_dll_sts0">
    <name>phy_dll_sts</name>
    <desc>Slave DLL results for data slice 0.</desc>
  </register>
  <register offset="0xf80061d0" type="ro" uniqueid="ps7_ddrc_phy_dll_sts1">
    <name>phy_dll_sts</name>
    <desc>Slave DLL results for data slice 0.</desc>
  </register>
  <register offset="0xf80061d4" type="ro" uniqueid="ps7_ddrc_phy_dll_sts2">
    <name>phy_dll_sts</name>
    <desc>Slave DLL results for data slice 0.</desc>
  </register>
  <register offset="0xf80061d8" type="ro" uniqueid="ps7_ddrc_phy_dll_sts3">
    <name>phy_dll_sts</name>
    <desc>Slave DLL results for data slice 0.</desc>
  </register>
  <register offset="0xf80061e0" type="ro" uniqueid="ps7_ddrc_dll_lock_sts">
    <name>dll_lock_sts</name>
    <desc>DLL Lock Status</desc>
  </register>
  <register offset="0xf80061e4" type="ro" uniqueid="ps7_ddrc_phy_ctrl_sts">
    <name>phy_ctrl_sts</name>
    <desc>PHY Control status</desc>
  </register>
  <register offset="0xf80061e8" type="ro" uniqueid="ps7_ddrc_phy_ctrl_sts_reg2">
    <name>phy_ctrl_sts_reg2</name>
    <desc>PHY Control status (2)</desc>
  </register>
  <register offset="0xf8006200" type="ro" uniqueid="ps7_ddrc_axi_id">
    <name>axi_id</name>
    <desc>ID and revision information</desc>
  </register>
  <register offset="0xf8006204" type="rw" uniqueid="ps7_ddrc_page_mask">
    <name>page_mask</name>
    <desc>Page mask register</desc>
  </register>
  <register offset="0xf8006208" type="rw" uniqueid="ps7_ddrc_axi_priority_wr_port0">
    <name>axi_priority_wr_port</name>
    <desc>AXI Priority control for write port 0.</desc>
  </register>
  <register offset="0xf800620c" type="rw" uniqueid="ps7_ddrc_axi_priority_wr_port1">
    <name>axi_priority_wr_port</name>
    <desc>AXI Priority control for write port 0.</desc>
  </register>
  <register offset="0xf8006210" type="rw" uniqueid="ps7_ddrc_axi_priority_wr_port2">
    <name>axi_priority_wr_port</name>
    <desc>AXI Priority control for write port 0.</desc>
  </register>
  <register offset="0xf8006214" type="rw" uniqueid="ps7_ddrc_axi_priority_wr_port3">
    <name>axi_priority_wr_port</name>
    <desc>AXI Priority control for write port 0.</desc>
  </register>
  <register offset="0xf8006218" type="rw" uniqueid="ps7_ddrc_axi_priority_rd_port0">
    <name>axi_priority_rd_port</name>
    <desc>AXI Priority control for read port 0.</desc>
  </register>
  <register offset="0xf800621c" type="rw" uniqueid="ps7_ddrc_axi_priority_rd_port1">
    <name>axi_priority_rd_port</name>
    <desc>AXI Priority control for read port 0.</desc>
  </register>
  <register offset="0xf8006220" type="rw" uniqueid="ps7_ddrc_axi_priority_rd_port2">
    <name>axi_priority_rd_port</name>
    <desc>AXI Priority control for read port 0.</desc>
  </register>
  <register offset="0xf8006224" type="rw" uniqueid="ps7_ddrc_axi_priority_rd_port3">
    <name>axi_priority_rd_port</name>
    <desc>AXI Priority control for read port 0.</desc>
  </register>
  <register offset="0xf8006248" type="rw" uniqueid="ps7_ddrc_AHB_priority_cfg0">
    <name>AHB_priority_cfg</name>
    <desc>AHB Priority control for port 0 (unused).</desc>
  </register>
  <register offset="0xf800624c" type="rw" uniqueid="ps7_ddrc_AHB_priority_cfg1">
    <name>AHB_priority_cfg</name>
    <desc>AHB Priority control for port 0 (unused).</desc>
  </register>
  <register offset="0xf8006250" type="rw" uniqueid="ps7_ddrc_AHB_priority_cfg2">
    <name>AHB_priority_cfg</name>
    <desc>AHB Priority control for port 0 (unused).</desc>
  </register>
  <register offset="0xf8006254" type="rw" uniqueid="ps7_ddrc_AHB_priority_cfg3">
    <name>AHB_priority_cfg</name>
    <desc>AHB Priority control for port 0 (unused).</desc>
  </register>
  <register offset="0xf8006260" type="ro" uniqueid="ps7_ddrc_perf_mon0">
    <name>perf_mon</name>
    <desc>Performance monitoring register 1 for port 0.</desc>
  </register>
  <register offset="0xf8006264" type="ro" uniqueid="ps7_ddrc_perf_mon1">
    <name>perf_mon</name>
    <desc>Performance monitoring register 1 for port 0.</desc>
  </register>
  <register offset="0xf8006268" type="ro" uniqueid="ps7_ddrc_perf_mon2">
    <name>perf_mon</name>
    <desc>Performance monitoring register 1 for port 0.</desc>
  </register>
  <register offset="0xf800626c" type="ro" uniqueid="ps7_ddrc_perf_mon3">
    <name>perf_mon</name>
    <desc>Performance monitoring register 1 for port 0.</desc>
  </register>
  <register offset="0xf8006270" type="ro" uniqueid="ps7_ddrc_perf_mon20">
    <name>perf_mon2</name>
    <desc>Performance monitoring register 2 for port 0.</desc>
  </register>
  <register offset="0xf8006274" type="ro" uniqueid="ps7_ddrc_perf_mon21">
    <name>perf_mon2</name>
    <desc>Performance monitoring register 2 for port 0.</desc>
  </register>
  <register offset="0xf8006278" type="ro" uniqueid="ps7_ddrc_perf_mon22">
    <name>perf_mon2</name>
    <desc>Performance monitoring register 2 for port 0.</desc>
  </register>
  <register offset="0xf800627c" type="ro" uniqueid="ps7_ddrc_perf_mon23">
    <name>perf_mon2</name>
    <desc>Performance monitoring register 2 for port 0.</desc>
  </register>
  <register offset="0xf8006280" type="ro" uniqueid="ps7_ddrc_perf_mon30">
    <name>perf_mon3</name>
    <desc>Performance monitoring register 3 for port 0.</desc>
  </register>
  <register offset="0xf8006284" type="ro" uniqueid="ps7_ddrc_perf_mon31">
    <name>perf_mon3</name>
    <desc>Performance monitoring register 3 for port 0.</desc>
  </register>
  <register offset="0xf8006288" type="ro" uniqueid="ps7_ddrc_perf_mon32">
    <name>perf_mon3</name>
    <desc>Performance monitoring register 3 for port 0.</desc>
  </register>
  <register offset="0xf800628c" type="ro" uniqueid="ps7_ddrc_perf_mon33">
    <name>perf_mon3</name>
    <desc>Performance monitoring register 3 for port 0.</desc>
  </register>
  <register offset="0xf8006290" type="rw" uniqueid="ps7_ddrc_trusted_mem_cfg">
    <name>trusted_mem_cfg</name>
    <desc>Trusted Memory configuration</desc>
  </register>
  <register offset="0xf8006294" type="rw" uniqueid="ps7_ddrc_excl_access_cfg0">
    <name>excl_access_cfg</name>
    <desc>Exclusive access configuration for port 0.</desc>
  </register>
  <register offset="0xf8006298" type="rw" uniqueid="ps7_ddrc_excl_access_cfg1">
    <name>excl_access_cfg</name>
    <desc>Exclusive access configuration for port 0.</desc>
  </register>
  <register offset="0xf800629c" type="rw" uniqueid="ps7_ddrc_excl_access_cfg2">
    <name>excl_access_cfg</name>
    <desc>Exclusive access configuration for port 0.</desc>
  </register>
  <register offset="0xf80062a0" type="rw" uniqueid="ps7_ddrc_excl_access_cfg3">
    <name>excl_access_cfg</name>
    <desc>Exclusive access configuration for port 0.</desc>
  </register>
  <register offset="0xf80062a4" type="ro" uniqueid="ps7_ddrc_mode_reg_read">
    <name>mode_reg_read</name>
    <desc>Mode register read data</desc>
  </register>
  <register offset="0xf80062a8" type="rw" uniqueid="ps7_ddrc_lpddr_ctrl0">
    <name>lpddr_ctrl0</name>
    <desc>LPDDR2 Control 0 Register</desc>
  </register>
  <register offset="0xf80062ac" type="rw" uniqueid="ps7_ddrc_lpddr_ctrl1">
    <name>lpddr_ctrl1</name>
    <desc>LPDDR2 Control 1 Register</desc>
  </register>
  <register offset="0xf80062b0" type="rw" uniqueid="ps7_ddrc_lpddr_ctrl2">
    <name>lpddr_ctrl2</name>
    <desc>LPDDR2 Control 2 Register</desc>
  </register>
  <register offset="0xf80062b4" type="rw" uniqueid="ps7_ddrc_lpddr_ctrl3">
    <name>lpddr_ctrl3</name>
    <desc>LPDDR2 Control 3 Register</desc>
  </register>
  <register offset="0xf80062b8" type="ro" uniqueid="ps7_ddrc_phy_wr_lvl_fsm">
    <name>phy_wr_lvl_fsm</name>
    <desc>PHY write leveling state machine status</desc>
  </register>
  <register offset="0xf80062bc" type="ro" uniqueid="ps7_ddrc_phy_rd_lvl_fsm">
    <name>phy_rd_lvl_fsm</name>
    <desc>PHY read leveling state machine status</desc>
  </register>
  <register offset="0xf80062c0" type="ro" uniqueid="ps7_ddrc_phy_gate_lvl_fsm">
    <name>phy_gate_lvl_fsm</name>
    <desc>PHY gate leveling state machine status</desc>
  </register>
  <register offset="0xe000a000" type="rw" uniqueid="ps7_gpio_MASK_DATA_0_LSW">
    <name>MASK_DATA_0_LSW</name>
    <desc>Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins</desc>
  </register>
  <register offset="0xe000a004" type="rw" uniqueid="ps7_gpio_MASK_DATA_0_MSW">
    <name>MASK_DATA_0_MSW</name>
    <desc>Maskable single-word-based data access register: Mask and data access for the most significant word of this bank of GPIO pins</desc>
  </register>
  <register offset="0xe000a008" type="rw" uniqueid="ps7_gpio_MASK_DATA_1_LSW">
    <name>MASK_DATA_1_LSW</name>
    <desc>Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins</desc>
  </register>
  <register offset="0xe000a00c" type="rw" uniqueid="ps7_gpio_MASK_DATA_1_MSW">
    <name>MASK_DATA_1_MSW</name>
    <desc>Maskable single-word-based data access register: Mask and data access for the most significant word of this bank of GPIO pins</desc>
  </register>
  <register offset="0xe000a010" type="rw" uniqueid="ps7_gpio_MASK_DATA_2_LSW">
    <name>MASK_DATA_2_LSW</name>
    <desc>Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins</desc>
  </register>
  <register offset="0xe000a014" type="rw" uniqueid="ps7_gpio_MASK_DATA_2_MSW">
    <name>MASK_DATA_2_MSW</name>
    <desc>Maskable single-word-based data access register: Mask and data access for the most significant word of this bank of GPIO pins</desc>
  </register>
  <register offset="0xe000a018" type="rw" uniqueid="ps7_gpio_MASK_DATA_3_LSW">
    <name>MASK_DATA_3_LSW</name>
    <desc>Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins</desc>
  </register>
  <register offset="0xe000a01c" type="rw" uniqueid="ps7_gpio_MASK_DATA_3_MSW">
    <name>MASK_DATA_3_MSW</name>
    <desc>Maskable single-word-based data access register: Mask and data access for the most significant word of this bank of GPIO pins</desc>
  </register>
  <register offset="0xe000a040" type="rw" uniqueid="ps7_gpio_DATA_0">
    <name>DATA_0</name>
    <desc>Unmasked double-word-based data access register: data access for this bank of GPIO pins</desc>
  </register>
  <register offset="0xe000a044" type="rw" uniqueid="ps7_gpio_DATA_1">
    <name>DATA_1</name>
    <desc>Unmasked double-word-based data access register: data access for this bank of GPIO pins</desc>
  </register>
  <register offset="0xe000a048" type="rw" uniqueid="ps7_gpio_DATA_2">
    <name>DATA_2</name>
    <desc>Unmasked double-word-based data access register: data access for this bank of GPIO pins</desc>
  </register>
  <register offset="0xe000a04c" type="rw" uniqueid="ps7_gpio_DATA_3">
    <name>DATA_3</name>
    <desc>Unmasked double-word-based data access register: data access for this bank of GPIO pins</desc>
  </register>
  <register offset="0xe000a060" type="ro" uniqueid="ps7_gpio_DATA_0_RO">
    <name>DATA_0_RO</name>
    <desc>Read only pin value register: read only pin values for this bank of GPIO pins</desc>
  </register>
  <register offset="0xe000a064" type="ro" uniqueid="ps7_gpio_DATA_1_RO">
    <name>DATA_1_RO</name>
    <desc>Read only pin value register: read only pin values for this bank of GPIO pins</desc>
  </register>
  <register offset="0xe000a068" type="ro" uniqueid="ps7_gpio_DATA_2_RO">
    <name>DATA_2_RO</name>
    <desc>Read only pin value register: read only pin values for this bank of GPIO pins</desc>
  </register>
  <register offset="0xe000a06c" type="ro" uniqueid="ps7_gpio_DATA_3_RO">
    <name>DATA_3_RO</name>
    <desc>Read only pin value register: read only pin values for this bank of GPIO pins</desc>
  </register>
  <register offset="0xe000a200" type="rw" uniqueid="ps7_gpio_BYPM_0">
    <name>BYPM_0</name>
    <desc>Bypass configuration register: Configures bank 0 for bypass mode or software control mode</desc>
  </register>
  <register offset="0xe000a204" type="rw" uniqueid="ps7_gpio_DIRM_0">
    <name>DIRM_0</name>
    <desc>Direction mode configuration register: Configures bank 0 for direction mode, either input or output</desc>
  </register>
  <register offset="0xe000a208" type="rw" uniqueid="ps7_gpio_OEN_0">
    <name>OEN_0</name>
    <desc>Output enable register: Configures the output enables of bank 0</desc>
  </register>
  <register offset="0xe000a20c" type="ro" uniqueid="ps7_gpio_INT_MASK_0">
    <name>INT_MASK_0</name>
    <desc>Interrupt Mask status register: Reports the interrupt mask state for bank 0</desc>
  </register>
  <register offset="0xe000a210" type="wo" uniqueid="ps7_gpio_INT_EN_0">
    <name>INT_EN_0</name>
    <desc>Interrupt Enable configuration register: Clears the interrupt mask for bank 0</desc>
  </register>
  <register offset="0xe000a214" type="wo" uniqueid="ps7_gpio_INT_DIS_0">
    <name>INT_DIS_0</name>
    <desc>Interrupt Disable configuration register: Sets the interrupt mask for bank 0</desc>
  </register>
  <register offset="0xe000a218" type="rw" uniqueid="ps7_gpio_INT_STAT_0">
    <name>INT_STAT_0</name>
    <desc>Interrupt Status register: Reports the interrupt status for bank 0</desc>
  </register>
  <register offset="0xe000a21c" type="rw" uniqueid="ps7_gpio_INT_TYPE_0">
    <name>INT_TYPE_0</name>
    <desc>Interrupt Type configuration register: Configures the interrupt type for bank 0</desc>
  </register>
  <register offset="0xe000a220" type="rw" uniqueid="ps7_gpio_INT_POLARITY_0">
    <name>INT_POLARITY_0</name>
    <desc>Interrupt polarity configuration register: Configures the interrupt polarity for bank 0</desc>
  </register>
  <register offset="0xe000a224" type="rw" uniqueid="ps7_gpio_INT_ANY_0">
    <name>INT_ANY_0</name>
    <desc>Interrupt On Any configuration register: Configures the interrupt to trigger on any edge for bank 0</desc>
  </register>
  <register offset="0xe000a240" type="rw" uniqueid="ps7_gpio_BYPM_1">
    <name>BYPM_1</name>
    <desc>Bypass configuration register: Configures bank 1 for bypass mode or software control mode</desc>
  </register>
  <register offset="0xe000a244" type="rw" uniqueid="ps7_gpio_DIRM_1">
    <name>DIRM_1</name>
    <desc>Direction mode configuration register: Configures bank 1 for direction mode, either input or output</desc>
  </register>
  <register offset="0xe000a248" type="rw" uniqueid="ps7_gpio_OEN_1">
    <name>OEN_1</name>
    <desc>Output enable register: Configures the output enables of bank 1</desc>
  </register>
  <register offset="0xe000a24c" type="ro" uniqueid="ps7_gpio_INT_MASK_1">
    <name>INT_MASK_1</name>
    <desc>Interrupt Mask status register: Reports the interrupt mask state for bank 1</desc>
  </register>
  <register offset="0xe000a250" type="wo" uniqueid="ps7_gpio_INT_EN_1">
    <name>INT_EN_1</name>
    <desc>Interrupt Enable configuration register: Clears the interrupt mask for bank 1</desc>
  </register>
  <register offset="0xe000a254" type="wo" uniqueid="ps7_gpio_INT_DIS_1">
    <name>INT_DIS_1</name>
    <desc>Interrupt Disable configuration register: Sets the interrupt mask for bank 1</desc>
  </register>
  <register offset="0xe000a258" type="rw" uniqueid="ps7_gpio_INT_STAT_1">
    <name>INT_STAT_1</name>
    <desc>Interrupt Status register: Reports the interrupt status for bank 1</desc>
  </register>
  <register offset="0xe000a25c" type="rw" uniqueid="ps7_gpio_INT_TYPE_1">
    <name>INT_TYPE_1</name>
    <desc>Interrupt Type configuration register: Configures the interrupt type for bank 1</desc>
  </register>
  <register offset="0xe000a260" type="rw" uniqueid="ps7_gpio_INT_POLARITY_1">
    <name>INT_POLARITY_1</name>
    <desc>Interrupt polarity configuration register: Configures the interrupt polarity for bank 1</desc>
  </register>
  <register offset="0xe000a264" type="rw" uniqueid="ps7_gpio_INT_ANY_1">
    <name>INT_ANY_1</name>
    <desc>Interrupt On Any configuration register: Configures the interrupt to trigger on any edge for bank 1</desc>
  </register>
  <register offset="0xe000a280" type="rw" uniqueid="ps7_gpio_BYPM_2">
    <name>BYPM_2</name>
    <desc>Bypass configuration register: Configures bank 2 for bypass mode or software control mode</desc>
  </register>
  <register offset="0xe000a284" type="rw" uniqueid="ps7_gpio_DIRM_2">
    <name>DIRM_2</name>
    <desc>Direction mode configuration register: Configures bank 2 for direction mode, either input or output</desc>
  </register>
  <register offset="0xe000a288" type="rw" uniqueid="ps7_gpio_OEN_2">
    <name>OEN_2</name>
    <desc>Output enable register: Configures the output enables of bank 2</desc>
  </register>
  <register offset="0xe000a28c" type="ro" uniqueid="ps7_gpio_INT_MASK_2">
    <name>INT_MASK_2</name>
    <desc>Interrupt Mask status register: Reports the interrupt mask state for bank 2</desc>
  </register>
  <register offset="0xe000a290" type="wo" uniqueid="ps7_gpio_INT_EN_2">
    <name>INT_EN_2</name>
    <desc>Interrupt Enable configuration register: Clears the interrupt mask for bank 2</desc>
  </register>
  <register offset="0xe000a294" type="wo" uniqueid="ps7_gpio_INT_DIS_2">
    <name>INT_DIS_2</name>
    <desc>Interrupt Disable configuration register: Sets the interrupt mask for bank 2</desc>
  </register>
  <register offset="0xe000a298" type="rw" uniqueid="ps7_gpio_INT_STAT_2">
    <name>INT_STAT_2</name>
    <desc>Interrupt Status register: Reports the interrupt status for bank 2</desc>
  </register>
  <register offset="0xe000a29c" type="rw" uniqueid="ps7_gpio_INT_TYPE_2">
    <name>INT_TYPE_2</name>
    <desc>Interrupt Type configuration register: Configures the interrupt type for bank 2</desc>
  </register>
  <register offset="0xe000a2a0" type="rw" uniqueid="ps7_gpio_INT_POLARITY_2">
    <name>INT_POLARITY_2</name>
    <desc>Interrupt polarity configuration register: Configures the interrupt polarity for bank 2</desc>
  </register>
  <register offset="0xe000a2a4" type="rw" uniqueid="ps7_gpio_INT_ANY_2">
    <name>INT_ANY_2</name>
    <desc>Interrupt On Any configuration register: Configures the interrupt to trigger on any edge for bank 2</desc>
  </register>
  <register offset="0xe000a2c0" type="rw" uniqueid="ps7_gpio_BYPM_3">
    <name>BYPM_3</name>
    <desc>Bypass configuration register: Configures bank 3 for bypass mode or software control mode</desc>
  </register>
  <register offset="0xe000a2c4" type="rw" uniqueid="ps7_gpio_DIRM_3">
    <name>DIRM_3</name>
    <desc>Direction mode configuration register: Configures bank 3 for direction mode, either input or output</desc>
  </register>
  <register offset="0xe000a2c8" type="rw" uniqueid="ps7_gpio_OEN_3">
    <name>OEN_3</name>
    <desc>Output enable register: Configures the output enables of bank 3</desc>
  </register>
  <register offset="0xe000a2cc" type="ro" uniqueid="ps7_gpio_INT_MASK_3">
    <name>INT_MASK_3</name>
    <desc>Interrupt Mask status register: Reports the interrupt mask state for bank 3</desc>
  </register>
  <register offset="0xe000a2d0" type="wo" uniqueid="ps7_gpio_INT_EN_3">
    <name>INT_EN_3</name>
    <desc>Interrupt Enable configuration register: Clears the interrupt mask for bank 3</desc>
  </register>
  <register offset="0xe000a2d4" type="wo" uniqueid="ps7_gpio_INT_DIS_3">
    <name>INT_DIS_3</name>
    <desc>Interrupt Disable configuration register: Sets the interrupt mask for bank 3</desc>
  </register>
  <register offset="0xe000a2d8" type="rw" uniqueid="ps7_gpio_INT_STAT_3">
    <name>INT_STAT_3</name>
    <desc>Interrupt Status register: Reports the interrupt status for bank 3</desc>
  </register>
  <register offset="0xe000a2dc" type="rw" uniqueid="ps7_gpio_INT_TYPE_3">
    <name>INT_TYPE_3</name>
    <desc>Interrupt Type configuration register: Configures the interrupt type for bank 3</desc>
  </register>
  <register offset="0xe000a2e0" type="rw" uniqueid="ps7_gpio_INT_POLARITY_3">
    <name>INT_POLARITY_3</name>
    <desc>Interrupt polarity configuration register: Configures the interrupt polarity for bank 3</desc>
  </register>
  <register offset="0xe000a2e4" type="rw" uniqueid="ps7_gpio_INT_ANY_3">
    <name>INT_ANY_3</name>
    <desc>Interrupt On Any configuration register: Configures the interrupt to trigger on any edge for bank 3</desc>
  </register>
  <register offset="0xf8007000" type="rw" uniqueid="ps7_devcfg_CTRL">
    <name>CTRL</name>
    <desc>Control Register : This register defines basic control registers.
Some of the register bits can be locked by control bits in the LOCK Register 0x004.</desc>
  </register>
  <register offset="0xf8007004" type="rw" uniqueid="ps7_devcfg_LOCK">
    <name>LOCK</name>
    <desc>This register defines LOCK register used to lock changes in the Control Register 0x000 after configuration. All those LOCK register is set only register. The only way to clear those registers is power on reset signal.</desc>
  </register>
  <register offset="0xf8007008" type="rw" uniqueid="ps7_devcfg_CFG">
    <name>CFG</name>
    <desc>Configuration Register : This register contains configuration information for the AXI transfers, and other general setup.</desc>
  </register>
  <register offset="0xf800700c" type="rw" uniqueid="ps7_devcfg_INT_STS">
    <name>INT_STS</name>
    <desc>Interrupt Status Register : This register contains interrupt status flags.
All register bits are clear on write by writing 1s to those bits that need to be cleared.
Note that individual status bits will be set if the corresponding condition is satisfied regardless of whether the interrupt mask bit in 0x010 is set.
However, external interrupt will only be generated if an interrupt status flag is set and the corresponding mask bit is not set</desc>
  </register>
  <register offset="0xf8007010" type="rw" uniqueid="ps7_devcfg_INT_MASK">
    <name>INT_MASK</name>
    <desc>Interrupt Mask Register: This register contains interrupt mask information.
Set a bit to 1 to mask the interrupt generation from the corresponding interrupting source in Interrupt Status Register 0x00C.</desc>
  </register>
  <register offset="0xf8007014" type="rw" uniqueid="ps7_devcfg_STATUS">
    <name>STATUS</name>
    <desc>Status Register: This register contains miscellaneous status.</desc>
  </register>
  <register offset="0xf8007018" type="rw" uniqueid="ps7_devcfg_DMA_SRC_ADDR">
    <name>DMA_SRC_ADDR</name>
    <desc>DMA Source address Register: This register contains the source address for DMA transfer.
A DMA command consists of source address, destination address, source transfer length, and destination transfer length.
It is important that the parameters are programmed in the exact sequence as described</desc>
  </register>
  <register offset="0xf800701c" type="rw" uniqueid="ps7_devcfg_DMA_DST_ADDR">
    <name>DMA_DST_ADDR</name>
    <desc>DMA Destination address Register: This register contains the destination address for DMA transfer.
A DMA command consists of source address, destination address, source transfer length, and destination transfer length.
It is important that the parameters are programmed in the exact sequence as described.</desc>
  </register>
  <register offset="0xf8007020" type="rw" uniqueid="ps7_devcfg_DMA_SRC_LEN">
    <name>DMA_SRC_LEN</name>
    <desc>DMA Source transfer Length Register: This register contains the DMA source transfer length in unit of 4-byte word.
A DMA command that consists of source address, destination address, source transfer length, and destination transfer length.
It is important that the parameters are programmed in the exact sequence as described.</desc>
  </register>
  <register offset="0xf8007024" type="rw" uniqueid="ps7_devcfg_DMA_DEST_LEN">
    <name>DMA_DEST_LEN</name>
    <desc>DMA Destination transfer
Length Register: This register contains the DMA destination transfer length in unit of 4-byte word.
A DMA command that consists of source address, destination address, source transfer length, and destination transfer length is accepted when this register is written to.
It is important that the parameters are programmed in the exact sequence as described.</desc>
  </register>
  <register offset="0xf8007028" type="wo" uniqueid="ps7_devcfg_ROM_SHADOW">
    <name>ROM_SHADOW</name>
    <desc>ROM Shadow Register: This register defines ROM shadow</desc>
  </register>
  <register offset="0xf800702c" type="rw" uniqueid="ps7_devcfg_MULTIBOOT_ADDR">
    <name>MULTIBOOT_ADDR</name>
    <desc>MULTI Boot Addr Pointer Register: This register defines multi-boot address pointer. This register is power on reset only used to remember multi-boot address pointer set by previous boot.</desc>
  </register>
  <register offset="0xf8007030" type="rw" uniqueid="ps7_devcfg_SW_ID">
    <name>SW_ID</name>
    <desc>Software ID Register: This register defines PS boot software ID. It will be used by firmware and software to perform consistent check for subsequent PS software and FPGA image loads. It is both readable and writeable after reset, and it becomes read only after system has entered user mode (bit 15 of reg 0x000 is set).</desc>
  </register>
  <register offset="0xf8007034" type="rw" uniqueid="ps7_devcfg_UNLOCK">
    <name>UNLOCK</name>
    <desc>Unlock Register: User should use this register to unlock device configuration register to prevent code corruption in ROM by writing 0x757BDF0D into this register. Power on reset</desc>
  </register>
  <register offset="0xf8007080" type="rw" uniqueid="ps7_devcfg_MCTRL">
    <name>MCTRL</name>
    <desc>Miscellaneous control Register: This register contains miscellaneous controls.</desc>
  </register>
  <register offset="0xf8007100" type="rw" uniqueid="ps7_devcfg_XADCIF_CFG">
    <name>XADCIF_CFG</name>
    <desc>XADC Interface Configuration Register : This register configures the XADC Interface operation</desc>
  </register>
  <register offset="0xf8007104" type="rw" uniqueid="ps7_devcfg_XADCIF_INT_STS">
    <name>XADCIF_INT_STS</name>
    <desc>XADC Interface Interrupt Status Register : This register contains the interrupt status flags of the XADC interface block.
All register bits are clear on write by writing 1s to those bits that need to be cleared.
Note that individual status bits will be set if the corresponding condition is satisfied regardless of whether the interrupt mask bit in 0x108 is set.
However, external interrupt will only be generated if an interrupt status flag is set and the corresponding mask bit is not set</desc>
  </register>
  <register offset="0xf8007108" type="rw" uniqueid="ps7_devcfg_XADCIF_INT_MASK">
    <name>XADCIF_INT_MASK</name>
    <desc>XADC Interface Interrupt Mask Register : This register contains the interrupt mask information.
Set a bit to 1 to mask the interrupt generation from the corresponding interrupting source in 0x104</desc>
  </register>
  <register offset="0xf800710c" type="ro" uniqueid="ps7_devcfg_XADCIF_MSTS">
    <name>XADCIF_MSTS</name>
    <desc>XADC Interface miscellaneous Status Register : This register contains miscellaneous status of the XADC Interface</desc>
  </register>
  <register offset="0xf8007110" type="wo" uniqueid="ps7_devcfg_XADCIF_CMDFIFO">
    <name>XADCIF_CMDFIFO</name>
    <desc>XADC Interface Command FIFO Register : This address is the entry point to the command FIFO.
Commands get push into the FIFO when there is a write to this address</desc>
  </register>
  <register offset="0xf8007114" type="ro" uniqueid="ps7_devcfg_XADCIF_RDFIFO">
    <name>XADCIF_RDFIFO</name>
    <desc>XADC Interface Data FIFO Register : This address is the exit point of the read data FIFO.
Read data is returned when there is a read from this address</desc>
  </register>
  <register offset="0xf8007118" type="rw" uniqueid="ps7_devcfg_XADCIF_MCTL">
    <name>XADCIF_MCTL</name>
    <desc>XADC Interface Miscellaneous Control Register : This register provides miscellaneous control of the XADC Interface.</desc>
  </register>
  <register offset="0xf8f00000" type="rw" uniqueid="ps7_mpcore_SCU_CONTROL_REGISTER">
    <name>SCU_CONTROL_REGISTER</name>
    <desc>SCU Control Register</desc>
  </register>
  <register offset="0xf8f00004" type="ro" uniqueid="ps7_mpcore_SCU_CONFIGURATION_REGISTER">
    <name>SCU_CONFIGURATION_REGISTER</name>
    <desc>SCU Configuration Register</desc>
  </register>
  <register offset="0xf8f00008" type="rw" uniqueid="ps7_mpcore_SCU_CPU_Power_Status_Register">
    <name>SCU_CPU_Power_Status_Register</name>
    <desc>SCU CPU Power Status Register</desc>
  </register>
  <register offset="0xf8f0000c" type="rw" uniqueid="ps7_mpcore_SCU_Invalidate_All_Registers_in_Secure_State">
    <name>SCU_Invalidate_All_Registers_in_Secure_State</name>
    <desc>SCU Invalidate All Registers in
Secure State</desc>
  </register>
  <register offset="0xf8f00040" type="rw" uniqueid="ps7_mpcore_Filtering_Start_Address_Register">
    <name>Filtering_Start_Address_Register</name>
    <desc>Filtering Start Address Register</desc>
  </register>
  <register offset="0xf8f00044" type="rw" uniqueid="ps7_mpcore_Filtering_End_Address_Register">
    <name>Filtering_End_Address_Register</name>
    <desc>Defined by FILTEREND input</desc>
  </register>
  <register offset="0xf8f00050" type="rw" uniqueid="ps7_mpcore_SCU_Access_Control_Register_SAC">
    <name>SCU_Access_Control_Register_SAC</name>
    <desc>SCU Access Control (SAC) Register</desc>
  </register>
  <register offset="0xf8f00054" type="ro" uniqueid="ps7_mpcore_SCU_Non_secure_Access_Control_Register">
    <name>SCU_Non_secure_Access_Control_Register</name>
    <desc>SCU Non-secure Access Control Register
SNSAC</desc>
  </register>
  <register offset="0xf8f00100" type="rw" uniqueid="ps7_mpcore_ICCICR">
    <name>ICCICR</name>
    <desc>CPU Interface Control Register</desc>
  </register>
  <register offset="0xf8f00104" type="rw" uniqueid="ps7_mpcore_ICCPMR">
    <name>ICCPMR</name>
    <desc>Interrupt Priority Mask Register</desc>
  </register>
  <register offset="0xf8f00108" type="rw" uniqueid="ps7_mpcore_ICCBPR">
    <name>ICCBPR</name>
    <desc>Binary Point Register</desc>
  </register>
  <register offset="0xf8f0010c" type="rw" uniqueid="ps7_mpcore_ICCIAR">
    <name>ICCIAR</name>
    <desc>Interrupt Acknowledge Register</desc>
  </register>
  <register offset="0xf8f00110" type="rw" uniqueid="ps7_mpcore_ICCEOIR">
    <name>ICCEOIR</name>
    <desc>End Of Interrupt Register</desc>
  </register>
  <register offset="0xf8f00114" type="rw" uniqueid="ps7_mpcore_ICCRPR">
    <name>ICCRPR</name>
    <desc>Running Priority Register</desc>
  </register>
  <register offset="0xf8f00118" type="rw" uniqueid="ps7_mpcore_ICCHPIR">
    <name>ICCHPIR</name>
    <desc>Highest Pending Interrupt Register</desc>
  </register>
  <register offset="0xf8f0011c" type="rw" uniqueid="ps7_mpcore_ICCABPR">
    <name>ICCABPR</name>
    <desc>Aliased Non-secure Binary Point Register</desc>
  </register>
  <register offset="0xf8f001fc" type="ro" uniqueid="ps7_mpcore_ICCIDR">
    <name>ICCIDR</name>
    <desc>CPU Interface Implementer Identification Register</desc>
  </register>
  <register offset="0xf8f00200" type="rw" uniqueid="ps7_mpcore_Global_Timer_Counter_Register0">
    <name>Global_Timer_Counter_Register</name>
    <desc>Global Timer Counter Register 0</desc>
  </register>
  <register offset="0xf8f00204" type="rw" uniqueid="ps7_mpcore_Global_Timer_Counter_Register1">
    <name>Global_Timer_Counter_Register</name>
    <desc>Global Timer Counter Register 0</desc>
  </register>
  <register offset="0xf8f00208" type="rw" uniqueid="ps7_mpcore_Global_Timer_Control_Register">
    <name>Global_Timer_Control_Register</name>
    <desc>Global Timer Control Register</desc>
  </register>
  <register offset="0xf8f0020c" type="rw" uniqueid="ps7_mpcore_Global_Timer_Interrupt_Status_Register">
    <name>Global_Timer_Interrupt_Status_Register</name>
    <desc>Global Timer Interrupt Status Register</desc>
  </register>
  <register offset="0xf8f00210" type="rw" uniqueid="ps7_mpcore_Comparator_Value_Register0">
    <name>Comparator_Value_Register</name>
    <desc>Comparator Value Register_0</desc>
  </register>
  <register offset="0xf8f00214" type="rw" uniqueid="ps7_mpcore_Comparator_Value_Register1">
    <name>Comparator_Value_Register</name>
    <desc>Comparator Value Register_0</desc>
  </register>
  <register offset="0xf8f00218" type="rw" uniqueid="ps7_mpcore_Auto_increment_Register">
    <name>Auto_increment_Register</name>
    <desc>Auto-increment Register</desc>
  </register>
  <register offset="0xf8f00600" type="rw" uniqueid="ps7_mpcore_Private_Timer_Load_Register">
    <name>Private_Timer_Load_Register</name>
    <desc>Private Timer Load Register</desc>
  </register>
  <register offset="0xf8f00604" type="rw" uniqueid="ps7_mpcore_Private_Timer_Counter_Register">
    <name>Private_Timer_Counter_Register</name>
    <desc>Private Timer Counter Register</desc>
  </register>
  <register offset="0xf8f00608" type="rw" uniqueid="ps7_mpcore_Private_Timer_Control_Register">
    <name>Private_Timer_Control_Register</name>
    <desc>Private Timer Control Register</desc>
  </register>
  <register offset="0xf8f0060c" type="rw" uniqueid="ps7_mpcore_Private_Timer_Interrupt_Status_Register">
    <name>Private_Timer_Interrupt_Status_Register</name>
    <desc>Private Timer Interrupt Status Register</desc>
  </register>
  <register offset="0xf8f00620" type="rw" uniqueid="ps7_mpcore_Watchdog_Load_Register">
    <name>Watchdog_Load_Register</name>
    <desc>Watchdog Load Register</desc>
  </register>
  <register offset="0xf8f00624" type="rw" uniqueid="ps7_mpcore_Watchdog_Counter_Register">
    <name>Watchdog_Counter_Register</name>
    <desc>Watchdog Counter Register</desc>
  </register>
  <register offset="0xf8f00628" type="rw" uniqueid="ps7_mpcore_Watchdog_Control_Register">
    <name>Watchdog_Control_Register</name>
    <desc>Watchdog Control Register</desc>
  </register>
  <register offset="0xf8f0062c" type="rw" uniqueid="ps7_mpcore_Watchdog_Interrupt_Status_Register">
    <name>Watchdog_Interrupt_Status_Register</name>
    <desc>Watchdog Interrupt Status Register</desc>
  </register>
  <register offset="0xf8f00630" type="rw" uniqueid="ps7_mpcore_Watchdog_Reset_Status_Register">
    <name>Watchdog_Reset_Status_Register</name>
    <desc>Watchdog Reset Status Register</desc>
  </register>
  <register offset="0xf8f00634" type="rw" uniqueid="ps7_mpcore_Watchdog_Disable_Register">
    <name>Watchdog_Disable_Register</name>
    <desc>Watchdog Disable Register</desc>
  </register>
  <register offset="0xf8f01000" type="rw" uniqueid="ps7_mpcore_ICDDCR">
    <name>ICDDCR</name>
    <desc>Distributor Control Register</desc>
  </register>
  <register offset="0xf8f01004" type="ro" uniqueid="ps7_mpcore_ICDICTR">
    <name>ICDICTR</name>
    <desc>Interrupt Controller Type Register</desc>
  </register>
  <register offset="0xf8f01008" type="ro" uniqueid="ps7_mpcore_ICDIIDR">
    <name>ICDIIDR</name>
    <desc>Distributor Implementer Identification Register</desc>
  </register>
  <register offset="0xf8f01080" type="rw" uniqueid="ps7_mpcore_ICDISR0">
    <name>ICDISR</name>
    <desc>Interrupt Security Register_0</desc>
  </register>
  <register offset="0xf8f01084" type="rw" uniqueid="ps7_mpcore_ICDISR1">
    <name>ICDISR</name>
    <desc>Interrupt Security Register_0</desc>
  </register>
  <register offset="0xf8f01088" type="rw" uniqueid="ps7_mpcore_ICDISR2">
    <name>ICDISR</name>
    <desc>Interrupt Security Register_0</desc>
  </register>
  <register offset="0xf8f01100" type="rw" uniqueid="ps7_mpcore_ICDISER0">
    <name>ICDISER0</name>
    <desc>Interrupt Set-Enable Register 0</desc>
  </register>
  <register offset="0xf8f01104" type="rw" uniqueid="ps7_mpcore_ICDISER1">
    <name>ICDISER1</name>
    <desc>Interrupt Set-Enable Register 1</desc>
  </register>
  <register offset="0xf8f01108" type="rw" uniqueid="ps7_mpcore_ICDISER2">
    <name>ICDISER2</name>
    <desc>Interrupt Set-Enable Register 2</desc>
  </register>
  <register offset="0xf8f01180" type="rw" uniqueid="ps7_mpcore_ICDICER0">
    <name>ICDICER0</name>
    <desc>Interrupt Clear-Enable Register 0</desc>
  </register>
  <register offset="0xf8f01184" type="rw" uniqueid="ps7_mpcore_ICDICER1">
    <name>ICDICER1</name>
    <desc>Interrupt Clear-Enable Register 1</desc>
  </register>
  <register offset="0xf8f01188" type="rw" uniqueid="ps7_mpcore_ICDICER2">
    <name>ICDICER2</name>
    <desc>Interrupt Clear-Enable Register 2</desc>
  </register>
  <register offset="0xf8f01200" type="rw" uniqueid="ps7_mpcore_ICDISPR0">
    <name>ICDISPR</name>
    <desc>Interrupt Set-Pending Register_0</desc>
  </register>
  <register offset="0xf8f01204" type="rw" uniqueid="ps7_mpcore_ICDISPR1">
    <name>ICDISPR</name>
    <desc>Interrupt Set-Pending Register_0</desc>
  </register>
  <register offset="0xf8f01208" type="rw" uniqueid="ps7_mpcore_ICDISPR2">
    <name>ICDISPR</name>
    <desc>Interrupt Set-Pending Register_0</desc>
  </register>
  <register offset="0xf8f01280" type="rw" uniqueid="ps7_mpcore_ICDICPR0">
    <name>ICDICPR</name>
    <desc>Interrupt Clear-Pending Register_0</desc>
  </register>
  <register offset="0xf8f01284" type="rw" uniqueid="ps7_mpcore_ICDICPR1">
    <name>ICDICPR</name>
    <desc>Interrupt Clear-Pending Register_0</desc>
  </register>
  <register offset="0xf8f01288" type="rw" uniqueid="ps7_mpcore_ICDICPR2">
    <name>ICDICPR</name>
    <desc>Interrupt Clear-Pending Register_0</desc>
  </register>
  <register offset="0xf8f01300" type="rw" uniqueid="ps7_mpcore_ICDABR0">
    <name>ICDABR</name>
    <desc>Active Bit register_0</desc>
  </register>
  <register offset="0xf8f01304" type="rw" uniqueid="ps7_mpcore_ICDABR1">
    <name>ICDABR</name>
    <desc>Active Bit register_0</desc>
  </register>
  <register offset="0xf8f01308" type="rw" uniqueid="ps7_mpcore_ICDABR2">
    <name>ICDABR</name>
    <desc>Active Bit register_0</desc>
  </register>
  <register offset="0xf8f01400" type="rw" uniqueid="ps7_mpcore_ICDIPR0">
    <name>ICDIPR</name>
    <desc>Interrupt Priority Register_0</desc>
  </register>
  <register offset="0xf8f01404" type="rw" uniqueid="ps7_mpcore_ICDIPR1">
    <name>ICDIPR</name>
    <desc>Interrupt Priority Register_0</desc>
  </register>
  <register offset="0xf8f01408" type="rw" uniqueid="ps7_mpcore_ICDIPR2">
    <name>ICDIPR</name>
    <desc>Interrupt Priority Register_0</desc>
  </register>
  <register offset="0xf8f0140c" type="rw" uniqueid="ps7_mpcore_ICDIPR3">
    <name>ICDIPR</name>
    <desc>Interrupt Priority Register_0</desc>
  </register>
  <register offset="0xf8f01410" type="rw" uniqueid="ps7_mpcore_ICDIPR4">
    <name>ICDIPR</name>
    <desc>Interrupt Priority Register_0</desc>
  </register>
  <register offset="0xf8f01414" type="rw" uniqueid="ps7_mpcore_ICDIPR5">
    <name>ICDIPR</name>
    <desc>Interrupt Priority Register_0</desc>
  </register>
  <register offset="0xf8f01418" type="rw" uniqueid="ps7_mpcore_ICDIPR6">
    <name>ICDIPR</name>
    <desc>Interrupt Priority Register_0</desc>
  </register>
  <register offset="0xf8f0141c" type="rw" uniqueid="ps7_mpcore_ICDIPR7">
    <name>ICDIPR</name>
    <desc>Interrupt Priority Register_0</desc>
  </register>
  <register offset="0xf8f01420" type="rw" uniqueid="ps7_mpcore_ICDIPR8">
    <name>ICDIPR</name>
    <desc>Interrupt Priority Register_0</desc>
  </register>
  <register offset="0xf8f01424" type="rw" uniqueid="ps7_mpcore_ICDIPR9">
    <name>ICDIPR</name>
    <desc>Interrupt Priority Register_0</desc>
  </register>
  <register offset="0xf8f01428" type="rw" uniqueid="ps7_mpcore_ICDIPR10">
    <name>ICDIPR</name>
    <desc>Interrupt Priority Register_0</desc>
  </register>
  <register offset="0xf8f0142c" type="rw" uniqueid="ps7_mpcore_ICDIPR11">
    <name>ICDIPR</name>
    <desc>Interrupt Priority Register_0</desc>
  </register>
  <register offset="0xf8f01430" type="rw" uniqueid="ps7_mpcore_ICDIPR12">
    <name>ICDIPR</name>
    <desc>Interrupt Priority Register_0</desc>
  </register>
  <register offset="0xf8f01434" type="rw" uniqueid="ps7_mpcore_ICDIPR13">
    <name>ICDIPR</name>
    <desc>Interrupt Priority Register_0</desc>
  </register>
  <register offset="0xf8f01438" type="rw" uniqueid="ps7_mpcore_ICDIPR14">
    <name>ICDIPR</name>
    <desc>Interrupt Priority Register_0</desc>
  </register>
  <register offset="0xf8f0143c" type="rw" uniqueid="ps7_mpcore_ICDIPR15">
    <name>ICDIPR</name>
    <desc>Interrupt Priority Register_0</desc>
  </register>
  <register offset="0xf8f01440" type="rw" uniqueid="ps7_mpcore_ICDIPR16">
    <name>ICDIPR</name>
    <desc>Interrupt Priority Register_0</desc>
  </register>
  <register offset="0xf8f01444" type="rw" uniqueid="ps7_mpcore_ICDIPR17">
    <name>ICDIPR</name>
    <desc>Interrupt Priority Register_0</desc>
  </register>
  <register offset="0xf8f01448" type="rw" uniqueid="ps7_mpcore_ICDIPR18">
    <name>ICDIPR</name>
    <desc>Interrupt Priority Register_0</desc>
  </register>
  <register offset="0xf8f0144c" type="rw" uniqueid="ps7_mpcore_ICDIPR19">
    <name>ICDIPR</name>
    <desc>Interrupt Priority Register_0</desc>
  </register>
  <register offset="0xf8f01450" type="rw" uniqueid="ps7_mpcore_ICDIPR20">
    <name>ICDIPR</name>
    <desc>Interrupt Priority Register_0</desc>
  </register>
  <register offset="0xf8f01454" type="rw" uniqueid="ps7_mpcore_ICDIPR21">
    <name>ICDIPR</name>
    <desc>Interrupt Priority Register_0</desc>
  </register>
  <register offset="0xf8f01458" type="rw" uniqueid="ps7_mpcore_ICDIPR22">
    <name>ICDIPR</name>
    <desc>Interrupt Priority Register_0</desc>
  </register>
  <register offset="0xf8f0145c" type="rw" uniqueid="ps7_mpcore_ICDIPR23">
    <name>ICDIPR</name>
    <desc>Interrupt Priority Register_0</desc>
  </register>
  <register offset="0xf8f01800" type="rw" uniqueid="ps7_mpcore_ICDIPTR0">
    <name>ICDIPTR</name>
    <desc>Interrupt Processor Targets Register_0</desc>
  </register>
  <register offset="0xf8f01804" type="rw" uniqueid="ps7_mpcore_ICDIPTR1">
    <name>ICDIPTR</name>
    <desc>Interrupt Processor Targets Register_0</desc>
  </register>
  <register offset="0xf8f01808" type="rw" uniqueid="ps7_mpcore_ICDIPTR2">
    <name>ICDIPTR</name>
    <desc>Interrupt Processor Targets Register_0</desc>
  </register>
  <register offset="0xf8f0180c" type="rw" uniqueid="ps7_mpcore_ICDIPTR3">
    <name>ICDIPTR</name>
    <desc>Interrupt Processor Targets Register_0</desc>
  </register>
  <register offset="0xf8f01810" type="rw" uniqueid="ps7_mpcore_ICDIPTR4">
    <name>ICDIPTR</name>
    <desc>Interrupt Processor Targets Register_0</desc>
  </register>
  <register offset="0xf8f01814" type="rw" uniqueid="ps7_mpcore_ICDIPTR5">
    <name>ICDIPTR</name>
    <desc>Interrupt Processor Targets Register_0</desc>
  </register>
  <register offset="0xf8f01818" type="rw" uniqueid="ps7_mpcore_ICDIPTR6">
    <name>ICDIPTR</name>
    <desc>Interrupt Processor Targets Register_0</desc>
  </register>
  <register offset="0xf8f0181c" type="rw" uniqueid="ps7_mpcore_ICDIPTR7">
    <name>ICDIPTR</name>
    <desc>Interrupt Processor Targets Register_0</desc>
  </register>
  <register offset="0xf8f01820" type="rw" uniqueid="ps7_mpcore_ICDIPTR8">
    <name>ICDIPTR</name>
    <desc>Interrupt Processor Targets Register_0</desc>
  </register>
  <register offset="0xf8f01824" type="rw" uniqueid="ps7_mpcore_ICDIPTR9">
    <name>ICDIPTR</name>
    <desc>Interrupt Processor Targets Register_0</desc>
  </register>
  <register offset="0xf8f01828" type="rw" uniqueid="ps7_mpcore_ICDIPTR10">
    <name>ICDIPTR</name>
    <desc>Interrupt Processor Targets Register_0</desc>
  </register>
  <register offset="0xf8f0182c" type="rw" uniqueid="ps7_mpcore_ICDIPTR11">
    <name>ICDIPTR</name>
    <desc>Interrupt Processor Targets Register_0</desc>
  </register>
  <register offset="0xf8f01830" type="rw" uniqueid="ps7_mpcore_ICDIPTR12">
    <name>ICDIPTR</name>
    <desc>Interrupt Processor Targets Register_0</desc>
  </register>
  <register offset="0xf8f01834" type="rw" uniqueid="ps7_mpcore_ICDIPTR13">
    <name>ICDIPTR</name>
    <desc>Interrupt Processor Targets Register_0</desc>
  </register>
  <register offset="0xf8f01838" type="rw" uniqueid="ps7_mpcore_ICDIPTR14">
    <name>ICDIPTR</name>
    <desc>Interrupt Processor Targets Register_0</desc>
  </register>
  <register offset="0xf8f0183c" type="rw" uniqueid="ps7_mpcore_ICDIPTR15">
    <name>ICDIPTR</name>
    <desc>Interrupt Processor Targets Register_0</desc>
  </register>
  <register offset="0xf8f01840" type="rw" uniqueid="ps7_mpcore_ICDIPTR16">
    <name>ICDIPTR</name>
    <desc>Interrupt Processor Targets Register_0</desc>
  </register>
  <register offset="0xf8f01844" type="rw" uniqueid="ps7_mpcore_ICDIPTR17">
    <name>ICDIPTR</name>
    <desc>Interrupt Processor Targets Register_0</desc>
  </register>
  <register offset="0xf8f01848" type="rw" uniqueid="ps7_mpcore_ICDIPTR18">
    <name>ICDIPTR</name>
    <desc>Interrupt Processor Targets Register_0</desc>
  </register>
  <register offset="0xf8f0184c" type="rw" uniqueid="ps7_mpcore_ICDIPTR19">
    <name>ICDIPTR</name>
    <desc>Interrupt Processor Targets Register_0</desc>
  </register>
  <register offset="0xf8f01850" type="rw" uniqueid="ps7_mpcore_ICDIPTR20">
    <name>ICDIPTR</name>
    <desc>Interrupt Processor Targets Register_0</desc>
  </register>
  <register offset="0xf8f01854" type="rw" uniqueid="ps7_mpcore_ICDIPTR21">
    <name>ICDIPTR</name>
    <desc>Interrupt Processor Targets Register_0</desc>
  </register>
  <register offset="0xf8f01858" type="rw" uniqueid="ps7_mpcore_ICDIPTR22">
    <name>ICDIPTR</name>
    <desc>Interrupt Processor Targets Register_0</desc>
  </register>
  <register offset="0xf8f0185c" type="rw" uniqueid="ps7_mpcore_ICDIPTR23">
    <name>ICDIPTR</name>
    <desc>Interrupt Processor Targets Register_0</desc>
  </register>
  <register offset="0xf8f01c00" type="rw" uniqueid="ps7_mpcore_ICDICFR0">
    <name>ICDICFR0</name>
    <desc>Interrupt Configuration Register 0</desc>
  </register>
  <register offset="0xf8f01c04" type="rw" uniqueid="ps7_mpcore_ICDICFR1">
    <name>ICDICFR1</name>
    <desc>Interrupt Configuration Register 1</desc>
  </register>
  <register offset="0xf8f01c08" type="rw" uniqueid="ps7_mpcore_ICDICFR2">
    <name>ICDICFR2</name>
    <desc>Interrupt Configuration Register 2</desc>
  </register>
  <register offset="0xf8f01c0c" type="rw" uniqueid="ps7_mpcore_ICDICFR3">
    <name>ICDICFR3</name>
    <desc>Interrupt Configuration Register 3</desc>
  </register>
  <register offset="0xf8f01c10" type="rw" uniqueid="ps7_mpcore_ICDICFR4">
    <name>ICDICFR4</name>
    <desc>Interrupt Configuration Register 4</desc>
  </register>
  <register offset="0xf8f01c14" type="rw" uniqueid="ps7_mpcore_ICDICFR5">
    <name>ICDICFR5</name>
    <desc>Interrupt Configuration Register 5</desc>
  </register>
  <register offset="0xf8f01d00" type="ro" uniqueid="ps7_mpcore_ppi_status">
    <name>ppi_status</name>
    <desc>PPI Status Register</desc>
  </register>
  <register offset="0xf8f01d04" type="ro" uniqueid="ps7_mpcore_spi_status_0">
    <name>spi_status_0</name>
    <desc>SPI Status Register 0</desc>
  </register>
  <register offset="0xf8f01d08" type="rw" uniqueid="ps7_mpcore_spi_status_1">
    <name>spi_status_1</name>
    <desc>SPI Status Register 1</desc>
  </register>
  <register offset="0xf8f01d0c" type="rw" uniqueid="ps7_mpcore_spi_status_2">
    <name>spi_status_2</name>
    <desc>SPI Status Register 2</desc>
  </register>
  <register offset="0xf8f01f00" type="rw" uniqueid="ps7_mpcore_ICDSGIR">
    <name>ICDSGIR</name>
    <desc>Software Generated Interrupt Register</desc>
  </register>
  <register offset="0xf8f01fd0" type="rw" uniqueid="ps7_mpcore_ICPIDR4">
    <name>ICPIDR4</name>
    <desc>Peripheral ID4</desc>
  </register>
  <register offset="0xf8f01fd4" type="rw" uniqueid="ps7_mpcore_ICPIDR5">
    <name>ICPIDR5</name>
    <desc>Peripheral ID5</desc>
  </register>
  <register offset="0xf8f01fd8" type="rw" uniqueid="ps7_mpcore_ICPIDR6">
    <name>ICPIDR6</name>
    <desc>Peripheral ID6</desc>
  </register>
  <register offset="0xf8f01fdc" type="rw" uniqueid="ps7_mpcore_ICPIDR7">
    <name>ICPIDR7</name>
    <desc>Peripheral ID7</desc>
  </register>
  <register offset="0xf8f01fe0" type="rw" uniqueid="ps7_mpcore_ICPIDR0">
    <name>ICPIDR0</name>
    <desc>Peripheral ID0</desc>
  </register>
  <register offset="0xf8f01fe4" type="rw" uniqueid="ps7_mpcore_ICPIDR1">
    <name>ICPIDR1</name>
    <desc>Peripheral ID1</desc>
  </register>
  <register offset="0xf8f01fe8" type="rw" uniqueid="ps7_mpcore_ICPIDR2">
    <name>ICPIDR2</name>
    <desc>Peripheral ID2</desc>
  </register>
  <register offset="0xf8f01fec" type="rw" uniqueid="ps7_mpcore_ICPIDR3">
    <name>ICPIDR3</name>
    <desc>Peripheral ID3</desc>
  </register>
  <register offset="0xf8f01ff0" type="rw" uniqueid="ps7_mpcore_ICCIDR0">
    <name>ICCIDR0</name>
    <desc>Component ID0</desc>
  </register>
  <register offset="0xf8f01ff4" type="rw" uniqueid="ps7_mpcore_ICCIDR1">
    <name>ICCIDR1</name>
    <desc>Component ID1</desc>
  </register>
  <register offset="0xf8f01ff8" type="rw" uniqueid="ps7_mpcore_ICCIDR2">
    <name>ICCIDR2</name>
    <desc>Component ID2</desc>
  </register>
  <register offset="0xf8f01ffc" type="rw" uniqueid="ps7_mpcore_ICCIDR3">
    <name>ICCIDR3</name>
    <desc>Component ID3</desc>
  </register>
  <register offset="0xf8801004" type="ro" uniqueid="ps7_debug_etb_RDP">
    <name>RDP</name>
    <desc>RAM Depth Register</desc>
  </register>
  <register offset="0xf880100c" type="ro" uniqueid="ps7_debug_etb_STS">
    <name>STS</name>
    <desc>Status Register</desc>
  </register>
  <register offset="0xf8801010" type="ro" uniqueid="ps7_debug_etb_RRD">
    <name>RRD</name>
    <desc>RAM Read Data Register</desc>
  </register>
  <register offset="0xf8801014" type="rw" uniqueid="ps7_debug_etb_RRP">
    <name>RRP</name>
    <desc>RAM Read Pointer Register</desc>
  </register>
  <register offset="0xf8801018" type="rw" uniqueid="ps7_debug_etb_RWP">
    <name>RWP</name>
    <desc>RAM Write Pointer Register</desc>
  </register>
  <register offset="0xf880101c" type="rw" uniqueid="ps7_debug_etb_TRG">
    <name>TRG</name>
    <desc>Trigger Counter Register</desc>
  </register>
  <register offset="0xf8801020" type="rw" uniqueid="ps7_debug_etb_CTL">
    <name>CTL</name>
    <desc>Control Register</desc>
  </register>
  <register offset="0xf8801024" type="rw" uniqueid="ps7_debug_etb_RWD">
    <name>RWD</name>
    <desc>RAM Write Data Register</desc>
  </register>
  <register offset="0xf8801300" type="ro" uniqueid="ps7_debug_etb_FFSR">
    <name>FFSR</name>
    <desc>Formatter and Flush Status Register</desc>
  </register>
  <register offset="0xf8801304" type="rw" uniqueid="ps7_debug_etb_FFCR">
    <name>FFCR</name>
    <desc>Formatter and Flush Control Register</desc>
  </register>
  <register offset="0xf8801ee0" type="wo" uniqueid="ps7_debug_etb_ITMISCOP0">
    <name>ITMISCOP0</name>
    <desc>Integration Test Miscellaneous Output Register 0</desc>
  </register>
  <register offset="0xf8801ee4" type="wo" uniqueid="ps7_debug_etb_ITTRFLINACK">
    <name>ITTRFLINACK</name>
    <desc>Integration Test Trigger In and Flush In Acknowledge Register</desc>
  </register>
  <register offset="0xf8801ee8" type="wo" uniqueid="ps7_debug_etb_ITTRFLIN">
    <name>ITTRFLIN</name>
    <desc>Integration Test Trigger In and Flush In Register</desc>
  </register>
  <register offset="0xf8801eec" type="ro" uniqueid="ps7_debug_etb_ITATBDATA0">
    <name>ITATBDATA0</name>
    <desc>Integration Test ATB Data Register</desc>
  </register>
  <register offset="0xf8801ef0" type="wo" uniqueid="ps7_debug_etb_ITATBCTR2">
    <name>ITATBCTR2</name>
    <desc>Integration Test ATB Control Register 2</desc>
  </register>
  <register offset="0xf8801ef4" type="ro" uniqueid="ps7_debug_etb_ITATBCTR1">
    <name>ITATBCTR1</name>
    <desc>Integration Test ATB Control Register 1</desc>
  </register>
  <register offset="0xf8801ef8" type="ro" uniqueid="ps7_debug_etb_ITATBCTR0">
    <name>ITATBCTR0</name>
    <desc>Integration Test ATB Control Register 0</desc>
  </register>
  <register offset="0xf8801f00" type="rw" uniqueid="ps7_debug_etb_IMCR">
    <name>IMCR</name>
    <desc>Integration Mode Control Register</desc>
  </register>
  <register offset="0xf8801fa0" type="rw" uniqueid="ps7_debug_etb_CTSR">
    <name>CTSR</name>
    <desc>Claim Tag Set Register</desc>
  </register>
  <register offset="0xf8801fa4" type="rw" uniqueid="ps7_debug_etb_CTCR">
    <name>CTCR</name>
    <desc>Claim Tag Clear Register</desc>
  </register>
  <register offset="0xf8801fb0" type="wo" uniqueid="ps7_debug_etb_LAR">
    <name>LAR</name>
    <desc>Lock Access Register</desc>
  </register>
  <register offset="0xf8801fb4" type="ro" uniqueid="ps7_debug_etb_LSR">
    <name>LSR</name>
    <desc>Lock Status Register</desc>
  </register>
  <register offset="0xf8801fb8" type="ro" uniqueid="ps7_debug_etb_ASR">
    <name>ASR</name>
    <desc>Authentication Status Register</desc>
  </register>
  <register offset="0xf8801fc8" type="ro" uniqueid="ps7_debug_etb_DEVID">
    <name>DEVID</name>
    <desc>Device ID</desc>
  </register>
  <register offset="0xf8801fcc" type="ro" uniqueid="ps7_debug_etb_DTIR">
    <name>DTIR</name>
    <desc>Device Type Identifier Register</desc>
  </register>
  <register offset="0xf8801fd0" type="ro" uniqueid="ps7_debug_etb_PERIPHID4">
    <name>PERIPHID4</name>
    <desc>Peripheral ID4</desc>
  </register>
  <register offset="0xf8801fd4" type="ro" uniqueid="ps7_debug_etb_PERIPHID5">
    <name>PERIPHID5</name>
    <desc>Peripheral ID5</desc>
  </register>
  <register offset="0xf8801fd8" type="ro" uniqueid="ps7_debug_etb_PERIPHID6">
    <name>PERIPHID6</name>
    <desc>Peripheral ID6</desc>
  </register>
  <register offset="0xf8801fdc" type="ro" uniqueid="ps7_debug_etb_PERIPHID7">
    <name>PERIPHID7</name>
    <desc>Peripheral ID7</desc>
  </register>
  <register offset="0xf8801fe0" type="ro" uniqueid="ps7_debug_etb_PERIPHID0">
    <name>PERIPHID0</name>
    <desc>Peripheral ID0</desc>
  </register>
  <register offset="0xf8801fe4" type="ro" uniqueid="ps7_debug_etb_PERIPHID1">
    <name>PERIPHID1</name>
    <desc>Peripheral ID1</desc>
  </register>
  <register offset="0xf8801fe8" type="ro" uniqueid="ps7_debug_etb_PERIPHID2">
    <name>PERIPHID2</name>
    <desc>Peripheral ID2</desc>
  </register>
  <register offset="0xf8801fec" type="ro" uniqueid="ps7_debug_etb_PERIPHID3">
    <name>PERIPHID3</name>
    <desc>Peripheral ID3</desc>
  </register>
  <register offset="0xf8801ff0" type="ro" uniqueid="ps7_debug_etb_COMPID0">
    <name>COMPID0</name>
    <desc>Component ID0</desc>
  </register>
  <register offset="0xf8801ff4" type="ro" uniqueid="ps7_debug_etb_COMPID1">
    <name>COMPID1</name>
    <desc>Component ID1</desc>
  </register>
  <register offset="0xf8801ff8" type="ro" uniqueid="ps7_debug_etb_COMPID2">
    <name>COMPID2</name>
    <desc>Component ID2</desc>
  </register>
  <register offset="0xf8801ffc" type="ro" uniqueid="ps7_debug_etb_COMPID3">
    <name>COMPID3</name>
    <desc>Component ID3</desc>
  </register>
  <register offset="0xe000e000" type="ro" uniqueid="ps7_smcc_memc_status">
    <name>memc_status</name>
    <desc>The read-only memc_status Register provides information on the configuration of the SMC and also the current state of the SMC. You cannot read this register in the Reset state</desc>
  </register>
  <register offset="0xe000e004" type="ro" uniqueid="ps7_smcc_memif_cfg">
    <name>memif_cfg</name>
    <desc>The read-only memif_cfg Register provides information on the configuration of the memory interface. You cannot read this register in the Reset state</desc>
  </register>
  <register offset="0xe000e008" type="wo" uniqueid="ps7_smcc_memc_cfg_set">
    <name>memc_cfg_set</name>
    <desc>The write-only memc_cfg_set Register enables the SMC to be changed to low-power state, and interrupts enabled. You cannot write to this register in the Reset state.</desc>
  </register>
  <register offset="0xe000e00c" type="wo" uniqueid="ps7_smcc_memc_cfg_clr">
    <name>memc_cfg_clr</name>
    <desc>The write-only memc_cfg_clr Register enables the SMC to be moved out of the low-power state, and the interrupts disabled. You cannot write to this register in the Reset state</desc>
  </register>
  <register offset="0xe000e010" type="wo" uniqueid="ps7_smcc_direct_cmd">
    <name>direct_cmd</name>
    <desc>The write-only direct_cmd Register passes commands to the external memory, and controls the updating of the chip configuration registers with values held in the set_cycles Register and set_opmode Register. You cannot write to this register in either the Reset or low-power states</desc>
  </register>
  <register offset="0xe000e014" type="wo" uniqueid="ps7_smcc_set_cycles">
    <name>set_cycles</name>
    <desc>This write-only register contains values that are written to the sram_cycles register or nand_cycles when the SMC receives a write to the Direct Command Register.You cannot write to this register in either the Reset or low-power states.</desc>
  </register>
  <register offset="0xe000e018" type="rw" uniqueid="ps7_smcc_set_opmode">
    <name>set_opmode</name>
    <desc>This write-only register is the holding register for the opmode&lt;x&gt;_&lt;n&gt; Registers. You cannot write to it in either the Reset or low-power states</desc>
  </register>
  <register offset="0xe000e020" type="rw" uniqueid="ps7_smcc_refresh_period_0">
    <name>refresh_period_0</name>
    <desc>The read/write refresh_period_0 Register enables the SMC to insert idle cycles during consecutive bursts, that enables the PSRAM devices on memory interface 0, to initiate a refresh cycle. You cannot access this register in either the Reset or low-power states.
Note
You can only access this register when you are using an SRAM memory interface.</desc>
  </register>
  <register offset="0xe000e024" type="rw" uniqueid="ps7_smcc_refresh_period_1">
    <name>refresh_period_1</name>
    <desc>The read/write refresh_period_1 Register enables the SMC to insert idle cycles during consecutive bursts, that enables the PSRAM devices on memory interface 1, to initiate a refresh cycle</desc>
  </register>
  <register offset="0xe000e100" type="ro" uniqueid="ps7_smcc_sram_cycles0_0">
    <name>sram_cycles0_0</name>
    <desc>There is an instance of this register for each SRAM chip supported. You cannot read the read-only sram_cycles Register in the Reset state</desc>
  </register>
  <register offset="0xe000e104" type="ro" uniqueid="ps7_smcc_opmode0_0">
    <name>opmode0_0</name>
    <desc>There is an instance of the opmode Register for each chip supported. This register is read-only and you cannot read it in the Reset state</desc>
  </register>
  <register offset="0xe000e120" type="ro" uniqueid="ps7_smcc_sram_cycles0_1">
    <name>sram_cycles0_1</name>
    <desc>There is an instance of this register for each SRAM chip supported. You cannot read the read-only sram_cycles Register in the Reset state</desc>
  </register>
  <register offset="0xe000e124" type="ro" uniqueid="ps7_smcc_opmode0_1">
    <name>opmode0_1</name>
    <desc>There is an instance of the opmode Register for each chip supported. This register is read-only and you cannot read it in the Reset state.</desc>
  </register>
  <register offset="0xe000e180" type="ro" uniqueid="ps7_smcc_nand_cycles1_0">
    <name>nand_cycles1_0</name>
    <desc>There is an instance of this register for each NAND chip supported. You cannot read the read-only nand_cycles Register in the Reset state</desc>
  </register>
  <register offset="0xe000e184" type="ro" uniqueid="ps7_smcc_opmode1_0">
    <name>opmode1_0</name>
    <desc>There is an instance of the opmode Register for each chip supported. This register is read-only and you cannot read it in the Reset state</desc>
  </register>
  <register offset="0xe000e200" type="ro" uniqueid="ps7_smcc_user_status">
    <name>user_status</name>
    <desc>The user_status Register is read-only and returns the value of the user_status[7:0] signals. You can read this register in all operating states</desc>
  </register>
  <register offset="0xe000e204" type="wo" uniqueid="ps7_smcc_user_config">
    <name>user_config</name>
    <desc>The user_config Register is write-only and controls the status of the user_config[7:0] signals. You can write to this register in all operating states</desc>
  </register>
  <register offset="0xe000e300" type="ro" uniqueid="ps7_smcc_ecc_status_0">
    <name>ecc_status_0</name>
    <desc>The ecc_status Register is read-only and contains status information for the ECC. Although this is a read-only register, the bottom five bits can be written to clear the corresponding interrupts.To clear the interrupt, you must write a 1 to the appropriate bit.</desc>
  </register>
  <register offset="0xe000e304" type="rw" uniqueid="ps7_smcc_ecc_memcfg_0">
    <name>ecc_memcfg_0</name>
    <desc>The ecc_memcfg Register is read-write and contains information about the structure of the memory. Note
You must not write to this register while the ECC block is busy. You can read the current ECC block status from the ECC Status Register</desc>
  </register>
  <register offset="0xe000e308" type="rw" uniqueid="ps7_smcc_ecc_memcommand1_0">
    <name>ecc_memcommand1_0</name>
    <desc>The ecc_memcommand1 Register is read-write and contains the commands that the ECC block uses to detect the start of an ECC operation</desc>
  </register>
  <register offset="0xe000e30c" type="rw" uniqueid="ps7_smcc_ecc_memcommand2_0">
    <name>ecc_memcommand2_0</name>
    <desc>The ecc_memcommand2 Register is read-write and contains the commands that the ECC block uses to access different parts of a NAND page. The reset value is suitable for ONFI 1.0 compliant devices</desc>
  </register>
  <register offset="0xe000e310" type="ro" uniqueid="ps7_smcc_ecc_addr0_0">
    <name>ecc_addr0_0</name>
    <desc>The ecc_addr0 Register is read-only and contains the lower 32 bits of the ECC address</desc>
  </register>
  <register offset="0xe000e314" type="ro" uniqueid="ps7_smcc_ecc_addr1_0">
    <name>ecc_addr1_0</name>
    <desc>The ecc_addr1 Register is read-only and contains the upper 24 bits of the ECC address</desc>
  </register>
  <register offset="0xe000e318" type="ro" uniqueid="ps7_smcc_ecc_value0_0">
    <name>ecc_value0_0</name>
    <desc>The five ecc_value Registers are read-only and contain block information for the ECC.
Note
Writing any value to an ecc_value Register clears the ecc_int bit.</desc>
  </register>
  <register offset="0xe000e31c" type="ro" uniqueid="ps7_smcc_ecc_value1_0">
    <name>ecc_value1_0</name>
    <desc>The five ecc_value Registers are read-only and contain block information for the ECC.
Note
Writing any value to an ecc_value Register clears the ecc_int bit.</desc>
  </register>
  <register offset="0xe000e320" type="ro" uniqueid="ps7_smcc_ecc_value2_0">
    <name>ecc_value2_0</name>
    <desc>The five ecc_value Registers are read-only and contain block information for the ECC.
Note
Writing any value to an ecc_value Register clears the ecc_int bit.</desc>
  </register>
  <register offset="0xe000e324" type="ro" uniqueid="ps7_smcc_ecc_value3_0">
    <name>ecc_value3_0</name>
    <desc>The five ecc_value Registers are read-only and contain block information for the ECC.
Note
Writing any value to an ecc_value Register clears the ecc_int bit.</desc>
  </register>
  <register offset="0xe000e400" type="ro" uniqueid="ps7_smcc_ecc_status_1">
    <name>ecc_status_1</name>
    <desc>The ecc_status Register is read-only and contains status information for the ECC. Although this is a read-only register, the bottom five bits can be written to clear the corresponding interrupts.</desc>
  </register>
  <register offset="0xe000e404" type="rw" uniqueid="ps7_smcc_ecc_memcfg_1">
    <name>ecc_memcfg_1</name>
    <desc>The ecc_memcfg Register is read-write and contains information about the structure of the memory. Note
You must not write to this register while the ECC block is busy. You can read the current ECC block status from the ECC Status Register</desc>
  </register>
  <register offset="0xe000e408" type="rw" uniqueid="ps7_smcc_ecc_memcommand1_1">
    <name>ecc_memcommand1_1</name>
    <desc>The ecc_memcommand1 Register is read-write and contains the commands that the ECC block uses to detect the start of an ECC operation</desc>
  </register>
  <register offset="0xe000e40c" type="rw" uniqueid="ps7_smcc_ecc_memcommand2_1">
    <name>ecc_memcommand2_1</name>
    <desc>The ecc_memcommand2 Register is read-write and contains the commands that the ECC block uses to access different parts of a NAND page. The reset value is suitable for ONFI 1.0 compliant devices</desc>
  </register>
  <register offset="0xe000e410" type="ro" uniqueid="ps7_smcc_ecc_addr0_1">
    <name>ecc_addr0_1</name>
    <desc>The ecc_addr0 Register is read-only and contains the lower 32 bits of the ECC address</desc>
  </register>
  <register offset="0xe000e414" type="ro" uniqueid="ps7_smcc_ecc_addr1_1">
    <name>ecc_addr1_1</name>
    <desc>The ecc_addr1 Register is read-only and contains the upper 24 bits of the ECC address</desc>
  </register>
  <register offset="0xe000e418" type="ro" uniqueid="ps7_smcc_ecc_value0_1">
    <name>ecc_value0_1</name>
    <desc>The five ecc_value Registers are read-only and contain block information for the ECC.
Note
Writing any value to an ecc_value Register clears the ecc_int bit.</desc>
  </register>
  <register offset="0xe000e41c" type="ro" uniqueid="ps7_smcc_ecc_value1_1">
    <name>ecc_value1_1</name>
    <desc>The five ecc_value Registers are read-only and contain block information for the ECC.
Note
Writing any value to an ecc_value Register clears the ecc_int bit.</desc>
  </register>
  <register offset="0xe000e420" type="ro" uniqueid="ps7_smcc_ecc_value2_1">
    <name>ecc_value2_1</name>
    <desc>The five ecc_value Registers are read-only and contain block information for the ECC.
Note
Writing any value to an ecc_value Register clears the ecc_int bit.</desc>
  </register>
  <register offset="0xe000e424" type="ro" uniqueid="ps7_smcc_ecc_value3_1">
    <name>ecc_value3_1</name>
    <desc>The five ecc_value Registers are read-only and contain block information for the ECC.
Note
Writing any value to an ecc_value Register clears the ecc_int bit.</desc>
  </register>
  <register offset="0xe000ee00" type="rw" uniqueid="ps7_smcc_integration_test">
    <name>integration_test</name>
    <desc>The read/write int_cfg Register selects the integration test registers. This register is only for test. You cannot read or write to this register in the Reset state.</desc>
  </register>
  <register offset="0xe000efe0" type="ro" uniqueid="ps7_smcc_periph_id_0">
    <name>periph_id_0</name>
    <desc>The periph_id_0 Register is hard-coded and the fields in the register determine the reset value</desc>
  </register>
  <register offset="0xe000efe4" type="ro" uniqueid="ps7_smcc_periph_id_1">
    <name>periph_id_1</name>
    <desc>The periph_id_1 Register is hard-coded and the fields in the register determine the reset value.</desc>
  </register>
  <register offset="0xe000efe8" type="ro" uniqueid="ps7_smcc_periph_id_2">
    <name>periph_id_2</name>
    <desc>The periph_id_2 Register is hard-coded and the fields in the register determine the reset value.</desc>
  </register>
  <register offset="0xe000efec" type="ro" uniqueid="ps7_smcc_periph_id_3">
    <name>periph_id_3</name>
    <desc>The periph_id_3 Register is hard-coded and the fields in the register determine the reset value.</desc>
  </register>
  <register offset="0xe000eff0" type="ro" uniqueid="ps7_smcc_pcell_id_0">
    <name>pcell_id_0</name>
    <desc>The pcell_id_0 Register is hard-coded and the fields in the register determine the reset value</desc>
  </register>
  <register offset="0xe000eff4" type="ro" uniqueid="ps7_smcc_pcell_id_1">
    <name>pcell_id_1</name>
    <desc>The pcell_id_1 Register is hard-coded and the fields in the register determine the reset value</desc>
  </register>
  <register offset="0xe000eff8" type="ro" uniqueid="ps7_smcc_pcell_id_2">
    <name>pcell_id_2</name>
    <desc>The pcell_id_2 Register is hard-coded and the fields in the register determine the reset value</desc>
  </register>
  <register offset="0xe000effc" type="ro" uniqueid="ps7_smcc_pcell_id_3">
    <name>pcell_id_3</name>
    <desc>The pcell_id_3 Register is hard-coded and the fields in the register determine the reset value</desc>
  </register>
 <register offset="0xe2000000" type="ro" uniqueid="ps7_smcc_nor_cs0">
    <name>NOR CS0 DATA</name>
    <desc>--</desc>
  </register>

 <register offset="0xe4000000" type="ro" uniqueid="ps7_smcc_nor_cs1">
    <name>NOR CS1 DATA</name>
    <desc>--</desc>
  </register>
</registers>
