<?xml version="1.0" encoding="iso-8859-1" ?>
<!DOCTYPE parameters PUBLIC "presets" "presets.dtd" >
<presets>

  <preset param="pcw_nor_peripheral_enable" name="0" strength="7">
      <disable param="pcw_nor_peripheral_freqmhz"/>
      <disable param="pcw_nor_nor_io"/>
      <disable param="pcw_nor_grp_a25_enable"/>
      <disable param="pcw_nor_grp_cs0_enable"/>
      <disable param="pcw_nor_grp_cs1_enable"/>
      <disable param="pcw_nor_grp_sram_cs0_enable"/>
      <disable param="pcw_nor_grp_sram_cs1_enable"/>
      <disable param="pcw_nor_grp_sram_int_enable"/>
  </preset>
  <preset param="pcw_nor_peripheral_enable" name="" strength="7">
      <disable param="pcw_nor_peripheral_freqmhz"/>
      <disable param="pcw_nor_nor_io"/>
      <disable param="pcw_nor_grp_a25_enable"/>
      <disable param="pcw_nor_grp_cs0_enable"/>
      <disable param="pcw_nor_grp_cs1_enable"/>
      <disable param="pcw_nor_grp_sram_cs0_enable"/>
      <disable param="pcw_nor_grp_sram_cs1_enable"/>
      <disable param="pcw_nor_grp_sram_int_enable"/>
  </preset>
  <preset param="pcw_nor_peripheral_enable" name="1" strength="7">
      <disable param="pcw_qspi_peripheral_enable"/>
      <disable param="pcw_qspi_qspi_io"/>
      <disable param="pcw_qspi_grp_ss1_enable"/>
      <disable param="pcw_qspi_grp_io1_enable"/>
      <disable param="pcw_qspi_grp_fbclk_enable"/>
      <disable param="pcw_nand_peripheral_enable"/>
      <disable param="pcw_nand_nand_io"/>
      <disable param="pcw_nand_grp_d8_enable"/>
      <set param="pcw_nor_nor_io" value="MIO 3 .. 39" />
      <set param="pcw_smc_peripheral_valid" value="1"/>
      <set param="ps7_smcc_set_opmode_set_bls" value="1"/>
  </preset>



  <preset param="pcw_nor_grp_a25_enable" name="0" strength="6">
      <disable param="pcw_nor_grp_a25_io"/>
  </preset>
  <preset param="pcw_nor_grp_a25_enable" name="" strength="6">
      <disable param="pcw_nor_grp_a25_io"/>
  </preset>
  <preset param="pcw_nor_grp_a25_enable" name="1" strength="6">
    <set param="pcw_nor_grp_a25_io" value="MIO 1" />
    <disable param="pcw_nor_grp_cs1_enable"/>
    <disable param="pcw_nor_grp_sram_cs1_enable"/>
    <set param="pcw_nor_internal_a25" value="1" />
  </preset>

  <preset param="pcw_nor_grp_sram_int_enable" name="" strength="6">
      <disable param="pcw_nor_grp_sram_int_io"/>
  </preset>
  <preset param="pcw_nor_grp_sram_int_enable" name="0" strength="6">
      <disable param="pcw_nor_grp_sram_int_io"/>
  </preset>
  <preset param="pcw_nor_grp_sram_int_enable" name="1" strength="6">
    <set param="pcw_nor_grp_sram_int_io" value="EMIO" />
    <disable param="pcw_nor_grp_sram_int_io" />
    <set param="pcw_en_emio_sram_int" value="1" />
  </preset>

  <preset param="pcw_nor_grp_sram_int_io" name="EMIO" strength="5">
  </preset>


  <preset param="pcw_nor_grp_cs0_enable" name="" strength="6">
      <disable param="pcw_nor_grp_cs0_io"/>
  </preset>
  <preset param="pcw_nor_grp_cs0_enable" name="0" strength="6">
      <disable param="pcw_nor_grp_cs0_io"/>
  </preset>
  <preset param="pcw_nor_grp_cs0_enable" name="1" strength="6">
    <set param="pcw_nor_grp_cs0_io" value="MIO 0" />
    <set param="pcw_nor_internal_cs0" value="1" />
    <disable param="pcw_nor_grp_sram_cs0_enable"/>
  </preset>

  <preset param="pcw_nor_grp_sram_cs0_enable" name="" strength="6">
      <disable param="pcw_nor_grp_sram_cs0_io"/>
  </preset>
  <preset param="pcw_nor_grp_sram_cs0_enable" name="0" strength="6">
      <disable param="pcw_nor_grp_sram_cs0_io"/>
  </preset>
  <preset param="pcw_nor_grp_sram_cs0_enable" name="1" strength="6">
    <set param="pcw_nor_grp_sram_cs0_io" value="MIO 0" />
    <disable param="pcw_nor_grp_cs0_enable"/>
    <set param="pcw_nor_internal_sram_cs0" value="1" />
  </preset>


  <preset param="pcw_nor_grp_cs1_enable" name="0" strength="6">
      <disable param="pcw_nor_grp_cs1_io"/>
  </preset>
  <preset param="pcw_nor_grp_cs1_enable" name="" strength="6">
      <disable param="pcw_nor_grp_cs1_io"/>
  </preset>
  <preset param="pcw_nor_grp_cs1_enable" name="1" strength="6">
    <set param="pcw_nor_grp_cs1_io" value="MIO 1" />
    <disable param="pcw_nor_grp_a25_enable"/>
    <disable param="pcw_nor_grp_sram_cs1_enable"/>
    <set param="pcw_nor_internal_cs1" value="1" />
  </preset>

  <preset param="pcw_nor_grp_sram_cs1_enable" name="" strength="6">
      <disable param="pcw_nor_grp_sram_cs1_io"/>
  </preset>
  <preset param="pcw_nor_grp_sram_cs0_enable" name="0" strength="6">
      <disable param="pcw_nor_grp_sram_cs1_io"/>
  </preset>
  <preset param="pcw_nor_grp_sram_cs1_enable" name="1" strength="6">
    <set param="pcw_nor_grp_sram_cs1_io" value="MIO 1" />
    <disable param="pcw_nor_grp_cs1_enable"/>
    <disable param="pcw_nor_grp_a25_enable"/>
    <set param="pcw_nor_internal_sram_cs1" value="1" />
  </preset>





  <preset param="pcw_nor_nor_io" name="MIO 3 .. 39" strength="5">

      <set param="pcw_nor_data[0]_io" value="MIO 3" />
      <set param="pcw_mio_mio[3]_signal" value="data[0]" />
      <set param="pcw_mio_mio[3]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[3]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_3" value="nor" />

      <set param="pcw_nor_data[1]_io" value="MIO 4" />
      <set param="pcw_mio_mio[4]_signal" value="data[1]" />
      <set param="pcw_mio_mio[4]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[4]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_4" value="nor" />

      <set param="pcw_nor_data[2]_io" value="MIO 5" />
      <set param="pcw_mio_mio[5]_signal" value="data[2]" />
      <set param="pcw_mio_mio[5]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[5]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_5" value="nor" />

      <set param="pcw_nor_data[3]_io" value="MIO 6" />
      <set param="pcw_mio_mio[6]_signal" value="data[3]" />
      <set param="pcw_mio_mio[6]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[6]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_6" value="nor" />

      <set param="pcw_nor_oe_b_io" value="MIO 7" />
      <set param="pcw_mio_mio[7]_signal" value="oe_b" />
      <set param="pcw_mio_mio[7]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[7]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_7" value="nor" />

      <set param="pcw_nor_bls_b_io" value="MIO 8" />
      <set param="pcw_mio_mio[8]_signal" value="bls_b" />
      <set param="pcw_mio_mio[8]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[8]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_8" value="nor" />

      <set param="pcw_nor_data[6]_io" value="MIO 9" />
      <set param="pcw_mio_mio[9]_signal" value="data[6]" />
      <set param="pcw_mio_mio[9]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[9]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_9" value="nor" />

      <set param="pcw_nor_data[7]_io" value="MIO 10" />
      <set param="pcw_mio_mio[10]_signal" value="data[7]" />
      <set param="pcw_mio_mio[10]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[10]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_10" value="nor" />

      <set param="pcw_nor_data[4]_io" value="MIO 11" />
      <set param="pcw_mio_mio[11]_signal" value="data[4]" />
      <set param="pcw_mio_mio[11]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[11]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_11" value="nor" />

      <set param="pcw_nor_data[5]_io" value="MIO 13" />
      <set param="pcw_mio_mio[13]_signal" value="data[5]" />
      <set param="pcw_mio_mio[13]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[13]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_13" value="nor" />

      <set param="pcw_nor_addr[0]_io" value="MIO 15" />
      <set param="pcw_mio_mio[15]_signal" value="addr[0]" />
      <set param="pcw_mio_mio[15]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[15]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_15" value="nor" />

      <set param="pcw_nor_addr[1]_io" value="MIO 16" />
      <set param="pcw_mio_mio[16]_signal" value="addr[1]" />
      <set param="pcw_mio_mio[16]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[16]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_16" value="nor" />

      <set param="pcw_nor_addr[2]_io" value="MIO 17" />
      <set param="pcw_mio_mio[17]_signal" value="addr[2]" />
      <set param="pcw_mio_mio[17]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[17]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_17" value="nor" />

      <set param="pcw_nor_addr[3]_io" value="MIO 18" />
      <set param="pcw_mio_mio[18]_signal" value="addr[3]" />
      <set param="pcw_mio_mio[18]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[18]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_18" value="nor" />

      <set param="pcw_nor_addr[4]_io" value="MIO 19" />
      <set param="pcw_mio_mio[19]_signal" value="addr[4]" />
      <set param="pcw_mio_mio[19]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[19]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_19" value="nor" />

      <set param="pcw_nor_addr[5]_io" value="MIO 20" />
      <set param="pcw_mio_mio[20]_signal" value="addr[5]" />
      <set param="pcw_mio_mio[20]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[20]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_20" value="nor" />

      <set param="pcw_nor_addr[6]_io" value="MIO 21" />
      <set param="pcw_mio_mio[21]_signal" value="addr[6]" />
      <set param="pcw_mio_mio[21]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[21]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_21" value="nor" />
      <set param="pcw_nor_addr[7]_io" value="MIO 22" />
      <set param="pcw_mio_mio[22]_signal" value="addr[7]" />
      <set param="pcw_mio_mio[22]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[22]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_22" value="nor" />

      <set param="pcw_nor_addr[8]_io" value="MIO 23" />
      <set param="pcw_mio_mio[23]_signal" value="addr[8]" />
      <set param="pcw_mio_mio[23]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[23]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_23" value="nor" />

      <set param="pcw_nor_addr[9]_io" value="MIO 24" />
      <set param="pcw_mio_mio[24]_signal" value="addr[9]" />
      <set param="pcw_mio_mio[24]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[24]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_24" value="nor" />

      <set param="pcw_nor_addr[10]_io" value="MIO 25" />
      <set param="pcw_mio_mio[25]_signal" value="addr[10]" />
      <set param="pcw_mio_mio[25]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[25]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_25" value="nor" />

      <set param="pcw_nor_addr[11]_io" value="MIO 26" />
      <set param="pcw_mio_mio[26]_signal" value="addr[11]" />
      <set param="pcw_mio_mio[26]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[26]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_26" value="nor" />

      <set param="pcw_nor_addr[12]_io" value="MIO 27" />
      <set param="pcw_mio_mio[27]_signal" value="addr[12]" />
      <set param="pcw_mio_mio[27]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[27]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_27" value="nor" />

      <set param="pcw_nor_addr[13]_io" value="MIO 28" />
      <set param="pcw_mio_mio[28]_signal" value="addr[13]" />
      <set param="pcw_mio_mio[28]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[28]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_28" value="nor" />

      <set param="pcw_nor_addr[14]_io" value="MIO 29" />
      <set param="pcw_mio_mio[29]_signal" value="addr[14]" />
      <set param="pcw_mio_mio[29]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[29]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_29" value="nor" />

      <set param="pcw_nor_addr[15]_io" value="MIO 30" />
      <set param="pcw_mio_mio[30]_signal" value="addr[15]" />
      <set param="pcw_mio_mio[30]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[30]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_30" value="nor" />

      <set param="pcw_nor_addr[16]_io" value="MIO 31" />
      <set param="pcw_mio_mio[31]_signal" value="addr[16]" />
      <set param="pcw_mio_mio[31]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[31]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_31" value="nor" />

      <set param="pcw_nor_addr[17]_io" value="MIO 32" />
      <set param="pcw_mio_mio[32]_signal" value="addr[17]" />
      <set param="pcw_mio_mio[32]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[32]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_32" value="nor" />

      <set param="pcw_nor_addr[18]_io" value="MIO 33" />
      <set param="pcw_mio_mio[33]_signal" value="addr[18]" />
      <set param="pcw_mio_mio[33]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[33]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_33" value="nor" />

      <set param="pcw_nor_addr[19]_io" value="MIO 34" />
      <set param="pcw_mio_mio[34]_signal" value="addr[19]" />
      <set param="pcw_mio_mio[34]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[34]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_34" value="nor" />

      <set param="pcw_nor_addr[20]_io" value="MIO 35" />
      <set param="pcw_mio_mio[35]_signal" value="addr[20]" />
      <set param="pcw_mio_mio[35]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[35]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_35" value="nor" />

      <set param="pcw_nor_addr[21]_io" value="MIO 36" />
      <set param="pcw_mio_mio[36]_signal" value="addr[21]" />
      <set param="pcw_mio_mio[36]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[36]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_36" value="nor" />

      <set param="pcw_nor_addr[22]_io" value="MIO 37" />
      <set param="pcw_mio_mio[37]_signal" value="addr[22]" />
      <set param="pcw_mio_mio[37]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[37]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_37" value="nor" />

      <set param="pcw_nor_addr[23]_io" value="MIO 38" />
      <set param="pcw_mio_mio[38]_signal" value="addr[23]" />
      <set param="pcw_mio_mio[38]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[38]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_38" value="nor" />

      <set param="pcw_nor_addr[24]_io" value="MIO 39" />
      <set param="pcw_mio_mio[39]_signal" value="addr[24]" />
      <set param="pcw_mio_mio[39]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[39]_signalgroup" value="SRAM/NOR Flash" />
      <set param="pcw_preset_mio_39" value="nor" />

  </preset>


  <preset param="pcw_nor_grp_a25_io" name="MIO 1" strength="5">
      <set param="pcw_nor_addr[25]_io" value="MIO 1" />
      <set param="pcw_mio_mio[1]_signal" value="addr[25]" />
      <set param="pcw_mio_mio[1]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[1]_signalgroup" value="addr[25]" />
      <set param="pcw_preset_mio_1" value="smc_a25" />
  </preset>

  <preset param="pcw_nor_grp_cs0_io" name="MIO 0" strength="5">
      <set param="pcw_nor_cs_b[0]_io" value="MIO 0" />
      <set param="pcw_mio_mio[0]_signal" value="cs0" />
      <set param="pcw_mio_mio[0]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[0]_signalgroup" value="CS0" />
      <set param="pcw_preset_mio_0" value="smc_cs0" />
  </preset>

  <preset param="pcw_nor_grp_cs1_io" name="MIO 1" strength="5">
      <set param="pcw_nor_cs_b[1]_io" value="MIO 1" />
      <set param="pcw_mio_mio[1]_signal" value="cs1" />
      <set param="pcw_mio_mio[1]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[1]_signalgroup" value="CS1" />
      <set param="pcw_preset_mio_1" value="smc_cs1" />
  </preset>

  <preset param="pcw_nor_grp_sram_cs0_io" name="MIO 0" strength="5">
      <set param="pcw_nor_cs_b[0]_io" value="MIO 0" />
      <set param="pcw_mio_mio[0]_signal" value="cs0" />
      <set param="pcw_mio_mio[0]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[0]_signalgroup" value="CS0" />
      <set param="pcw_preset_mio_0" value="smc_cs0" />
  </preset>

  <preset param="pcw_nor_grp_sram_cs1_io" name="MIO 1" strength="5">
      <set param="pcw_nor_cs_b[1]_io" value="MIO 1" />
      <set param="pcw_mio_mio[1]_signal" value="cs1" />
      <set param="pcw_mio_mio[1]_peripheral" value="SRAM/NOR Flash" />
      <set param="pcw_mio_mio[1]_signalgroup" value="CS1" />
      <set param="pcw_preset_mio_1" value="smc_cs1" />
  </preset>



</presets>

