<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE parameters>

<parameters>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCR_ReturnStackEn">
<name>ReturnStackEn</name>
<desc>Return stack enable</desc>
<sw_param offset="0xf889d000" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCR_TimestampEn">
<name>TimestampEn</name>
<desc>Timestamp enable</desc>
<sw_param offset="0xf889d000" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCR_ProcSelect">
<name>ProcSelect</name>
<desc>Select for external multiplexor if PTM is shared between multiple processors.</desc>
<sw_param offset="0xf889d000" start="27" end="25" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCR_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889d000" start="24" end="16" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCR_ContexIDSize">
<name>ContexIDSize</name>
<desc>Context ID Size</desc>
<sw_param offset="0xf889d000" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCR_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xf889d000" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCR_CycleAccurate">
<name>CycleAccurate</name>
<desc>Enables cycle counting</desc>
<sw_param offset="0xf889d000" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCR_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xf889d000" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCR_ProgBit">
<name>ProgBit</name>
<desc>This bit must be set to b1 when the PTM is being programmed.</desc>
<sw_param offset="0xf889d000" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCR_DebugReqCtrl">
<name>DebugReqCtrl</name>
<desc>Debug Request Control
When set to b1 and the trigger event occurs, the PTMDBGRQ output is asserted until PTMDBGACK is observed. This enables a debugger to force the processor into Debug state.</desc>
<sw_param offset="0xf889d000" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCR_BranchOutput">
<name>BranchOutput</name>
<desc>When this bit is set to b1, addresses are output for all executed branches, both direct and indirect.</desc>
<sw_param offset="0xf889d000" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCR_reserved_3">
<name>reserved_3</name>
<desc>Reserved</desc>
<sw_param offset="0xf889d000" start="7" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCR_PowerDown">
<name>PowerDown</name>
<desc>This bit enables external control of the PTM. This bit must be cleared by the trace software tools at the beginning of a debug session.
When this bit is set to b0, both the PTM and the trace interface in the processor are enabled.
To avoid corruption of trace data, this bit must not be set before the Programming Status bit in the PTM Status Register has been read as 1.</desc>
<sw_param offset="0xf889d000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCCR_IDRegPresent">
<name>IDRegPresent</name>
<desc>Indicates that the ID Register is present.</desc>
<sw_param offset="0xf889d004" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCCR_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889d004" start="30" end="28" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCCR_SoftwareAccess">
<name>SoftwareAccess</name>
<desc>Indicates that software access is supported.</desc>
<sw_param offset="0xf889d004" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCCR_TraceSSB">
<name>TraceSSB</name>
<desc>Indicates that the trace start/stop block is present.</desc>
<sw_param offset="0xf889d004" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCCR_NumCntxtIDComp">
<name>NumCntxtIDComp</name>
<desc>Specifies the number of Context ID comparators, one.</desc>
<sw_param offset="0xf889d004" start="25" end="24" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCCR_FIFOFULLLogic">
<name>FIFOFULLLogic</name>
<desc>Indicates that it is not possible to stall the processor to prevent FIFO overflow.</desc>
<sw_param offset="0xf889d004" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCCR_NumExtOut">
<name>NumExtOut</name>
<desc>Specifies the number of external outputs, two.</desc>
<sw_param offset="0xf889d004" start="22" end="20" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCCR_NumExtIn">
<name>NumExtIn</name>
<desc>Specifies the number of external inputs, four.</desc>
<sw_param offset="0xf889d004" start="19" end="17" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCCR_Sequencer">
<name>Sequencer</name>
<desc>Indicates that the sequencer is present.</desc>
<sw_param offset="0xf889d004" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCCR_NumCounters">
<name>NumCounters</name>
<desc>Specifies the number of counters, two.</desc>
<sw_param offset="0xf889d004" start="15" end="13" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCCR_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xf889d004" start="12" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCCR_NumAddrComp">
<name>NumAddrComp</name>
<desc>Specifies the number of address comparator pairs, four.</desc>
<sw_param offset="0xf889d004" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMTRIGGER_TrigEvent">
<name>TrigEvent</name>
<desc>Trigger event. Subdivided as:
Function, bits [16:14]
Specifies the function that combines the two resources that define the event.
Resource B, bits [13:7] and Resource A, bits [6:0]
Specify the two resources that are combined by the logical operation specified by the Function field.</desc>
<sw_param offset="0xf889d008" start="16" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMSR_TrigFlag">
<name>TrigFlag</name>
<desc>Trigger bit. Set when the trigger occurs and prevents the trigger from being output until the PTM is next programmed.</desc>
<sw_param offset="0xf889d010" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMSR_TSSRStat">
<name>TSSRStat</name>
<desc>Holds the current status of the trace start/stop resource. If set to 1, indicates that a trace start address has been matched, without a corresponding trace stop address match.</desc>
<sw_param offset="0xf889d010" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMSR_ProgBit">
<name>ProgBit</name>
<desc>Effective state of the Programming bit. You must wait for this bit to go to b1 before starting to program the PTM.</desc>
<sw_param offset="0xf889d010" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMSR_Overflow">
<name>Overflow</name>
<desc>If set to 1, there is an overflow that has not yet been traced.</desc>
<sw_param offset="0xf889d010" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMSCR_NumProcs">
<name>NumProcs</name>
<desc>Number of supported processors minus 1.</desc>
<sw_param offset="0xf889d014" start="14" end="12" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMSCR_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889d014" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMSCR_FIFOFULL">
<name>FIFOFULL</name>
<desc>FIFOFULL not supported</desc>
<sw_param offset="0xf889d014" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMSCR_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xf889d014" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMTSSCR_StopAddrSel">
<name>StopAddrSel</name>
<desc>When a bit is set to 1, it selects a single address comparator (8-1) as a stop address for the TraceEnable
Start/Stop block. For example, if you set bit [16] to 1 it selects single address comparator 1 as a stop address.</desc>
<sw_param offset="0xf889d018" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMTSSCR_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889d018" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMTSSCR_StartAddrSel">
<name>StartAddrSel</name>
<desc>When a bit is set to 1, it selects a single address comparator (8-1) as a start address for the TraceEnable
Start/Stop block. For example, if you set bit [0] to 1 it selects single address comparator 1 as a start address.</desc>
<sw_param offset="0xf889d018" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMTECR1_TraceSSEn">
<name>TraceSSEn</name>
<desc>Trace start/stop control enable. The possible values of this bit are:
0 Tracing is unaffected by the trace start/stop logic.
1 Tracing is controlled by the trace on and off addresses configured for the trace start/stop logic.
The trace start/stop resource is not affected by the value of this bit.</desc>
<sw_param offset="0xf889d024" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMTECR1_ExcIncFlag">
<name>ExcIncFlag</name>
<desc>Exclude/include flag. The possible values of this bit are:
0 Include. The specified address range comparators indicate the regions where tracing can occur.
No tracing occurs outside this region.
1 Exclude. The specified address range comparators indicate regions to be excluded from the
trace. When outside an exclude region, tracing can occur.</desc>
<sw_param offset="0xf889d024" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMTECR1_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889d024" start="23" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMTECR1_AddrCompSel">
<name>AddrCompSel</name>
<desc>When a bit is set to 1, it selects an address range comparator, 4-1, for include/exclude control. For example, bit [0] set to 1 selects address range comparator 1.</desc>
<sw_param offset="0xf889d024" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACVR1_Address">
<name>Address</name>
<desc>Address for comparison</desc>
<sw_param offset="0xf889d040" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACVR2_Address">
<name>Address</name>
<desc>Address for comparison</desc>
<sw_param offset="0xf889d044" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACVR3_Address">
<name>Address</name>
<desc>Address for comparison</desc>
<sw_param offset="0xf889d048" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACVR4_Address">
<name>Address</name>
<desc>Address for comparison</desc>
<sw_param offset="0xf889d04c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACVR5_Address">
<name>Address</name>
<desc>Address for comparison</desc>
<sw_param offset="0xf889d050" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACVR6_Address">
<name>Address</name>
<desc>Address for comparison</desc>
<sw_param offset="0xf889d054" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACVR7_Address">
<name>Address</name>
<desc>Address for comparison</desc>
<sw_param offset="0xf889d058" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACVR8_Address">
<name>Address</name>
<desc>Address for comparison</desc>
<sw_param offset="0xf889d05c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR1_SecLevelCtrl">
<name>SecLevelCtrl</name>
<desc>Security level control</desc>
<sw_param offset="0xf889d080" start="11" end="10" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR1_ContextIDCompCtrl">
<name>ContextIDCompCtrl</name>
<desc>Context ID comparator control.</desc>
<sw_param offset="0xf889d080" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR1_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889d080" start="7" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR1_AccessType">
<name>AccessType</name>
<desc>Access type. Returns the value: Instruction execute.</desc>
<sw_param offset="0xf889d080" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR2_SecLevelCtrl">
<name>SecLevelCtrl</name>
<desc>Security level control</desc>
<sw_param offset="0xf889d084" start="11" end="10" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR2_ContextIDCompCtrl">
<name>ContextIDCompCtrl</name>
<desc>Context ID comparator control.</desc>
<sw_param offset="0xf889d084" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR2_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889d084" start="7" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR2_AccessType">
<name>AccessType</name>
<desc>Access type. Returns the value: Instruction execute.</desc>
<sw_param offset="0xf889d084" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR3_SecLevelCtrl">
<name>SecLevelCtrl</name>
<desc>Security level control</desc>
<sw_param offset="0xf889d088" start="11" end="10" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR3_ContextIDCompCtrl">
<name>ContextIDCompCtrl</name>
<desc>Context ID comparator control.</desc>
<sw_param offset="0xf889d088" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR3_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889d088" start="7" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR3_AccessType">
<name>AccessType</name>
<desc>Access type. Returns the value: Instruction execute.</desc>
<sw_param offset="0xf889d088" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR4_SecLevelCtrl">
<name>SecLevelCtrl</name>
<desc>Security level control</desc>
<sw_param offset="0xf889d08c" start="11" end="10" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR4_ContextIDCompCtrl">
<name>ContextIDCompCtrl</name>
<desc>Context ID comparator control.</desc>
<sw_param offset="0xf889d08c" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR4_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889d08c" start="7" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR4_AccessType">
<name>AccessType</name>
<desc>Access type. Returns the value: Instruction execute.</desc>
<sw_param offset="0xf889d08c" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR5_SecLevelCtrl">
<name>SecLevelCtrl</name>
<desc>Security level control</desc>
<sw_param offset="0xf889d090" start="11" end="10" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR5_ContextIDCompCtrl">
<name>ContextIDCompCtrl</name>
<desc>Context ID comparator control.</desc>
<sw_param offset="0xf889d090" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR5_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889d090" start="7" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR5_AccessType">
<name>AccessType</name>
<desc>Access type. Returns the value: Instruction execute.</desc>
<sw_param offset="0xf889d090" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR6_SecLevelCtrl">
<name>SecLevelCtrl</name>
<desc>Security level control</desc>
<sw_param offset="0xf889d094" start="11" end="10" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR6_ContextIDCompCtrl">
<name>ContextIDCompCtrl</name>
<desc>Context ID comparator control.</desc>
<sw_param offset="0xf889d094" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR6_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889d094" start="7" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR6_AccessType">
<name>AccessType</name>
<desc>Access type. Returns the value: Instruction execute.</desc>
<sw_param offset="0xf889d094" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR7_SecLevelCtrl">
<name>SecLevelCtrl</name>
<desc>Security level control</desc>
<sw_param offset="0xf889d098" start="11" end="10" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR7_ContextIDCompCtrl">
<name>ContextIDCompCtrl</name>
<desc>Context ID comparator control.</desc>
<sw_param offset="0xf889d098" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR7_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889d098" start="7" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR7_AccessType">
<name>AccessType</name>
<desc>Access type. Returns the value: Instruction execute.</desc>
<sw_param offset="0xf889d098" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR8_SecLevelCtrl">
<name>SecLevelCtrl</name>
<desc>Security level control</desc>
<sw_param offset="0xf889d09c" start="11" end="10" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR8_ContextIDCompCtrl">
<name>ContextIDCompCtrl</name>
<desc>Context ID comparator control.</desc>
<sw_param offset="0xf889d09c" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR8_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889d09c" start="7" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMACTR8_AccessType">
<name>AccessType</name>
<desc>Access type. Returns the value: Instruction execute.</desc>
<sw_param offset="0xf889d09c" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCNTRLDVR1_InitValue">
<name>InitValue</name>
<desc>Counter initial value</desc>
<sw_param offset="0xf889d140" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCNTRLDVR2_InitValue">
<name>InitValue</name>
<desc>Counter initial value</desc>
<sw_param offset="0xf889d144" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCNTENR1_Reserved_1">
<name>Reserved_1</name>
<desc>Reserved, RAO/WI</desc>
<sw_param offset="0xf889d150" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCNTENR1_ExtOutEvent">
<name>ExtOutEvent</name>
<desc>Count enable event. Subdivided as:
Function, bits [16:14]
Specifies the function that combines the two resources that define the event.
Resource B, bits [13:7] and Resource A, bits [6:0]
Specify the two resources that are combined by the logical operation specified by the Function field.</desc>
<sw_param offset="0xf889d150" start="16" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCNTENR2_Reserved_1">
<name>Reserved_1</name>
<desc>Reserved, RAO/WI</desc>
<sw_param offset="0xf889d154" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCNTENR2_ExtOutEvent">
<name>ExtOutEvent</name>
<desc>Count enable event. Subdivided as:
Function, bits [16:14]
Specifies the function that combines the two resources that define the event.
Resource B, bits [13:7] and Resource A, bits [6:0]
Specify the two resources that are combined by the logical operation specified by the Function field.</desc>
<sw_param offset="0xf889d154" start="16" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCNTRLDEVR1_CntReloadEvent">
<name>CntReloadEvent</name>
<desc>Count reload event. Subdivided as:
Function, bits [16:14]
Specifies the function that combines the two resources that define the event.
Resource B, bits [13:7] and Resource A, bits [6:0]
Specify the two resources that are combined by the logical operation specified by the Function field.</desc>
<sw_param offset="0xf889d160" start="16" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCNTRLDEVR2_CntReloadEvent">
<name>CntReloadEvent</name>
<desc>Count reload event. Subdivided as:
Function, bits [16:14]
Specifies the function that combines the two resources that define the event.
Resource B, bits [13:7] and Resource A, bits [6:0]
Specify the two resources that are combined by the logical operation specified by the Function field.</desc>
<sw_param offset="0xf889d164" start="16" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCNTVR1_CurrCount">
<name>CurrCount</name>
<desc>Current counter value.</desc>
<sw_param offset="0xf889d170" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCNTVR2_CurrCount">
<name>CurrCount</name>
<desc>Current counter value.</desc>
<sw_param offset="0xf889d174" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMSQ12EVR_TransEvent">
<name>TransEvent</name>
<desc>A Sequencer State Transition Event Register, ETMSQmnEVR, defines the evnet that causes the sequencer state transition from state m to state n.
The format is subdivided as:
Function, bits [16:14]
Specifies the function that combines the two resources that define the event.
Resource B, bits [13:7] and Resource A, bits [6:0]
Specify the two resources that are combined by the logical operation specified by the Function field.</desc>
<sw_param offset="0xf889d180" start="16" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMSQ21EVR_TransEvent">
<name>TransEvent</name>
<desc>A Sequencer State Transition Event Register, ETMSQmnEVR, defines the evnet that causes the sequencer state transition from state m to state n.
The format is subdivided as:
Function, bits [16:14]
Specifies the function that combines the two resources that define the event.
Resource B, bits [13:7] and Resource A, bits [6:0]
Specify the two resources that are combined by the logical operation specified by the Function field.</desc>
<sw_param offset="0xf889d184" start="16" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMSQ23EVR_TransEvent">
<name>TransEvent</name>
<desc>A Sequencer State Transition Event Register, ETMSQmnEVR, defines the evnet that causes the sequencer state transition from state m to state n.
The format is subdivided as:
Function, bits [16:14]
Specifies the function that combines the two resources that define the event.
Resource B, bits [13:7] and Resource A, bits [6:0]
Specify the two resources that are combined by the logical operation specified by the Function field.</desc>
<sw_param offset="0xf889d188" start="16" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMSQ31EVR_TransEvent">
<name>TransEvent</name>
<desc>A Sequencer State Transition Event Register, ETMSQmnEVR, defines the evnet that causes the sequencer state transition from state m to state n.
The format is subdivided as:
Function, bits [16:14]
Specifies the function that combines the two resources that define the event.
Resource B, bits [13:7] and Resource A, bits [6:0]
Specify the two resources that are combined by the logical operation specified by the Function field.</desc>
<sw_param offset="0xf889d18c" start="16" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMSQ32EVR_TransEvent">
<name>TransEvent</name>
<desc>A Sequencer State Transition Event Register, ETMSQmnEVR, defines the evnet that causes the sequencer state transition from state m to state n.
The format is subdivided as:
Function, bits [16:14]
Specifies the function that combines the two resources that define the event.
Resource B, bits [13:7] and Resource A, bits [6:0]
Specify the two resources that are combined by the logical operation specified by the Function field.</desc>
<sw_param offset="0xf889d190" start="16" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMSQ13EVR_TransEvent">
<name>TransEvent</name>
<desc>A Sequencer State Transition Event Register, ETMSQmnEVR, defines the evnet that causes the sequencer state transition from state m to state n.
The format is subdivided as:
Function, bits [16:14]
Specifies the function that combines the two resources that define the event.
Resource B, bits [13:7] and Resource A, bits [6:0]
Specify the two resources that are combined by the logical operation specified by the Function field.</desc>
<sw_param offset="0xf889d194" start="16" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMSQR_CurrentSeqState">
<name>CurrentSeqState</name>
<desc>Indicates the current sequencer state</desc>
<sw_param offset="0xf889d19c" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMEXTOUTEVR1_ExtOutputEvent">
<name>ExtOutputEvent</name>
<desc>External output event. Subdivided as:
Function, bits [16:14]
Specifies the function that combines the two resources that define the event.
Resource B, bits [13:7] and Resource A, bits [6:0]
Specify the two resources that are combined by the logical operation specified by the Function field.</desc>
<sw_param offset="0xf889d1a0" start="16" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMEXTOUTEVR2_ExtOutputEvent">
<name>ExtOutputEvent</name>
<desc>External output event. Subdivided as:
Function, bits [16:14]
Specifies the function that combines the two resources that define the event.
Resource B, bits [13:7] and Resource A, bits [6:0]
Specify the two resources that are combined by the logical operation specified by the Function field.</desc>
<sw_param offset="0xf889d1a4" start="16" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCIDCVR1_ContextID">
<name>ContextID</name>
<desc>Holds a 32-bit Context ID value</desc>
<sw_param offset="0xf889d1b0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCIDCMR_ContextMask">
<name>ContextMask</name>
<desc>Holds a 32-bit Context ID mask</desc>
<sw_param offset="0xf889d1bc" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMSYNCFR_SyncFreq">
<name>SyncFreq</name>
<desc>Synchronization frequency</desc>
<sw_param offset="0xf889d1e0" start="11" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMSYNCFR_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889d1e0" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMIDR_ImplCode">
<name>ImplCode</name>
<desc>Implementor code. The field reads 0x41, ASCII code for A, indicating ARM Limited.</desc>
<sw_param offset="0xf889d1e4" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMIDR_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889d1e4" start="23" end="21" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMIDR_reserved_1">
<name>reserved_1</name>
<desc>Reserved, RAO</desc>
<sw_param offset="0xf889d1e4" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMIDR_SecExtSupp">
<name>SecExtSupp</name>
<desc>Support for security extensions.</desc>
<sw_param offset="0xf889d1e4" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMIDR_Thumb32Supp">
<name>Thumb32Supp</name>
<desc>Support for 32-bit Thumb instructions.</desc>
<sw_param offset="0xf889d1e4" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMIDR_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xf889d1e4" start="17" end="16" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMIDR_Reserved_F">
<name>Reserved_F</name>
<desc>Reserved, 0b1111</desc>
<sw_param offset="0xf889d1e4" start="15" end="12" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMIDR_MajorVer">
<name>MajorVer</name>
<desc>Major architecture version number, 0b0011</desc>
<sw_param offset="0xf889d1e4" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMIDR_MinorVer">
<name>MinorVer</name>
<desc>Minor architecture version number, 0b0000</desc>
<sw_param offset="0xf889d1e4" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMIDR_ImplRev">
<name>ImplRev</name>
<desc>Implementation revision.</desc>
<sw_param offset="0xf889d1e4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCCER_BarrTS">
<name>BarrTS</name>
<desc>Timestamps are not generated for DMB/DSB</desc>
<sw_param offset="0xf889d1e8" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCCER_BarrWP">
<name>BarrWP</name>
<desc>DMB/DSB instructions are not treated as waypoints.</desc>
<sw_param offset="0xf889d1e8" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCCER_RetStack">
<name>RetStack</name>
<desc>Return stack implemented.</desc>
<sw_param offset="0xf889d1e8" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCCER_Timestamp">
<name>Timestamp</name>
<desc>Timestamping implemented.</desc>
<sw_param offset="0xf889d1e8" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCCER_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889d1e8" start="21" end="16" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCCER_InstrumRes">
<name>InstrumRes</name>
<desc>Specifies the number of instrumentation resources.</desc>
<sw_param offset="0xf889d1e8" start="15" end="13" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCCER_Reserved_1">
<name>Reserved_1</name>
<desc>Reserved, RAO</desc>
<sw_param offset="0xf889d1e8" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCCER_RegReads">
<name>RegReads</name>
<desc>Indicates that all registers, except some Integration Test Registers, are readable.</desc>
<sw_param offset="0xf889d1e8" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCCER_ExtInSize">
<name>ExtInSize</name>
<desc>Specifies the size of the extended external input bus, 52.</desc>
<sw_param offset="0xf889d1e8" start="10" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMCCER_ExtInSel">
<name>ExtInSel</name>
<desc>Specifies the number of extended external input selectors, 2.</desc>
<sw_param offset="0xf889d1e8" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMEXTINSELR_ExtInSel2">
<name>ExtInSel2</name>
<desc>Second extended external input selector</desc>
<sw_param offset="0xf889d1ec" start="13" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMEXTINSELR_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889d1ec" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMEXTINSELR_ExtInSel1">
<name>ExtInSel1</name>
<desc>First extended external input selector</desc>
<sw_param offset="0xf889d1ec" start="5" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMAUXCR_ForceSyncInsert">
<name>ForceSyncInsert</name>
<desc>Force insertion of synchronization packets, regardless of current trace activity.
Possible values for this bit are:
b0 = Synchronization packets delayed when trace activity is high. This is the reset value.
b1 = Synchronization packets inserted regardless of trace activity.
This bit might be set if synchronization packets occur too far apart. Setting this bit might cause the trace FIFO to overflow more frequently when trace activity is high.</desc>
<sw_param offset="0xf889d1fc" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMAUXCR_DisableWPUpdate">
<name>DisableWPUpdate</name>
<desc>Specifies whether the PTM issues waypoint update packets if there are more than 4096 bytes between waypoints. Possible values for this bit are:
b0 = PTM always issues update packets if there are more than 4096 bytes between waypoints. This is the reset value.
b1 = PTM does not issue waypoint update packets unless required to do so as the result of an exception or debug entry.</desc>
<sw_param offset="0xf889d1fc" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMAUXCR_DisableTSOnBarr">
<name>DisableTSOnBarr</name>
<desc>Specifies whether the PTM issues a timestamp on a barrier instruction. Possible values for this bit are:
b0 = PTM issues timestamps on barrier instructions. This is the reset value.
b1 = PTM does not issue timestamps on barriers</desc>
<sw_param offset="0xf889d1fc" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMAUXCR_DisableForcedOF">
<name>DisableForcedOF</name>
<desc>Specifies whether the PTM enters overflow state when synchronization is requested,
and the previous synchronization sequence has not yet completed. This does not affect entry to overflow state when the FIFO becomes full. Possible values for this bit are:
b0 = Forced overflow enabled. This is the reset value.
b1 = Forced overflow disabled.</desc>
<sw_param offset="0xf889d1fc" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMTRACEIDR_TraceID">
<name>TraceID</name>
<desc>Before trace is generated, you must program this register with a non-reserved value.
Reserved values are 0x00 and any value in the range 0x70-0x7F. The reset value of this register is 0x00.</desc>
<sw_param offset="0xf889d200" start="6" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_OSLSR_a">
<name>a</name>
<desc>Shows that OS Locking is not implemented.</desc>
<sw_param offset="0xf889d304" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMPDSR_a">
<name>a</name>
<desc>Indicates that the PTM Trace Registers can be accessed.</desc>
<sw_param offset="0xf889d314" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ITMISCOUT_PTMEXTOUT">
<name>PTMEXTOUT</name>
<desc>Drives the PTMEXTOUT[1:0] outputs</desc>
<sw_param offset="0xf889dedc" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ITMISCOUT_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889dedc" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ITMISCOUT_PTMIDLEACK">
<name>PTMIDLEACK</name>
<desc>Drives the PTMIDLEACK output</desc>
<sw_param offset="0xf889dedc" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ITMISCOUT_PTMDBGREQ">
<name>PTMDBGREQ</name>
<desc>Drives the PTMDBGREQ output</desc>
<sw_param offset="0xf889dedc" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ITMISCOUT_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xf889dedc" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ITMISCIN_STANDBYWFI">
<name>STANDBYWFI</name>
<desc>Returns the value of the STANDBYWFI input</desc>
<sw_param offset="0xf889dee0" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ITMISCIN_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889dee0" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ITMISCIN_PTMDBGACK">
<name>PTMDBGACK</name>
<desc>Returns the value of the PTMDBGACK input</desc>
<sw_param offset="0xf889dee0" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ITMISCIN_EXTIN">
<name>EXTIN</name>
<desc>Returns the value of the EXTIN[3:0] inputs</desc>
<sw_param offset="0xf889dee0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ITTRIGGER_PTMTRIGGER">
<name>PTMTRIGGER</name>
<desc>Drives the PTMTRIGGER output</desc>
<sw_param offset="0xf889dee8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ITATBDATA0_ATDATAM31">
<name>ATDATAM31</name>
<desc>Drives the ATDATAM[31] output</desc>
<sw_param offset="0xf889deec" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ITATBDATA0_ATDATAM23">
<name>ATDATAM23</name>
<desc>Drives the ATDATAM[23] output</desc>
<sw_param offset="0xf889deec" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ITATBDATA0_ATDATAM15">
<name>ATDATAM15</name>
<desc>Drives the ATDATAM[15] output</desc>
<sw_param offset="0xf889deec" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ITATBDATA0_ATDATAM7">
<name>ATDATAM7</name>
<desc>Drives the ATDATAM[7] output</desc>
<sw_param offset="0xf889deec" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ITATBDATA0_ATDATAM0">
<name>ATDATAM0</name>
<desc>Drives the ATDATAM[0] output</desc>
<sw_param offset="0xf889deec" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ITATBCTR2_AFVALIDM">
<name>AFVALIDM</name>
<desc>Returns the value of the AFVALIDM input</desc>
<sw_param offset="0xf889def0" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ITATBCTR2_ATREADYM">
<name>ATREADYM</name>
<desc>Returns the value of the ATREADYM input</desc>
<sw_param offset="0xf889def0" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ITATBID_ATIDM">
<name>ATIDM</name>
<desc>Drives the ATIDM[6:0] outputs</desc>
<sw_param offset="0xf889def4" start="6" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ITATBCTR0_ATBYTESM">
<name>ATBYTESM</name>
<desc>Drives the ATBYTESM[9:8] outputs</desc>
<sw_param offset="0xf889def8" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ITATBCTR0_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889def8" start="7" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ITATBCTR0_AFREADYM">
<name>AFREADYM</name>
<desc>Drives the AFREADYM output</desc>
<sw_param offset="0xf889def8" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ITATBCTR0_ATVALIDM">
<name>ATVALIDM</name>
<desc>Drives the ATVALIDM output</desc>
<sw_param offset="0xf889def8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ETMITCTRL_a">
<name>a</name>
<desc>Enable Integration Test registers.
Before entering integration mode, the PTM must be pwoered up and in programmng mode.
THis means bit 0 of the Main Control Register is set to 0, and bit 10 of the Main Control Register ist set 1.
After leaving integration mode, the PTM must be reset before attempting to perform tracing.</desc>
<sw_param offset="0xf889df00" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_CTSR_a">
<name>a</name>
<desc>The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed.
Read:
1= Claim tag is implemented, 0 = Claim tag is not implemented
Write:
1= Set claim tag bit, 0= No effect</desc>
<sw_param offset="0xf889dfa0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_CTCR_a">
<name>a</name>
<desc>The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed.
Read: Current value of claim tag.
Write: 1= Clear claim tag bit, 0= No effect</desc>
<sw_param offset="0xf889dfa4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_LAR_a">
<name>a</name>
<desc>Write Access Code.
Write behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
After reset (via PRESETDBGn), PTM is locked, i.e., writes to all other registers using lower 2GB addresses are ignored.
To unlock, 0xC5ACCE55 must be written this register.
After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register.
- PADDRDBG31=1 (upper 2GB):
PTM is unlocked when upper 2GB addresses are used to write to all the registers.
However, write to this register is ignored using a upper 2GB address!
Note: read from this register always returns 0, regardless of PADDRDBG31.</desc>
<sw_param offset="0xf889dfb0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_LSR_n8BIT">
<name>n8BIT</name>
<desc>Set to 0 since PTM implements a 32-bit lock access register</desc>
<sw_param offset="0xf889dfb4" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_LSR_STATUS">
<name>STATUS</name>
<desc>Read behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
When a lower 2GB address is used to read this register, this bit indicates whether PTM is in locked state
(1= locked, 0= unlocked).
- PADDRDBG31=1 (upper 2GB):
always returns 0.</desc>
<sw_param offset="0xf889dfb4" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_LSR_IMP">
<name>IMP</name>
<desc>Read behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
always returns 1, meaning lock mechanism are implemented.
- PADDRDBG31=1 (upper 2GB):
always returns 0, meaning lock mechanism is NOT implemented.</desc>
<sw_param offset="0xf889dfb4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ASR_SNI">
<name>SNI</name>
<desc>Secure non-invasive debug
Always 2'b00,.
This functionality is not implemented</desc>
<sw_param offset="0xf889dfb8" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ASR_SI">
<name>SI</name>
<desc>Secure invasive debug
Always 2'b00.
This functionality is not implemented.</desc>
<sw_param offset="0xf889dfb8" start="5" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ASR_NSNI">
<name>NSNI</name>
<desc>Non-secure non-invasive debug
IF NIDEN or DBGEN is 1, this field is 2'b11, indicating the functionality is implemented and enabled.
Otherwise, this field is 2'b10 (implemented but disabled)</desc>
<sw_param offset="0xf889dfb8" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_ASR_NSI">
<name>NSI</name>
<desc>Non-secure invasive debug
Always 2'b00.
This functionality is not implemented.</desc>
<sw_param offset="0xf889dfb8" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_DEVID_a">
<name>a</name>
<desc>Component capability</desc>
<sw_param offset="0xf889dfc8" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_DTIR_a">
<name>a</name>
<desc>A trace source and processor trace</desc>
<sw_param offset="0xf889dfcc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_PERIPHID4_n4KB_count">
<name>n4KB_count</name>
<desc>4KB Count, set to 0</desc>
<sw_param offset="0xf889dfd0" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_PERIPHID4_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 continuation code</desc>
<sw_param offset="0xf889dfd0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_PERIPHID5_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf889dfd4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_PERIPHID6_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf889dfd8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_PERIPHID7_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf889dfdc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_PERIPHID0_a">
<name>a</name>
<desc>PartNumber0</desc>
<sw_param offset="0xf889dfe0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_PERIPHID1_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 Identity Code [3:0]</desc>
<sw_param offset="0xf889dfe4" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_PERIPHID1_PartNumber1">
<name>PartNumber1</name>
<desc>PartNumber1</desc>
<sw_param offset="0xf889dfe4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_PERIPHID2_RevNum">
<name>RevNum</name>
<desc>Revision number of Peripheral</desc>
<sw_param offset="0xf889dfe8" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_PERIPHID2_JEDEC">
<name>JEDEC</name>
<desc>Indicates that a JEDEC assigned value is used</desc>
<sw_param offset="0xf889dfe8" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_PERIPHID2_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 Identity Code [6:4]</desc>
<sw_param offset="0xf889dfe8" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_PERIPHID3_RevAnd">
<name>RevAnd</name>
<desc>RevAnd, at top level</desc>
<sw_param offset="0xf889dfec" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_PERIPHID3_CustMod">
<name>CustMod</name>
<desc>Customer Modified</desc>
<sw_param offset="0xf889dfec" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_COMPID0_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf889dff0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_COMPID1_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf889dff4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_COMPID2_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf889dff8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm1_COMPID3_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf889dffc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCR_ReturnStackEn">
<name>ReturnStackEn</name>
<desc>Return stack enable</desc>
<sw_param offset="0xf889c000" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCR_TimestampEn">
<name>TimestampEn</name>
<desc>Timestamp enable</desc>
<sw_param offset="0xf889c000" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCR_ProcSelect">
<name>ProcSelect</name>
<desc>Select for external multiplexor if PTM is shared between multiple processors.</desc>
<sw_param offset="0xf889c000" start="27" end="25" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCR_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889c000" start="24" end="16" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCR_ContexIDSize">
<name>ContexIDSize</name>
<desc>Context ID Size</desc>
<sw_param offset="0xf889c000" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCR_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xf889c000" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCR_CycleAccurate">
<name>CycleAccurate</name>
<desc>Enables cycle counting</desc>
<sw_param offset="0xf889c000" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCR_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xf889c000" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCR_ProgBit">
<name>ProgBit</name>
<desc>This bit must be set to b1 when the PTM is being programmed.</desc>
<sw_param offset="0xf889c000" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCR_DebugReqCtrl">
<name>DebugReqCtrl</name>
<desc>Debug Request Control
When set to b1 and the trigger event occurs, the PTMDBGRQ output is asserted until PTMDBGACK is observed. This enables a debugger to force the processor into Debug state.</desc>
<sw_param offset="0xf889c000" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCR_BranchOutput">
<name>BranchOutput</name>
<desc>When this bit is set to b1, addresses are output for all executed branches, both direct and indirect.</desc>
<sw_param offset="0xf889c000" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCR_reserved_3">
<name>reserved_3</name>
<desc>Reserved</desc>
<sw_param offset="0xf889c000" start="7" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCR_PowerDown">
<name>PowerDown</name>
<desc>This bit enables external control of the PTM. This bit must be cleared by the trace software tools at the beginning of a debug session.
When this bit is set to b0, both the PTM and the trace interface in the processor are enabled.
To avoid corruption of trace data, this bit must not be set before the Programming Status bit in the PTM Status Register has been read as 1.</desc>
<sw_param offset="0xf889c000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCCR_IDRegPresent">
<name>IDRegPresent</name>
<desc>Indicates that the ID Register is present.</desc>
<sw_param offset="0xf889c004" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCCR_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889c004" start="30" end="28" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCCR_SoftwareAccess">
<name>SoftwareAccess</name>
<desc>Indicates that software access is supported.</desc>
<sw_param offset="0xf889c004" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCCR_TraceSSB">
<name>TraceSSB</name>
<desc>Indicates that the trace start/stop block is present.</desc>
<sw_param offset="0xf889c004" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCCR_NumCntxtIDComp">
<name>NumCntxtIDComp</name>
<desc>Specifies the number of Context ID comparators, one.</desc>
<sw_param offset="0xf889c004" start="25" end="24" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCCR_FIFOFULLLogic">
<name>FIFOFULLLogic</name>
<desc>Indicates that it is not possible to stall the processor to prevent FIFO overflow.</desc>
<sw_param offset="0xf889c004" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCCR_NumExtOut">
<name>NumExtOut</name>
<desc>Specifies the number of external outputs, two.</desc>
<sw_param offset="0xf889c004" start="22" end="20" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCCR_NumExtIn">
<name>NumExtIn</name>
<desc>Specifies the number of external inputs, four.</desc>
<sw_param offset="0xf889c004" start="19" end="17" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCCR_Sequencer">
<name>Sequencer</name>
<desc>Indicates that the sequencer is present.</desc>
<sw_param offset="0xf889c004" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCCR_NumCounters">
<name>NumCounters</name>
<desc>Specifies the number of counters, two.</desc>
<sw_param offset="0xf889c004" start="15" end="13" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCCR_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xf889c004" start="12" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCCR_NumAddrComp">
<name>NumAddrComp</name>
<desc>Specifies the number of address comparator pairs, four.</desc>
<sw_param offset="0xf889c004" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMTRIGGER_TrigEvent">
<name>TrigEvent</name>
<desc>Trigger event. Subdivided as:
Function, bits [16:14]
Specifies the function that combines the two resources that define the event.
Resource B, bits [13:7] and Resource A, bits [6:0]
Specify the two resources that are combined by the logical operation specified by the Function field.</desc>
<sw_param offset="0xf889c008" start="16" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMSR_TrigFlag">
<name>TrigFlag</name>
<desc>Trigger bit. Set when the trigger occurs and prevents the trigger from being output until the PTM is next programmed.</desc>
<sw_param offset="0xf889c010" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMSR_TSSRStat">
<name>TSSRStat</name>
<desc>Holds the current status of the trace start/stop resource. If set to 1, indicates that a trace start address has been matched, without a corresponding trace stop address match.</desc>
<sw_param offset="0xf889c010" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMSR_ProgBit">
<name>ProgBit</name>
<desc>Effective state of the Programming bit. You must wait for this bit to go to b1 before starting to program the PTM.</desc>
<sw_param offset="0xf889c010" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMSR_Overflow">
<name>Overflow</name>
<desc>If set to 1, there is an overflow that has not yet been traced.</desc>
<sw_param offset="0xf889c010" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMSCR_NumProcs">
<name>NumProcs</name>
<desc>Number of supported processors minus 1.</desc>
<sw_param offset="0xf889c014" start="14" end="12" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMSCR_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889c014" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMSCR_FIFOFULL">
<name>FIFOFULL</name>
<desc>FIFOFULL not supported</desc>
<sw_param offset="0xf889c014" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMSCR_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xf889c014" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMTSSCR_StopAddrSel">
<name>StopAddrSel</name>
<desc>When a bit is set to 1, it selects a single address comparator (8-1) as a stop address for the TraceEnable
Start/Stop block. For example, if you set bit [16] to 1 it selects single address comparator 1 as a stop address.</desc>
<sw_param offset="0xf889c018" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMTSSCR_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889c018" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMTSSCR_StartAddrSel">
<name>StartAddrSel</name>
<desc>When a bit is set to 1, it selects a single address comparator (8-1) as a start address for the TraceEnable
Start/Stop block. For example, if you set bit [0] to 1 it selects single address comparator 1 as a start address.</desc>
<sw_param offset="0xf889c018" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMTECR1_TraceSSEn">
<name>TraceSSEn</name>
<desc>Trace start/stop control enable. The possible values of this bit are:
0 Tracing is unaffected by the trace start/stop logic.
1 Tracing is controlled by the trace on and off addresses configured for the trace start/stop logic.
The trace start/stop resource is not affected by the value of this bit.</desc>
<sw_param offset="0xf889c024" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMTECR1_ExcIncFlag">
<name>ExcIncFlag</name>
<desc>Exclude/include flag. The possible values of this bit are:
0 Include. The specified address range comparators indicate the regions where tracing can occur.
No tracing occurs outside this region.
1 Exclude. The specified address range comparators indicate regions to be excluded from the
trace. When outside an exclude region, tracing can occur.</desc>
<sw_param offset="0xf889c024" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMTECR1_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889c024" start="23" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMTECR1_AddrCompSel">
<name>AddrCompSel</name>
<desc>When a bit is set to 1, it selects an address range comparator, 4-1, for include/exclude control. For example, bit [0] set to 1 selects address range comparator 1.</desc>
<sw_param offset="0xf889c024" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACVR1_Address">
<name>Address</name>
<desc>Address for comparison</desc>
<sw_param offset="0xf889c040" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACVR2_Address">
<name>Address</name>
<desc>Address for comparison</desc>
<sw_param offset="0xf889c044" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACVR3_Address">
<name>Address</name>
<desc>Address for comparison</desc>
<sw_param offset="0xf889c048" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACVR4_Address">
<name>Address</name>
<desc>Address for comparison</desc>
<sw_param offset="0xf889c04c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACVR5_Address">
<name>Address</name>
<desc>Address for comparison</desc>
<sw_param offset="0xf889c050" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACVR6_Address">
<name>Address</name>
<desc>Address for comparison</desc>
<sw_param offset="0xf889c054" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACVR7_Address">
<name>Address</name>
<desc>Address for comparison</desc>
<sw_param offset="0xf889c058" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACVR8_Address">
<name>Address</name>
<desc>Address for comparison</desc>
<sw_param offset="0xf889c05c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR1_SecLevelCtrl">
<name>SecLevelCtrl</name>
<desc>Security level control</desc>
<sw_param offset="0xf889c080" start="11" end="10" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR1_ContextIDCompCtrl">
<name>ContextIDCompCtrl</name>
<desc>Context ID comparator control.</desc>
<sw_param offset="0xf889c080" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR1_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889c080" start="7" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR1_AccessType">
<name>AccessType</name>
<desc>Access type. Returns the value: Instruction execute.</desc>
<sw_param offset="0xf889c080" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR2_SecLevelCtrl">
<name>SecLevelCtrl</name>
<desc>Security level control</desc>
<sw_param offset="0xf889c084" start="11" end="10" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR2_ContextIDCompCtrl">
<name>ContextIDCompCtrl</name>
<desc>Context ID comparator control.</desc>
<sw_param offset="0xf889c084" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR2_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889c084" start="7" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR2_AccessType">
<name>AccessType</name>
<desc>Access type. Returns the value: Instruction execute.</desc>
<sw_param offset="0xf889c084" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR3_SecLevelCtrl">
<name>SecLevelCtrl</name>
<desc>Security level control</desc>
<sw_param offset="0xf889c088" start="11" end="10" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR3_ContextIDCompCtrl">
<name>ContextIDCompCtrl</name>
<desc>Context ID comparator control.</desc>
<sw_param offset="0xf889c088" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR3_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889c088" start="7" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR3_AccessType">
<name>AccessType</name>
<desc>Access type. Returns the value: Instruction execute.</desc>
<sw_param offset="0xf889c088" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR4_SecLevelCtrl">
<name>SecLevelCtrl</name>
<desc>Security level control</desc>
<sw_param offset="0xf889c08c" start="11" end="10" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR4_ContextIDCompCtrl">
<name>ContextIDCompCtrl</name>
<desc>Context ID comparator control.</desc>
<sw_param offset="0xf889c08c" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR4_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889c08c" start="7" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR4_AccessType">
<name>AccessType</name>
<desc>Access type. Returns the value: Instruction execute.</desc>
<sw_param offset="0xf889c08c" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR5_SecLevelCtrl">
<name>SecLevelCtrl</name>
<desc>Security level control</desc>
<sw_param offset="0xf889c090" start="11" end="10" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR5_ContextIDCompCtrl">
<name>ContextIDCompCtrl</name>
<desc>Context ID comparator control.</desc>
<sw_param offset="0xf889c090" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR5_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889c090" start="7" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR5_AccessType">
<name>AccessType</name>
<desc>Access type. Returns the value: Instruction execute.</desc>
<sw_param offset="0xf889c090" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR6_SecLevelCtrl">
<name>SecLevelCtrl</name>
<desc>Security level control</desc>
<sw_param offset="0xf889c094" start="11" end="10" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR6_ContextIDCompCtrl">
<name>ContextIDCompCtrl</name>
<desc>Context ID comparator control.</desc>
<sw_param offset="0xf889c094" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR6_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889c094" start="7" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR6_AccessType">
<name>AccessType</name>
<desc>Access type. Returns the value: Instruction execute.</desc>
<sw_param offset="0xf889c094" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR7_SecLevelCtrl">
<name>SecLevelCtrl</name>
<desc>Security level control</desc>
<sw_param offset="0xf889c098" start="11" end="10" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR7_ContextIDCompCtrl">
<name>ContextIDCompCtrl</name>
<desc>Context ID comparator control.</desc>
<sw_param offset="0xf889c098" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR7_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889c098" start="7" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR7_AccessType">
<name>AccessType</name>
<desc>Access type. Returns the value: Instruction execute.</desc>
<sw_param offset="0xf889c098" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR8_SecLevelCtrl">
<name>SecLevelCtrl</name>
<desc>Security level control</desc>
<sw_param offset="0xf889c09c" start="11" end="10" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR8_ContextIDCompCtrl">
<name>ContextIDCompCtrl</name>
<desc>Context ID comparator control.</desc>
<sw_param offset="0xf889c09c" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR8_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889c09c" start="7" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMACTR8_AccessType">
<name>AccessType</name>
<desc>Access type. Returns the value: Instruction execute.</desc>
<sw_param offset="0xf889c09c" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCNTRLDVR1_InitValue">
<name>InitValue</name>
<desc>Counter initial value</desc>
<sw_param offset="0xf889c140" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCNTRLDVR2_InitValue">
<name>InitValue</name>
<desc>Counter initial value</desc>
<sw_param offset="0xf889c144" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCNTENR1_Reserved_1">
<name>Reserved_1</name>
<desc>Reserved, RAO/WI</desc>
<sw_param offset="0xf889c150" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCNTENR1_ExtOutEvent">
<name>ExtOutEvent</name>
<desc>Count enable event. Subdivided as:
Function, bits [16:14]
Specifies the function that combines the two resources that define the event.
Resource B, bits [13:7] and Resource A, bits [6:0]
Specify the two resources that are combined by the logical operation specified by the Function field.</desc>
<sw_param offset="0xf889c150" start="16" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCNTENR2_Reserved_1">
<name>Reserved_1</name>
<desc>Reserved, RAO/WI</desc>
<sw_param offset="0xf889c154" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCNTENR2_ExtOutEvent">
<name>ExtOutEvent</name>
<desc>Count enable event. Subdivided as:
Function, bits [16:14]
Specifies the function that combines the two resources that define the event.
Resource B, bits [13:7] and Resource A, bits [6:0]
Specify the two resources that are combined by the logical operation specified by the Function field.</desc>
<sw_param offset="0xf889c154" start="16" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCNTRLDEVR1_CntReloadEvent">
<name>CntReloadEvent</name>
<desc>Count reload event. Subdivided as:
Function, bits [16:14]
Specifies the function that combines the two resources that define the event.
Resource B, bits [13:7] and Resource A, bits [6:0]
Specify the two resources that are combined by the logical operation specified by the Function field.</desc>
<sw_param offset="0xf889c160" start="16" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCNTRLDEVR2_CntReloadEvent">
<name>CntReloadEvent</name>
<desc>Count reload event. Subdivided as:
Function, bits [16:14]
Specifies the function that combines the two resources that define the event.
Resource B, bits [13:7] and Resource A, bits [6:0]
Specify the two resources that are combined by the logical operation specified by the Function field.</desc>
<sw_param offset="0xf889c164" start="16" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCNTVR1_CurrCount">
<name>CurrCount</name>
<desc>Current counter value.</desc>
<sw_param offset="0xf889c170" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCNTVR2_CurrCount">
<name>CurrCount</name>
<desc>Current counter value.</desc>
<sw_param offset="0xf889c174" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMSQ12EVR_TransEvent">
<name>TransEvent</name>
<desc>A Sequencer State Transition Event Register, ETMSQmnEVR, defines the evnet that causes the sequencer state transition from state m to state n.
The format is subdivided as:
Function, bits [16:14]
Specifies the function that combines the two resources that define the event.
Resource B, bits [13:7] and Resource A, bits [6:0]
Specify the two resources that are combined by the logical operation specified by the Function field.</desc>
<sw_param offset="0xf889c180" start="16" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMSQ21EVR_TransEvent">
<name>TransEvent</name>
<desc>A Sequencer State Transition Event Register, ETMSQmnEVR, defines the evnet that causes the sequencer state transition from state m to state n.
The format is subdivided as:
Function, bits [16:14]
Specifies the function that combines the two resources that define the event.
Resource B, bits [13:7] and Resource A, bits [6:0]
Specify the two resources that are combined by the logical operation specified by the Function field.</desc>
<sw_param offset="0xf889c184" start="16" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMSQ23EVR_TransEvent">
<name>TransEvent</name>
<desc>A Sequencer State Transition Event Register, ETMSQmnEVR, defines the evnet that causes the sequencer state transition from state m to state n.
The format is subdivided as:
Function, bits [16:14]
Specifies the function that combines the two resources that define the event.
Resource B, bits [13:7] and Resource A, bits [6:0]
Specify the two resources that are combined by the logical operation specified by the Function field.</desc>
<sw_param offset="0xf889c188" start="16" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMSQ31EVR_TransEvent">
<name>TransEvent</name>
<desc>A Sequencer State Transition Event Register, ETMSQmnEVR, defines the evnet that causes the sequencer state transition from state m to state n.
The format is subdivided as:
Function, bits [16:14]
Specifies the function that combines the two resources that define the event.
Resource B, bits [13:7] and Resource A, bits [6:0]
Specify the two resources that are combined by the logical operation specified by the Function field.</desc>
<sw_param offset="0xf889c18c" start="16" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMSQ32EVR_TransEvent">
<name>TransEvent</name>
<desc>A Sequencer State Transition Event Register, ETMSQmnEVR, defines the evnet that causes the sequencer state transition from state m to state n.
The format is subdivided as:
Function, bits [16:14]
Specifies the function that combines the two resources that define the event.
Resource B, bits [13:7] and Resource A, bits [6:0]
Specify the two resources that are combined by the logical operation specified by the Function field.</desc>
<sw_param offset="0xf889c190" start="16" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMSQ13EVR_TransEvent">
<name>TransEvent</name>
<desc>A Sequencer State Transition Event Register, ETMSQmnEVR, defines the evnet that causes the sequencer state transition from state m to state n.
The format is subdivided as:
Function, bits [16:14]
Specifies the function that combines the two resources that define the event.
Resource B, bits [13:7] and Resource A, bits [6:0]
Specify the two resources that are combined by the logical operation specified by the Function field.</desc>
<sw_param offset="0xf889c194" start="16" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMSQR_CurrentSeqState">
<name>CurrentSeqState</name>
<desc>Indicates the current sequencer state</desc>
<sw_param offset="0xf889c19c" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMEXTOUTEVR1_ExtOutputEvent">
<name>ExtOutputEvent</name>
<desc>External output event. Subdivided as:
Function, bits [16:14]
Specifies the function that combines the two resources that define the event.
Resource B, bits [13:7] and Resource A, bits [6:0]
Specify the two resources that are combined by the logical operation specified by the Function field.</desc>
<sw_param offset="0xf889c1a0" start="16" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMEXTOUTEVR2_ExtOutputEvent">
<name>ExtOutputEvent</name>
<desc>External output event. Subdivided as:
Function, bits [16:14]
Specifies the function that combines the two resources that define the event.
Resource B, bits [13:7] and Resource A, bits [6:0]
Specify the two resources that are combined by the logical operation specified by the Function field.</desc>
<sw_param offset="0xf889c1a4" start="16" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCIDCVR1_ContextID">
<name>ContextID</name>
<desc>Holds a 32-bit Context ID value</desc>
<sw_param offset="0xf889c1b0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCIDCMR_ContextMask">
<name>ContextMask</name>
<desc>Holds a 32-bit Context ID mask</desc>
<sw_param offset="0xf889c1bc" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMSYNCFR_SyncFreq">
<name>SyncFreq</name>
<desc>Synchronization frequency</desc>
<sw_param offset="0xf889c1e0" start="11" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMSYNCFR_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889c1e0" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMIDR_ImplCode">
<name>ImplCode</name>
<desc>Implementor code. The field reads 0x41, ASCII code for A, indicating ARM Limited.</desc>
<sw_param offset="0xf889c1e4" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMIDR_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889c1e4" start="23" end="21" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMIDR_reserved_1">
<name>reserved_1</name>
<desc>Reserved, RAO</desc>
<sw_param offset="0xf889c1e4" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMIDR_SecExtSupp">
<name>SecExtSupp</name>
<desc>Support for security extensions.</desc>
<sw_param offset="0xf889c1e4" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMIDR_Thumb32Supp">
<name>Thumb32Supp</name>
<desc>Support for 32-bit Thumb instructions.</desc>
<sw_param offset="0xf889c1e4" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMIDR_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xf889c1e4" start="17" end="16" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMIDR_Reserved_F">
<name>Reserved_F</name>
<desc>Reserved, 0b1111</desc>
<sw_param offset="0xf889c1e4" start="15" end="12" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMIDR_MajorVer">
<name>MajorVer</name>
<desc>Major architecture version number, 0b0011</desc>
<sw_param offset="0xf889c1e4" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMIDR_MinorVer">
<name>MinorVer</name>
<desc>Minor architecture version number, 0b0000</desc>
<sw_param offset="0xf889c1e4" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMIDR_ImplRev">
<name>ImplRev</name>
<desc>Implementation revision.</desc>
<sw_param offset="0xf889c1e4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCCER_BarrTS">
<name>BarrTS</name>
<desc>Timestamps are not generated for DMB/DSB</desc>
<sw_param offset="0xf889c1e8" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCCER_BarrWP">
<name>BarrWP</name>
<desc>DMB/DSB instructions are not treated as waypoints.</desc>
<sw_param offset="0xf889c1e8" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCCER_RetStack">
<name>RetStack</name>
<desc>Return stack implemented.</desc>
<sw_param offset="0xf889c1e8" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCCER_Timestamp">
<name>Timestamp</name>
<desc>Timestamping implemented.</desc>
<sw_param offset="0xf889c1e8" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCCER_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889c1e8" start="21" end="16" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCCER_InstrumRes">
<name>InstrumRes</name>
<desc>Specifies the number of instrumentation resources.</desc>
<sw_param offset="0xf889c1e8" start="15" end="13" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCCER_Reserved_1">
<name>Reserved_1</name>
<desc>Reserved, RAO</desc>
<sw_param offset="0xf889c1e8" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCCER_RegReads">
<name>RegReads</name>
<desc>Indicates that all registers, except some Integration Test Registers, are readable.</desc>
<sw_param offset="0xf889c1e8" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCCER_ExtInSize">
<name>ExtInSize</name>
<desc>Specifies the size of the extended external input bus, 52.</desc>
<sw_param offset="0xf889c1e8" start="10" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMCCER_ExtInSel">
<name>ExtInSel</name>
<desc>Specifies the number of extended external input selectors, 2.</desc>
<sw_param offset="0xf889c1e8" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMEXTINSELR_ExtInSel2">
<name>ExtInSel2</name>
<desc>Second extended external input selector</desc>
<sw_param offset="0xf889c1ec" start="13" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMEXTINSELR_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889c1ec" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMEXTINSELR_ExtInSel1">
<name>ExtInSel1</name>
<desc>First extended external input selector</desc>
<sw_param offset="0xf889c1ec" start="5" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMAUXCR_ForceSyncInsert">
<name>ForceSyncInsert</name>
<desc>Force insertion of synchronization packets, regardless of current trace activity.
Possible values for this bit are:
b0 = Synchronization packets delayed when trace activity is high. This is the reset value.
b1 = Synchronization packets inserted regardless of trace activity.
This bit might be set if synchronization packets occur too far apart. Setting this bit might cause the trace FIFO to overflow more frequently when trace activity is high.</desc>
<sw_param offset="0xf889c1fc" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMAUXCR_DisableWPUpdate">
<name>DisableWPUpdate</name>
<desc>Specifies whether the PTM issues waypoint update packets if there are more than 4096 bytes between waypoints. Possible values for this bit are:
b0 = PTM always issues update packets if there are more than 4096 bytes between waypoints. This is the reset value.
b1 = PTM does not issue waypoint update packets unless required to do so as the result of an exception or debug entry.</desc>
<sw_param offset="0xf889c1fc" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMAUXCR_DisableTSOnBarr">
<name>DisableTSOnBarr</name>
<desc>Specifies whether the PTM issues a timestamp on a barrier instruction. Possible values for this bit are:
b0 = PTM issues timestamps on barrier instructions. This is the reset value.
b1 = PTM does not issue timestamps on barriers</desc>
<sw_param offset="0xf889c1fc" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMAUXCR_DisableForcedOF">
<name>DisableForcedOF</name>
<desc>Specifies whether the PTM enters overflow state when synchronization is requested,
and the previous synchronization sequence has not yet completed. This does not affect entry to overflow state when the FIFO becomes full. Possible values for this bit are:
b0 = Forced overflow enabled. This is the reset value.
b1 = Forced overflow disabled.</desc>
<sw_param offset="0xf889c1fc" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMTRACEIDR_TraceID">
<name>TraceID</name>
<desc>Before trace is generated, you must program this register with a non-reserved value.
Reserved values are 0x00 and any value in the range 0x70-0x7F. The reset value of this register is 0x00.</desc>
<sw_param offset="0xf889c200" start="6" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_OSLSR_a">
<name>a</name>
<desc>Shows that OS Locking is not implemented.</desc>
<sw_param offset="0xf889c304" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMPDSR_a">
<name>a</name>
<desc>Indicates that the PTM Trace Registers can be accessed.</desc>
<sw_param offset="0xf889c314" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ITMISCOUT_PTMEXTOUT">
<name>PTMEXTOUT</name>
<desc>Drives the PTMEXTOUT[1:0] outputs</desc>
<sw_param offset="0xf889cedc" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ITMISCOUT_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889cedc" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ITMISCOUT_PTMIDLEACK">
<name>PTMIDLEACK</name>
<desc>Drives the PTMIDLEACK output</desc>
<sw_param offset="0xf889cedc" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ITMISCOUT_PTMDBGREQ">
<name>PTMDBGREQ</name>
<desc>Drives the PTMDBGREQ output</desc>
<sw_param offset="0xf889cedc" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ITMISCOUT_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xf889cedc" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ITMISCIN_STANDBYWFI">
<name>STANDBYWFI</name>
<desc>Returns the value of the STANDBYWFI input</desc>
<sw_param offset="0xf889cee0" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ITMISCIN_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889cee0" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ITMISCIN_PTMDBGACK">
<name>PTMDBGACK</name>
<desc>Returns the value of the PTMDBGACK input</desc>
<sw_param offset="0xf889cee0" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ITMISCIN_EXTIN">
<name>EXTIN</name>
<desc>Returns the value of the EXTIN[3:0] inputs</desc>
<sw_param offset="0xf889cee0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ITTRIGGER_PTMTRIGGER">
<name>PTMTRIGGER</name>
<desc>Drives the PTMTRIGGER output</desc>
<sw_param offset="0xf889cee8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ITATBDATA0_ATDATAM31">
<name>ATDATAM31</name>
<desc>Drives the ATDATAM[31] output</desc>
<sw_param offset="0xf889ceec" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ITATBDATA0_ATDATAM23">
<name>ATDATAM23</name>
<desc>Drives the ATDATAM[23] output</desc>
<sw_param offset="0xf889ceec" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ITATBDATA0_ATDATAM15">
<name>ATDATAM15</name>
<desc>Drives the ATDATAM[15] output</desc>
<sw_param offset="0xf889ceec" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ITATBDATA0_ATDATAM7">
<name>ATDATAM7</name>
<desc>Drives the ATDATAM[7] output</desc>
<sw_param offset="0xf889ceec" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ITATBDATA0_ATDATAM0">
<name>ATDATAM0</name>
<desc>Drives the ATDATAM[0] output</desc>
<sw_param offset="0xf889ceec" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ITATBCTR2_AFVALIDM">
<name>AFVALIDM</name>
<desc>Returns the value of the AFVALIDM input</desc>
<sw_param offset="0xf889cef0" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ITATBCTR2_ATREADYM">
<name>ATREADYM</name>
<desc>Returns the value of the ATREADYM input</desc>
<sw_param offset="0xf889cef0" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ITATBID_ATIDM">
<name>ATIDM</name>
<desc>Drives the ATIDM[6:0] outputs</desc>
<sw_param offset="0xf889cef4" start="6" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ITATBCTR0_ATBYTESM">
<name>ATBYTESM</name>
<desc>Drives the ATBYTESM[9:8] outputs</desc>
<sw_param offset="0xf889cef8" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ITATBCTR0_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf889cef8" start="7" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ITATBCTR0_AFREADYM">
<name>AFREADYM</name>
<desc>Drives the AFREADYM output</desc>
<sw_param offset="0xf889cef8" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ITATBCTR0_ATVALIDM">
<name>ATVALIDM</name>
<desc>Drives the ATVALIDM output</desc>
<sw_param offset="0xf889cef8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ETMITCTRL_a">
<name>a</name>
<desc>Enable Integration Test registers.
Before entering integration mode, the PTM must be pwoered up and in programmng mode.
THis means bit 0 of the Main Control Register is set to 0, and bit 10 of the Main Control Register ist set 1.
After leaving integration mode, the PTM must be reset before attempting to perform tracing.</desc>
<sw_param offset="0xf889cf00" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_CTSR_a">
<name>a</name>
<desc>The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed.
Read:
1= Claim tag is implemented, 0 = Claim tag is not implemented
Write:
1= Set claim tag bit, 0= No effect</desc>
<sw_param offset="0xf889cfa0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_CTCR_a">
<name>a</name>
<desc>The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed.
Read: Current value of claim tag.
Write: 1= Clear claim tag bit, 0= No effect</desc>
<sw_param offset="0xf889cfa4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_LAR_a">
<name>a</name>
<desc>Write Access Code.
Write behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
After reset (via PRESETDBGn), PTM is locked, i.e., writes to all other registers using lower 2GB addresses are ignored.
To unlock, 0xC5ACCE55 must be written this register.
After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register.
- PADDRDBG31=1 (upper 2GB):
PTM is unlocked when upper 2GB addresses are used to write to all the registers.
However, write to this register is ignored using a upper 2GB address!
Note: read from this register always returns 0, regardless of PADDRDBG31.</desc>
<sw_param offset="0xf889cfb0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_LSR_n8BIT">
<name>n8BIT</name>
<desc>Set to 0 since PTM implements a 32-bit lock access register</desc>
<sw_param offset="0xf889cfb4" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_LSR_STATUS">
<name>STATUS</name>
<desc>Read behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
When a lower 2GB address is used to read this register, this bit indicates whether PTM is in locked state
(1= locked, 0= unlocked).
- PADDRDBG31=1 (upper 2GB):
always returns 0.</desc>
<sw_param offset="0xf889cfb4" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_LSR_IMP">
<name>IMP</name>
<desc>Read behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
always returns 1, meaning lock mechanism are implemented.
- PADDRDBG31=1 (upper 2GB):
always returns 0, meaning lock mechanism is NOT implemented.</desc>
<sw_param offset="0xf889cfb4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ASR_SNI">
<name>SNI</name>
<desc>Secure non-invasive debug
Always 2'b00,.
This functionality is not implemented</desc>
<sw_param offset="0xf889cfb8" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ASR_SI">
<name>SI</name>
<desc>Secure invasive debug
Always 2'b00.
This functionality is not implemented.</desc>
<sw_param offset="0xf889cfb8" start="5" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ASR_NSNI">
<name>NSNI</name>
<desc>Non-secure non-invasive debug
IF NIDEN or DBGEN is 1, this field is 2'b11, indicating the functionality is implemented and enabled.
Otherwise, this field is 2'b10 (implemented but disabled)</desc>
<sw_param offset="0xf889cfb8" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_ASR_NSI">
<name>NSI</name>
<desc>Non-secure invasive debug
Always 2'b00.
This functionality is not implemented.</desc>
<sw_param offset="0xf889cfb8" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_DEVID_a">
<name>a</name>
<desc>Component capability</desc>
<sw_param offset="0xf889cfc8" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_DTIR_a">
<name>a</name>
<desc>A trace source and processor trace</desc>
<sw_param offset="0xf889cfcc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_PERIPHID4_n4KB_count">
<name>n4KB_count</name>
<desc>4KB Count, set to 0</desc>
<sw_param offset="0xf889cfd0" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_PERIPHID4_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 continuation code</desc>
<sw_param offset="0xf889cfd0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_PERIPHID5_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf889cfd4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_PERIPHID6_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf889cfd8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_PERIPHID7_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf889cfdc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_PERIPHID0_a">
<name>a</name>
<desc>PartNumber0</desc>
<sw_param offset="0xf889cfe0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_PERIPHID1_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 Identity Code [3:0]</desc>
<sw_param offset="0xf889cfe4" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_PERIPHID1_PartNumber1">
<name>PartNumber1</name>
<desc>PartNumber1</desc>
<sw_param offset="0xf889cfe4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_PERIPHID2_RevNum">
<name>RevNum</name>
<desc>Revision number of Peripheral</desc>
<sw_param offset="0xf889cfe8" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_PERIPHID2_JEDEC">
<name>JEDEC</name>
<desc>Indicates that a JEDEC assigned value is used</desc>
<sw_param offset="0xf889cfe8" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_PERIPHID2_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 Identity Code [6:4]</desc>
<sw_param offset="0xf889cfe8" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_PERIPHID3_RevAnd">
<name>RevAnd</name>
<desc>RevAnd, at top level</desc>
<sw_param offset="0xf889cfec" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_PERIPHID3_CustMod">
<name>CustMod</name>
<desc>Customer Modified</desc>
<sw_param offset="0xf889cfec" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_COMPID0_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf889cff0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_COMPID1_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf889cff4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_COMPID2_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf889cff8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_ptm0_COMPID3_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf889cffc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_sd1_SDMA_system_address_register_SDMA_System_Address">
<name>SDMA_System_Address</name>
<desc>Watchdog enable - if set, the watchdog is enabled and can generate any signals that are enabled.</desc>
<sw_param offset="0xe0101000" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_sd1_Block_Size_Block_Count_Blocks_Count_for_Current_Transfer">
<name>Blocks_Count_for_Current_Transfer</name>
<desc>This register is enabled when Block Count Enable in the Transfer
Mode register is set to 1 and is valid only for multiple block transfers. The HC decrements the block count after each block transfer and stops when the count reaches zero. It can be accessed only if no transaction is
executing (i.e after a transaction has stopped). Read operations
during transfer return an invalid value and write operations shall
be ignored. When saving transfer context as a result of Suspend command, the number of blocks yet to be transferred can be determined
by reading this register. When restoring transfer context prior to
issuing a Resume command, the HD shall restore the previously
save block count.
0000h - Stop Count
0001h - 1 block
0002h - 2 blocks
--- ---
FFFFh - 65535 blocks</desc>
<sw_param offset="0xe0101004" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_sd1_Block_Size_Block_Count_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0101004" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_sd1_Block_Size_Block_Count_Host_SDMA_Buffer_Size">
<name>Host_SDMA_Buffer_Size</name>
<desc>Counter clock prescale - selects the prescaler division ratio:
00 = pclk divided by 8
01 = pclk divided by 64
10 = pclk divided by 256
11 = pclk divided by 4096
Note: If a restart signal is received the prescaler should be reset.</desc>
<sw_param offset="0xe0101004" start="14" end="12" />
</parameter>
<parameter uniqueid="ps7_sd1_Block_Size_Block_Count_Transfer_Block_Size">
<name>Transfer_Block_Size</name>
<desc>This register specifies the block size for block data transfers for CMD17, CMD18, CMD24, CMD25, and CMD53. It can be accessed only if no transaction is executing (i.e after a transaction has stopped). Read operations during transfer return an invalid value and write operations shall be ignored.
0000h - No Data Transfer
0001h - 1 Byte
0002h - 2 Bytes
0003h - 3 Bytes
0004h - 4 Bytes
--- ---
01FFh - 511 Bytes
0200h - 512 Bytes
--- ---
0800h - 2048 Bytes</desc>
<sw_param offset="0xe0101004" start="11" end="0" />
</parameter>
<parameter uniqueid="ps7_sd1_Argument_Command_Argument">
<name>Command_Argument</name>
<desc>The SD Command Argument is specified as bit39-8 of Command-Format.</desc>
<sw_param offset="0xe0101008" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_sd1_Transfer_Mode_Command_Command_Index">
<name>Command_Index</name>
<desc>This bit shall be set to the command number (CMD0-63, ACMD0-63).</desc>
<sw_param offset="0xe010100c" start="28" end="24" />
</parameter>
<parameter uniqueid="ps7_sd1_Transfer_Mode_Command_Command_Type">
<name>Command_Type</name>
<desc>There are three types of special commands. Suspend, Resume and Abort. These bits shall bet set to 00b for all other commands. Suspend Command If the Suspend command succeeds, the HC shall assume the SD Bus has been released and that it is possible to issue the next command which uses the DAT line. The HC shall de-assert Read Wait for read transactions and stop checking busy for write transactions. The Interrupt cycle shall start, in 4-bit mode. If the Suspend command fails, the HC shall maintain its current state. and the HD shall restart the transfer by setting Continue Request in the Block Gap Control Register. Resume Command The HD re-starts the data transfer by restoring the registers in the range of 000-00Dh. The HC shall check for busy before starting write transfers. Abort Command If this command is set when executing a read transfer, the HC shall stop reads to the buffer. If this command is set when executing a write transfer, the HC shall stop driving the DAT line. After issuing the Abort command, the HD should issue a software reset
00b - Normal
01b - Suspend
10b - Resume
11b - Abort</desc>
<sw_param offset="0xe010100c" start="23" end="22" />
</parameter>
<parameter uniqueid="ps7_sd1_Transfer_Mode_Command_Data_Present_Select">
<name>Data_Present_Select</name>
<desc>This bit is set to 1 to indicate that data is present and shall be transferred using the DAT line. If is set to 0 for the following:
1. Commands using only CMD line (ex. CMD52)
2. Commands with no data transfer but using busy signal on DAT[0]
line (R1b or R5b ex. CMD38)
3. Resume Command
0 - No Data Present
1 - Data Present</desc>
<sw_param offset="0xe010100c" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_sd1_Transfer_Mode_Command_Command_Index_Check_Enable">
<name>Command_Index_Check_Enable</name>
<desc>If this bit is set to 1, the HC shall check the index field in the response to see if it has the same value as the command index. If it is not, it is reported as a Command Index Error. If this bit is set to 0, the Index field is not checked.
0 - Disable
1 - Enable</desc>
<sw_param offset="0xe010100c" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_sd1_Transfer_Mode_Command_Command_CRC_Check_Enable">
<name>Command_CRC_Check_Enable</name>
<desc>If this bit is set to 1, the HC shall check the CRC field in the response. If an error is detected, it is reported as a Command CRC Error. If this bit is set to 0, the CRC field is not checked.
0 - Disable
1 - Enable</desc>
<sw_param offset="0xe010100c" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_sd1_Transfer_Mode_Command_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe010100c" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_sd1_Transfer_Mode_Command_Response_Type_Select">
<name>Response_Type_Select</name>
<desc>Response Type Select
00 - No Response
01 - Response length 136
10 - Response length 48
11 - Response length 48 check
Busy after response</desc>
<sw_param offset="0xe010100c" start="17" end="16" />
</parameter>
<parameter uniqueid="ps7_sd1_Transfer_Mode_Command_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe010100c" start="15" end="6" />
</parameter>
<parameter uniqueid="ps7_sd1_Transfer_Mode_Command_Multi_Single_Block_Select">
<name>Multi_Single_Block_Select</name>
<desc>This bit enables multiple block DAT line data transfers.
0 - Single Block
1 - Multiple Block</desc>
<sw_param offset="0xe010100c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_sd1_Transfer_Mode_Command_Data_Transfer_Direction_Select">
<name>Data_Transfer_Direction_Select</name>
<desc>This bit defines the direction of DAT line data transfers.
0 - Write (Host to Card)
1 - Read (Card to Host)</desc>
<sw_param offset="0xe010100c" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_sd1_Transfer_Mode_Command_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe010100c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_sd1_Transfer_Mode_Command_Auto_CMD12_Enable">
<name>Auto_CMD12_Enable</name>
<desc>Multiple block transfers for memory require CMD12 to stop the ransaction. When this bit is set to 1, the HC shall issue CMD12 utomatically when last block transfer is completed. The HD shall not set this bit to issue commands that do not require CMD12 to stop data transfer.
0 - Disable
1 - Enable</desc>
<sw_param offset="0xe010100c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_sd1_Transfer_Mode_Command_Block_Count_Enable">
<name>Block_Count_Enable</name>
<desc>This bit is used to enable the Block count register, which is only relevant for multiple block transfers. When this bit is 0, the Block Count register is disabled, which is useful in executing an infinite transfer.
0 - Disable
1 - Enable</desc>
<sw_param offset="0xe010100c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_sd1_Transfer_Mode_Command_DMA_Enable">
<name>DMA_Enable</name>
<desc>DMA can be enabled only if DMA Support bit in the Capabilities register is set. If this bit is set to 1, a DMA operation shall begin when the HD writes to the upper byte of Command register (00Fh).
0 - Disable
1 - Enable</desc>
<sw_param offset="0xe010100c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_sd1_Response0_Command_Response">
<name>Command_Response</name>
<desc>command responses registers</desc>
<sw_param offset="0xe0101010" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_sd1_Response1_Command_Response">
<name>Command_Response</name>
<desc>command responses registers</desc>
<sw_param offset="0xe0101014" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_sd1_Response2_Command_Response">
<name>Command_Response</name>
<desc>command responses registers</desc>
<sw_param offset="0xe0101018" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_sd1_Response3_Command_Response">
<name>Command_Response</name>
<desc>command responses registers</desc>
<sw_param offset="0xe010101c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_sd1_Buffer_Data_Port_Buffer_Data">
<name>Buffer_Data</name>
<desc>The Host Controller Buffer can be accessed through this 32-bit Data Port Register.</desc>
<sw_param offset="0xe0101020" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_sd1_Present_State_CMD_Line_Signal_Level">
<name>CMD_Line_Signal_Level</name>
<desc>This status is used to check CMD line level to recover from errors, and for debugging.</desc>
<sw_param offset="0xe0101024" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_sd1_Present_State_DAT_Bit3_Bit0_Line_Signal_Level">
<name>DAT_Bit3_Bit0_Line_Signal_Level</name>
<desc>This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[0].
D23 - DAT[3]
D22 - DAT[2]
D21 - DAT[1]
D20 - DAT[0]</desc>
<sw_param offset="0xe0101024" start="23" end="20" />
</parameter>
<parameter uniqueid="ps7_sd1_Present_State_Write_Protect_Switch_Pin_Level">
<name>Write_Protect_Switch_Pin_Level</name>
<desc>The Write Protect Switch is supported for memory and combo cards. This bit reflects the SDWP# pin.
0 - Write protected (SDWP# = 1)
1 - Write enabled (SDWP# = 0)</desc>
<sw_param offset="0xe0101024" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_sd1_Present_State_Card_Detect_Pin_Level">
<name>Card_Detect_Pin_Level</name>
<desc>This bit reflects the inverse value of the SDCD# pin.
0 - No Card present (SDCD# = 1)
1 - Card present (SDCD# = 0)</desc>
<sw_param offset="0xe0101024" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_sd1_Present_State_Card_State_Stable">
<name>Card_State_Stable</name>
<desc>This bit is used for testing. If it is 0, the Card Detect Pin Level is not stable. If this bit is set to 1, it means the Card Detect Pin Level is stable. The Software Reset For All in the Software Reset Register shall not affect this bit.
0 - Reset of Debouncing
1 - No Card or Inserted</desc>
<sw_param offset="0xe0101024" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_sd1_Present_State_Card_Inserted">
<name>Card_Inserted</name>
<desc>This bit indicates whether a card has been inserted. Changing from 0 to 1 generates a Card Insertion interrupt in the Normal Interrupt Status register and changing from 1 to 0 generates a Card Removal Interrupt in the Normal Interrupt Status register. The Software Reset For All in the Software Reset register shall not affect this bit. If a Card is removed while its power is on and its clock is oscillating, the HC shall clear SD Bus Power in the Power Control register and SD Clock Enable in the Clock control register. In addition the HD should clear the HC by the Software Reset For All in Software register. The card detect is active regardless of the SD Bus Power.
0 - Reset or Debouncing or No Card
1 - Card Inserted</desc>
<sw_param offset="0xe0101024" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_sd1_Present_State_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe0101024" start="15" end="12" />
</parameter>
<parameter uniqueid="ps7_sd1_Present_State_Buffer_Read_Enable">
<name>Buffer_Read_Enable</name>
<desc>This status is used for non-DMA read transfers. This read only flag indicates that valid data exists in the host side buffer status. If this bit is 1, readable data exists in the buffer. A change of this bit from 1 to 0 occurs when all the block data is read from the buffer. A change of this bit from 0 to 1 occurs when all the block data is ready in the buffer and generates the Buffer Read Ready Interrupt.
0 - Read Disable
1 - Read Enable.</desc>
<sw_param offset="0xe0101024" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_sd1_Present_State_Buffer_Write_Enable">
<name>Buffer_Write_Enable</name>
<desc>This status is used for non-DMA write transfers. This read only flag indicates if space is available for write data. If this bit is 1, data can be written to the buffer. A change of this bit from 1 to 0 occurs when all the block data is written to the buffer. A change of this bit from 0 to 1 occurs when top of block data can be written to the buffer and generates the Buffer Write Ready Interrupt.
0 - Write Disable
1 - Write Enable.</desc>
<sw_param offset="0xe0101024" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_sd1_Present_State_Read_Transfer_Active">
<name>Read_Transfer_Active</name>
<desc>This status is used for detecting completion of a read transfer.
This bit is set to 1 for either of the following conditions:
1. After the end bit of the read command
2. When writing a 1 to continue Request in the Block Gap Control register to restart a read transfer
This bit is cleared to 0 for either of the following
conditions:
1. When the last data block as specified by block length is transferred to the system.
2. When all valid data blocks have been transferred to the system and no current block transfers are being sent as a result of the Stop At Block Gap Request set to 1. A transfer complete interrupt is generated when this bit changes to 0.
1 - Transferring data
0 - No valid data</desc>
<sw_param offset="0xe0101024" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_sd1_Present_State_Write_Transfer_Active">
<name>Write_Transfer_Active</name>
<desc>This status indicates a write transfer is active. If this bit is 0, it means no valid write data exists in the HC. This bit is set in either of the following cases:
1. After the end bit of the write command.
2. When writing a 1 to Continue Request in the Block Gap Control register to restart a write transfer.
This bit is cleared in either of the following cases:
1. After getting the CRC status of the last data block as specified by the transfer count (Single or Multiple)
2. After getting a CRC status of any block where data transmission is about to be stopped by a Stop At Block Gap Request.
During a write transaction, a Block Gap Event interrupt is generated when this bit is changed to 0, as a result of the Stop At Block Gap Request being set. This status is useful for the HD in determining when to issue commands during write busy.
1 - transferring data
0 - No valid data</desc>
<sw_param offset="0xe0101024" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_sd1_Present_State_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0101024" start="7" end="3" />
</parameter>
<parameter uniqueid="ps7_sd1_Present_State_DAT_Line_Active">
<name>DAT_Line_Active</name>
<desc>This bit indicates whether one of the DAT line on SD bus is in use.
1 - DAT line active
0 - DAT line inactive</desc>
<sw_param offset="0xe0101024" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_sd1_Present_State_Command_Inhibit_DAT">
<name>Command_Inhibit_DAT</name>
<desc>This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1. If this bit is 0, it indicates the HC can issue the next SD command. Commands with busy signal belong to Command Inhibit (DAT) (ex. R1b, R5b type). Changing from 1 to 0 generates a Transfer Complete interrupt in the Normal interrupt status register.
Note: The SD Host Driver can save registers in the range of 000-00Dh for a suspend transaction after this bit has changed from 1 to 0.
1 - cannot issue command which uses the DAT line
0 - Can issue command which uses the DAT line</desc>
<sw_param offset="0xe0101024" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_sd1_Present_State_Command_Inhibit_CMD">
<name>Command_Inhibit_CMD</name>
<desc>If this bit is 0, it indicates the CMD line is not in use and the HC can issue a SD command using the CMD line. This bit is set immediately after the Command register (00Fh) is written. This bit is cleared when the command response is received. Even if the Command Inhibit (DAT) is set to 1, Commands using only the CMD line can be issued if this bit is 0. Changing from 1 to 0 generates a Command complete interrupt in the Normal Interrupt Status register. If the HC cannot issue the command because of a command conflict error or because of Command Not Issued By Auto CMD12 Error, this bit shall remain 1 and the Command Complete is not set. Status issuing Auto CMD12 is not read from this bit.</desc>
<sw_param offset="0xe0101024" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_sd1_Host_control_Power_control_Block_Gap_Control_Wakeup_control_reserved_3">
<name>reserved_3</name>
<desc>Reserved</desc>
<sw_param offset="0xe0101028" start="31" end="27" />
</parameter>
<parameter uniqueid="ps7_sd1_Host_control_Power_control_Block_Gap_Control_Wakeup_control_Wakeup_Event_Enable_On_SD_Card_Removal">
<name>Wakeup_Event_Enable_On_SD_Card_Removal</name>
<desc>This bit enables wakeup event via
Card Removal assertion in the
Normal Interrupt Status register.
FN_WUS (Wake up Support) in
CIS does not affect this bit.
1 - Enable
0 - Disable</desc>
<sw_param offset="0xe0101028" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_sd1_Host_control_Power_control_Block_Gap_Control_Wakeup_control_Wakeup_Event_Enable_On_SD_Card_Insertion">
<name>Wakeup_Event_Enable_On_SD_Card_Insertion</name>
<desc>This bit enables wakeup event via Card Insertion assertion in the Normal Interrupt Status register. FN_WUS (Wake up Support) in CIS does not affect this bit.
1 - Enable
0 - Disable</desc>
<sw_param offset="0xe0101028" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_sd1_Host_control_Power_control_Block_Gap_Control_Wakeup_control_Wakeup_Event_Enable_On_Card_Interrupt">
<name>Wakeup_Event_Enable_On_Card_Interrupt</name>
<desc>This bit enables wakeup event via
Card Interrupt assertion in the
Normal Interrupt Status register.
This bit can be set to 1 if FN_WUS
(Wake Up Support) in CIS is set to
1.
1 - Enable
0 - Disable</desc>
<sw_param offset="0xe0101028" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_sd1_Host_control_Power_control_Block_Gap_Control_Wakeup_control_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe0101028" start="23" end="20" />
</parameter>
<parameter uniqueid="ps7_sd1_Host_control_Power_control_Block_Gap_Control_Wakeup_control_Interrupt_At_Block_Gap">
<name>Interrupt_At_Block_Gap</name>
<desc>This bit is valid only in 4-bit mode of the SDIO
card and selects a sample point in the interrupt
cycle. Setting to 1 enables interrupt detection at
the block gap for a multiple block transfer. If the
SD card cannot signal an interrupt during a multiple
block transfer, this bit should be set to 0.
When the HD detects an SD card insertion, it shall
set this bit according to the CCCR of the SDIO
card.</desc>
<sw_param offset="0xe0101028" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_sd1_Host_control_Power_control_Block_Gap_Control_Wakeup_control_Read_Wait_Control">
<name>Read_Wait_Control</name>
<desc>The read wait function is optional for SDIO cards.
If the card supports read wait, set this bit to
enable use of the read wait protocol to stop read
data using DAT[2] line. Otherwise the HC has to
stop the SD clock to hold read data, which
restricts commands generation. When the HD
detects an SD card insertion, it shall set this bit
according to the CCCR of the SDIO card. If the
card does not support read wait, this bit shall
never be set to 1 otherwise DAT line conflict may
occur. If this bit is set to 0, Suspend / Resume
cannot be supported
1 - Enable Read Wait Control
0 - Disable Read Wait Control</desc>
<sw_param offset="0xe0101028" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_sd1_Host_control_Power_control_Block_Gap_Control_Wakeup_control_Continue_Request">
<name>Continue_Request</name>
<desc>This bit is used to restart a transaction which was stopped using the Stop At Block Gap Request. To
cancel stop at the block gap, set Stop At block
Gap Request to 0 and set this bit to restart the
transfer.
The HC automatically clears this bit in either of
the following cases:
1) In the case of a read transaction, the DAT Line
Active changes from 0 to 1 as a read transaction
restarts.
2) In the case of a write transaction, the Write
transfer active changes from 0 to 1 as the write
transaction restarts.
Therefore it is not necessary for Host driver to set
this bit to 0. If Stop At Block Gap Request is set to
1, any write to this bit is ignored.
1 - Restart
0 - Ignored</desc>
<sw_param offset="0xe0101028" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_sd1_Host_control_Power_control_Block_Gap_Control_Wakeup_control_Stop_At_Block_Gap_Request">
<name>Stop_At_Block_Gap_Request</name>
<desc>This bit is used to stop executing a transaction at the next block gap for non- DMA,SDMA and ADMA transfers. Until the transfer complete is set
to 1, indicating a transfer completion the HD shall leave this bit set to 1. Clearing both the Stop At Block Gap Request and Continue Request shall not cause the transaction to restart. Read Wait is used to stop the read transaction at the block gap. The HC shall honour Stop At Block Gap Request for write transfers, but for read transfers it requires that the SD card support Read Wait. Therefore the HD shall not set this bit during read transfers unless the SD card supports Read Wait and has set Read Wait Control to 1. In case of write transfers in which the HD writes data to the Buffer Data Port register, the HD shall set this bit after all block data is written. If this bit is set to 1, the HD shall not write data to Buffer data port register. This bit affects Read Transfer Active, Write Transfer Active, DAT line active and Command Inhibit (DAT) in the Present State register.
1 - Stop
0 - Transfer</desc>
<sw_param offset="0xe0101028" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_sd1_Host_control_Power_control_Block_Gap_Control_Wakeup_control_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe0101028" start="15" end="12" />
</parameter>
<parameter uniqueid="ps7_sd1_Host_control_Power_control_Block_Gap_Control_Wakeup_control_SD_Bus_Voltage_Select">
<name>SD_Bus_Voltage_Select</name>
<desc>By setting these bits, the HD selects the voltage level for the SD card. Before setting this register, the HD shall check the voltage support bits
in the capabilities register. If an unsupported voltage is selected, the
Host System shall not supply SD bus voltage
111b - 3.3 Flattop.)
110b - 3.0 V(Typ.)
101b - 1.8 V(Typ.)
100b - 000b - Reserved</desc>
<sw_param offset="0xe0101028" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_sd1_Host_control_Power_control_Block_Gap_Control_Wakeup_control_SD_Bus_Power">
<name>SD_Bus_Power</name>
<desc>Before setting this bit, the SD host driver shall set SD Bus Voltage Select. If the HC detects the No Card State, this bit shall be cleared.
1 - Power on
0 - Power off</desc>
<sw_param offset="0xe0101028" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_sd1_Host_control_Power_control_Block_Gap_Control_Wakeup_control_Card_detect_signal_detetction">
<name>Card_detect_signal_detetction</name>
<desc>This bit selects source for card detection.
1- The card detect test level is selected
0 -SDCD# is selected (for normal use)</desc>
<sw_param offset="0xe0101028" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_sd1_Host_control_Power_control_Block_Gap_Control_Wakeup_control_Card_Detect_Test_Level">
<name>Card_Detect_Test_Level</name>
<desc>This bit is enabled while the Card Detect Signal Selection is set to 1 and it
indicates card inserted or not. Generates (card ins or card removal) interrupt when the normal int sts enable bit is set.
1 - Card Inserted
0 - No Card</desc>
<sw_param offset="0xe0101028" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_sd1_Host_control_Power_control_Block_Gap_Control_Wakeup_control_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0101028" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_sd1_Host_control_Power_control_Block_Gap_Control_Wakeup_control_DMA_Select">
<name>DMA_Select</name>
<desc>One of supported DMA modes can be selected. The host driver shall check support of DMA modes by referring the Capabilities register.
00 - SDMA is selected
01 - 32-bit Address ADMA1 is selected
10 -32-bit Address ADMA2 is selected
11 - 64-bit Address ADMA2 is selected</desc>
<sw_param offset="0xe0101028" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_sd1_Host_control_Power_control_Block_Gap_Control_Wakeup_control_High_Speed_Enable">
<name>High_Speed_Enable</name>
<desc>This bit is optional. Before setting this bit, the HD shall check the High Speed Support in the capabilities register. If this bit is set to 0 (default), the HC outputs CMD line and DAT lines at the falling edge of the SD clock (up to 25 MHz/20MHz for MMC). If this bit is set to 1, the HC outputs CMD line and DAT lines at the rising edge of the SD clock (up to 50 MHz for SD/52MHz for MMC)
1 - High Speed Mode
0 - Normal Speed Mode</desc>
<sw_param offset="0xe0101028" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_sd1_Host_control_Power_control_Block_Gap_Control_Wakeup_control_Data_Transfer_Width_SD1_or_SD4">
<name>Data_Transfer_Width_SD1_or_SD4</name>
<desc>This bit selects the data width of the HC. The HD shall select it to match the data width of the SD card.
1 - 4 bit mode
0 - 1 bit mode</desc>
<sw_param offset="0xe0101028" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_sd1_Host_control_Power_control_Block_Gap_Control_Wakeup_control_LED_Control">
<name>LED_Control</name>
<desc>This bit is used to caution the user not to remove the card while the SD card is being accessed. If the software is going to issue multiple SD commands, this bit can be set during all transactions. It is not necessary to change for each transaction.
1 - LED on
0 - LED off</desc>
<sw_param offset="0xe0101028" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_sd1_Clock_Control_Timeout_control_Software_reset_Software_Reset_for_DAT_Line">
<name>Software_Reset_for_DAT_Line</name>
<desc>Only part of data circuit is reset. The following registers and bits are cleared by this bit:
Buffer Data Port Register
Buffer is cleared and Initialized.
Present State register
Buffer read Enable
Buffer write Enable
Read Transfer Active
Write Transfer Active
DAT Line Active
Command Inhibit (DAT)
Block Gap Control register
Continue Request
Stop At Block Gap Request
Normal Interrupt Status register
Buffer Read Ready
Buffer Write Ready
Block Gap Event
Transfer Complete
1 - Reset
0 - Work</desc>
<sw_param offset="0xe010102c" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_sd1_Clock_Control_Timeout_control_Software_reset_Software_Reset_for_CMD_Line">
<name>Software_Reset_for_CMD_Line</name>
<desc>Only part of command circuit is reset. The following registers and bits are cleared by this bit:
Present State register
Command Inhibit (CMD)
Normal Interrupt Status register
Command Complete
1 - Reset
0 - Work</desc>
<sw_param offset="0xe010102c" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_sd1_Clock_Control_Timeout_control_Software_reset_Software_Reset_for_All">
<name>Software_Reset_for_All</name>
<desc>This reset affects the entire HC except for the card detection circuit. Register bits of type ROC, RW, RW1C, RWAC are cleared to 0. During its initialization, the HD shall set this bit to 1 to reset the HC. The HC shall reset this bit to 0 when capabilities registers are valid and the HD
can read them. Additional use of Software Reset For All may not affect the value of the Capabilities registers. If this bit is set to 1, the SD card shall reset itself and must be re initialized by the HD.
1 - Reset
0 - Work</desc>
<sw_param offset="0xe010102c" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_sd1_Clock_Control_Timeout_control_Software_reset_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe010102c" start="23" end="20" />
</parameter>
<parameter uniqueid="ps7_sd1_Clock_Control_Timeout_control_Software_reset_Data_Timeout_Counter_Value_">
<name>Data_Timeout_Counter_Value_</name>
<desc>This value determines the interval by which DAT line time-outs are detected. Refer to the Data Time-out Error in the Error Interrupt Status register for information on factors that dictate time-out generation. Time-out clock frequency will be generated by dividing the sdclockTMCLK by this value. When setting this register, prevent inadvertent time-out events by clearing the Data
Time-out Error Status Enable (in the Error Interrupt Status Enable register)
1111 - Reserved
1110 - TMCLK * 2^27
------------------------------
------------------------------
0001 - TMCLK * 2^14
0000 - TMCLK * 2^13</desc>
<sw_param offset="0xe010102c" start="19" end="16" />
</parameter>
<parameter uniqueid="ps7_sd1_Clock_Control_Timeout_control_Software_reset_SDCLK_Frequency_Select">
<name>SDCLK_Frequency_Select</name>
<desc>This register is used to select the frequency of the SDCLK pin. The frequency is not programmed directly; rather this register holds the divisor of the Base Clock Frequency For SD clock in the capabilities register. Only the following settings are allowed.
80h - base clock divided by 256
40h - base clock divided by 128
20h - base clock divided by 64
10h - base clock divided by 32
08h - base clock divided by 16
04h - base clock divided by 8
02h - base clock divided by 4
01h - base clock divided by 2
00h - base clock(10MHz-63MHz)
Setting 00h specifies the highest frequency of the SD Clock. When setting multiple bits, the most significant bit is used as the divisor. But multiple bits should not be set. The two default divider values can be calculated by the frequency that is defined by the Base Clock Frequency For SD Clock in the Capabilities register.
1) 25 MHz divider value
2) 400 KHz divider value
The frequency of the SDCLK is set by the following formula:
Clock Frequency = (Baseclock) / divisor.
Thus choose the smallest possible divisor which results in a clock frequency that is less than or equal to the target frequency.
Maximum Frequency for SD = 50Mhz (base clock)
Maximum Frequency for MMC = 52Mhz (base clock)
Minimum Frequency = 195.3125Khz (50Mhz / 256), same calc for MMC also</desc>
<sw_param offset="0xe010102c" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_sd1_Clock_Control_Timeout_control_Software_reset_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe010102c" start="7" end="3" />
</parameter>
<parameter uniqueid="ps7_sd1_Clock_Control_Timeout_control_Software_reset_SD_Clock_Enable">
<name>SD_Clock_Enable</name>
<desc>The HC shall stop SDCLK when writing this bit to 0. SDCLK frequency Select can be changed when this bit is 0. Then, the HC shall maintain the same clock frequency until SDCLK is stopped (Stop at SDCLK = 0). If the HC detects the No Card state, this bit shall be cleared.
1 - Enable
0 - Disable</desc>
<sw_param offset="0xe010102c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_sd1_Clock_Control_Timeout_control_Software_reset_Internal_Clock_Stable">
<name>Internal_Clock_Stable</name>
<desc>This bit is set to 1 when SD clock is stable after writing to Internal Clock Enable in this register to 1. The SD Host Driver shall wait to set SD Clock Enable until this bit is set to 1.
Note: This is useful when using PLL for a clock oscillator that requires setup time.
1 - Ready
0 - Not Ready</desc>
<sw_param offset="0xe010102c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_sd1_Clock_Control_Timeout_control_Software_reset_Internal_Clock_Enable">
<name>Internal_Clock_Enable</name>
<desc>This bit is set to 0 when the HD is not using the HC or the HC awaits a wakeup event. The HC should stop its internal clock to go very low power state. Still, registers shall be able to be read and written. Clock starts to oscillate when this bit is set to 1. When clock oscillation is stable, the HC shall set Internal Clock Stable in this register to 1. This bit shall not affect card detection.
1 - Oscillate
0 - Stop</desc>
<sw_param offset="0xe010102c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_Error_interrupt_status_Ceata_Error_Status">
<name>Ceata_Error_Status</name>
<desc>Occurs when ATA command termination has occured due to an error condition the device has encountered.
0 - no error
1 - error</desc>
<sw_param offset="0xe0101030" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_Error_interrupt_status_Target_Response_error">
<name>Target_Response_error</name>
<desc>Occurs when detecting ERROR in m_hresp(dma transaction)
0 - no error
1 - error</desc>
<sw_param offset="0xe0101030" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_Error_interrupt_status_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe0101030" start="27" end="26" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_Error_interrupt_status_ADMA_Error">
<name>ADMA_Error</name>
<desc>This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register.
1- Error
0 -No error</desc>
<sw_param offset="0xe0101030" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_Error_interrupt_status_Auto_CMD12_Error">
<name>Auto_CMD12_Error</name>
<desc>Occurs when detecting that one of the bits in Auto CMD12 Error Status register has changed from 0 to 1. This bit is set to 1 also when Auto CMD12 is not executed due to the previous command error.
0 - No Error
1 - Error</desc>
<sw_param offset="0xe0101030" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_Error_interrupt_status_Current_Limit_Error">
<name>Current_Limit_Error</name>
<desc>By setting the SD Bus Power bit in the Power Control Register, the HC is requested to supply power for the SD Bus. If the HC supports the Current Limit Function, it can be protected from an Illegal card by stopping power supply to the card in which case this bit indicates a failure status. Reading 1 means the HC is not supplying power to SD card due to some failure. Reading 0 means that the HC is supplying power and no error has occurred. This bit shall always set to be 0, if the HC does not support this function.
0 - No Error
1 - Power Fail</desc>
<sw_param offset="0xe0101030" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_Error_interrupt_status_Data_End_Bit_Error">
<name>Data_End_Bit_Error</name>
<desc>Occurs when detecting 0 at the end bit position of read data which uses the DAT line or the end bit position of the CRC status.
0 - No Error
1 - Error</desc>
<sw_param offset="0xe0101030" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_Error_interrupt_status_Data_CRC_Error">
<name>Data_CRC_Error</name>
<desc>Occurs when detecting CRC error when transferring read data which uses the DAT line or when detecting the Write CRC Status having a value of other than '010'.
0 - No Error
1 - Error</desc>
<sw_param offset="0xe0101030" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_Error_interrupt_status_Data_Timeout_Error">
<name>Data_Timeout_Error</name>
<desc>Occurs when detecting one of following timeout conditions.
1. Busy Timeout for R1b, R5b type.
2. Busy Timeout after Write CRC status
3. Write CRC status Timeout
4. Read Data Timeout
0 - No Error
1 - Timeout</desc>
<sw_param offset="0xe0101030" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_Error_interrupt_status_Command_Index_Error">
<name>Command_Index_Error</name>
<desc>Occurs if a Command Index error occurs in the Command Response.
0 - No Error
1 - Error</desc>
<sw_param offset="0xe0101030" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_Error_interrupt_status_Command_End_Bit_Error">
<name>Command_End_Bit_Error</name>
<desc>Occurs when detecting that the end bit of a command response is 0.
0 - No Error
1 - End Bit Error Generated</desc>
<sw_param offset="0xe0101030" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_Error_interrupt_status_Command_CRC_Error">
<name>Command_CRC_Error</name>
<desc>Command CRC Error is generated in two cases.
1. If a response is returned and the Command Time-out Error is set to 0, this bit is set to 1 when detecting a CRT error in the command response
2. The HC detects a CMD line conflict by monitoring the CMD line when a command is issued. If the HC drives the CMD line to 1 level, but detects 0 level on the CMD line at the next SDCLK edge, then the HC shall abort the command (Stop driving CMD line) and set this bit to 1. The Command Timeout Error shall also be set to 1 to distinguish CMD line conflict.
0 - No Error
1 - CRC Error Generated</desc>
<sw_param offset="0xe0101030" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_Error_interrupt_status_Command_Timeout_Error">
<name>Command_Timeout_Error</name>
<desc>Occurs only if the no response is returned within 64 SDCLK cycles from the end bit of the command. If the HC detects a CMD line conflict, in which case Command CRC Error shall also be set. This bit shall be set without waiting for 64 SDCLK cycles because the command will be aborted by the HC.
0 - No Error
1 - Timeout</desc>
<sw_param offset="0xe0101030" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_Error_interrupt_status_Error_Interrupt">
<name>Error_Interrupt</name>
<desc>If any of the bits in the Error Interrupt Status Register are set, then this bit is set. Therefore the HD can test for an error by checking this bit first.
0 - No Error.
1 - Error.</desc>
<sw_param offset="0xe0101030" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_Error_interrupt_status_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0101030" start="14" end="11" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_Error_interrupt_status_Boot_terminate_Interrupt">
<name>Boot_terminate_Interrupt</name>
<desc>This status is set if the boot opeartion get terminated
0 - Boot operation is not teminated.
1 - Boot operation is teminated</desc>
<sw_param offset="0xe0101030" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_Error_interrupt_status_Boot_ack_rcv">
<name>Boot_ack_rcv</name>
<desc>This status is set if the boot acknowledge is received from device.
0 - Boot ack is not received.
1 - Boot ack is received.</desc>
<sw_param offset="0xe0101030" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_Error_interrupt_status_Card_Interrupt">
<name>Card_Interrupt</name>
<desc>Writing this bit to 1 does not clear this bit. It is cleared by resetting the SD card interrupt factor. In 1-bit mode, the HC shall detect the Card Interrupt without SD Clock to support wakeup. In 4-bit mode, the card interrupt signal is sampled during the interrupt cycle, so there are some sample delays between the interrupt signal from the card and the interrupt to the Host system.
when this status has been set and the HD needs to start this interrupt service, Card Interrupt Status Enable in the Normal Interrupt Status register shall be set to 0 in order to clear the card interrupt statuses latched in the HC and stop driving the Host System. After completion of the card interrupt service (the reset factor in the SD card and the interrupt signal may not be asserted), set Card Interrupt Status Enable to 1 and start sampling the interrupt signal again.
0 - No Card Interrupt
1 - Generate Card Interrupt</desc>
<sw_param offset="0xe0101030" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_Error_interrupt_status_Card_Removal">
<name>Card_Removal</name>
<desc>This status is set if the Card Inserted in the Present State register changes from 1 to 0. When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed.
Because the card detect may possibly be changed when the HD clear this bit an Interrupt event may not be generated.
0 - Card State Stable or Debouncing
1 - Card Removed</desc>
<sw_param offset="0xe0101030" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_Error_interrupt_status_Card_Insertion">
<name>Card_Insertion</name>
<desc>This status is set if the Card Inserted in the Present State register changes from 0 to 1. When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed.
Because the card detect may possibly be changed when the HD clear this bit an Interrupt event may not be generated.
0 - Card State Stable or Debouncing
1 - Card Inserted</desc>
<sw_param offset="0xe0101030" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_Error_interrupt_status_Buffer_Read_Ready">
<name>Buffer_Read_Ready</name>
<desc>This status is set if the Buffer Read Enable
changes from 0 to 1.
0 - Not Ready to read Buffer.
1 - Ready to read Buffer.</desc>
<sw_param offset="0xe0101030" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_Error_interrupt_status_Buffer_Write_Ready">
<name>Buffer_Write_Ready</name>
<desc>This status is set if the Buffer Write Enable
changes from 0 to 1.
0 - Not Ready to Write Buffer.
1 - Ready to Write Buffer.</desc>
<sw_param offset="0xe0101030" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_Error_interrupt_status_DMA_Interrupt">
<name>DMA_Interrupt</name>
<desc>This status is set if the HC detects the Host
DMA Buffer Boundary in the Block Size
regiser.
0 - No DMA Interrupt
1 - DMA Interrupt is Generated</desc>
<sw_param offset="0xe0101030" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_Error_interrupt_status_Block_Gap_Event">
<name>Block_Gap_Event</name>
<desc>If the Stop At Block Gap Request in the Block
Gap Control Register is set, this bit is set.
Read Transaction:
This bit is set at the falling edge of the DAT
Line Active Status (When the transaction is
stopped at SD Bus timing. The Read Wait
must be supported inorder to use this function).
Write Transaction:
This bit is set at the falling edge of Write
Transfer Active Status (After getting CRC status
at SD Bus timing).
0 - No Block Gap Event
1 - Transaction stopped at Block
Gap</desc>
<sw_param offset="0xe0101030" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_Error_interrupt_status_Transfer_Complete">
<name>Transfer_Complete</name>
<desc>This bit is set when a read / write transaction is completed.
Read Transaction:
This bit is set at the falling edge of Read Transfer Active Status.
There are two cases in which the Interrupt is generated. The first is when a data transfer is completed as specified by data length (After the last data has been read to the Host System). The second is when data has stopped at the block gap and completed the data transfer by setting the Stop At Block Gap Request in the Block Gap Control Register (After valid
data has been read to the Host System).
Write Transaction:
This bit is set at the falling edge of the DAT
Line Active Status.
There are two cases in which the Interrupt is generated. The first is when the last data is written to the card as specified by data length and Busy signal is released. The second is when data transfers are stopped at the block gap by setting Stop At Block Gap Request in the Block Gap Control Register and data transfers completed. (After valid data is written to the SD card and the busy signal is released).
Note: Transfer Complete has higher priority than Data Time-out Error. If both bits are set to 1, the data transfer can be considered complete
0 - No Data Transfer Complete
1 - Data Transfer Complete</desc>
<sw_param offset="0xe0101030" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_Error_interrupt_status_Command_Complete">
<name>Command_Complete</name>
<desc>This bit is set when get the end bit of the command response (Except Auto CMD12).
Note: Command Time-out Error has higher priority than Command Complete. If both are set to 1, it can be considered that the response was not received correctly.
0 - No Command Complete
1 - Command Complete</desc>
<sw_param offset="0xe0101030" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_enable_Error_interrupt_status_enable_Ceata_Error_Status_Enable">
<name>Ceata_Error_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101034" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_enable_Error_interrupt_status_enable_Target_Response_Error_Status_Enable">
<name>Target_Response_Error_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101034" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_enable_Error_interrupt_status_enable_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe0101034" start="27" end="26" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_enable_Error_interrupt_status_enable_ADMA_Error_Status_Enable">
<name>ADMA_Error_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101034" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_enable_Error_interrupt_status_enable_Auto_CMD12_Error_Status_Enable">
<name>Auto_CMD12_Error_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101034" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_enable_Error_interrupt_status_enable_Current_Limit_Error_Status_Enable">
<name>Current_Limit_Error_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101034" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_enable_Error_interrupt_status_enable_Data_End_Bit_Error_Status_Enable">
<name>Data_End_Bit_Error_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101034" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_enable_Error_interrupt_status_enable_Data_CRC_Error_Status_Enable">
<name>Data_CRC_Error_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101034" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_enable_Error_interrupt_status_enable_Data_Timeout_Error_Status_Enable">
<name>Data_Timeout_Error_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101034" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_enable_Error_interrupt_status_enable_Command_Index_Error_Status_Enable">
<name>Command_Index_Error_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101034" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_enable_Error_interrupt_status_enable_Command_End_Bit_Error_Status_Enable">
<name>Command_End_Bit_Error_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101034" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_enable_Error_interrupt_status_enable_Command_CRC_Error_Status_Enable">
<name>Command_CRC_Error_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101034" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_enable_Error_interrupt_status_enable_Command_Timeout_Error_Status_Enable">
<name>Command_Timeout_Error_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101034" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_enable_Error_interrupt_status_enable_Fixed_to_0">
<name>Fixed_to_0</name>
<desc>The HC shall control error Interrupts using the Error Interrupt Status Enable register.</desc>
<sw_param offset="0xe0101034" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_enable_Error_interrupt_status_enable_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0101034" start="14" end="11" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_enable_Error_interrupt_status_enable_Boot_terminate_Interrupt_enable">
<name>Boot_terminate_Interrupt_enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101034" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_enable_Error_interrupt_status_enable_Boot_ack_rcv_enable">
<name>Boot_ack_rcv_enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101034" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_enable_Error_interrupt_status_enable_Card_Interrupt_Status_Enable">
<name>Card_Interrupt_Status_Enable</name>
<desc>If this bit is set to 0, the HC shall clear Interrupt request to the System. The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. The HD should clear the Card Interrupt Status Enable before servicing the Card Interrupt and should set this bit again after all Interrupt requests from the card are cleared to prevent inadvertent Interrupts.
0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101034" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_enable_Error_interrupt_status_enable_Card_Removal_Status_Enable">
<name>Card_Removal_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101034" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_enable_Error_interrupt_status_enable_Card_Insertion_Status_Enable">
<name>Card_Insertion_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101034" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_enable_Error_interrupt_status_enable_Buffer_Read_Ready_Status_Enable">
<name>Buffer_Read_Ready_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101034" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_enable_Error_interrupt_status_enable_Buffer_Write_Ready_Status_Enable">
<name>Buffer_Write_Ready_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101034" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_enable_Error_interrupt_status_enable_DMA_Interrupt_Status_Enable">
<name>DMA_Interrupt_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101034" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_enable_Error_interrupt_status_enable_Block_Gap_Event_Status_Enable">
<name>Block_Gap_Event_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101034" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_enable_Error_interrupt_status_enable_Transfer_Complete_Status_Enable">
<name>Transfer_Complete_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101034" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_status_enable_Error_interrupt_status_enable_Command_Complete_Status_Enable">
<name>Command_Complete_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101034" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Ceata_Error_Signal_Enable">
<name>Ceata_Error_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101038" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Target_Response_Error_Signal_Enable">
<name>Target_Response_Error_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101038" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe0101038" start="27" end="26" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_ADMA_Error_Signal_Enable">
<name>ADMA_Error_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101038" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Auto_CMD12_Error_Signal_Enable">
<name>Auto_CMD12_Error_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101038" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Current_Limit_Error_Signal_Enable">
<name>Current_Limit_Error_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101038" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Data_End_Bit_Error_Signal_Enable">
<name>Data_End_Bit_Error_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101038" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Data_CRC_Error_Signal_Enable">
<name>Data_CRC_Error_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101038" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Data_Timeout_Error_Signal_Enable">
<name>Data_Timeout_Error_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101038" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Command_Index_Error_Signal_Enable">
<name>Command_Index_Error_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101038" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Command_End_Bit_Error_Signal_Enable">
<name>Command_End_Bit_Error_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101038" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Command_CRC_Error_Signal_Enable">
<name>Command_CRC_Error_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101038" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Command_Timeout_Error_Signal_Enable">
<name>Command_Timeout_Error_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101038" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Fixed_to_0">
<name>Fixed_to_0</name>
<desc>The HD shall control error Interrupts using the Error Interrupt Signal Enable register.</desc>
<sw_param offset="0xe0101038" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0101038" start="14" end="11" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Boot_terminate_Interrupt_signal_enable">
<name>Boot_terminate_Interrupt_signal_enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101038" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Boot_ack_rcv_signal_enable">
<name>Boot_ack_rcv_signal_enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101038" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Card_Interrupt_Signal_Enable">
<name>Card_Interrupt_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101038" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Card_Removal_Signal_Enable">
<name>Card_Removal_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101038" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Card_Insertion_Signal_Enable">
<name>Card_Insertion_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101038" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Buffer_Read_Ready_Signal_Enable">
<name>Buffer_Read_Ready_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101038" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Buffer_Write_Ready_Signal_Enable">
<name>Buffer_Write_Ready_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101038" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_DMA_Interrupt_Signal_Enable">
<name>DMA_Interrupt_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101038" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Block_Gap_Event_Signal_Enable">
<name>Block_Gap_Event_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101038" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Transfer_Complete_Signal_Enable">
<name>Transfer_Complete_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101038" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_sd1_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Command_Complete_Signal_Enable">
<name>Command_Complete_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0101038" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_sd1_Auto_CMD12_error_status_Command_Not_Issued_By_Auto_CMD12_Error">
<name>Command_Not_Issued_By_Auto_CMD12_Error</name>
<desc>Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 error (D04 - D01) in this register.
0 - No Error
1 - Not Issued</desc>
<sw_param offset="0xe010103c" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_sd1_Auto_CMD12_error_status_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe010103c" start="6" end="5" />
</parameter>
<parameter uniqueid="ps7_sd1_Auto_CMD12_error_status_Auto_CMD12_Index_Error">
<name>Auto_CMD12_Index_Error</name>
<desc>Occurs if the Command Index error occurs in response to a command.
0 - No Error
1 - Error</desc>
<sw_param offset="0xe010103c" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_sd1_Auto_CMD12_error_status_Auto_CMD12_End_Bit_Error">
<name>Auto_CMD12_End_Bit_Error</name>
<desc>Occurs when detecting that the end bit of command response is 0.
0 - No Error
1 - End Bit Error Generated</desc>
<sw_param offset="0xe010103c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_sd1_Auto_CMD12_error_status_Auto_CMD12_CRC_Error">
<name>Auto_CMD12_CRC_Error</name>
<desc>Occurs when detecting a CRC error in the command response.
0 - No Error
1 - CRC Error Generated</desc>
<sw_param offset="0xe010103c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_sd1_Auto_CMD12_error_status_Auto_CMD12_Timeout_Error">
<name>Auto_CMD12_Timeout_Error</name>
<desc>Occurs if the no response is returned within 64 SDCLK cycles from the end bit of the command. If this bit is set to 1, the other error status bits (D04 - D02) are meaningless.
0 - No Error
1 - Timeout</desc>
<sw_param offset="0xe010103c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_sd1_Auto_CMD12_error_status_Auto_CMD12_not_Executed">
<name>Auto_CMD12_not_Executed</name>
<desc>If memory multiple block data transfer is not started due to command
error, this bit is not set because it is not necessary to issue Auto CMD12. Setting this bit to 1 means the HC cannot issue Auto CMD12 to stop memory multiple block transfer due to some error. If this bit is set to 1, other error status bits (D04 - D01) are meaningless.
0 - Executed
1 - Not Executed</desc>
<sw_param offset="0xe010103c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_sd1_Capabilities_Spi_block_mode">
<name>Spi_block_mode</name>
<desc>Spi block mode
0 - Not Supported
1 - Supported</desc>
<sw_param offset="0xe0101040" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_sd1_Capabilities_Spi_mode">
<name>Spi_mode</name>
<desc>Spi mode
0 - Not Supported
1 - Supported</desc>
<sw_param offset="0xe0101040" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_sd1_Capabilities_n64_bit_System_Bus_Support">
<name>n64_bit_System_Bus_Support</name>
<desc>1 - supports 64 bit system address
0 - Does not support 64 bit system
address</desc>
<sw_param offset="0xe0101040" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_sd1_Capabilities_Interrupt_mode">
<name>Interrupt_mode</name>
<desc>Interrupt mode
0 - Not Supported
1 - Supported</desc>
<sw_param offset="0xe0101040" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_sd1_Capabilities_Voltage_Support_1_8_V">
<name>Voltage_Support_1_8_V</name>
<desc>0 - 1.8 V Not Supported
1 - 1.8 V Supported</desc>
<sw_param offset="0xe0101040" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_sd1_Capabilities_Voltage_Support_3_0_V">
<name>Voltage_Support_3_0_V</name>
<desc>0 - 3.0 V Not Supported
1 - 3.0 V Supported</desc>
<sw_param offset="0xe0101040" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_sd1_Capabilities_Voltage_Support_3_3_V">
<name>Voltage_Support_3_3_V</name>
<desc>0 - 3.3 V Not Supported
1 - 3.3 V Supported</desc>
<sw_param offset="0xe0101040" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_sd1_Capabilities_Suspend_Resume_Support">
<name>Suspend_Resume_Support</name>
<desc>This bit indicates whether the HC supports Suspend / Resume functionality. If this bit is 0, the Suspend and Resume mechanism are not supported and the HD shall not issue either Suspend / Resume commands.
0 - Not Supported
1 - Supported</desc>
<sw_param offset="0xe0101040" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_sd1_Capabilities_SDMA_Support">
<name>SDMA_Support</name>
<desc>This bit indicates whether the HC is capable of using DMA to transfer data between system memory and the HC directly.
0 - SDMA Not Supported
1 - SDMA Supported.</desc>
<sw_param offset="0xe0101040" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_sd1_Capabilities_High_Speed_Support">
<name>High_Speed_Support</name>
<desc>This bit indicates whether the HC and the Host System support High Speed mode and they can supply SD Clock frequency from 25Mhz to 50 Mhz (for SD)/ 20MHz to 52MHz (for MMC).
0 - High Speed Not Supported
1 - High Speed Supported</desc>
<sw_param offset="0xe0101040" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_sd1_Capabilities_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe0101040" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_sd1_Capabilities_ADMA2_Support">
<name>ADMA2_Support</name>
<desc>1 - ADMA2 support.
0 - ADMA2 not support</desc>
<sw_param offset="0xe0101040" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_sd1_Capabilities_Extended_Media_Bus_Support">
<name>Extended_Media_Bus_Support</name>
<desc>This bit indicates whether the Host Controller is capable bus.
1 - Extended Media Bus Supported
0 - Extended Media Bus not Supported</desc>
<sw_param offset="0xe0101040" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_sd1_Capabilities_Max_Block_Length">
<name>Max_Block_Length</name>
<desc>This value indicates the maximum block size that the HD can read and write to the buffer in the HC. The buffer shall transfer this block size without wait cycles. Three sizes can be defined as indicated below.
00 - 512 byte
01 - 1024 byte
10 - 2048 byte
11 - 4096 byte</desc>
<sw_param offset="0xe0101040" start="17" end="16" />
</parameter>
<parameter uniqueid="ps7_sd1_Capabilities_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe0101040" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_sd1_Capabilities_Base_Clock_Frequency_for_SD_Clock">
<name>Base_Clock_Frequency_for_SD_Clock</name>
<desc>This value indicates the base (maximum) clock frequency for the SD clock. Unit values are 1Mhz. If the real frequency is 16.5 Mhz, the larger value shall be set 010001b (17 Mhz) because the HD uses this value to calculate the clock divider value and it shall not exceed the upper limit of the SD clock frequency. The supported range is 10Mhz to 63 Mhz. If these bits are all 0, the Host System has to get information via another method. Not 0 - 1 Mhz to 63 Mhz
000000b - Get information via another method.</desc>
<sw_param offset="0xe0101040" start="13" end="8" />
</parameter>
<parameter uniqueid="ps7_sd1_Capabilities_Timeout_Clock_Unit">
<name>Timeout_Clock_Unit</name>
<desc>This bit shows the unit of base clock frequency used to detect Data Timeout Error.
0 - Khz
1 - Mhz</desc>
<sw_param offset="0xe0101040" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_sd1_Capabilities_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0101040" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_sd1_Capabilities_Timeout_Clock_Frequency">
<name>Timeout_Clock_Frequency</name>
<desc>This bit shows the base clock frequency used to detect Data Timeout Error.
Not 0 - 1Khz to 63Khz or 1Mhz to 63Mhz 000000b - Get Information via another method.</desc>
<sw_param offset="0xe0101040" start="5" end="0" />
</parameter>
<parameter uniqueid="ps7_sd1_Maximum_current_capabilities_Maximum_Current_for_1_8V">
<name>Maximum_Current_for_1_8V</name>
<desc>Maximum Current for 1.8V</desc>
<sw_param offset="0xe0101048" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_sd1_Maximum_current_capabilities_Maximum_Current_for_3_0V">
<name>Maximum_Current_for_3_0V</name>
<desc>Maximum Current for 3.0V</desc>
<sw_param offset="0xe0101048" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_sd1_Maximum_current_capabilities_Maximum_Current_for_3_3V">
<name>Maximum_Current_for_3_3V</name>
<desc>Maximum Current for 3.3V</desc>
<sw_param offset="0xe0101048" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_sd1_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Vendor_Specific_Error_Status">
<name>Force_Event_for_Vendor_Specific_Error_Status</name>
<desc>Additional status bits can be defined in
this register by the vendor.
1 - Interrupt is generated
0 - No interrupt</desc>
<sw_param offset="0xe0101050" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_sd1_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Ceata_error">
<name>Force_Event_for_Ceata_error</name>
<desc>Force Event for Ceata Error
1 - Interrupt is generated
0 - No interrupt</desc>
<sw_param offset="0xe0101050" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_sd1_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_event_for_Target_Response_error">
<name>Force_event_for_Target_Response_error</name>
<desc>Force Event for Target Response Error
1 - Interrupt is generated
0 - No interrupt</desc>
<sw_param offset="0xe0101050" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_sd1_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe0101050" start="27" end="26" />
</parameter>
<parameter uniqueid="ps7_sd1_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_ADMA_Error">
<name>Force_Event_for_ADMA_Error</name>
<desc>Force Event for ADMA Error
1 - Interrupt is generated
0 - No interrupt</desc>
<sw_param offset="0xe0101050" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_sd1_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Auto_CMD12_Error">
<name>Force_Event_for_Auto_CMD12_Error</name>
<desc>Force Event for Auto CMD12 Error
1 - Interrupt is generated
0 - No interrupt</desc>
<sw_param offset="0xe0101050" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_sd1_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Current_Limit_Error">
<name>Force_Event_for_Current_Limit_Error</name>
<desc>Force Event for Current Limit Error
1 - Interrupt is generated
0 - No interrupt</desc>
<sw_param offset="0xe0101050" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_sd1_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Data_End_Bit_Error">
<name>Force_Event_for_Data_End_Bit_Error</name>
<desc>Force Event for Data End Bit Error
1 - Interrupt is generated
0 - No interrupt</desc>
<sw_param offset="0xe0101050" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_sd1_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Data_CRC_Error">
<name>Force_Event_for_Data_CRC_Error</name>
<desc>Force Event for Data CRC Error
1 - Interrupt is generated
0 - No interrupt</desc>
<sw_param offset="0xe0101050" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_sd1_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Data__Timeout_Error">
<name>Force_Event_for_Data__Timeout_Error</name>
<desc>Force Event for Data Timeout Error
1 - Interrupt is generated
0 - No interrupt</desc>
<sw_param offset="0xe0101050" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_sd1_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Command_Index_Error">
<name>Force_Event_for_Command_Index_Error</name>
<desc>Force Event for Command Index Error
1 - Interrupt is generated
0 - No interrupt</desc>
<sw_param offset="0xe0101050" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_sd1_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Command_End_Bit_Error">
<name>Force_Event_for_Command_End_Bit_Error</name>
<desc>Force Event for Command End Bit Error
1 - Interrupt is generated
0 - No interrupt</desc>
<sw_param offset="0xe0101050" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_sd1_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Command_CRC_Error">
<name>Force_Event_for_Command_CRC_Error</name>
<desc>Force Event for Command CRC Error
1 - Interrupt is generated
0 - No interrupt</desc>
<sw_param offset="0xe0101050" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_sd1_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Command_Timeout_Error">
<name>Force_Event_for_Command_Timeout_Error</name>
<desc>Force Event for Command Timeout Error
1 - Interrupt is generated
0 - No interrupt</desc>
<sw_param offset="0xe0101050" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_sd1_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe0101050" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_sd1_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_command_not_issued_by_Auto_CMD12_Error">
<name>Force_Event_for_command_not_issued_by_Auto_CMD12_Error</name>
<desc>1 - Interrupt is generated
0 - no interrupt</desc>
<sw_param offset="0xe0101050" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_sd1_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0101050" start="6" end="5" />
</parameter>
<parameter uniqueid="ps7_sd1_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Auto_CMD12_Index_Error">
<name>Force_Event_for_Auto_CMD12_Index_Error</name>
<desc>1 - Interrupt is generated
0 - no interrupt</desc>
<sw_param offset="0xe0101050" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_sd1_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Auto_CMD12_End_bit_Error">
<name>Force_Event_for_Auto_CMD12_End_bit_Error</name>
<desc>1 - Interrupt is generated
0 - no interrupt</desc>
<sw_param offset="0xe0101050" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_sd1_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Auto_CMD12_CRC_Error">
<name>Force_Event_for_Auto_CMD12_CRC_Error</name>
<desc>1 - Interrupt is generated
0 - no interrupt</desc>
<sw_param offset="0xe0101050" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_sd1_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Auto_CMD12_timeout_Error">
<name>Force_Event_for_Auto_CMD12_timeout_Error</name>
<desc>1 - Interrupt is generated
0 - no interrupt</desc>
<sw_param offset="0xe0101050" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_sd1_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Auto_CMD12_NOT_Executed">
<name>Force_Event_for_Auto_CMD12_NOT_Executed</name>
<desc>1 - Interrupt is generated
0 - no interrupt</desc>
<sw_param offset="0xe0101050" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_sd1_ADMA_error_status_ADMA_Length_Mismatch_Error">
<name>ADMA_Length_Mismatch_Error</name>
<desc>This error occurs in the following 2 cases.
1. While Block Count Enable being set, the total
data length specified by the
Descriptor table is different from that specified by
the Block Count and
Block Length.
2. Total data length can not be divided by the block
length.
1 - Error
0 - No error</desc>
<sw_param offset="0xe0101054" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_sd1_ADMA_error_status_ADMA_Error_State">
<name>ADMA_Error_State</name>
<desc>This field indicates the state of ADMA when error is occurred during ADMA data transfer. This field never indicates "10" because ADMA never stops in this state.
D01 - D00 : ADMA Error State when
error is occurred
Contents of SYS_SDR register
00 - ST_STOP (Stop DMA) Points next of the error
descriptor
01 - ST_FDS (Fetch Descriptor) Points the error
descriptor
10 - Never set this state (Not used)
11 - ST_TFR (Transfer Data) Points the next of the
error descriptor</desc>
<sw_param offset="0xe0101054" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_sd1_ADMA_system_address_ADMA_System_Address">
<name>ADMA_System_Address</name>
<desc>This register holds byte address of executing
command of the Descriptor table.
32-bit Address Descriptor uses lower 32-
bit of this register. At the start of ADMA,
the Host Driver shall set start address of
the Descriptor table. The ADMA
increments this register address, which
points to next line, when every fetching a
Descriptor line. When the ADMA Error
Interrupt is generated, this register shall
hold valid Descriptor address depending
on the ADMA state. The Host Driver shall
program Descriptor Table on 32-bit
boundary and set 32-bit boundary
address to this register. ADMA2 ignores
lower 2-bit of this register and assumes it
to be 00b.
32-bit Address ADMA Register Value 32-
bit System Address
0x00000000 0x00000000
0x00000004 0x00000004
to
0xFFFFFFFC 0xFFFFFFFC</desc>
<sw_param offset="0xe0101058" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_sd1_Boot_Timeout_control_Boot_Data_Timeout_Counter_Value">
<name>Boot_Data_Timeout_Counter_Value</name>
<desc>This value determines the interval by
which DAT line time-outs are detected
during boot operation for MMC3.31
card.
The value is in number of sd clock.</desc>
<sw_param offset="0xe0101060" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_sd1_Debug_Selection_Debug_sel">
<name>Debug_sel</name>
<desc>1- cmd register, Interrupt status, transmitter
module, ahb_iface module and clk
sdcard signals are probed out.
0 - receiver module and fifo_ctrl module
signals are probed out</desc>
<sw_param offset="0xe0101064" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_sd1_SPI_interrupt_support_SPI_INT_SUPPORT">
<name>SPI_INT_SUPPORT</name>
<desc>This bit is set to indicate the assertion of interrupts in the SPI mode at any time, irrespective of the status of the card select (CS) line. If this bit is zero,
then SDIO card can only assert the interrupt line in the SPI mode when the CS line is asserted.</desc>
<sw_param offset="0xe01010f0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_sd1_Slot_interrupt_status_Host_controller_version_Specification_Version_Number">
<name>Specification_Version_Number</name>
<desc>This status indicates the Host Controller Spec. Version. The upper and lower 4-bits indicate the version. 00 - SD Host Specification version
1.0
01 - SD Host Specification version 2.00 including only the feature of theTest Register
others - Reserved</desc>
<sw_param offset="0xe01010fc" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_sd1_Slot_interrupt_status_Host_controller_version_Vendor_Version_Number">
<name>Vendor_Version_Number</name>
<desc>This status is reserved for the vendor version number. The HD should not use this status.</desc>
<sw_param offset="0xe01010fc" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_sd1_Slot_interrupt_status_Host_controller_version_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe01010fc" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_sd1_Slot_interrupt_status_Host_controller_version_Interrupt_Signal_for_Each_Slot">
<name>Interrupt_Signal_for_Each_Slot</name>
<desc>These status bit indicate the logical OR of Interrupt signal and Wakeup
signal for each slot. A maximum of 8 slots can be defined. If one interrupt
signal is associated with multiple slots. the HD can know which interrupt
is generated by reading these status bits. By a power on reset or by Software Reset For All, the Interrupt signal shall be de asserted and this
status shall read 00h.
Bit 00 - Slot 1
Bit 01 - Slot 2
Bit 02 - Slot 3
----- -----
Bit 07 - Slot 8</desc>
<sw_param offset="0xe01010fc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_sd0_SDMA_system_address_register_SDMA_System_Address">
<name>SDMA_System_Address</name>
<desc>Watchdog enable - if set, the watchdog is enabled and can generate any signals that are enabled.</desc>
<sw_param offset="0xe0100000" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_sd0_Block_Size_Block_Count_Blocks_Count_for_Current_Transfer">
<name>Blocks_Count_for_Current_Transfer</name>
<desc>This register is enabled when Block Count Enable in the Transfer
Mode register is set to 1 and is valid only for multiple block transfers. The HC decrements the block count after each block transfer and stops when the count reaches zero. It can be accessed only if no transaction is
executing (i.e after a transaction has stopped). Read operations
during transfer return an invalid value and write operations shall
be ignored. When saving transfer context as a result of Suspend command, the number of blocks yet to be transferred can be determined
by reading this register. When restoring transfer context prior to
issuing a Resume command, the HD shall restore the previously
save block count.
0000h - Stop Count
0001h - 1 block
0002h - 2 blocks
--- ---
FFFFh - 65535 blocks</desc>
<sw_param offset="0xe0100004" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_sd0_Block_Size_Block_Count_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0100004" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_sd0_Block_Size_Block_Count_Host_SDMA_Buffer_Size">
<name>Host_SDMA_Buffer_Size</name>
<desc>Counter clock prescale - selects the prescaler division ratio:
00 = pclk divided by 8
01 = pclk divided by 64
10 = pclk divided by 256
11 = pclk divided by 4096
Note: If a restart signal is received the prescaler should be reset.</desc>
<sw_param offset="0xe0100004" start="14" end="12" />
</parameter>
<parameter uniqueid="ps7_sd0_Block_Size_Block_Count_Transfer_Block_Size">
<name>Transfer_Block_Size</name>
<desc>This register specifies the block size for block data transfers for CMD17, CMD18, CMD24, CMD25, and CMD53. It can be accessed only if no transaction is executing (i.e after a transaction has stopped). Read operations during transfer return an invalid value and write operations shall be ignored.
0000h - No Data Transfer
0001h - 1 Byte
0002h - 2 Bytes
0003h - 3 Bytes
0004h - 4 Bytes
--- ---
01FFh - 511 Bytes
0200h - 512 Bytes
--- ---
0800h - 2048 Bytes</desc>
<sw_param offset="0xe0100004" start="11" end="0" />
</parameter>
<parameter uniqueid="ps7_sd0_Argument_Command_Argument">
<name>Command_Argument</name>
<desc>The SD Command Argument is specified as bit39-8 of Command-Format.</desc>
<sw_param offset="0xe0100008" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_sd0_Transfer_Mode_Command_Command_Index">
<name>Command_Index</name>
<desc>This bit shall be set to the command number (CMD0-63, ACMD0-63).</desc>
<sw_param offset="0xe010000c" start="28" end="24" />
</parameter>
<parameter uniqueid="ps7_sd0_Transfer_Mode_Command_Command_Type">
<name>Command_Type</name>
<desc>There are three types of special commands. Suspend, Resume and Abort. These bits shall bet set to 00b for all other commands. Suspend Command If the Suspend command succeeds, the HC shall assume the SD Bus has been released and that it is possible to issue the next command which uses the DAT line. The HC shall de-assert Read Wait for read transactions and stop checking busy for write transactions. The Interrupt cycle shall start, in 4-bit mode. If the Suspend command fails, the HC shall maintain its current state. and the HD shall restart the transfer by setting Continue Request in the Block Gap Control Register. Resume Command The HD re-starts the data transfer by restoring the registers in the range of 000-00Dh. The HC shall check for busy before starting write transfers. Abort Command If this command is set when executing a read transfer, the HC shall stop reads to the buffer. If this command is set when executing a write transfer, the HC shall stop driving the DAT line. After issuing the Abort command, the HD should issue a software reset
00b - Normal
01b - Suspend
10b - Resume
11b - Abort</desc>
<sw_param offset="0xe010000c" start="23" end="22" />
</parameter>
<parameter uniqueid="ps7_sd0_Transfer_Mode_Command_Data_Present_Select">
<name>Data_Present_Select</name>
<desc>This bit is set to 1 to indicate that data is present and shall be transferred using the DAT line. If is set to 0 for the following:
1. Commands using only CMD line (ex. CMD52)
2. Commands with no data transfer but using busy signal on DAT[0]
line (R1b or R5b ex. CMD38)
3. Resume Command
0 - No Data Present
1 - Data Present</desc>
<sw_param offset="0xe010000c" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_sd0_Transfer_Mode_Command_Command_Index_Check_Enable">
<name>Command_Index_Check_Enable</name>
<desc>If this bit is set to 1, the HC shall check the index field in the response to see if it has the same value as the command index. If it is not, it is reported as a Command Index Error. If this bit is set to 0, the Index field is not checked.
0 - Disable
1 - Enable</desc>
<sw_param offset="0xe010000c" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_sd0_Transfer_Mode_Command_Command_CRC_Check_Enable">
<name>Command_CRC_Check_Enable</name>
<desc>If this bit is set to 1, the HC shall check the CRC field in the response. If an error is detected, it is reported as a Command CRC Error. If this bit is set to 0, the CRC field is not checked.
0 - Disable
1 - Enable</desc>
<sw_param offset="0xe010000c" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_sd0_Transfer_Mode_Command_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe010000c" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_sd0_Transfer_Mode_Command_Response_Type_Select">
<name>Response_Type_Select</name>
<desc>Response Type Select
00 - No Response
01 - Response length 136
10 - Response length 48
11 - Response length 48 check
Busy after response</desc>
<sw_param offset="0xe010000c" start="17" end="16" />
</parameter>
<parameter uniqueid="ps7_sd0_Transfer_Mode_Command_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe010000c" start="15" end="6" />
</parameter>
<parameter uniqueid="ps7_sd0_Transfer_Mode_Command_Multi_Single_Block_Select">
<name>Multi_Single_Block_Select</name>
<desc>This bit enables multiple block DAT line data transfers.
0 - Single Block
1 - Multiple Block</desc>
<sw_param offset="0xe010000c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_sd0_Transfer_Mode_Command_Data_Transfer_Direction_Select">
<name>Data_Transfer_Direction_Select</name>
<desc>This bit defines the direction of DAT line data transfers.
0 - Write (Host to Card)
1 - Read (Card to Host)</desc>
<sw_param offset="0xe010000c" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_sd0_Transfer_Mode_Command_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe010000c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_sd0_Transfer_Mode_Command_Auto_CMD12_Enable">
<name>Auto_CMD12_Enable</name>
<desc>Multiple block transfers for memory require CMD12 to stop the ransaction. When this bit is set to 1, the HC shall issue CMD12 utomatically when last block transfer is completed. The HD shall not set this bit to issue commands that do not require CMD12 to stop data transfer.
0 - Disable
1 - Enable</desc>
<sw_param offset="0xe010000c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_sd0_Transfer_Mode_Command_Block_Count_Enable">
<name>Block_Count_Enable</name>
<desc>This bit is used to enable the Block count register, which is only relevant for multiple block transfers. When this bit is 0, the Block Count register is disabled, which is useful in executing an infinite transfer.
0 - Disable
1 - Enable</desc>
<sw_param offset="0xe010000c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_sd0_Transfer_Mode_Command_DMA_Enable">
<name>DMA_Enable</name>
<desc>DMA can be enabled only if DMA Support bit in the Capabilities register is set. If this bit is set to 1, a DMA operation shall begin when the HD writes to the upper byte of Command register (00Fh).
0 - Disable
1 - Enable</desc>
<sw_param offset="0xe010000c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_sd0_Response0_Command_Response">
<name>Command_Response</name>
<desc>command responses registers</desc>
<sw_param offset="0xe0100010" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_sd0_Response1_Command_Response">
<name>Command_Response</name>
<desc>command responses registers</desc>
<sw_param offset="0xe0100014" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_sd0_Response2_Command_Response">
<name>Command_Response</name>
<desc>command responses registers</desc>
<sw_param offset="0xe0100018" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_sd0_Response3_Command_Response">
<name>Command_Response</name>
<desc>command responses registers</desc>
<sw_param offset="0xe010001c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_sd0_Buffer_Data_Port_Buffer_Data">
<name>Buffer_Data</name>
<desc>The Host Controller Buffer can be accessed through this 32-bit Data Port Register.</desc>
<sw_param offset="0xe0100020" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_sd0_Present_State_CMD_Line_Signal_Level">
<name>CMD_Line_Signal_Level</name>
<desc>This status is used to check CMD line level to recover from errors, and for debugging.</desc>
<sw_param offset="0xe0100024" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_sd0_Present_State_DAT_Bit3_Bit0_Line_Signal_Level">
<name>DAT_Bit3_Bit0_Line_Signal_Level</name>
<desc>This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[0].
D23 - DAT[3]
D22 - DAT[2]
D21 - DAT[1]
D20 - DAT[0]</desc>
<sw_param offset="0xe0100024" start="23" end="20" />
</parameter>
<parameter uniqueid="ps7_sd0_Present_State_Write_Protect_Switch_Pin_Level">
<name>Write_Protect_Switch_Pin_Level</name>
<desc>The Write Protect Switch is supported for memory and combo cards. This bit reflects the SDWP# pin.
0 - Write protected (SDWP# = 1)
1 - Write enabled (SDWP# = 0)</desc>
<sw_param offset="0xe0100024" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_sd0_Present_State_Card_Detect_Pin_Level">
<name>Card_Detect_Pin_Level</name>
<desc>This bit reflects the inverse value of the SDCD# pin.
0 - No Card present (SDCD# = 1)
1 - Card present (SDCD# = 0)</desc>
<sw_param offset="0xe0100024" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_sd0_Present_State_Card_State_Stable">
<name>Card_State_Stable</name>
<desc>This bit is used for testing. If it is 0, the Card Detect Pin Level is not stable. If this bit is set to 1, it means the Card Detect Pin Level is stable. The Software Reset For All in the Software Reset Register shall not affect this bit.
0 - Reset of Debouncing
1 - No Card or Inserted</desc>
<sw_param offset="0xe0100024" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_sd0_Present_State_Card_Inserted">
<name>Card_Inserted</name>
<desc>This bit indicates whether a card has been inserted. Changing from 0 to 1 generates a Card Insertion interrupt in the Normal Interrupt Status register and changing from 1 to 0 generates a Card Removal Interrupt in the Normal Interrupt Status register. The Software Reset For All in the Software Reset register shall not affect this bit. If a Card is removed while its power is on and its clock is oscillating, the HC shall clear SD Bus Power in the Power Control register and SD Clock Enable in the Clock control register. In addition the HD should clear the HC by the Software Reset For All in Software register. The card detect is active regardless of the SD Bus Power.
0 - Reset or Debouncing or No Card
1 - Card Inserted</desc>
<sw_param offset="0xe0100024" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_sd0_Present_State_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe0100024" start="15" end="12" />
</parameter>
<parameter uniqueid="ps7_sd0_Present_State_Buffer_Read_Enable">
<name>Buffer_Read_Enable</name>
<desc>This status is used for non-DMA read transfers. This read only flag indicates that valid data exists in the host side buffer status. If this bit is 1, readable data exists in the buffer. A change of this bit from 1 to 0 occurs when all the block data is read from the buffer. A change of this bit from 0 to 1 occurs when all the block data is ready in the buffer and generates the Buffer Read Ready Interrupt.
0 - Read Disable
1 - Read Enable.</desc>
<sw_param offset="0xe0100024" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_sd0_Present_State_Buffer_Write_Enable">
<name>Buffer_Write_Enable</name>
<desc>This status is used for non-DMA write transfers. This read only flag indicates if space is available for write data. If this bit is 1, data can be written to the buffer. A change of this bit from 1 to 0 occurs when all the block data is written to the buffer. A change of this bit from 0 to 1 occurs when top of block data can be written to the buffer and generates the Buffer Write Ready Interrupt.
0 - Write Disable
1 - Write Enable.</desc>
<sw_param offset="0xe0100024" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_sd0_Present_State_Read_Transfer_Active">
<name>Read_Transfer_Active</name>
<desc>This status is used for detecting completion of a read transfer.
This bit is set to 1 for either of the following conditions:
1. After the end bit of the read command
2. When writing a 1 to continue Request in the Block Gap Control register to restart a read transfer
This bit is cleared to 0 for either of the following
conditions:
1. When the last data block as specified by block length is transferred to the system.
2. When all valid data blocks have been transferred to the system and no current block transfers are being sent as a result of the Stop At Block Gap Request set to 1. A transfer complete interrupt is generated when this bit changes to 0.
1 - Transferring data
0 - No valid data</desc>
<sw_param offset="0xe0100024" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_sd0_Present_State_Write_Transfer_Active">
<name>Write_Transfer_Active</name>
<desc>This status indicates a write transfer is active. If this bit is 0, it means no valid write data exists in the HC. This bit is set in either of the following cases:
1. After the end bit of the write command.
2. When writing a 1 to Continue Request in the Block Gap Control register to restart a write transfer.
This bit is cleared in either of the following cases:
1. After getting the CRC status of the last data block as specified by the transfer count (Single or Multiple)
2. After getting a CRC status of any block where data transmission is about to be stopped by a Stop At Block Gap Request.
During a write transaction, a Block Gap Event interrupt is generated when this bit is changed to 0, as a result of the Stop At Block Gap Request being set. This status is useful for the HD in determining when to issue commands during write busy.
1 - transferring data
0 - No valid data</desc>
<sw_param offset="0xe0100024" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_sd0_Present_State_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0100024" start="7" end="3" />
</parameter>
<parameter uniqueid="ps7_sd0_Present_State_DAT_Line_Active">
<name>DAT_Line_Active</name>
<desc>This bit indicates whether one of the DAT line on SD bus is in use.
1 - DAT line active
0 - DAT line inactive</desc>
<sw_param offset="0xe0100024" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_sd0_Present_State_Command_Inhibit_DAT">
<name>Command_Inhibit_DAT</name>
<desc>This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1. If this bit is 0, it indicates the HC can issue the next SD command. Commands with busy signal belong to Command Inhibit (DAT) (ex. R1b, R5b type). Changing from 1 to 0 generates a Transfer Complete interrupt in the Normal interrupt status register.
Note: The SD Host Driver can save registers in the range of 000-00Dh for a suspend transaction after this bit has changed from 1 to 0.
1 - cannot issue command which uses the DAT line
0 - Can issue command which uses the DAT line</desc>
<sw_param offset="0xe0100024" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_sd0_Present_State_Command_Inhibit_CMD">
<name>Command_Inhibit_CMD</name>
<desc>If this bit is 0, it indicates the CMD line is not in use and the HC can issue a SD command using the CMD line. This bit is set immediately after the Command register (00Fh) is written. This bit is cleared when the command response is received. Even if the Command Inhibit (DAT) is set to 1, Commands using only the CMD line can be issued if this bit is 0. Changing from 1 to 0 generates a Command complete interrupt in the Normal Interrupt Status register. If the HC cannot issue the command because of a command conflict error or because of Command Not Issued By Auto CMD12 Error, this bit shall remain 1 and the Command Complete is not set. Status issuing Auto CMD12 is not read from this bit.</desc>
<sw_param offset="0xe0100024" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_sd0_Host_control_Power_control_Block_Gap_Control_Wakeup_control_reserved_3">
<name>reserved_3</name>
<desc>Reserved</desc>
<sw_param offset="0xe0100028" start="31" end="27" />
</parameter>
<parameter uniqueid="ps7_sd0_Host_control_Power_control_Block_Gap_Control_Wakeup_control_Wakeup_Event_Enable_On_SD_Card_Removal">
<name>Wakeup_Event_Enable_On_SD_Card_Removal</name>
<desc>This bit enables wakeup event via
Card Removal assertion in the
Normal Interrupt Status register.
FN_WUS (Wake up Support) in
CIS does not affect this bit.
1 - Enable
0 - Disable</desc>
<sw_param offset="0xe0100028" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_sd0_Host_control_Power_control_Block_Gap_Control_Wakeup_control_Wakeup_Event_Enable_On_SD_Card_Insertion">
<name>Wakeup_Event_Enable_On_SD_Card_Insertion</name>
<desc>This bit enables wakeup event via Card Insertion assertion in the Normal Interrupt Status register. FN_WUS (Wake up Support) in CIS does not affect this bit.
1 - Enable
0 - Disable</desc>
<sw_param offset="0xe0100028" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_sd0_Host_control_Power_control_Block_Gap_Control_Wakeup_control_Wakeup_Event_Enable_On_Card_Interrupt">
<name>Wakeup_Event_Enable_On_Card_Interrupt</name>
<desc>This bit enables wakeup event via
Card Interrupt assertion in the
Normal Interrupt Status register.
This bit can be set to 1 if FN_WUS
(Wake Up Support) in CIS is set to
1.
1 - Enable
0 - Disable</desc>
<sw_param offset="0xe0100028" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_sd0_Host_control_Power_control_Block_Gap_Control_Wakeup_control_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe0100028" start="23" end="20" />
</parameter>
<parameter uniqueid="ps7_sd0_Host_control_Power_control_Block_Gap_Control_Wakeup_control_Interrupt_At_Block_Gap">
<name>Interrupt_At_Block_Gap</name>
<desc>This bit is valid only in 4-bit mode of the SDIO
card and selects a sample point in the interrupt
cycle. Setting to 1 enables interrupt detection at
the block gap for a multiple block transfer. If the
SD card cannot signal an interrupt during a multiple
block transfer, this bit should be set to 0.
When the HD detects an SD card insertion, it shall
set this bit according to the CCCR of the SDIO
card.</desc>
<sw_param offset="0xe0100028" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_sd0_Host_control_Power_control_Block_Gap_Control_Wakeup_control_Read_Wait_Control">
<name>Read_Wait_Control</name>
<desc>The read wait function is optional for SDIO cards.
If the card supports read wait, set this bit to
enable use of the read wait protocol to stop read
data using DAT[2] line. Otherwise the HC has to
stop the SD clock to hold read data, which
restricts commands generation. When the HD
detects an SD card insertion, it shall set this bit
according to the CCCR of the SDIO card. If the
card does not support read wait, this bit shall
never be set to 1 otherwise DAT line conflict may
occur. If this bit is set to 0, Suspend / Resume
cannot be supported
1 - Enable Read Wait Control
0 - Disable Read Wait Control</desc>
<sw_param offset="0xe0100028" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_sd0_Host_control_Power_control_Block_Gap_Control_Wakeup_control_Continue_Request">
<name>Continue_Request</name>
<desc>This bit is used to restart a transaction which was stopped using the Stop At Block Gap Request. To
cancel stop at the block gap, set Stop At block
Gap Request to 0 and set this bit to restart the
transfer.
The HC automatically clears this bit in either of
the following cases:
1) In the case of a read transaction, the DAT Line
Active changes from 0 to 1 as a read transaction
restarts.
2) In the case of a write transaction, the Write
transfer active changes from 0 to 1 as the write
transaction restarts.
Therefore it is not necessary for Host driver to set
this bit to 0. If Stop At Block Gap Request is set to
1, any write to this bit is ignored.
1 - Restart
0 - Ignored</desc>
<sw_param offset="0xe0100028" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_sd0_Host_control_Power_control_Block_Gap_Control_Wakeup_control_Stop_At_Block_Gap_Request">
<name>Stop_At_Block_Gap_Request</name>
<desc>This bit is used to stop executing a transaction at the next block gap for non- DMA,SDMA and ADMA transfers. Until the transfer complete is set
to 1, indicating a transfer completion the HD shall leave this bit set to 1. Clearing both the Stop At Block Gap Request and Continue Request shall not cause the transaction to restart. Read Wait is used to stop the read transaction at the block gap. The HC shall honour Stop At Block Gap Request for write transfers, but for read transfers it requires that the SD card support Read Wait. Therefore the HD shall not set this bit during read transfers unless the SD card supports Read Wait and has set Read Wait Control to 1. In case of write transfers in which the HD writes data to the Buffer Data Port register, the HD shall set this bit after all block data is written. If this bit is set to 1, the HD shall not write data to Buffer data port register. This bit affects Read Transfer Active, Write Transfer Active, DAT line active and Command Inhibit (DAT) in the Present State register.
1 - Stop
0 - Transfer</desc>
<sw_param offset="0xe0100028" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_sd0_Host_control_Power_control_Block_Gap_Control_Wakeup_control_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe0100028" start="15" end="12" />
</parameter>
<parameter uniqueid="ps7_sd0_Host_control_Power_control_Block_Gap_Control_Wakeup_control_SD_Bus_Voltage_Select">
<name>SD_Bus_Voltage_Select</name>
<desc>By setting these bits, the HD selects the voltage level for the SD card. Before setting this register, the HD shall check the voltage support bits
in the capabilities register. If an unsupported voltage is selected, the
Host System shall not supply SD bus voltage
111b - 3.3 Flattop.)
110b - 3.0 V(Typ.)
101b - 1.8 V(Typ.)
100b - 000b - Reserved</desc>
<sw_param offset="0xe0100028" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_sd0_Host_control_Power_control_Block_Gap_Control_Wakeup_control_SD_Bus_Power">
<name>SD_Bus_Power</name>
<desc>Before setting this bit, the SD host driver shall set SD Bus Voltage Select. If the HC detects the No Card State, this bit shall be cleared.
1 - Power on
0 - Power off</desc>
<sw_param offset="0xe0100028" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_sd0_Host_control_Power_control_Block_Gap_Control_Wakeup_control_Card_detect_signal_detetction">
<name>Card_detect_signal_detetction</name>
<desc>This bit selects source for card detection.
1- The card detect test level is selected
0 -SDCD# is selected (for normal use)</desc>
<sw_param offset="0xe0100028" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_sd0_Host_control_Power_control_Block_Gap_Control_Wakeup_control_Card_Detect_Test_Level">
<name>Card_Detect_Test_Level</name>
<desc>This bit is enabled while the Card Detect Signal Selection is set to 1 and it
indicates card inserted or not. Generates (card ins or card removal) interrupt when the normal int sts enable bit is set.
1 - Card Inserted
0 - No Card</desc>
<sw_param offset="0xe0100028" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_sd0_Host_control_Power_control_Block_Gap_Control_Wakeup_control_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0100028" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_sd0_Host_control_Power_control_Block_Gap_Control_Wakeup_control_DMA_Select">
<name>DMA_Select</name>
<desc>One of supported DMA modes can be selected. The host driver shall check support of DMA modes by referring the Capabilities register.
00 - SDMA is selected
01 - 32-bit Address ADMA1 is selected
10 -32-bit Address ADMA2 is selected
11 - 64-bit Address ADMA2 is selected</desc>
<sw_param offset="0xe0100028" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_sd0_Host_control_Power_control_Block_Gap_Control_Wakeup_control_High_Speed_Enable">
<name>High_Speed_Enable</name>
<desc>This bit is optional. Before setting this bit, the HD shall check the High Speed Support in the capabilities register. If this bit is set to 0 (default), the HC outputs CMD line and DAT lines at the falling edge of the SD clock (up to 25 MHz/20MHz for MMC). If this bit is set to 1, the HC outputs CMD line and DAT lines at the rising edge of the SD clock (up to 50 MHz for SD/52MHz for MMC)
1 - High Speed Mode
0 - Normal Speed Mode</desc>
<sw_param offset="0xe0100028" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_sd0_Host_control_Power_control_Block_Gap_Control_Wakeup_control_Data_Transfer_Width_SD1_or_SD4">
<name>Data_Transfer_Width_SD1_or_SD4</name>
<desc>This bit selects the data width of the HC. The HD shall select it to match the data width of the SD card.
1 - 4 bit mode
0 - 1 bit mode</desc>
<sw_param offset="0xe0100028" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_sd0_Host_control_Power_control_Block_Gap_Control_Wakeup_control_LED_Control">
<name>LED_Control</name>
<desc>This bit is used to caution the user not to remove the card while the SD card is being accessed. If the software is going to issue multiple SD commands, this bit can be set during all transactions. It is not necessary to change for each transaction.
1 - LED on
0 - LED off</desc>
<sw_param offset="0xe0100028" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_sd0_Clock_Control_Timeout_control_Software_reset_Software_Reset_for_DAT_Line">
<name>Software_Reset_for_DAT_Line</name>
<desc>Only part of data circuit is reset. The following registers and bits are cleared by this bit:
Buffer Data Port Register
Buffer is cleared and Initialized.
Present State register
Buffer read Enable
Buffer write Enable
Read Transfer Active
Write Transfer Active
DAT Line Active
Command Inhibit (DAT)
Block Gap Control register
Continue Request
Stop At Block Gap Request
Normal Interrupt Status register
Buffer Read Ready
Buffer Write Ready
Block Gap Event
Transfer Complete
1 - Reset
0 - Work</desc>
<sw_param offset="0xe010002c" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_sd0_Clock_Control_Timeout_control_Software_reset_Software_Reset_for_CMD_Line">
<name>Software_Reset_for_CMD_Line</name>
<desc>Only part of command circuit is reset. The following registers and bits are cleared by this bit:
Present State register
Command Inhibit (CMD)
Normal Interrupt Status register
Command Complete
1 - Reset
0 - Work</desc>
<sw_param offset="0xe010002c" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_sd0_Clock_Control_Timeout_control_Software_reset_Software_Reset_for_All">
<name>Software_Reset_for_All</name>
<desc>This reset affects the entire HC except for the card detection circuit. Register bits of type ROC, RW, RW1C, RWAC are cleared to 0. During its initialization, the HD shall set this bit to 1 to reset the HC. The HC shall reset this bit to 0 when capabilities registers are valid and the HD
can read them. Additional use of Software Reset For All may not affect the value of the Capabilities registers. If this bit is set to 1, the SD card shall reset itself and must be re initialized by the HD.
1 - Reset
0 - Work</desc>
<sw_param offset="0xe010002c" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_sd0_Clock_Control_Timeout_control_Software_reset_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe010002c" start="23" end="20" />
</parameter>
<parameter uniqueid="ps7_sd0_Clock_Control_Timeout_control_Software_reset_Data_Timeout_Counter_Value_">
<name>Data_Timeout_Counter_Value_</name>
<desc>This value determines the interval by which DAT line time-outs are detected. Refer to the Data Time-out Error in the Error Interrupt Status register for information on factors that dictate time-out generation. Time-out clock frequency will be generated by dividing the sdclockTMCLK by this value. When setting this register, prevent inadvertent time-out events by clearing the Data
Time-out Error Status Enable (in the Error Interrupt Status Enable register)
1111 - Reserved
1110 - TMCLK * 2^27
------------------------------
------------------------------
0001 - TMCLK * 2^14
0000 - TMCLK * 2^13</desc>
<sw_param offset="0xe010002c" start="19" end="16" />
</parameter>
<parameter uniqueid="ps7_sd0_Clock_Control_Timeout_control_Software_reset_SDCLK_Frequency_Select">
<name>SDCLK_Frequency_Select</name>
<desc>This register is used to select the frequency of the SDCLK pin. The frequency is not programmed directly; rather this register holds the divisor of the Base Clock Frequency For SD clock in the capabilities register. Only the following settings are allowed.
80h - base clock divided by 256
40h - base clock divided by 128
20h - base clock divided by 64
10h - base clock divided by 32
08h - base clock divided by 16
04h - base clock divided by 8
02h - base clock divided by 4
01h - base clock divided by 2
00h - base clock(10MHz-63MHz)
Setting 00h specifies the highest frequency of the SD Clock. When setting multiple bits, the most significant bit is used as the divisor. But multiple bits should not be set. The two default divider values can be calculated by the frequency that is defined by the Base Clock Frequency For SD Clock in the Capabilities register.
1) 25 MHz divider value
2) 400 KHz divider value
The frequency of the SDCLK is set by the following formula:
Clock Frequency = (Baseclock) / divisor.
Thus choose the smallest possible divisor which results in a clock frequency that is less than or equal to the target frequency.
Maximum Frequency for SD = 50Mhz (base clock)
Maximum Frequency for MMC = 52Mhz (base clock)
Minimum Frequency = 195.3125Khz (50Mhz / 256), same calc for MMC also</desc>
<sw_param offset="0xe010002c" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_sd0_Clock_Control_Timeout_control_Software_reset_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe010002c" start="7" end="3" />
</parameter>
<parameter uniqueid="ps7_sd0_Clock_Control_Timeout_control_Software_reset_SD_Clock_Enable">
<name>SD_Clock_Enable</name>
<desc>The HC shall stop SDCLK when writing this bit to 0. SDCLK frequency Select can be changed when this bit is 0. Then, the HC shall maintain the same clock frequency until SDCLK is stopped (Stop at SDCLK = 0). If the HC detects the No Card state, this bit shall be cleared.
1 - Enable
0 - Disable</desc>
<sw_param offset="0xe010002c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_sd0_Clock_Control_Timeout_control_Software_reset_Internal_Clock_Stable">
<name>Internal_Clock_Stable</name>
<desc>This bit is set to 1 when SD clock is stable after writing to Internal Clock Enable in this register to 1. The SD Host Driver shall wait to set SD Clock Enable until this bit is set to 1.
Note: This is useful when using PLL for a clock oscillator that requires setup time.
1 - Ready
0 - Not Ready</desc>
<sw_param offset="0xe010002c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_sd0_Clock_Control_Timeout_control_Software_reset_Internal_Clock_Enable">
<name>Internal_Clock_Enable</name>
<desc>This bit is set to 0 when the HD is not using the HC or the HC awaits a wakeup event. The HC should stop its internal clock to go very low power state. Still, registers shall be able to be read and written. Clock starts to oscillate when this bit is set to 1. When clock oscillation is stable, the HC shall set Internal Clock Stable in this register to 1. This bit shall not affect card detection.
1 - Oscillate
0 - Stop</desc>
<sw_param offset="0xe010002c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_Error_interrupt_status_Ceata_Error_Status">
<name>Ceata_Error_Status</name>
<desc>Occurs when ATA command termination has occured due to an error condition the device has encountered.
0 - no error
1 - error</desc>
<sw_param offset="0xe0100030" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_Error_interrupt_status_Target_Response_error">
<name>Target_Response_error</name>
<desc>Occurs when detecting ERROR in m_hresp(dma transaction)
0 - no error
1 - error</desc>
<sw_param offset="0xe0100030" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_Error_interrupt_status_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe0100030" start="27" end="26" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_Error_interrupt_status_ADMA_Error">
<name>ADMA_Error</name>
<desc>This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register.
1- Error
0 -No error</desc>
<sw_param offset="0xe0100030" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_Error_interrupt_status_Auto_CMD12_Error">
<name>Auto_CMD12_Error</name>
<desc>Occurs when detecting that one of the bits in Auto CMD12 Error Status register has changed from 0 to 1. This bit is set to 1 also when Auto CMD12 is not executed due to the previous command error.
0 - No Error
1 - Error</desc>
<sw_param offset="0xe0100030" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_Error_interrupt_status_Current_Limit_Error">
<name>Current_Limit_Error</name>
<desc>By setting the SD Bus Power bit in the Power Control Register, the HC is requested to supply power for the SD Bus. If the HC supports the Current Limit Function, it can be protected from an Illegal card by stopping power supply to the card in which case this bit indicates a failure status. Reading 1 means the HC is not supplying power to SD card due to some failure. Reading 0 means that the HC is supplying power and no error has occurred. This bit shall always set to be 0, if the HC does not support this function.
0 - No Error
1 - Power Fail</desc>
<sw_param offset="0xe0100030" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_Error_interrupt_status_Data_End_Bit_Error">
<name>Data_End_Bit_Error</name>
<desc>Occurs when detecting 0 at the end bit position of read data which uses the DAT line or the end bit position of the CRC status.
0 - No Error
1 - Error</desc>
<sw_param offset="0xe0100030" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_Error_interrupt_status_Data_CRC_Error">
<name>Data_CRC_Error</name>
<desc>Occurs when detecting CRC error when transferring read data which uses the DAT line or when detecting the Write CRC Status having a value of other than '010'.
0 - No Error
1 - Error</desc>
<sw_param offset="0xe0100030" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_Error_interrupt_status_Data_Timeout_Error">
<name>Data_Timeout_Error</name>
<desc>Occurs when detecting one of following timeout conditions.
1. Busy Timeout for R1b, R5b type.
2. Busy Timeout after Write CRC status
3. Write CRC status Timeout
4. Read Data Timeout
0 - No Error
1 - Timeout</desc>
<sw_param offset="0xe0100030" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_Error_interrupt_status_Command_Index_Error">
<name>Command_Index_Error</name>
<desc>Occurs if a Command Index error occurs in the Command Response.
0 - No Error
1 - Error</desc>
<sw_param offset="0xe0100030" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_Error_interrupt_status_Command_End_Bit_Error">
<name>Command_End_Bit_Error</name>
<desc>Occurs when detecting that the end bit of a command response is 0.
0 - No Error
1 - End Bit Error Generated</desc>
<sw_param offset="0xe0100030" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_Error_interrupt_status_Command_CRC_Error">
<name>Command_CRC_Error</name>
<desc>Command CRC Error is generated in two cases.
1. If a response is returned and the Command Time-out Error is set to 0, this bit is set to 1 when detecting a CRT error in the command response
2. The HC detects a CMD line conflict by monitoring the CMD line when a command is issued. If the HC drives the CMD line to 1 level, but detects 0 level on the CMD line at the next SDCLK edge, then the HC shall abort the command (Stop driving CMD line) and set this bit to 1. The Command Timeout Error shall also be set to 1 to distinguish CMD line conflict.
0 - No Error
1 - CRC Error Generated</desc>
<sw_param offset="0xe0100030" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_Error_interrupt_status_Command_Timeout_Error">
<name>Command_Timeout_Error</name>
<desc>Occurs only if the no response is returned within 64 SDCLK cycles from the end bit of the command. If the HC detects a CMD line conflict, in which case Command CRC Error shall also be set. This bit shall be set without waiting for 64 SDCLK cycles because the command will be aborted by the HC.
0 - No Error
1 - Timeout</desc>
<sw_param offset="0xe0100030" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_Error_interrupt_status_Error_Interrupt">
<name>Error_Interrupt</name>
<desc>If any of the bits in the Error Interrupt Status Register are set, then this bit is set. Therefore the HD can test for an error by checking this bit first.
0 - No Error.
1 - Error.</desc>
<sw_param offset="0xe0100030" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_Error_interrupt_status_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0100030" start="14" end="11" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_Error_interrupt_status_Boot_terminate_Interrupt">
<name>Boot_terminate_Interrupt</name>
<desc>This status is set if the boot opeartion get terminated
0 - Boot operation is not teminated.
1 - Boot operation is teminated</desc>
<sw_param offset="0xe0100030" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_Error_interrupt_status_Boot_ack_rcv">
<name>Boot_ack_rcv</name>
<desc>This status is set if the boot acknowledge is received from device.
0 - Boot ack is not received.
1 - Boot ack is received.</desc>
<sw_param offset="0xe0100030" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_Error_interrupt_status_Card_Interrupt">
<name>Card_Interrupt</name>
<desc>Writing this bit to 1 does not clear this bit. It is cleared by resetting the SD card interrupt factor. In 1-bit mode, the HC shall detect the Card Interrupt without SD Clock to support wakeup. In 4-bit mode, the card interrupt signal is sampled during the interrupt cycle, so there are some sample delays between the interrupt signal from the card and the interrupt to the Host system.
when this status has been set and the HD needs to start this interrupt service, Card Interrupt Status Enable in the Normal Interrupt Status register shall be set to 0 in order to clear the card interrupt statuses latched in the HC and stop driving the Host System. After completion of the card interrupt service (the reset factor in the SD card and the interrupt signal may not be asserted), set Card Interrupt Status Enable to 1 and start sampling the interrupt signal again.
0 - No Card Interrupt
1 - Generate Card Interrupt</desc>
<sw_param offset="0xe0100030" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_Error_interrupt_status_Card_Removal">
<name>Card_Removal</name>
<desc>This status is set if the Card Inserted in the Present State register changes from 1 to 0. When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed.
Because the card detect may possibly be changed when the HD clear this bit an Interrupt event may not be generated.
0 - Card State Stable or Debouncing
1 - Card Removed</desc>
<sw_param offset="0xe0100030" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_Error_interrupt_status_Card_Insertion">
<name>Card_Insertion</name>
<desc>This status is set if the Card Inserted in the Present State register changes from 0 to 1. When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed.
Because the card detect may possibly be changed when the HD clear this bit an Interrupt event may not be generated.
0 - Card State Stable or Debouncing
1 - Card Inserted</desc>
<sw_param offset="0xe0100030" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_Error_interrupt_status_Buffer_Read_Ready">
<name>Buffer_Read_Ready</name>
<desc>This status is set if the Buffer Read Enable
changes from 0 to 1.
0 - Not Ready to read Buffer.
1 - Ready to read Buffer.</desc>
<sw_param offset="0xe0100030" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_Error_interrupt_status_Buffer_Write_Ready">
<name>Buffer_Write_Ready</name>
<desc>This status is set if the Buffer Write Enable
changes from 0 to 1.
0 - Not Ready to Write Buffer.
1 - Ready to Write Buffer.</desc>
<sw_param offset="0xe0100030" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_Error_interrupt_status_DMA_Interrupt">
<name>DMA_Interrupt</name>
<desc>This status is set if the HC detects the Host
DMA Buffer Boundary in the Block Size
regiser.
0 - No DMA Interrupt
1 - DMA Interrupt is Generated</desc>
<sw_param offset="0xe0100030" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_Error_interrupt_status_Block_Gap_Event">
<name>Block_Gap_Event</name>
<desc>If the Stop At Block Gap Request in the Block
Gap Control Register is set, this bit is set.
Read Transaction:
This bit is set at the falling edge of the DAT
Line Active Status (When the transaction is
stopped at SD Bus timing. The Read Wait
must be supported inorder to use this function).
Write Transaction:
This bit is set at the falling edge of Write
Transfer Active Status (After getting CRC status
at SD Bus timing).
0 - No Block Gap Event
1 - Transaction stopped at Block
Gap</desc>
<sw_param offset="0xe0100030" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_Error_interrupt_status_Transfer_Complete">
<name>Transfer_Complete</name>
<desc>This bit is set when a read / write transaction is completed.
Read Transaction:
This bit is set at the falling edge of Read Transfer Active Status.
There are two cases in which the Interrupt is generated. The first is when a data transfer is completed as specified by data length (After the last data has been read to the Host System). The second is when data has stopped at the block gap and completed the data transfer by setting the Stop At Block Gap Request in the Block Gap Control Register (After valid
data has been read to the Host System).
Write Transaction:
This bit is set at the falling edge of the DAT
Line Active Status.
There are two cases in which the Interrupt is generated. The first is when the last data is written to the card as specified by data length and Busy signal is released. The second is when data transfers are stopped at the block gap by setting Stop At Block Gap Request in the Block Gap Control Register and data transfers completed. (After valid data is written to the SD card and the busy signal is released).
Note: Transfer Complete has higher priority than Data Time-out Error. If both bits are set to 1, the data transfer can be considered complete
0 - No Data Transfer Complete
1 - Data Transfer Complete</desc>
<sw_param offset="0xe0100030" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_Error_interrupt_status_Command_Complete">
<name>Command_Complete</name>
<desc>This bit is set when get the end bit of the command response (Except Auto CMD12).
Note: Command Time-out Error has higher priority than Command Complete. If both are set to 1, it can be considered that the response was not received correctly.
0 - No Command Complete
1 - Command Complete</desc>
<sw_param offset="0xe0100030" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_enable_Error_interrupt_status_enable_Ceata_Error_Status_Enable">
<name>Ceata_Error_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100034" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_enable_Error_interrupt_status_enable_Target_Response_Error_Status_Enable">
<name>Target_Response_Error_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100034" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_enable_Error_interrupt_status_enable_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe0100034" start="27" end="26" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_enable_Error_interrupt_status_enable_ADMA_Error_Status_Enable">
<name>ADMA_Error_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100034" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_enable_Error_interrupt_status_enable_Auto_CMD12_Error_Status_Enable">
<name>Auto_CMD12_Error_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100034" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_enable_Error_interrupt_status_enable_Current_Limit_Error_Status_Enable">
<name>Current_Limit_Error_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100034" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_enable_Error_interrupt_status_enable_Data_End_Bit_Error_Status_Enable">
<name>Data_End_Bit_Error_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100034" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_enable_Error_interrupt_status_enable_Data_CRC_Error_Status_Enable">
<name>Data_CRC_Error_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100034" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_enable_Error_interrupt_status_enable_Data_Timeout_Error_Status_Enable">
<name>Data_Timeout_Error_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100034" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_enable_Error_interrupt_status_enable_Command_Index_Error_Status_Enable">
<name>Command_Index_Error_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100034" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_enable_Error_interrupt_status_enable_Command_End_Bit_Error_Status_Enable">
<name>Command_End_Bit_Error_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100034" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_enable_Error_interrupt_status_enable_Command_CRC_Error_Status_Enable">
<name>Command_CRC_Error_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100034" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_enable_Error_interrupt_status_enable_Command_Timeout_Error_Status_Enable">
<name>Command_Timeout_Error_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100034" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_enable_Error_interrupt_status_enable_Fixed_to_0">
<name>Fixed_to_0</name>
<desc>The HC shall control error Interrupts using the Error Interrupt Status Enable register.</desc>
<sw_param offset="0xe0100034" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_enable_Error_interrupt_status_enable_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0100034" start="14" end="11" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_enable_Error_interrupt_status_enable_Boot_terminate_Interrupt_enable">
<name>Boot_terminate_Interrupt_enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100034" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_enable_Error_interrupt_status_enable_Boot_ack_rcv_enable">
<name>Boot_ack_rcv_enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100034" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_enable_Error_interrupt_status_enable_Card_Interrupt_Status_Enable">
<name>Card_Interrupt_Status_Enable</name>
<desc>If this bit is set to 0, the HC shall clear Interrupt request to the System. The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. The HD should clear the Card Interrupt Status Enable before servicing the Card Interrupt and should set this bit again after all Interrupt requests from the card are cleared to prevent inadvertent Interrupts.
0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100034" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_enable_Error_interrupt_status_enable_Card_Removal_Status_Enable">
<name>Card_Removal_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100034" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_enable_Error_interrupt_status_enable_Card_Insertion_Status_Enable">
<name>Card_Insertion_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100034" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_enable_Error_interrupt_status_enable_Buffer_Read_Ready_Status_Enable">
<name>Buffer_Read_Ready_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100034" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_enable_Error_interrupt_status_enable_Buffer_Write_Ready_Status_Enable">
<name>Buffer_Write_Ready_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100034" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_enable_Error_interrupt_status_enable_DMA_Interrupt_Status_Enable">
<name>DMA_Interrupt_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100034" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_enable_Error_interrupt_status_enable_Block_Gap_Event_Status_Enable">
<name>Block_Gap_Event_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100034" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_enable_Error_interrupt_status_enable_Transfer_Complete_Status_Enable">
<name>Transfer_Complete_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100034" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_status_enable_Error_interrupt_status_enable_Command_Complete_Status_Enable">
<name>Command_Complete_Status_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100034" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Ceata_Error_Signal_Enable">
<name>Ceata_Error_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100038" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Target_Response_Error_Signal_Enable">
<name>Target_Response_Error_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100038" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe0100038" start="27" end="26" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_ADMA_Error_Signal_Enable">
<name>ADMA_Error_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100038" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Auto_CMD12_Error_Signal_Enable">
<name>Auto_CMD12_Error_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100038" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Current_Limit_Error_Signal_Enable">
<name>Current_Limit_Error_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100038" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Data_End_Bit_Error_Signal_Enable">
<name>Data_End_Bit_Error_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100038" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Data_CRC_Error_Signal_Enable">
<name>Data_CRC_Error_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100038" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Data_Timeout_Error_Signal_Enable">
<name>Data_Timeout_Error_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100038" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Command_Index_Error_Signal_Enable">
<name>Command_Index_Error_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100038" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Command_End_Bit_Error_Signal_Enable">
<name>Command_End_Bit_Error_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100038" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Command_CRC_Error_Signal_Enable">
<name>Command_CRC_Error_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100038" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Command_Timeout_Error_Signal_Enable">
<name>Command_Timeout_Error_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100038" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Fixed_to_0">
<name>Fixed_to_0</name>
<desc>The HD shall control error Interrupts using the Error Interrupt Signal Enable register.</desc>
<sw_param offset="0xe0100038" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0100038" start="14" end="11" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Boot_terminate_Interrupt_signal_enable">
<name>Boot_terminate_Interrupt_signal_enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100038" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Boot_ack_rcv_signal_enable">
<name>Boot_ack_rcv_signal_enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100038" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Card_Interrupt_Signal_Enable">
<name>Card_Interrupt_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100038" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Card_Removal_Signal_Enable">
<name>Card_Removal_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100038" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Card_Insertion_Signal_Enable">
<name>Card_Insertion_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100038" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Buffer_Read_Ready_Signal_Enable">
<name>Buffer_Read_Ready_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100038" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Buffer_Write_Ready_Signal_Enable">
<name>Buffer_Write_Ready_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100038" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_DMA_Interrupt_Signal_Enable">
<name>DMA_Interrupt_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100038" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Block_Gap_Event_Signal_Enable">
<name>Block_Gap_Event_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100038" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Transfer_Complete_Signal_Enable">
<name>Transfer_Complete_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100038" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_sd0_Normal_interrupt_signal_enable_Error_interrupt_signal_enable_Command_Complete_Signal_Enable">
<name>Command_Complete_Signal_Enable</name>
<desc>0 - Masked
1 - Enabled</desc>
<sw_param offset="0xe0100038" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_sd0_Auto_CMD12_error_status_Command_Not_Issued_By_Auto_CMD12_Error">
<name>Command_Not_Issued_By_Auto_CMD12_Error</name>
<desc>Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 error (D04 - D01) in this register.
0 - No Error
1 - Not Issued</desc>
<sw_param offset="0xe010003c" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_sd0_Auto_CMD12_error_status_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe010003c" start="6" end="5" />
</parameter>
<parameter uniqueid="ps7_sd0_Auto_CMD12_error_status_Auto_CMD12_Index_Error">
<name>Auto_CMD12_Index_Error</name>
<desc>Occurs if the Command Index error occurs in response to a command.
0 - No Error
1 - Error</desc>
<sw_param offset="0xe010003c" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_sd0_Auto_CMD12_error_status_Auto_CMD12_End_Bit_Error">
<name>Auto_CMD12_End_Bit_Error</name>
<desc>Occurs when detecting that the end bit of command response is 0.
0 - No Error
1 - End Bit Error Generated</desc>
<sw_param offset="0xe010003c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_sd0_Auto_CMD12_error_status_Auto_CMD12_CRC_Error">
<name>Auto_CMD12_CRC_Error</name>
<desc>Occurs when detecting a CRC error in the command response.
0 - No Error
1 - CRC Error Generated</desc>
<sw_param offset="0xe010003c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_sd0_Auto_CMD12_error_status_Auto_CMD12_Timeout_Error">
<name>Auto_CMD12_Timeout_Error</name>
<desc>Occurs if the no response is returned within 64 SDCLK cycles from the end bit of the command. If this bit is set to 1, the other error status bits (D04 - D02) are meaningless.
0 - No Error
1 - Timeout</desc>
<sw_param offset="0xe010003c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_sd0_Auto_CMD12_error_status_Auto_CMD12_not_Executed">
<name>Auto_CMD12_not_Executed</name>
<desc>If memory multiple block data transfer is not started due to command
error, this bit is not set because it is not necessary to issue Auto CMD12. Setting this bit to 1 means the HC cannot issue Auto CMD12 to stop memory multiple block transfer due to some error. If this bit is set to 1, other error status bits (D04 - D01) are meaningless.
0 - Executed
1 - Not Executed</desc>
<sw_param offset="0xe010003c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_sd0_Capabilities_Spi_block_mode">
<name>Spi_block_mode</name>
<desc>Spi block mode
0 - Not Supported
1 - Supported</desc>
<sw_param offset="0xe0100040" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_sd0_Capabilities_Spi_mode">
<name>Spi_mode</name>
<desc>Spi mode
0 - Not Supported
1 - Supported</desc>
<sw_param offset="0xe0100040" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_sd0_Capabilities_n64_bit_System_Bus_Support">
<name>n64_bit_System_Bus_Support</name>
<desc>1 - supports 64 bit system address
0 - Does not support 64 bit system
address</desc>
<sw_param offset="0xe0100040" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_sd0_Capabilities_Interrupt_mode">
<name>Interrupt_mode</name>
<desc>Interrupt mode
0 - Not Supported
1 - Supported</desc>
<sw_param offset="0xe0100040" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_sd0_Capabilities_Voltage_Support_1_8_V">
<name>Voltage_Support_1_8_V</name>
<desc>0 - 1.8 V Not Supported
1 - 1.8 V Supported</desc>
<sw_param offset="0xe0100040" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_sd0_Capabilities_Voltage_Support_3_0_V">
<name>Voltage_Support_3_0_V</name>
<desc>0 - 3.0 V Not Supported
1 - 3.0 V Supported</desc>
<sw_param offset="0xe0100040" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_sd0_Capabilities_Voltage_Support_3_3_V">
<name>Voltage_Support_3_3_V</name>
<desc>0 - 3.3 V Not Supported
1 - 3.3 V Supported</desc>
<sw_param offset="0xe0100040" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_sd0_Capabilities_Suspend_Resume_Support">
<name>Suspend_Resume_Support</name>
<desc>This bit indicates whether the HC supports Suspend / Resume functionality. If this bit is 0, the Suspend and Resume mechanism are not supported and the HD shall not issue either Suspend / Resume commands.
0 - Not Supported
1 - Supported</desc>
<sw_param offset="0xe0100040" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_sd0_Capabilities_SDMA_Support">
<name>SDMA_Support</name>
<desc>This bit indicates whether the HC is capable of using DMA to transfer data between system memory and the HC directly.
0 - SDMA Not Supported
1 - SDMA Supported.</desc>
<sw_param offset="0xe0100040" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_sd0_Capabilities_High_Speed_Support">
<name>High_Speed_Support</name>
<desc>This bit indicates whether the HC and the Host System support High Speed mode and they can supply SD Clock frequency from 25Mhz to 50 Mhz (for SD)/ 20MHz to 52MHz (for MMC).
0 - High Speed Not Supported
1 - High Speed Supported</desc>
<sw_param offset="0xe0100040" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_sd0_Capabilities_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe0100040" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_sd0_Capabilities_ADMA2_Support">
<name>ADMA2_Support</name>
<desc>1 - ADMA2 support.
0 - ADMA2 not support</desc>
<sw_param offset="0xe0100040" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_sd0_Capabilities_Extended_Media_Bus_Support">
<name>Extended_Media_Bus_Support</name>
<desc>This bit indicates whether the Host Controller is capable bus.
1 - Extended Media Bus Supported
0 - Extended Media Bus not Supported</desc>
<sw_param offset="0xe0100040" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_sd0_Capabilities_Max_Block_Length">
<name>Max_Block_Length</name>
<desc>This value indicates the maximum block size that the HD can read and write to the buffer in the HC. The buffer shall transfer this block size without wait cycles. Three sizes can be defined as indicated below.
00 - 512 byte
01 - 1024 byte
10 - 2048 byte
11 - 4096 byte</desc>
<sw_param offset="0xe0100040" start="17" end="16" />
</parameter>
<parameter uniqueid="ps7_sd0_Capabilities_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe0100040" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_sd0_Capabilities_Base_Clock_Frequency_for_SD_Clock">
<name>Base_Clock_Frequency_for_SD_Clock</name>
<desc>This value indicates the base (maximum) clock frequency for the SD clock. Unit values are 1Mhz. If the real frequency is 16.5 Mhz, the larger value shall be set 010001b (17 Mhz) because the HD uses this value to calculate the clock divider value and it shall not exceed the upper limit of the SD clock frequency. The supported range is 10Mhz to 63 Mhz. If these bits are all 0, the Host System has to get information via another method. Not 0 - 1 Mhz to 63 Mhz
000000b - Get information via another method.</desc>
<sw_param offset="0xe0100040" start="13" end="8" />
</parameter>
<parameter uniqueid="ps7_sd0_Capabilities_Timeout_Clock_Unit">
<name>Timeout_Clock_Unit</name>
<desc>This bit shows the unit of base clock frequency used to detect Data Timeout Error.
0 - Khz
1 - Mhz</desc>
<sw_param offset="0xe0100040" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_sd0_Capabilities_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0100040" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_sd0_Capabilities_Timeout_Clock_Frequency">
<name>Timeout_Clock_Frequency</name>
<desc>This bit shows the base clock frequency used to detect Data Timeout Error.
Not 0 - 1Khz to 63Khz or 1Mhz to 63Mhz 000000b - Get Information via another method.</desc>
<sw_param offset="0xe0100040" start="5" end="0" />
</parameter>
<parameter uniqueid="ps7_sd0_Maximum_current_capabilities_Maximum_Current_for_1_8V">
<name>Maximum_Current_for_1_8V</name>
<desc>Maximum Current for 1.8V</desc>
<sw_param offset="0xe0100048" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_sd0_Maximum_current_capabilities_Maximum_Current_for_3_0V">
<name>Maximum_Current_for_3_0V</name>
<desc>Maximum Current for 3.0V</desc>
<sw_param offset="0xe0100048" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_sd0_Maximum_current_capabilities_Maximum_Current_for_3_3V">
<name>Maximum_Current_for_3_3V</name>
<desc>Maximum Current for 3.3V</desc>
<sw_param offset="0xe0100048" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_sd0_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Vendor_Specific_Error_Status">
<name>Force_Event_for_Vendor_Specific_Error_Status</name>
<desc>Additional status bits can be defined in
this register by the vendor.
1 - Interrupt is generated
0 - No interrupt</desc>
<sw_param offset="0xe0100050" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_sd0_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Ceata_error">
<name>Force_Event_for_Ceata_error</name>
<desc>Force Event for Ceata Error
1 - Interrupt is generated
0 - No interrupt</desc>
<sw_param offset="0xe0100050" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_sd0_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_event_for_Target_Response_error">
<name>Force_event_for_Target_Response_error</name>
<desc>Force Event for Target Response Error
1 - Interrupt is generated
0 - No interrupt</desc>
<sw_param offset="0xe0100050" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_sd0_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe0100050" start="27" end="26" />
</parameter>
<parameter uniqueid="ps7_sd0_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_ADMA_Error">
<name>Force_Event_for_ADMA_Error</name>
<desc>Force Event for ADMA Error
1 - Interrupt is generated
0 - No interrupt</desc>
<sw_param offset="0xe0100050" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_sd0_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Auto_CMD12_Error">
<name>Force_Event_for_Auto_CMD12_Error</name>
<desc>Force Event for Auto CMD12 Error
1 - Interrupt is generated
0 - No interrupt</desc>
<sw_param offset="0xe0100050" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_sd0_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Current_Limit_Error">
<name>Force_Event_for_Current_Limit_Error</name>
<desc>Force Event for Current Limit Error
1 - Interrupt is generated
0 - No interrupt</desc>
<sw_param offset="0xe0100050" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_sd0_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Data_End_Bit_Error">
<name>Force_Event_for_Data_End_Bit_Error</name>
<desc>Force Event for Data End Bit Error
1 - Interrupt is generated
0 - No interrupt</desc>
<sw_param offset="0xe0100050" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_sd0_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Data_CRC_Error">
<name>Force_Event_for_Data_CRC_Error</name>
<desc>Force Event for Data CRC Error
1 - Interrupt is generated
0 - No interrupt</desc>
<sw_param offset="0xe0100050" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_sd0_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Data__Timeout_Error">
<name>Force_Event_for_Data__Timeout_Error</name>
<desc>Force Event for Data Timeout Error
1 - Interrupt is generated
0 - No interrupt</desc>
<sw_param offset="0xe0100050" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_sd0_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Command_Index_Error">
<name>Force_Event_for_Command_Index_Error</name>
<desc>Force Event for Command Index Error
1 - Interrupt is generated
0 - No interrupt</desc>
<sw_param offset="0xe0100050" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_sd0_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Command_End_Bit_Error">
<name>Force_Event_for_Command_End_Bit_Error</name>
<desc>Force Event for Command End Bit Error
1 - Interrupt is generated
0 - No interrupt</desc>
<sw_param offset="0xe0100050" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_sd0_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Command_CRC_Error">
<name>Force_Event_for_Command_CRC_Error</name>
<desc>Force Event for Command CRC Error
1 - Interrupt is generated
0 - No interrupt</desc>
<sw_param offset="0xe0100050" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_sd0_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Command_Timeout_Error">
<name>Force_Event_for_Command_Timeout_Error</name>
<desc>Force Event for Command Timeout Error
1 - Interrupt is generated
0 - No interrupt</desc>
<sw_param offset="0xe0100050" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_sd0_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe0100050" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_sd0_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_command_not_issued_by_Auto_CMD12_Error">
<name>Force_Event_for_command_not_issued_by_Auto_CMD12_Error</name>
<desc>1 - Interrupt is generated
0 - no interrupt</desc>
<sw_param offset="0xe0100050" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_sd0_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0100050" start="6" end="5" />
</parameter>
<parameter uniqueid="ps7_sd0_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Auto_CMD12_Index_Error">
<name>Force_Event_for_Auto_CMD12_Index_Error</name>
<desc>1 - Interrupt is generated
0 - no interrupt</desc>
<sw_param offset="0xe0100050" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_sd0_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Auto_CMD12_End_bit_Error">
<name>Force_Event_for_Auto_CMD12_End_bit_Error</name>
<desc>1 - Interrupt is generated
0 - no interrupt</desc>
<sw_param offset="0xe0100050" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_sd0_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Auto_CMD12_CRC_Error">
<name>Force_Event_for_Auto_CMD12_CRC_Error</name>
<desc>1 - Interrupt is generated
0 - no interrupt</desc>
<sw_param offset="0xe0100050" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_sd0_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Auto_CMD12_timeout_Error">
<name>Force_Event_for_Auto_CMD12_timeout_Error</name>
<desc>1 - Interrupt is generated
0 - no interrupt</desc>
<sw_param offset="0xe0100050" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_sd0_Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status_Force_Event_for_Auto_CMD12_NOT_Executed">
<name>Force_Event_for_Auto_CMD12_NOT_Executed</name>
<desc>1 - Interrupt is generated
0 - no interrupt</desc>
<sw_param offset="0xe0100050" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_sd0_ADMA_error_status_ADMA_Length_Mismatch_Error">
<name>ADMA_Length_Mismatch_Error</name>
<desc>This error occurs in the following 2 cases.
1. While Block Count Enable being set, the total
data length specified by the
Descriptor table is different from that specified by
the Block Count and
Block Length.
2. Total data length can not be divided by the block
length.
1 - Error
0 - No error</desc>
<sw_param offset="0xe0100054" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_sd0_ADMA_error_status_ADMA_Error_State">
<name>ADMA_Error_State</name>
<desc>This field indicates the state of ADMA when error is occurred during ADMA data transfer. This field never indicates "10" because ADMA never stops in this state.
D01 - D00 : ADMA Error State when
error is occurred
Contents of SYS_SDR register
00 - ST_STOP (Stop DMA) Points next of the error
descriptor
01 - ST_FDS (Fetch Descriptor) Points the error
descriptor
10 - Never set this state (Not used)
11 - ST_TFR (Transfer Data) Points the next of the
error descriptor</desc>
<sw_param offset="0xe0100054" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_sd0_ADMA_system_address_ADMA_System_Address">
<name>ADMA_System_Address</name>
<desc>This register holds byte address of executing
command of the Descriptor table.
32-bit Address Descriptor uses lower 32-
bit of this register. At the start of ADMA,
the Host Driver shall set start address of
the Descriptor table. The ADMA
increments this register address, which
points to next line, when every fetching a
Descriptor line. When the ADMA Error
Interrupt is generated, this register shall
hold valid Descriptor address depending
on the ADMA state. The Host Driver shall
program Descriptor Table on 32-bit
boundary and set 32-bit boundary
address to this register. ADMA2 ignores
lower 2-bit of this register and assumes it
to be 00b.
32-bit Address ADMA Register Value 32-
bit System Address
0x00000000 0x00000000
0x00000004 0x00000004
to
0xFFFFFFFC 0xFFFFFFFC</desc>
<sw_param offset="0xe0100058" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_sd0_Boot_Timeout_control_Boot_Data_Timeout_Counter_Value">
<name>Boot_Data_Timeout_Counter_Value</name>
<desc>This value determines the interval by
which DAT line time-outs are detected
during boot operation for MMC3.31
card.
The value is in number of sd clock.</desc>
<sw_param offset="0xe0100060" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_sd0_Debug_Selection_Debug_sel">
<name>Debug_sel</name>
<desc>1- cmd register, Interrupt status, transmitter
module, ahb_iface module and clk
sdcard signals are probed out.
0 - receiver module and fifo_ctrl module
signals are probed out</desc>
<sw_param offset="0xe0100064" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_sd0_SPI_interrupt_support_SPI_INT_SUPPORT">
<name>SPI_INT_SUPPORT</name>
<desc>This bit is set to indicate the assertion of interrupts in the SPI mode at any time, irrespective of the status of the card select (CS) line. If this bit is zero,
then SDIO card can only assert the interrupt line in the SPI mode when the CS line is asserted.</desc>
<sw_param offset="0xe01000f0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_sd0_Slot_interrupt_status_Host_controller_version_Specification_Version_Number">
<name>Specification_Version_Number</name>
<desc>This status indicates the Host Controller Spec. Version. The upper and lower 4-bits indicate the version. 00 - SD Host Specification version
1.0
01 - SD Host Specification version 2.00 including only the feature of theTest Register
others - Reserved</desc>
<sw_param offset="0xe01000fc" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_sd0_Slot_interrupt_status_Host_controller_version_Vendor_Version_Number">
<name>Vendor_Version_Number</name>
<desc>This status is reserved for the vendor version number. The HD should not use this status.</desc>
<sw_param offset="0xe01000fc" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_sd0_Slot_interrupt_status_Host_controller_version_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe01000fc" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_sd0_Slot_interrupt_status_Host_controller_version_Interrupt_Signal_for_Each_Slot">
<name>Interrupt_Signal_for_Each_Slot</name>
<desc>These status bit indicate the logical OR of Interrupt signal and Wakeup
signal for each slot. A maximum of 8 slots can be defined. If one interrupt
signal is associated with multiple slots. the HD can know which interrupt
is generated by reading these status bits. By a power on reset or by Software Reset For All, the Interrupt signal shall be de asserted and this
status shall read 00h.
Bit 00 - Slot 1
Bit 01 - Slot 2
Bit 02 - Slot 3
----- -----
Bit 07 - Slot 8</desc>
<sw_param offset="0xe01000fc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_SuppSize_a">
<name>a</name>
<desc>Each bit location represents a single port size that is
supported on the device, that is, 32-1 in bit locations [31:0].</desc>
<sw_param offset="0xf8803000" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_CurrentSize_a">
<name>a</name>
<desc>The Current Port Size Register has the same format as the Supported Port Sizes register but only one bit is set, and all others must be zero. Writing values with more than one bit set or setting a bit that is not indicated as supported is not supported and causes unpredictable behavior.</desc>
<sw_param offset="0xf8803004" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_SuppTrigMode_TrgRun">
<name>TrgRun</name>
<desc>Trigger Counter running. A trigger has occurred but the counter is not at zero.</desc>
<sw_param offset="0xf8803100" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_SuppTrigMode_Triggered">
<name>Triggered</name>
<desc>A trigger has occurred and the counter has reached zero.</desc>
<sw_param offset="0xf8803100" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_SuppTrigMode_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8803100" start="15" end="9" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_SuppTrigMode_TCount8">
<name>TCount8</name>
<desc>8-bit wide counter register implemented.</desc>
<sw_param offset="0xf8803100" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_SuppTrigMode_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xf8803100" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_SuppTrigMode_Mult64k">
<name>Mult64k</name>
<desc>Multiply the Trigger Counter by 65536 supported.</desc>
<sw_param offset="0xf8803100" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_SuppTrigMode_Mult256">
<name>Mult256</name>
<desc>Multiply the Trigger Counter by 256 supported.</desc>
<sw_param offset="0xf8803100" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_SuppTrigMode_Mult16">
<name>Mult16</name>
<desc>Multiply the Trigger Counter by 16 supported.</desc>
<sw_param offset="0xf8803100" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_SuppTrigMode_Mult4">
<name>Mult4</name>
<desc>Multiply the Trigger Counter by 4 supported.</desc>
<sw_param offset="0xf8803100" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_SuppTrigMode_Mult2">
<name>Mult2</name>
<desc>Multiply the Trigger Counter by 2 supported.</desc>
<sw_param offset="0xf8803100" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_TrigCount_TrigCount">
<name>TrigCount</name>
<desc>8-bit counter value for the number of words to be output from the formatter before a trigger is inserted.</desc>
<sw_param offset="0xf8803104" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_TrigMult_Mult64k">
<name>Mult64k</name>
<desc>Multiply the Trigger Counter by 65536.</desc>
<sw_param offset="0xf8803108" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_TrigMult_Mult256">
<name>Mult256</name>
<desc>Multiply the Trigger Counter by 256.</desc>
<sw_param offset="0xf8803108" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_TrigMult_Mult16">
<name>Mult16</name>
<desc>Multiply the Trigger Counter by 16.</desc>
<sw_param offset="0xf8803108" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_TrigMult_Mult4">
<name>Mult4</name>
<desc>Multiply the Trigger Counter by 4.</desc>
<sw_param offset="0xf8803108" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_TrigMult_Mult2">
<name>Mult2</name>
<desc>Multiply the Trigger Counter by 2.</desc>
<sw_param offset="0xf8803108" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_SuppTest_PContEn">
<name>PContEn</name>
<desc>Continuous mode.</desc>
<sw_param offset="0xf8803200" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_SuppTest_PTimeEn">
<name>PTimeEn</name>
<desc>Timed mode.</desc>
<sw_param offset="0xf8803200" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_SuppTest_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8803200" start="15" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_SuppTest_PatF0">
<name>PatF0</name>
<desc>FF/00 Pattern</desc>
<sw_param offset="0xf8803200" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_SuppTest_PatA5">
<name>PatA5</name>
<desc>AA/55 Pattern</desc>
<sw_param offset="0xf8803200" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_SuppTest_PatW0">
<name>PatW0</name>
<desc>Walking 0s Pattern</desc>
<sw_param offset="0xf8803200" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_SuppTest_PatW1">
<name>PatW1</name>
<desc>Walking 1s Pattern</desc>
<sw_param offset="0xf8803200" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_CurrentTest_PContEn">
<name>PContEn</name>
<desc>Continuous mode.</desc>
<sw_param offset="0xf8803204" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_CurrentTest_PTimeEn">
<name>PTimeEn</name>
<desc>Timed mode.</desc>
<sw_param offset="0xf8803204" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_CurrentTest_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8803204" start="15" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_CurrentTest_PatF0">
<name>PatF0</name>
<desc>FF/00 Pattern</desc>
<sw_param offset="0xf8803204" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_CurrentTest_PatA5">
<name>PatA5</name>
<desc>AA/55 Pattern</desc>
<sw_param offset="0xf8803204" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_CurrentTest_PatW0">
<name>PatW0</name>
<desc>Walking 0s Pattern</desc>
<sw_param offset="0xf8803204" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_CurrentTest_PatW1">
<name>PatW1</name>
<desc>Walking 1s Pattern</desc>
<sw_param offset="0xf8803204" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_TestRepeatCount_PattCount">
<name>PattCount</name>
<desc>8-bit counter value to indicate the number of TRACECLKIN cycles that a pattern runs for before switching to the next pattern.</desc>
<sw_param offset="0xf8803208" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_FFSR_TCPresent">
<name>TCPresent</name>
<desc>If this bit is set then TRACECTL is present.</desc>
<sw_param offset="0xf8803300" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_FFSR_FtStopped">
<name>FtStopped</name>
<desc>Formatter stopped.
The formatter has received a stop request signal and all trace data and post-amble has been output. Any more trace data on the ATB interface is ignored and ATREADYS goes HIGH.</desc>
<sw_param offset="0xf8803300" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_FFSR_FlInProg">
<name>FlInProg</name>
<desc>Flush In Progress. This is an indication of the current state of AFVALIDS.</desc>
<sw_param offset="0xf8803300" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_FFCR_StopTrig">
<name>StopTrig</name>
<desc>Stop the formatter after a Trigger Event is observed.</desc>
<sw_param offset="0xf8803304" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_FFCR_StopFl">
<name>StopFl</name>
<desc>Stop the formatter after a flush completes (return of AFREADYS). This forces the FIFO to drain off any part-completed packets.</desc>
<sw_param offset="0xf8803304" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_FFCR_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8803304" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_FFCR_TrigFl">
<name>TrigFl</name>
<desc>Indicates a trigger on Flush completion on AFREADYS being returned.</desc>
<sw_param offset="0xf8803304" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_FFCR_TrigEvt">
<name>TrigEvt</name>
<desc>Indicates a trigger on a Trigger Event.</desc>
<sw_param offset="0xf8803304" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_FFCR_TrigIn">
<name>TrigIn</name>
<desc>Indicates a trigger on TRIGIN being asserted.</desc>
<sw_param offset="0xf8803304" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_FFCR_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xf8803304" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_FFCR_FOnMan">
<name>FOnMan</name>
<desc>Manually generate a flush of the system. Setting this bit causes a flush to be generated. This is cleared when this flush has been serviced.</desc>
<sw_param offset="0xf8803304" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_FFCR_FOnTrig">
<name>FOnTrig</name>
<desc>Generate a flush using Trigger event.
Set this bit to cause a flush of data in the system when a Trigger Event occurs.</desc>
<sw_param offset="0xf8803304" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_FFCR_FOnFlIn">
<name>FOnFlIn</name>
<desc>Generate flush using the FLUSHIN interface. Set this bit to enable use of the FLUSHIN connection.</desc>
<sw_param offset="0xf8803304" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_FFCR_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xf8803304" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_FFCR_EnFCont">
<name>EnFCont</name>
<desc>Continuous Formatting, no TRACECTL. Embed in trigger packets and indicate null cycles using Sync packets. Can only be changed when FtStopped is HIGH.</desc>
<sw_param offset="0xf8803304" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_FFCR_EnFTC">
<name>EnFTC</name>
<desc>Enable Formatting. Do not embed Triggers into the formatted stream. Trace disable cycles and triggers are indicated by TRACECTL, where fitted. Can only be changed when FtStopped is HIGH.</desc>
<sw_param offset="0xf8803304" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_FormatSyncCount_CycCount">
<name>CycCount</name>
<desc>12-bit counter value to indicate the number of complete frames between full synchronization packets.</desc>
<sw_param offset="0xf8803308" start="11" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_EXTCTLIn_a">
<name>a</name>
<desc>Tied to 0</desc>
<sw_param offset="0xf8803400" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_EXTCTLOut_a">
<name>a</name>
<desc>Output not connected</desc>
<sw_param offset="0xf8803404" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_ITTRFLINACK_FLUSHINACK">
<name>FLUSHINACK</name>
<desc>Set the value of FLUSHINACK</desc>
<sw_param offset="0xf8803ee4" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_ITTRFLINACK_TRIGINACK">
<name>TRIGINACK</name>
<desc>Set the value of TRIGINACK</desc>
<sw_param offset="0xf8803ee4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_ITTRFLIN_FLUSHIN">
<name>FLUSHIN</name>
<desc>Read the value of FLUSHIN</desc>
<sw_param offset="0xf8803ee8" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_ITTRFLIN_TRIGIN">
<name>TRIGIN</name>
<desc>Read the value of TRIGIN</desc>
<sw_param offset="0xf8803ee8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_ITATBDATA0_ATDATA31">
<name>ATDATA31</name>
<desc>Read the value of ATDATAS[31]</desc>
<sw_param offset="0xf8803eec" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_ITATBDATA0_ATDATA23">
<name>ATDATA23</name>
<desc>Read the value of ATDATAS[23]</desc>
<sw_param offset="0xf8803eec" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_ITATBDATA0_ATDATA15">
<name>ATDATA15</name>
<desc>Read the value of ATDATAS[15]</desc>
<sw_param offset="0xf8803eec" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_ITATBDATA0_ATDATA7">
<name>ATDATA7</name>
<desc>Read the value of ATDATAS[7]</desc>
<sw_param offset="0xf8803eec" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_ITATBDATA0_ATDATA0">
<name>ATDATA0</name>
<desc>Read the value of ATDATAS[0]</desc>
<sw_param offset="0xf8803eec" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_ITATBCTR2_AFVALID">
<name>AFVALID</name>
<desc>Set the value of AFVALIDS</desc>
<sw_param offset="0xf8803ef0" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_ITATBCTR2_ATREADY">
<name>ATREADY</name>
<desc>Set the value of ATREADYS</desc>
<sw_param offset="0xf8803ef0" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_ITATBCTR1_ATID">
<name>ATID</name>
<desc>Read the value of ATIDS</desc>
<sw_param offset="0xf8803ef4" start="6" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_ITATBCTR0_ATBYTES">
<name>ATBYTES</name>
<desc>Read the value of ATBYTESS</desc>
<sw_param offset="0xf8803ef8" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_ITATBCTR0_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8803ef8" start="7" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_ITATBCTR0_AFREADY">
<name>AFREADY</name>
<desc>Read the value of AFREADYS</desc>
<sw_param offset="0xf8803ef8" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_ITATBCTR0_ATVALID">
<name>ATVALID</name>
<desc>Read the value of ATVALIDS</desc>
<sw_param offset="0xf8803ef8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_IMCR_a">
<name>a</name>
<desc>Enable Integration Test registers</desc>
<sw_param offset="0xf8803f00" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_CTSR_a">
<name>a</name>
<desc>The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed.
Read:
1= Claim tag is implemented, 0 = Claim tag is not implemented
Write:
1= Set claim tag bit, 0= No effect</desc>
<sw_param offset="0xf8803fa0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_CTCR_a">
<name>a</name>
<desc>The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed.
Read: Current value of claim tag.
Write: 1= Clear claim tag bit, 0= No effect</desc>
<sw_param offset="0xf8803fa4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_LAR_a">
<name>a</name>
<desc>Write Access Code.
Write behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
After reset (via PRESETDBGn), TPIU is locked, i.e., writes to all other registers using lower 2GB addresses are ignored.
To unlock, 0xC5ACCE55 must be written this register.
After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register.
- PADDRDBG31=1 (upper 2GB):
TPIU is unlocked when upper 2GB addresses are used to write to all the registers.
However, write to this register is ignored using a upper 2GB address!
Note: read from this register always returns 0, regardless of PADDRDBG31.</desc>
<sw_param offset="0xf8803fb0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_LSR_n8BIT">
<name>n8BIT</name>
<desc>Set to 0 since TPIU implements a 32-bit lock access register</desc>
<sw_param offset="0xf8803fb4" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_LSR_STATUS">
<name>STATUS</name>
<desc>Read behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
When a lower 2GB address is used to read this register, this bit indicates whether TPIU is in locked state
(1= locked, 0= unlocked).
- PADDRDBG31=1 (upper 2GB):
always returns 0.</desc>
<sw_param offset="0xf8803fb4" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_LSR_IMP">
<name>IMP</name>
<desc>Read behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
always returns 1, meaning lock mechanism are implemented.
- PADDRDBG31=1 (upper 2GB):
always returns 0, meaning lock mechanism is NOT implemented.</desc>
<sw_param offset="0xf8803fb4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_ASR_a">
<name>a</name>
<desc>Indicates functionality not implemented</desc>
<sw_param offset="0xf8803fb8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_DEVID_UartNRZ">
<name>UartNRZ</name>
<desc>UART/NRZ not supported</desc>
<sw_param offset="0xf8803fc8" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_DEVID_Manchester">
<name>Manchester</name>
<desc>Manchester not support</desc>
<sw_param offset="0xf8803fc8" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_DEVID_ClockData">
<name>ClockData</name>
<desc>Trace clock + data is supported</desc>
<sw_param offset="0xf8803fc8" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_DEVID_FifoSize">
<name>FifoSize</name>
<desc>FIFO size is 4</desc>
<sw_param offset="0xf8803fc8" start="8" end="6" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_DEVID_AsyncClock">
<name>AsyncClock</name>
<desc>ATCLK and TRACECLKIN is asynchronous</desc>
<sw_param offset="0xf8803fc8" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_DEVID_InputMux">
<name>InputMux</name>
<desc>No input multiplexing</desc>
<sw_param offset="0xf8803fc8" start="4" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_DTIR_a">
<name>a</name>
<desc>A trace sink and aspeicifically a TPIU</desc>
<sw_param offset="0xf8803fcc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_PERIPHID4_n4KB_count">
<name>n4KB_count</name>
<desc>4KB Count, set to 0</desc>
<sw_param offset="0xf8803fd0" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_PERIPHID4_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 continuation code</desc>
<sw_param offset="0xf8803fd0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_PERIPHID5_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf8803fd4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_PERIPHID6_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf8803fd8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_PERIPHID7_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf8803fdc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_PERIPHID0_a">
<name>a</name>
<desc>PartNumber0</desc>
<sw_param offset="0xf8803fe0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_PERIPHID1_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 Identity Code [3:0]</desc>
<sw_param offset="0xf8803fe4" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_PERIPHID1_PartNumber1">
<name>PartNumber1</name>
<desc>PartNumber1</desc>
<sw_param offset="0xf8803fe4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_PERIPHID2_RevNum">
<name>RevNum</name>
<desc>Revision number of Peripheral</desc>
<sw_param offset="0xf8803fe8" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_PERIPHID2_JEDEC">
<name>JEDEC</name>
<desc>Indicates that a JEDEC assigned value is used</desc>
<sw_param offset="0xf8803fe8" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_PERIPHID2_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 Identity Code [6:4]</desc>
<sw_param offset="0xf8803fe8" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_PERIPHID3_RevAnd">
<name>RevAnd</name>
<desc>RevAnd, at top level</desc>
<sw_param offset="0xf8803fec" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_PERIPHID3_CustMod">
<name>CustMod</name>
<desc>Customer Modified</desc>
<sw_param offset="0xf8803fec" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_COMPID0_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8803ff0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_COMPID1_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8803ff4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_COMPID2_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8803ff8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_tpiu_COMPID3_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8803ffc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMGLBCTRL_FTMENABLE">
<name>FTMENABLE</name>
<desc>Enable FTM</desc>
<sw_param offset="0xf880b000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMSTATUS_IDLE">
<name>IDLE</name>
<desc>FTM IDLE Status</desc>
<sw_param offset="0xf880b004" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMSTATUS_SPIDEN">
<name>SPIDEN</name>
<desc>Trustzone SPIDEN signal status</desc>
<sw_param offset="0xf880b004" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMSTATUS_DBGEN">
<name>DBGEN</name>
<desc>Trustzone DBGEN signal status</desc>
<sw_param offset="0xf880b004" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMSTATUS_SPNIDEN">
<name>SPNIDEN</name>
<desc>Trustzone SPNIDEN signal status</desc>
<sw_param offset="0xf880b004" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMSTATUS_NIDEN">
<name>NIDEN</name>
<desc>Trustzone NIDEN signal status</desc>
<sw_param offset="0xf880b004" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMSTATUS_FIFOFULL">
<name>FIFOFULL</name>
<desc>1 = FIFO is full</desc>
<sw_param offset="0xf880b004" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMSTATUS_FIFOEMPTY">
<name>FIFOEMPTY</name>
<desc>1 = FIFO is empty</desc>
<sw_param offset="0xf880b004" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMSTATUS_LOCKED">
<name>LOCKED</name>
<desc>Always read as zero</desc>
<sw_param offset="0xf880b004" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMCONTROL_CYCEN">
<name>CYCEN</name>
<desc>Enable Cycle Count packets</desc>
<sw_param offset="0xf880b008" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMCONTROL_TRACEN">
<name>TRACEN</name>
<desc>Enable Trace packets</desc>
<sw_param offset="0xf880b008" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMCONTROL_PROG">
<name>PROG</name>
<desc>Not used</desc>
<sw_param offset="0xf880b008" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMP2FDBG0_PSS2FPGA">
<name>PSS2FPGA</name>
<desc>Signals presented to the fabric. These signals do not affect the FTM, they are provided for user specific debug. To modify the contents of this register, the SPIDEN pin must be asserted.</desc>
<sw_param offset="0xf880b00c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMP2FDBG1_PSS2FPGA">
<name>PSS2FPGA</name>
<desc>Signals presented to the fabric. These signals do not affect the FTM, they are provided for user specific debug. To modify the contents of this register, the SPIDEN pin must be asserted.</desc>
<sw_param offset="0xf880b010" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMP2FDBG2_PSS2FPGA">
<name>PSS2FPGA</name>
<desc>Signals presented to the fabric. These signals do not affect the FTM, they are provided for user specific debug. To modify the contents of this register, the SPIDEN pin must be asserted.</desc>
<sw_param offset="0xf880b014" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMP2FDBG3_PSS2FPGA">
<name>PSS2FPGA</name>
<desc>Signals presented to the fabric. These signals do not affect the FTM, they are provided for user specific debug. To modify the contents of this register, the SPIDEN pin must be asserted.</desc>
<sw_param offset="0xf880b018" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMF2PDBG0_FPGA2PSS">
<name>FPGA2PSS</name>
<desc>Signals that are presented to the PSS from the Fabric.</desc>
<sw_param offset="0xf880b01c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMF2PDBG1_FPGA2PSS">
<name>FPGA2PSS</name>
<desc>Signals that are presented to the PSS from the Fabric.</desc>
<sw_param offset="0xf880b020" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMF2PDBG2_FPGA2PSS">
<name>FPGA2PSS</name>
<desc>Signals that are presented to the PSS from the Fabric.</desc>
<sw_param offset="0xf880b024" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMF2PDBG3_FPGA2PSS">
<name>FPGA2PSS</name>
<desc>Signals that are presented to the PSS from the Fabric.</desc>
<sw_param offset="0xf880b028" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_CYCOUNTPRE_PRESCALE">
<name>PRESCALE</name>
<desc>The incoming clock is divided by 2^ PRESCALE. For example: PRESCALE = 15 indicates that the Cycle Counter runs at the AXI clock divided by 2^15 = 32,768 (PRESCALE = 0 indicates no clock scaling)</desc>
<sw_param offset="0xf880b02c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMSYNCRELOAD_SYNCCOUNTTERM">
<name>SYNCCOUNTTERM</name>
<desc>Reset FTM Synchronization packet counter when this number of packets has been transmitted. THIS NUMBER HAS A MINIMUM VALUE of 12.</desc>
<sw_param offset="0xf880b030" start="11" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMSYNCCOUT_SYNCCOUT">
<name>SYNCCOUT</name>
<desc>Current value of the Synchronization packet counter. The initial value is zero. The counter value increments every time a packet is issued by the FTM. When the counter reaches SYNCCOUNTTERM, a Synchronization packet is emitted.</desc>
<sw_param offset="0xf880b034" start="11" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMATID_ATID">
<name>ATID</name>
<desc>ATID value supplied to ATB bus. The upper three bits, ATID[6:4], are directly driven from this register. The lower four bits, ATID[3:0], are OR-ed with the FPGAATID[3:0] pins.</desc>
<sw_param offset="0xf880b400" start="6" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMITTRIGOUTACK_TRIGACK">
<name>TRIGACK</name>
<desc>Read the current value of the FTMTrigOutAck[3:0] inputs</desc>
<sw_param offset="0xf880bed0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMITTRIGGER_TRIGGER">
<name>TRIGGER</name>
<desc>When ITEN is 1, this field determines the FTMTrigOut[3:0]</desc>
<sw_param offset="0xf880bed4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMITTRACEDIS_TRACEDIS">
<name>TRACEDIS</name>
<desc>Always read as zero.</desc>
<sw_param offset="0xf880bed8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMITCYCCOUNT_FTMCYCCOUNT">
<name>FTMCYCCOUNT</name>
<desc>Read/write the value of the cycle counter</desc>
<sw_param offset="0xf880bedc" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMITATBDATA0_ATDATA31">
<name>ATDATA31</name>
<desc>When ITEN is 1, this value determines the ATDATAM[31] output</desc>
<sw_param offset="0xf880beec" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMITATBDATA0_ATDATA23">
<name>ATDATA23</name>
<desc>When ITEN is 1, this value determines the ATDATAM[23] output</desc>
<sw_param offset="0xf880beec" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMITATBDATA0_ATDATA15">
<name>ATDATA15</name>
<desc>When ITEN is 1, this value determines the ATDATAM[15] output</desc>
<sw_param offset="0xf880beec" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMITATBDATA0_ATDATA7">
<name>ATDATA7</name>
<desc>When ITEN is 1, this value determines the ATDATAM[7] output</desc>
<sw_param offset="0xf880beec" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMITATBDATA0_ATDATA0">
<name>ATDATA0</name>
<desc>When ITEN is 1, this value determines the ATDATAM[0] output</desc>
<sw_param offset="0xf880beec" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMITATBCTR2_AFVALID">
<name>AFVALID</name>
<desc>Read the current value of the AFVALIDM input</desc>
<sw_param offset="0xf880bef0" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMITATBCTR2_ATREADY">
<name>ATREADY</name>
<desc>Read the current value of the ATREADYM input</desc>
<sw_param offset="0xf880bef0" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMITATBCTR1_ATID_test">
<name>ATID_test</name>
<desc>When ITEN is 1, this value determines the ATID output</desc>
<sw_param offset="0xf880bef4" start="6" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMITATBCTR0_ATBYTES">
<name>ATBYTES</name>
<desc>When ITEN is 1, this value determines the ATBYTESM[1:0] output</desc>
<sw_param offset="0xf880bef8" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMITATBCTR0_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf880bef8" start="7" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMITATBCTR0_AFREADY">
<name>AFREADY</name>
<desc>When ITEN is 1, this value determines the AFREADY output</desc>
<sw_param offset="0xf880bef8" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMITATBCTR0_ATVALID">
<name>ATVALID</name>
<desc>When ITEN is 1, this value determines the ATVALID output</desc>
<sw_param offset="0xf880bef8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMITCR_ITEN">
<name>ITEN</name>
<desc>Integration Test Enable</desc>
<sw_param offset="0xf880bf00" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_CLAIMTAGSET_CLAIMTAGSETVAL">
<name>CLAIMTAGSETVAL</name>
<desc>Read: 1 = Claim tag implemented, 0 = not implemented
Write: 1 = Set claim tag bit, 0 = no effect</desc>
<sw_param offset="0xf880bfa0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_CLAIMTAGCLR_CLAIMTAGCLRVAL">
<name>CLAIMTAGCLRVAL</name>
<desc>Read: value of CLAIMTAGSETVAL
Write: 1 = Clear claim tag bit, 0 = no effect</desc>
<sw_param offset="0xf880bfa4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_LOCK_ACCESS_LOCKACCESS">
<name>LOCKACCESS</name>
<desc>A value of 0xC5ACCE55 allows write access to FTM, any other value blocks write access</desc>
<sw_param offset="0xf880bfb0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_LOCK_STATUS_n8BITACCESS">
<name>n8BITACCESS</name>
<desc>8-bit lock access is not used</desc>
<sw_param offset="0xf880bfb4" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_LOCK_STATUS_LOCKSTATUS">
<name>LOCKSTATUS</name>
<desc>1 = Access Locked, 0 = Access OK</desc>
<sw_param offset="0xf880bfb4" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_LOCK_STATUS_LOCKIMP">
<name>LOCKIMP</name>
<desc>1 = Lock exists if PADDRDBG31 is low, else 0</desc>
<sw_param offset="0xf880bfb4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMAUTHSTATUS_AUTH_SPNIDEN">
<name>AUTH_SPNIDEN</name>
<desc>Secure Non-Invasive Debug</desc>
<sw_param offset="0xf880bfb8" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMAUTHSTATUS_reserved">
<name>reserved</name>
<desc>Secure Invasive Debug</desc>
<sw_param offset="0xf880bfb8" start="5" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMAUTHSTATUS_AUTH_NIDEN">
<name>AUTH_NIDEN</name>
<desc>Non-Secure Non-Invasive Debug</desc>
<sw_param offset="0xf880bfb8" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMAUTHSTATUS_reserved_1">
<name>reserved_1</name>
<desc>Non-Secure Invasive Debug</desc>
<sw_param offset="0xf880bfb8" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMDEVID_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf880bfc8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMDEV_TYPE_SubType">
<name>SubType</name>
<desc>Sub Type: Associated with a Data Engine or Co-processor</desc>
<sw_param offset="0xf880bfcc" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMDEV_TYPE_MajorType">
<name>MajorType</name>
<desc>Major Type: Trace Source</desc>
<sw_param offset="0xf880bfcc" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMPERIPHID4_n4KBCount">
<name>n4KBCount</name>
<desc>4KB Count</desc>
<sw_param offset="0xf880bfd0" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMPERIPHID4_JEP106">
<name>JEP106</name>
<desc>JEP106 Continuation Code</desc>
<sw_param offset="0xf880bfd0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMPERIPHID5_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf880bfd4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMPERIPHID6_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf880bfd8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMPERIPHID7_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf880bfdc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMPERIPHID0_PARTNUMLOWER">
<name>PARTNUMLOWER</name>
<desc>Part Number Lower</desc>
<sw_param offset="0xf880bfe0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMPERIPHID1_JEP106">
<name>JEP106</name>
<desc>JEP106 identity bits [3:0]</desc>
<sw_param offset="0xf880bfe4" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMPERIPHID1_PARTNUMUPPER">
<name>PARTNUMUPPER</name>
<desc>Part Number Upper [11:8]</desc>
<sw_param offset="0xf880bfe4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMPERIPHID2_REVISION">
<name>REVISION</name>
<desc>Revision</desc>
<sw_param offset="0xf880bfe8" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMPERIPHID2_JEDEC">
<name>JEDEC</name>
<desc>JEDEC used</desc>
<sw_param offset="0xf880bfe8" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMPERIPHID2_JEP106">
<name>JEP106</name>
<desc>JEP106 Identity [6:4]</desc>
<sw_param offset="0xf880bfe8" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMPERIPHID3_RevAnd">
<name>RevAnd</name>
<desc>RevAnd</desc>
<sw_param offset="0xf880bfec" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMPERIPHID3_CustMod">
<name>CustMod</name>
<desc>Customer Modified</desc>
<sw_param offset="0xf880bfec" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMCOMPONID0_Preamble">
<name>Preamble</name>
<desc>Preamble</desc>
<sw_param offset="0xf880bff0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMCOMPONID1_CompClass">
<name>CompClass</name>
<desc>Component Class = Coresight Component</desc>
<sw_param offset="0xf880bff4" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMCOMPONID1_Preamble">
<name>Preamble</name>
<desc>Preamble</desc>
<sw_param offset="0xf880bff4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMCOMPONID2_Preamble">
<name>Preamble</name>
<desc>Preamble</desc>
<sw_param offset="0xf880bff8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_ftm_FTMCOMPONID3_Preamble">
<name>Preamble</name>
<desc>Preamble</desc>
<sw_param offset="0xf880bffc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_RDCHAN_CTRL_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800a000" start="31" end="4" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_RDCHAN_CTRL_QosHeadOfCmdQEn">
<name>QosHeadOfCmdQEn</name>
<desc>When set, allows the priority of a transaction at the head of the RdCmdQ to be promoted if higher priority transactions are backed up behind it. The entire RdCmdQ will therefore be promoted when the fabric RdQos signal is promoted.
When disabled, only the new read commands issued will receive the promotion.</desc>
<sw_param offset="0xf800a000" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_RDCHAN_CTRL_FabricOutCmdEn">
<name>FabricOutCmdEn</name>
<desc>Enable control of outstanding read commands from the fabric
0 - The maximum number of outstanding read commands is always taken from APB register field, rdIssueCap0
1 - The maximum outstanding number of
read commands is selected from the fabric input, axds_rdissuecap1_en, as follows:
Max Outstanding Read Commands =
axds_rdissuecap1_en ? rdIssueCap1 : rdIssueCap0</desc>
<sw_param offset="0xf800a000" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_RDCHAN_CTRL_FabricQosEn">
<name>FabricQosEn</name>
<desc>Enable control of qos from the fabric
0 - The qos bits are derived from APB register, AFI_RDQOS.staticQos
1 - The qos bits are dynamically driven from the fabric input, axds_arqos[3:0]</desc>
<sw_param offset="0xf800a000" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_RDCHAN_CTRL_n32BitEn">
<name>n32BitEn</name>
<desc>Configures the Read Channel as a 32-bit interface.
1 - 32-bit enabled
0 - 64-bit enabled</desc>
<sw_param offset="0xf800a000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_RDCHAN_ISSUINGCAP_reserved_1">
<name>reserved_1</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800a004" start="31" end="7" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_RDCHAN_ISSUINGCAP_rdIssueCap1">
<name>rdIssueCap1</name>
<desc>Max number of outstanding read commands (Read Issuing Capability) field 1:
3'b000: 1 command
3'b001: 2 commands' ' '3'b111: 8 commands</desc>
<sw_param offset="0xf800a004" start="6" end="4" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_RDCHAN_ISSUINGCAP_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800a004" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_RDCHAN_ISSUINGCAP_rdIssueCap0">
<name>rdIssueCap0</name>
<desc>Max number of outstanding read commands (Read Issuing Capability) field 0:
3'b000: 1 command
3'b001: 2 commands' ' '3'b111: 8 commands</desc>
<sw_param offset="0xf800a004" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_RDQOS_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800a008" start="31" end="4" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_RDQOS_staticQos">
<name>staticQos</name>
<desc>Sets the level of the Qos field to be used for the read channel
4'b0000: Lowest Priority' ' '4'b1111: Highest Priority</desc>
<sw_param offset="0xf800a008" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_RDDATAFIFO_LEVEL_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800a00c" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_RDDATAFIFO_LEVEL_FifoLevel">
<name>FifoLevel</name>
<desc>Returns the level measured in Dwords (64-bits) of the Read Data FIFO
8'h00 - 0 Entries
8'h01 - 1 Entry' ' '8'h8F - 128 Entries</desc>
<sw_param offset="0xf800a00c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_RDDEBUG_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800a010" start="31" end="5" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_RDDEBUG_OutRdCmds">
<name>OutRdCmds</name>
<desc>Returns the number of read commands in flight between the AFI and the SAM switch
4'h0: 0
4'h1: 1
etc</desc>
<sw_param offset="0xf800a010" start="4" end="1" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_RDDEBUG_RdDataFifoOverflow">
<name>RdDataFifoOverflow</name>
<desc>Bit is set if the RdDataFIFO overflows</desc>
<sw_param offset="0xf800a010" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_WRCHAN_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800a014" start="31" end="12" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_WRCHAN_CTRL_WrDataThreshold">
<name>WrDataThreshold</name>
<desc>Sets the threshold at which to send the write command. Note that this is measured in data beats, and is therefore dependent on the '32bitEn' field.
4'b0000: Send Write Command When 1 data beat is pushed into the Write Data FIFO
4'b0001: Send Write Command When 2 data beats are pushed into the Write Data FIFO' ' '4'b1111: Send Write Command When 16 data beats are pushed into the Write Data FIFO
Note: If this field is programmed to be less than the actual burst length of the write command, the 'Wlast' will take priority. For example, if 'WrDataThreshold' is set to 4'b1111 (indicates 16 beats), and a Wlast is received after 8 beats, the write command is sent.</desc>
<sw_param offset="0xf800a014" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_WRCHAN_CTRL_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800a014" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_WRCHAN_CTRL_WrCmdReleaseMode">
<name>WrCmdReleaseMode</name>
<desc>Mode of Write Command Release.
2'b00: Release Wr Command on 'Wlast' enqueue into Write Data FIFO
2'b01: Release Wr Command on a particular threshold being reached on the enqueue into Write Data FIFO. The 'WrDataThreshold' field is used to program the actual threshold.
2'b10: Release Wr Command immediately it is received.
2'b11: Reserved</desc>
<sw_param offset="0xf800a014" start="5" end="4" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_WRCHAN_CTRL_QosHeadOfCmdQEn">
<name>QosHeadOfCmdQEn</name>
<desc>When set, allows the priority of a transaction at the head of the WrCmdQ to be promoted if higher priority transactions are backed up behind it. The entire WrCmdQ will therefore be 'promoted' when the fabric 'WrQos' signal is promoted.
When disabled, only the new write commands issued will receive the 'promotion'.</desc>
<sw_param offset="0xf800a014" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_WRCHAN_CTRL_FabricOutCmdEn">
<name>FabricOutCmdEn</name>
<desc>Enable control of outstanding write commands from the fabric
0 - The maximum number of outstanding write commands is always taken from APB register field, 'wrIssueCap0'1 - The maximum outstanding number of
write commands is selected from the fabric input, 'axds_wrissuecap1_en', as follows:
Max Outstanding Write Commands =
axds_wrissuecap1_en ? wrIssueCap1 : wrIssueCap0</desc>
<sw_param offset="0xf800a014" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_WRCHAN_CTRL_FabricQosEn">
<name>FabricQosEn</name>
<desc>Enable control of qos from the fabric
0 - The qos bits are derived from APB register, 'AFI_WRQOS.staticQos'1 - The qos bits are dynamically driven from the fabric input, 'axds_awqos[3:0]'</desc>
<sw_param offset="0xf800a014" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_WRCHAN_CTRL_n32BitEn">
<name>n32BitEn</name>
<desc>Configures the Write Channel as a 32-bit interface.
1 - 32-bit enabled
0 - 64-bit enabled</desc>
<sw_param offset="0xf800a014" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_WRCHAN_ISSUINGCAP_reserved_1">
<name>reserved_1</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800a018" start="31" end="7" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_WRCHAN_ISSUINGCAP_wrIssueCap1">
<name>wrIssueCap1</name>
<desc>Max number of outstanding write commands (Write Issuing Capability) field 1:
3'b000: 1 command
3'b001: 2 commands' ' '3'b111: 8 commands</desc>
<sw_param offset="0xf800a018" start="6" end="4" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_WRCHAN_ISSUINGCAP_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800a018" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_WRCHAN_ISSUINGCAP_wrIssueCap0">
<name>wrIssueCap0</name>
<desc>Max number of outstanding write commands (Write Issuing Capability) field 0:
3'b000: 1 command
3'b001: 2 commands' ' '3'b111: 8 commands</desc>
<sw_param offset="0xf800a018" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_WRQOS_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800a01c" start="31" end="4" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_WRQOS_staticQos">
<name>staticQos</name>
<desc>Sets the level of the Qos field to be used for the write channel
4'b0000: Lowest Priority' ' '4'b1111: Highest Priority</desc>
<sw_param offset="0xf800a01c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_WRDATAFIFO_LEVEL_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800a020" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_WRDATAFIFO_LEVEL_FifoLevel">
<name>FifoLevel</name>
<desc>Returns the level measured in Dwords (64-bits) of the Write Data FIFO
8'h00 - 0 Entries
8'h01 - 1 Entry' ' '8'h8F - 128 Entries</desc>
<sw_param offset="0xf800a020" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_WRDEBUG_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800a024" start="31" end="5" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_WRDEBUG_OutWrCmds">
<name>OutWrCmds</name>
<desc>Returns the number of write commands in flight between the AFI and the SAM switch
4'h0: 0
4'h1: 1
etc</desc>
<sw_param offset="0xf800a024" start="4" end="1" />
</parameter>
<parameter uniqueid="ps7_afi2_AFI_WRDEBUG_WrDataFifoOverflow">
<name>WrDataFifoOverflow</name>
<desc>Bit is set if the WrDataFIFO overflows</desc>
<sw_param offset="0xf800a024" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_RDCHAN_CTRL_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf8009000" start="31" end="4" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_RDCHAN_CTRL_QosHeadOfCmdQEn">
<name>QosHeadOfCmdQEn</name>
<desc>When set, allows the priority of a transaction at the head of the RdCmdQ to be promoted if higher priority transactions are backed up behind it. The entire RdCmdQ will therefore be promoted when the fabric RdQos signal is promoted.
When disabled, only the new read commands issued will receive the promotion.</desc>
<sw_param offset="0xf8009000" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_RDCHAN_CTRL_FabricOutCmdEn">
<name>FabricOutCmdEn</name>
<desc>Enable control of outstanding read commands from the fabric
0 - The maximum number of outstanding read commands is always taken from APB register field, rdIssueCap0
1 - The maximum outstanding number of
read commands is selected from the fabric input, axds_rdissuecap1_en, as follows:
Max Outstanding Read Commands =
axds_rdissuecap1_en ? rdIssueCap1 : rdIssueCap0</desc>
<sw_param offset="0xf8009000" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_RDCHAN_CTRL_FabricQosEn">
<name>FabricQosEn</name>
<desc>Enable control of qos from the fabric
0 - The qos bits are derived from APB register, AFI_RDQOS.staticQos
1 - The qos bits are dynamically driven from the fabric input, axds_arqos[3:0]</desc>
<sw_param offset="0xf8009000" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_RDCHAN_CTRL_n32BitEn">
<name>n32BitEn</name>
<desc>Configures the Read Channel as a 32-bit interface.
1 - 32-bit enabled
0 - 64-bit enabled</desc>
<sw_param offset="0xf8009000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_RDCHAN_ISSUINGCAP_reserved_1">
<name>reserved_1</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf8009004" start="31" end="7" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_RDCHAN_ISSUINGCAP_rdIssueCap1">
<name>rdIssueCap1</name>
<desc>Max number of outstanding read commands (Read Issuing Capability) field 1:
3'b000: 1 command
3'b001: 2 commands' ' '3'b111: 8 commands</desc>
<sw_param offset="0xf8009004" start="6" end="4" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_RDCHAN_ISSUINGCAP_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf8009004" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_RDCHAN_ISSUINGCAP_rdIssueCap0">
<name>rdIssueCap0</name>
<desc>Max number of outstanding read commands (Read Issuing Capability) field 0:
3'b000: 1 command
3'b001: 2 commands' ' '3'b111: 8 commands</desc>
<sw_param offset="0xf8009004" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_RDQOS_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf8009008" start="31" end="4" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_RDQOS_staticQos">
<name>staticQos</name>
<desc>Sets the level of the Qos field to be used for the read channel
4'b0000: Lowest Priority' ' '4'b1111: Highest Priority</desc>
<sw_param offset="0xf8009008" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_RDDATAFIFO_LEVEL_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800900c" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_RDDATAFIFO_LEVEL_FifoLevel">
<name>FifoLevel</name>
<desc>Returns the level measured in Dwords (64-bits) of the Read Data FIFO
8'h00 - 0 Entries
8'h01 - 1 Entry' ' '8'h8F - 128 Entries</desc>
<sw_param offset="0xf800900c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_RDDEBUG_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf8009010" start="31" end="5" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_RDDEBUG_OutRdCmds">
<name>OutRdCmds</name>
<desc>Returns the number of read commands in flight between the AFI and the SAM switch
4'h0: 0
4'h1: 1
etc</desc>
<sw_param offset="0xf8009010" start="4" end="1" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_RDDEBUG_RdDataFifoOverflow">
<name>RdDataFifoOverflow</name>
<desc>Bit is set if the RdDataFIFO overflows</desc>
<sw_param offset="0xf8009010" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_WRCHAN_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf8009014" start="31" end="12" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_WRCHAN_CTRL_WrDataThreshold">
<name>WrDataThreshold</name>
<desc>Sets the threshold at which to send the write command. Note that this is measured in data beats, and is therefore dependent on the '32bitEn' field.
4'b0000: Send Write Command When 1 data beat is pushed into the Write Data FIFO
4'b0001: Send Write Command When 2 data beats are pushed into the Write Data FIFO' ' '4'b1111: Send Write Command When 16 data beats are pushed into the Write Data FIFO
Note: If this field is programmed to be less than the actual burst length of the write command, the 'Wlast' will take priority. For example, if 'WrDataThreshold' is set to 4'b1111 (indicates 16 beats), and a Wlast is received after 8 beats, the write command is sent.</desc>
<sw_param offset="0xf8009014" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_WRCHAN_CTRL_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf8009014" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_WRCHAN_CTRL_WrCmdReleaseMode">
<name>WrCmdReleaseMode</name>
<desc>Mode of Write Command Release.
2'b00: Release Wr Command on 'Wlast' enqueue into Write Data FIFO
2'b01: Release Wr Command on a particular threshold being reached on the enqueue into Write Data FIFO. The 'WrDataThreshold' field is used to program the actual threshold.
2'b10: Release Wr Command immediately it is received.
2'b11: Reserved</desc>
<sw_param offset="0xf8009014" start="5" end="4" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_WRCHAN_CTRL_QosHeadOfCmdQEn">
<name>QosHeadOfCmdQEn</name>
<desc>When set, allows the priority of a transaction at the head of the WrCmdQ to be promoted if higher priority transactions are backed up behind it. The entire WrCmdQ will therefore be 'promoted' when the fabric 'WrQos' signal is promoted.
When disabled, only the new write commands issued will receive the 'promotion'.</desc>
<sw_param offset="0xf8009014" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_WRCHAN_CTRL_FabricOutCmdEn">
<name>FabricOutCmdEn</name>
<desc>Enable control of outstanding write commands from the fabric
0 - The maximum number of outstanding write commands is always taken from APB register field, 'wrIssueCap0'1 - The maximum outstanding number of
write commands is selected from the fabric input, 'axds_wrissuecap1_en', as follows:
Max Outstanding Write Commands =
axds_wrissuecap1_en ? wrIssueCap1 : wrIssueCap0</desc>
<sw_param offset="0xf8009014" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_WRCHAN_CTRL_FabricQosEn">
<name>FabricQosEn</name>
<desc>Enable control of qos from the fabric
0 - The qos bits are derived from APB register, 'AFI_WRQOS.staticQos'1 - The qos bits are dynamically driven from the fabric input, 'axds_awqos[3:0]'</desc>
<sw_param offset="0xf8009014" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_WRCHAN_CTRL_n32BitEn">
<name>n32BitEn</name>
<desc>Configures the Write Channel as a 32-bit interface.
1 - 32-bit enabled
0 - 64-bit enabled</desc>
<sw_param offset="0xf8009014" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_WRCHAN_ISSUINGCAP_reserved_1">
<name>reserved_1</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf8009018" start="31" end="7" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_WRCHAN_ISSUINGCAP_wrIssueCap1">
<name>wrIssueCap1</name>
<desc>Max number of outstanding write commands (Write Issuing Capability) field 1:
3'b000: 1 command
3'b001: 2 commands' ' '3'b111: 8 commands</desc>
<sw_param offset="0xf8009018" start="6" end="4" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_WRCHAN_ISSUINGCAP_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf8009018" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_WRCHAN_ISSUINGCAP_wrIssueCap0">
<name>wrIssueCap0</name>
<desc>Max number of outstanding write commands (Write Issuing Capability) field 0:
3'b000: 1 command
3'b001: 2 commands' ' '3'b111: 8 commands</desc>
<sw_param offset="0xf8009018" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_WRQOS_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800901c" start="31" end="4" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_WRQOS_staticQos">
<name>staticQos</name>
<desc>Sets the level of the Qos field to be used for the write channel
4'b0000: Lowest Priority' ' '4'b1111: Highest Priority</desc>
<sw_param offset="0xf800901c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_WRDATAFIFO_LEVEL_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf8009020" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_WRDATAFIFO_LEVEL_FifoLevel">
<name>FifoLevel</name>
<desc>Returns the level measured in Dwords (64-bits) of the Write Data FIFO
8'h00 - 0 Entries
8'h01 - 1 Entry' ' '8'h8F - 128 Entries</desc>
<sw_param offset="0xf8009020" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_WRDEBUG_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf8009024" start="31" end="5" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_WRDEBUG_OutWrCmds">
<name>OutWrCmds</name>
<desc>Returns the number of write commands in flight between the AFI and the SAM switch
4'h0: 0
4'h1: 1
etc</desc>
<sw_param offset="0xf8009024" start="4" end="1" />
</parameter>
<parameter uniqueid="ps7_afi1_AFI_WRDEBUG_WrDataFifoOverflow">
<name>WrDataFifoOverflow</name>
<desc>Bit is set if the WrDataFIFO overflows</desc>
<sw_param offset="0xf8009024" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_RDCHAN_CTRL_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800b000" start="31" end="4" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_RDCHAN_CTRL_QosHeadOfCmdQEn">
<name>QosHeadOfCmdQEn</name>
<desc>When set, allows the priority of a transaction at the head of the RdCmdQ to be promoted if higher priority transactions are backed up behind it. The entire RdCmdQ will therefore be promoted when the fabric RdQos signal is promoted.
When disabled, only the new read commands issued will receive the promotion.</desc>
<sw_param offset="0xf800b000" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_RDCHAN_CTRL_FabricOutCmdEn">
<name>FabricOutCmdEn</name>
<desc>Enable control of outstanding read commands from the fabric
0 - The maximum number of outstanding read commands is always taken from APB register field, rdIssueCap0
1 - The maximum outstanding number of
read commands is selected from the fabric input, axds_rdissuecap1_en, as follows:
Max Outstanding Read Commands =
axds_rdissuecap1_en ? rdIssueCap1 : rdIssueCap0</desc>
<sw_param offset="0xf800b000" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_RDCHAN_CTRL_FabricQosEn">
<name>FabricQosEn</name>
<desc>Enable control of qos from the fabric
0 - The qos bits are derived from APB register, AFI_RDQOS.staticQos
1 - The qos bits are dynamically driven from the fabric input, axds_arqos[3:0]</desc>
<sw_param offset="0xf800b000" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_RDCHAN_CTRL_n32BitEn">
<name>n32BitEn</name>
<desc>Configures the Read Channel as a 32-bit interface.
1 - 32-bit enabled
0 - 64-bit enabled</desc>
<sw_param offset="0xf800b000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_RDCHAN_ISSUINGCAP_reserved_1">
<name>reserved_1</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800b004" start="31" end="7" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_RDCHAN_ISSUINGCAP_rdIssueCap1">
<name>rdIssueCap1</name>
<desc>Max number of outstanding read commands (Read Issuing Capability) field 1:
3'b000: 1 command
3'b001: 2 commands' ' '3'b111: 8 commands</desc>
<sw_param offset="0xf800b004" start="6" end="4" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_RDCHAN_ISSUINGCAP_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800b004" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_RDCHAN_ISSUINGCAP_rdIssueCap0">
<name>rdIssueCap0</name>
<desc>Max number of outstanding read commands (Read Issuing Capability) field 0:
3'b000: 1 command
3'b001: 2 commands' ' '3'b111: 8 commands</desc>
<sw_param offset="0xf800b004" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_RDQOS_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800b008" start="31" end="4" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_RDQOS_staticQos">
<name>staticQos</name>
<desc>Sets the level of the Qos field to be used for the read channel
4'b0000: Lowest Priority' ' '4'b1111: Highest Priority</desc>
<sw_param offset="0xf800b008" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_RDDATAFIFO_LEVEL_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800b00c" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_RDDATAFIFO_LEVEL_FifoLevel">
<name>FifoLevel</name>
<desc>Returns the level measured in Dwords (64-bits) of the Read Data FIFO
8'h00 - 0 Entries
8'h01 - 1 Entry' ' '8'h8F - 128 Entries</desc>
<sw_param offset="0xf800b00c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_RDDEBUG_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800b010" start="31" end="5" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_RDDEBUG_OutRdCmds">
<name>OutRdCmds</name>
<desc>Returns the number of read commands in flight between the AFI and the SAM switch
4'h0: 0
4'h1: 1
etc</desc>
<sw_param offset="0xf800b010" start="4" end="1" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_RDDEBUG_RdDataFifoOverflow">
<name>RdDataFifoOverflow</name>
<desc>Bit is set if the RdDataFIFO overflows</desc>
<sw_param offset="0xf800b010" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_WRCHAN_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800b014" start="31" end="12" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_WRCHAN_CTRL_WrDataThreshold">
<name>WrDataThreshold</name>
<desc>Sets the threshold at which to send the write command. Note that this is measured in data beats, and is therefore dependent on the '32bitEn' field.
4'b0000: Send Write Command When 1 data beat is pushed into the Write Data FIFO
4'b0001: Send Write Command When 2 data beats are pushed into the Write Data FIFO' ' '4'b1111: Send Write Command When 16 data beats are pushed into the Write Data FIFO
Note: If this field is programmed to be less than the actual burst length of the write command, the 'Wlast' will take priority. For example, if 'WrDataThreshold' is set to 4'b1111 (indicates 16 beats), and a Wlast is received after 8 beats, the write command is sent.</desc>
<sw_param offset="0xf800b014" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_WRCHAN_CTRL_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800b014" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_WRCHAN_CTRL_WrCmdReleaseMode">
<name>WrCmdReleaseMode</name>
<desc>Mode of Write Command Release.
2'b00: Release Wr Command on 'Wlast' enqueue into Write Data FIFO
2'b01: Release Wr Command on a particular threshold being reached on the enqueue into Write Data FIFO. The 'WrDataThreshold' field is used to program the actual threshold.
2'b10: Release Wr Command immediately it is received.
2'b11: Reserved</desc>
<sw_param offset="0xf800b014" start="5" end="4" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_WRCHAN_CTRL_QosHeadOfCmdQEn">
<name>QosHeadOfCmdQEn</name>
<desc>When set, allows the priority of a transaction at the head of the WrCmdQ to be promoted if higher priority transactions are backed up behind it. The entire WrCmdQ will therefore be 'promoted' when the fabric 'WrQos' signal is promoted.
When disabled, only the new write commands issued will receive the 'promotion'.</desc>
<sw_param offset="0xf800b014" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_WRCHAN_CTRL_FabricOutCmdEn">
<name>FabricOutCmdEn</name>
<desc>Enable control of outstanding write commands from the fabric
0 - The maximum number of outstanding write commands is always taken from APB register field, 'wrIssueCap0'1 - The maximum outstanding number of
write commands is selected from the fabric input, 'axds_wrissuecap1_en', as follows:
Max Outstanding Write Commands =
axds_wrissuecap1_en ? wrIssueCap1 : wrIssueCap0</desc>
<sw_param offset="0xf800b014" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_WRCHAN_CTRL_FabricQosEn">
<name>FabricQosEn</name>
<desc>Enable control of qos from the fabric
0 - The qos bits are derived from APB register, 'AFI_WRQOS.staticQos'1 - The qos bits are dynamically driven from the fabric input, 'axds_awqos[3:0]'</desc>
<sw_param offset="0xf800b014" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_WRCHAN_CTRL_n32BitEn">
<name>n32BitEn</name>
<desc>Configures the Write Channel as a 32-bit interface.
1 - 32-bit enabled
0 - 64-bit enabled</desc>
<sw_param offset="0xf800b014" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_WRCHAN_ISSUINGCAP_reserved_1">
<name>reserved_1</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800b018" start="31" end="7" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_WRCHAN_ISSUINGCAP_wrIssueCap1">
<name>wrIssueCap1</name>
<desc>Max number of outstanding write commands (Write Issuing Capability) field 1:
3'b000: 1 command
3'b001: 2 commands' ' '3'b111: 8 commands</desc>
<sw_param offset="0xf800b018" start="6" end="4" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_WRCHAN_ISSUINGCAP_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800b018" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_WRCHAN_ISSUINGCAP_wrIssueCap0">
<name>wrIssueCap0</name>
<desc>Max number of outstanding write commands (Write Issuing Capability) field 0:
3'b000: 1 command
3'b001: 2 commands' ' '3'b111: 8 commands</desc>
<sw_param offset="0xf800b018" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_WRQOS_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800b01c" start="31" end="4" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_WRQOS_staticQos">
<name>staticQos</name>
<desc>Sets the level of the Qos field to be used for the write channel
4'b0000: Lowest Priority' ' '4'b1111: Highest Priority</desc>
<sw_param offset="0xf800b01c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_WRDATAFIFO_LEVEL_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800b020" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_WRDATAFIFO_LEVEL_FifoLevel">
<name>FifoLevel</name>
<desc>Returns the level measured in Dwords (64-bits) of the Write Data FIFO
8'h00 - 0 Entries
8'h01 - 1 Entry' ' '8'h8F - 128 Entries</desc>
<sw_param offset="0xf800b020" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_WRDEBUG_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800b024" start="31" end="5" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_WRDEBUG_OutWrCmds">
<name>OutWrCmds</name>
<desc>Returns the number of write commands in flight between the AFI and the SAM switch
4'h0: 0
4'h1: 1
etc</desc>
<sw_param offset="0xf800b024" start="4" end="1" />
</parameter>
<parameter uniqueid="ps7_afi3_AFI_WRDEBUG_WrDataFifoOverflow">
<name>WrDataFifoOverflow</name>
<desc>Bit is set if the WrDataFIFO overflows</desc>
<sw_param offset="0xf800b024" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_RDCHAN_CTRL_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf8008000" start="31" end="4" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_RDCHAN_CTRL_QosHeadOfCmdQEn">
<name>QosHeadOfCmdQEn</name>
<desc>When set, allows the priority of a transaction at the head of the RdCmdQ to be promoted if higher priority transactions are backed up behind it. The entire RdCmdQ will therefore be promoted when the fabric RdQos signal is promoted.
When disabled, only the new read commands issued will receive the promotion.</desc>
<sw_param offset="0xf8008000" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_RDCHAN_CTRL_FabricOutCmdEn">
<name>FabricOutCmdEn</name>
<desc>Enable control of outstanding read commands from the fabric
0 - The maximum number of outstanding read commands is always taken from APB register field, rdIssueCap0
1 - The maximum outstanding number of
read commands is selected from the fabric input, axds_rdissuecap1_en, as follows:
Max Outstanding Read Commands =
axds_rdissuecap1_en ? rdIssueCap1 : rdIssueCap0</desc>
<sw_param offset="0xf8008000" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_RDCHAN_CTRL_FabricQosEn">
<name>FabricQosEn</name>
<desc>Enable control of qos from the fabric
0 - The qos bits are derived from APB register, AFI_RDQOS.staticQos
1 - The qos bits are dynamically driven from the fabric input, axds_arqos[3:0]</desc>
<sw_param offset="0xf8008000" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_RDCHAN_CTRL_n32BitEn">
<name>n32BitEn</name>
<desc>Configures the Read Channel as a 32-bit interface.
1 - 32-bit enabled
0 - 64-bit enabled</desc>
<sw_param offset="0xf8008000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_RDCHAN_ISSUINGCAP_reserved_1">
<name>reserved_1</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf8008004" start="31" end="7" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_RDCHAN_ISSUINGCAP_rdIssueCap1">
<name>rdIssueCap1</name>
<desc>Max number of outstanding read commands (Read Issuing Capability) field 1:
3'b000: 1 command
3'b001: 2 commands' ' '3'b111: 8 commands</desc>
<sw_param offset="0xf8008004" start="6" end="4" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_RDCHAN_ISSUINGCAP_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf8008004" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_RDCHAN_ISSUINGCAP_rdIssueCap0">
<name>rdIssueCap0</name>
<desc>Max number of outstanding read commands (Read Issuing Capability) field 0:
3'b000: 1 command
3'b001: 2 commands' ' '3'b111: 8 commands</desc>
<sw_param offset="0xf8008004" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_RDQOS_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf8008008" start="31" end="4" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_RDQOS_staticQos">
<name>staticQos</name>
<desc>Sets the level of the Qos field to be used for the read channel
4'b0000: Lowest Priority' ' '4'b1111: Highest Priority</desc>
<sw_param offset="0xf8008008" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_RDDATAFIFO_LEVEL_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800800c" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_RDDATAFIFO_LEVEL_FifoLevel">
<name>FifoLevel</name>
<desc>Returns the level measured in Dwords (64-bits) of the Read Data FIFO
8'h00 - 0 Entries
8'h01 - 1 Entry' ' '8'h8F - 128 Entries</desc>
<sw_param offset="0xf800800c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_RDDEBUG_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf8008010" start="31" end="5" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_RDDEBUG_OutRdCmds">
<name>OutRdCmds</name>
<desc>Returns the number of read commands in flight between the AFI and the SAM switch
4'h0: 0
4'h1: 1
etc</desc>
<sw_param offset="0xf8008010" start="4" end="1" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_RDDEBUG_RdDataFifoOverflow">
<name>RdDataFifoOverflow</name>
<desc>Bit is set if the RdDataFIFO overflows</desc>
<sw_param offset="0xf8008010" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_WRCHAN_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf8008014" start="31" end="12" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_WRCHAN_CTRL_WrDataThreshold">
<name>WrDataThreshold</name>
<desc>Sets the threshold at which to send the write command. Note that this is measured in data beats, and is therefore dependent on the '32bitEn' field.
4'b0000: Send Write Command When 1 data beat is pushed into the Write Data FIFO
4'b0001: Send Write Command When 2 data beats are pushed into the Write Data FIFO' ' '4'b1111: Send Write Command When 16 data beats are pushed into the Write Data FIFO
Note: If this field is programmed to be less than the actual burst length of the write command, the 'Wlast' will take priority. For example, if 'WrDataThreshold' is set to 4'b1111 (indicates 16 beats), and a Wlast is received after 8 beats, the write command is sent.</desc>
<sw_param offset="0xf8008014" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_WRCHAN_CTRL_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf8008014" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_WRCHAN_CTRL_WrCmdReleaseMode">
<name>WrCmdReleaseMode</name>
<desc>Mode of Write Command Release.
2'b00: Release Wr Command on 'Wlast' enqueue into Write Data FIFO
2'b01: Release Wr Command on a particular threshold being reached on the enqueue into Write Data FIFO. The 'WrDataThreshold' field is used to program the actual threshold.
2'b10: Release Wr Command immediately it is received.
2'b11: Reserved</desc>
<sw_param offset="0xf8008014" start="5" end="4" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_WRCHAN_CTRL_QosHeadOfCmdQEn">
<name>QosHeadOfCmdQEn</name>
<desc>When set, allows the priority of a transaction at the head of the WrCmdQ to be promoted if higher priority transactions are backed up behind it. The entire WrCmdQ will therefore be 'promoted' when the fabric 'WrQos' signal is promoted.
When disabled, only the new write commands issued will receive the 'promotion'.</desc>
<sw_param offset="0xf8008014" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_WRCHAN_CTRL_FabricOutCmdEn">
<name>FabricOutCmdEn</name>
<desc>Enable control of outstanding write commands from the fabric
0 - The maximum number of outstanding write commands is always taken from APB register field, 'wrIssueCap0'1 - The maximum outstanding number of
write commands is selected from the fabric input, 'axds_wrissuecap1_en', as follows:
Max Outstanding Write Commands =
axds_wrissuecap1_en ? wrIssueCap1 : wrIssueCap0</desc>
<sw_param offset="0xf8008014" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_WRCHAN_CTRL_FabricQosEn">
<name>FabricQosEn</name>
<desc>Enable control of qos from the fabric
0 - The qos bits are derived from APB register, 'AFI_WRQOS.staticQos'1 - The qos bits are dynamically driven from the fabric input, 'axds_awqos[3:0]'</desc>
<sw_param offset="0xf8008014" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_WRCHAN_CTRL_n32BitEn">
<name>n32BitEn</name>
<desc>Configures the Write Channel as a 32-bit interface.
1 - 32-bit enabled
0 - 64-bit enabled</desc>
<sw_param offset="0xf8008014" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_WRCHAN_ISSUINGCAP_reserved_1">
<name>reserved_1</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf8008018" start="31" end="7" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_WRCHAN_ISSUINGCAP_wrIssueCap1">
<name>wrIssueCap1</name>
<desc>Max number of outstanding write commands (Write Issuing Capability) field 1:
3'b000: 1 command
3'b001: 2 commands' ' '3'b111: 8 commands</desc>
<sw_param offset="0xf8008018" start="6" end="4" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_WRCHAN_ISSUINGCAP_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf8008018" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_WRCHAN_ISSUINGCAP_wrIssueCap0">
<name>wrIssueCap0</name>
<desc>Max number of outstanding write commands (Write Issuing Capability) field 0:
3'b000: 1 command
3'b001: 2 commands' ' '3'b111: 8 commands</desc>
<sw_param offset="0xf8008018" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_WRQOS_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800801c" start="31" end="4" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_WRQOS_staticQos">
<name>staticQos</name>
<desc>Sets the level of the Qos field to be used for the write channel
4'b0000: Lowest Priority' ' '4'b1111: Highest Priority</desc>
<sw_param offset="0xf800801c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_WRDATAFIFO_LEVEL_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf8008020" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_WRDATAFIFO_LEVEL_FifoLevel">
<name>FifoLevel</name>
<desc>Returns the level measured in Dwords (64-bits) of the Write Data FIFO
8'h00 - 0 Entries
8'h01 - 1 Entry' ' '8'h8F - 128 Entries</desc>
<sw_param offset="0xf8008020" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_WRDEBUG_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf8008024" start="31" end="5" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_WRDEBUG_OutWrCmds">
<name>OutWrCmds</name>
<desc>Returns the number of write commands in flight between the AFI and the SAM switch
4'h0: 0
4'h1: 1
etc</desc>
<sw_param offset="0xf8008024" start="4" end="1" />
</parameter>
<parameter uniqueid="ps7_afi0_AFI_WRDEBUG_WrDataFifoOverflow">
<name>WrDataFifoOverflow</name>
<desc>Bit is set if the WrDataFIFO overflows</desc>
<sw_param offset="0xf8008024" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_ID_CIVERSION">
<name>CIVERSION</name>
<desc>Identifies the CI version</desc>
<sw_param offset="0xe0002000" start="31" end="29" />
</parameter>
<parameter uniqueid="ps7_usb0_ID_VERSION">
<name>VERSION</name>
<desc>Identifies the version of the core</desc>
<sw_param offset="0xe0002000" start="28" end="25" />
</parameter>
<parameter uniqueid="ps7_usb0_ID_REVISION">
<name>REVISION</name>
<desc>Revision number of the core</desc>
<sw_param offset="0xe0002000" start="24" end="21" />
</parameter>
<parameter uniqueid="ps7_usb0_ID_TAG">
<name>TAG</name>
<desc>Identifies the tag of the core ; Current 2.20a version</desc>
<sw_param offset="0xe0002000" start="20" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_ID_reserved">
<name>reserved</name>
<desc>RESERVED. Writes are ignored</desc>
<sw_param offset="0xe0002000" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_usb0_ID_NID">
<name>NID</name>
<desc>NID Complement of ID; Ones complement version of ID</desc>
<sw_param offset="0xe0002000" start="13" end="8" />
</parameter>
<parameter uniqueid="ps7_usb0_ID_reserved_1">
<name>reserved_1</name>
<desc>RESERVED. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xe0002000" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_usb0_ID_ID">
<name>ID</name>
<desc>ID Configuration number ; This number indicates the type of the USB-HS 2.0 core.</desc>
<sw_param offset="0xe0002000" start="5" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_HWGENERAL_SM">
<name>SM</name>
<desc>VUSB_HS_PHY_SERIAL - This constant selects that the serial engine is used or not.
0 - No Serial Engine- Always use parallel signalling</desc>
<sw_param offset="0xe0002004" start="11" end="10" />
</parameter>
<parameter uniqueid="ps7_usb0_HWGENERAL_PHYM">
<name>PHYM</name>
<desc>VUSB_HS_PHY_TYPE
- PHY interface type.
2 = ULPI</desc>
<sw_param offset="0xe0002004" start="9" end="6" />
</parameter>
<parameter uniqueid="ps7_usb0_HWGENERAL_PHYW">
<name>PHYW</name>
<desc>VUSB_HS_PHY16_8 - This constant selects which phy is being used.
0 = 8 bit wide data bus [60MHz clock from the transciever]</desc>
<sw_param offset="0xe0002004" start="5" end="4" />
</parameter>
<parameter uniqueid="ps7_usb0_HWGENERAL_BWT">
<name>BWT</name>
<desc>RESERVED.</desc>
<sw_param offset="0xe0002004" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_usb0_HWGENERAL_CLKC">
<name>CLKC</name>
<desc>VUSB_HS_CLOCK_CONFIGURATION - constant determines the clocking used in the core.
1 = xcvr_clk_0 &lt; pe_clk = clk</desc>
<sw_param offset="0xe0002004" start="2" end="1" />
</parameter>
<parameter uniqueid="ps7_usb0_HWGENERAL_RT">
<name>RT</name>
<desc>VUSB_HS_RESET_TYPE - Reset Type.
1 = Use Asynchronous Resets</desc>
<sw_param offset="0xe0002004" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_HWHOST_TTPER">
<name>TTPER</name>
<desc>VUSB_HS_TT_PERIODIC_CONTEXTS</desc>
<sw_param offset="0xe0002008" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_usb0_HWHOST_TTASY">
<name>TTASY</name>
<desc>VUSB_HS_TT_ASYNC_CONTEXTS</desc>
<sw_param offset="0xe0002008" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_HWHOST_a">
<name>a</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0002008" start="15" end="4" />
</parameter>
<parameter uniqueid="ps7_usb0_HWHOST_NPORT">
<name>NPORT</name>
<desc>VUSB_HS_NUM_PORT-1.
1- The VUSB_HS_NUM_PORT constant specifies the number of downstream ports by host port</desc>
<sw_param offset="0xe0002008" start="3" end="1" />
</parameter>
<parameter uniqueid="ps7_usb0_HWHOST_HC">
<name>HC</name>
<desc>VUSB_HS_HOST</desc>
<sw_param offset="0xe0002008" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_HWDEVICE_DEVEP">
<name>DEVEP</name>
<desc>VUSB_HS_DEV_EP - Number of endpoints.
12 = VUSB_HS_DEV_EP constant represents the 12 number of endpoints</desc>
<sw_param offset="0xe000200c" start="5" end="1" />
</parameter>
<parameter uniqueid="ps7_usb0_HWDEVICE_DC">
<name>DC</name>
<desc>Device capable</desc>
<sw_param offset="0xe000200c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_HWTXBUF_reserved_1">
<name>reserved_1</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0002010" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_usb0_HWTXBUF_reserved">
<name>reserved</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0002010" start="30" end="24" />
</parameter>
<parameter uniqueid="ps7_usb0_HWTXBUF_TXCHANADD">
<name>TXCHANADD</name>
<desc>VUSB_HS_TX_CHAN_ADD - Address bits for each Endpoint; 64 words buffer for each end point.
6 - To address 64 depth TX buffer for each end point</desc>
<sw_param offset="0xe0002010" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_HWTXBUF_TXADD">
<name>TXADD</name>
<desc>VUSB_HS_TX_ADD ; 768 Depth TX buffer.
10- Address of the depoth of TX buffer</desc>
<sw_param offset="0xe0002010" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb0_HWTXBUF_TXBURST">
<name>TXBURST</name>
<desc>VUSB_HS_TX_BURST. Burst size for Memory To TX Buffer Transfers</desc>
<sw_param offset="0xe0002010" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_HWRXBUF_a">
<name>a</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0002014" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_usb0_HWRXBUF_RXADD">
<name>RXADD</name>
<desc>VUSB_HS_RX_ADD ; 768 Depth TX buffer.
10- Address of the depoth of TX buffer</desc>
<sw_param offset="0xe0002014" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb0_HWRXBUF_RXBURST">
<name>RXBURST</name>
<desc>VUSB_HS_RX_BURST.
16 = Burst size of 16 for Memory To TX Buffer Transfers</desc>
<sw_param offset="0xe0002014" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_GPTIMER0LD_GPTLD">
<name>GPTLD</name>
<desc>General Purpose Timer Load Value register.
This field is the value to be loaded into the GPTCNT countdown timer on a reset action. The value in this register represents the time in microseconds minus 1 for the timer duration.
Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7.
Note: Max value is 0xFFFFFF or 16.777215 seconds</desc>
<sw_param offset="0xe0002080" start="23" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_GPTIMER0CTRL_GPTRUN">
<name>GPTRUN</name>
<desc>General Purpose Timer Run. This bit enables the general-purpose timer to run. Setting or clearing this bit will not have an effect on the GPTCNT counter value.</desc>
<sw_param offset="0xe0002084" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_usb0_GPTIMER0CTRL_GPTRST">
<name>GPTRST</name>
<desc>General Purpose Timer Reset. Writing a one to this bit will reload the GPTCNT with the value in GPTLD.</desc>
<sw_param offset="0xe0002084" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_usb0_GPTIMER0CTRL_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xe0002084" start="29" end="25" />
</parameter>
<parameter uniqueid="ps7_usb0_GPTIMER0CTRL_GPTMODE">
<name>GPTMODE</name>
<desc>0b' - One Shot; '1b' - Repeat. This bit selects between a single timer countdown and a looped countdown. In one-shot mode, the timer will count down to zero, generate an interrupt and stop until the counter is reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the counter to begin again.</desc>
<sw_param offset="0xe0002084" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_usb0_GPTIMER0CTRL_GPTCNT">
<name>GPTCNT</name>
<desc>General Purpose Timer Counter.
This field is the value of the running timer.</desc>
<sw_param offset="0xe0002084" start="23" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_GPTIMER1LD_GPTLD">
<name>GPTLD</name>
<desc>General Purpose Timer Load Value register.
This field is the value to be loaded into the GPTCNT countdown timer on a reset action. The value in this register represents the time in microseconds minus 1 for the timer duration.
Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7.
Note: Max value is 0xFFFFFF or 16.777215 seconds</desc>
<sw_param offset="0xe0002088" start="23" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_GPTIMER1CTRL_GPTRUN">
<name>GPTRUN</name>
<desc>General Purpose Timer Run. This bit enables the general-purpose timer to run. Setting or clearing this bit will not have an effect on the GPTCNT counter value.</desc>
<sw_param offset="0xe000208c" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_usb0_GPTIMER1CTRL_GPTRST">
<name>GPTRST</name>
<desc>General Purpose Timer Reset. Writing a one to this bit will reload the GPTCNT with the value in GPTLD.</desc>
<sw_param offset="0xe000208c" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_usb0_GPTIMER1CTRL_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xe000208c" start="29" end="25" />
</parameter>
<parameter uniqueid="ps7_usb0_GPTIMER1CTRL_GPTMODE">
<name>GPTMODE</name>
<desc>0b' - One Shot; '1b' - Repeat. This bit selects between a single timer countdown and a looped countdown. In one-shot mode, the timer will count down to zero, generate an interrupt and stop until the counter is reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the counter to begin again.</desc>
<sw_param offset="0xe000208c" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_usb0_GPTIMER1CTRL_GPTCNT">
<name>GPTCNT</name>
<desc>General Purpose Timer Counter.
This field is the value of the running timer.</desc>
<sw_param offset="0xe000208c" start="23" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_SBUSCFG_AHBBRST">
<name>AHBBRST</name>
<desc>VUSB_HS_RX_BURST
0: incremental bursts of unspecified length
1: INCR4, non multiple transfers of 4 are decomposed to singles
2: INCR8, non multiple transfers of 8 are decomposed to INCR4 or singles
3: INCR16, non multiple transfers of 16 are decomposed to INCR8, INCR4 or singles
4: Do not use this value!
5: INCR4, non multiple transfers of 4 are decomposed to INCR of unspecifed length
6: INCR8, non multiple transfers of 8 are decomposed to INCR4 or INCR of unspecifed length
7: INCR16, non multiple transfers of 16 are decomposed to INCR8, INCR4 or INCR of unspecifed length</desc>
<sw_param offset="0xe0002090" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_CAPLENGTH_HCIVERSION_HCIVERSION">
<name>HCIVERSION</name>
<desc>This is a two-byte register containing a BCD encoding of the EHCI revision number supported by this host controller. The most significant byte of this register represents a major revision and the least significant byte is the minor revision.</desc>
<sw_param offset="0xe0002100" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_CAPLENGTH_HCIVERSION_CAPLENGTH">
<name>CAPLENGTH</name>
<desc>This register indicates capability register length. This register is used to indicate which offset to add to the register base address at the beginning of the Operational Register</desc>
<sw_param offset="0xe0002100" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_HCSPARAMS_N_TT">
<name>N_TT</name>
<desc>This field indicates the number of embedded transaction translators associated with the USB2.0 host controller. For Multi-Port Host this field will always be equal to '0001b'. For all other implementation, N_TT = '0000b'.
This field will always be '0'</desc>
<sw_param offset="0xe0002104" start="27" end="24" />
</parameter>
<parameter uniqueid="ps7_usb0_HCSPARAMS_N_PTT">
<name>N_PTT</name>
<desc>Number of Ports per Transaction Translator. This field indicates the number of ports assigned to each transaction translator within the USB2.0 host controller.
For Multi-Port Host this field will always equal N_PORTS. For all other implementations, N_PTT = '0000b'.
This in a non-EHCI field to support embedded TT.</desc>
<sw_param offset="0xe0002104" start="23" end="20" />
</parameter>
<parameter uniqueid="ps7_usb0_HCSPARAMS_reserved_1">
<name>reserved_1</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0002104" start="19" end="17" />
</parameter>
<parameter uniqueid="ps7_usb0_HCSPARAMS_PI">
<name>PI</name>
<desc>Port indicator. This bit indicates whether the ports support port indicator control. When set to one, the
port status and control registers include a read/writable field for controlling the state of
the port indicator. This field will always be '1'</desc>
<sw_param offset="0xe0002104" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_HCSPARAMS_N_CC">
<name>N_CC</name>
<desc>This field indicates the number of companion controllers associated with this USB2.0 host controller. A zero in this field indicates there are no internal Companion Controllers. Portownership
hand-off is not supported. A value larger than zero in this field indicates there are companion USB1.1 host controller(s). Port-ownership hand-offs are supported. High, Full and Low speed devices are supported on the host controller root ports.</desc>
<sw_param offset="0xe0002104" start="15" end="12" />
</parameter>
<parameter uniqueid="ps7_usb0_HCSPARAMS_N_PCC">
<name>N_PCC</name>
<desc>This field indicates the number of ports supported per internal Companion Controller. It is used to indicate the port routing configuration to the system software.</desc>
<sw_param offset="0xe0002104" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_usb0_HCSPARAMS_reserved">
<name>reserved</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0002104" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_usb0_HCSPARAMS_PPC">
<name>PPC</name>
<desc>Port Power Control. This field indicates whether the host controller implementation includes port power control.
1 =indicates the ports have port power switches.
0 = indicates the ports do not have port power switches.</desc>
<sw_param offset="0xe0002104" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb0_HCSPARAMS_N_PORTS">
<name>N_PORTS</name>
<desc>Number of downstream ports supported by the host controller</desc>
<sw_param offset="0xe0002104" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_HCCPARAMS_EECP">
<name>EECP</name>
<desc>No Description</desc>
<sw_param offset="0xe0002108" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb0_HCCPARAMS_IST">
<name>IST</name>
<desc>Isochronous Scheduling Threshold.
This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule. When bit [7] is zero, the value of the least significant 3 bits indicates the number of micro-frames a host controller can hold a set of isochronous data structures (one or more) before flushing the state. When bit [7] is a one, then host software assumes the host controller may cache an isochronous data structure for an entire frame.
This field will always be 4'b0</desc>
<sw_param offset="0xe0002108" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_usb0_HCCPARAMS_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xe0002108" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_usb0_HCCPARAMS_ASP">
<name>ASP</name>
<desc>Asynchronous Schedule Park Capability. If this bit is set to a one, then the host controller supports the park feature for highspeed queue heads in the Asynchronous Schedule. The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode
Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register.
This field will always be '1'</desc>
<sw_param offset="0xe0002108" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_usb0_HCCPARAMS_PFL">
<name>PFL</name>
<desc>If this bit is set to zero, then the system software must use a frame list length of 1024 elements with this host controller. The USBCMD register Frame List Size field is a read-only register and must be set to zero.
If set to a one, then the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K-page boundary. This field will always be '1'</desc>
<sw_param offset="0xe0002108" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb0_HCCPARAMS_ADC">
<name>ADC</name>
<desc>64-bit Addressing Capability. For thi scontroller its always 0</desc>
<sw_param offset="0xe0002108" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_DCIVERSION_DCIVERSION">
<name>DCIVERSION</name>
<desc>The device controller interface conforms to the two-byte BCD encoding of the interface version number
contained in this register</desc>
<sw_param offset="0xe0002120" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_DCCPARAMS_HC">
<name>HC</name>
<desc>Host Capable. When this bit is 1, this controller is capable of operating as an EHCI compatible USB
2.0 host controller
1= The controller is USB 2.0 host controller capable</desc>
<sw_param offset="0xe0002124" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_usb0_DCCPARAMS_DC">
<name>DC</name>
<desc>Device Capable register. When this bit is 1, this controller is capable of operating as a USB 2.0 device.
1= The controller is USB 2.0 device capable</desc>
<sw_param offset="0xe0002124" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb0_DCCPARAMS_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xe0002124" start="6" end="5" />
</parameter>
<parameter uniqueid="ps7_usb0_DCCPARAMS_DEN">
<name>DEN</name>
<desc>This field indicates the number of endpoints built into the device controller.
12 = 12 endpoints are supported</desc>
<sw_param offset="0xe0002124" start="4" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_USBCMD_ITC">
<name>ITC</name>
<desc>Interrupt Threshold Control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts.
00h Immediate (no threshold)
01h 1 micro-frame
02h 2 micro-frames
04h 4 micro-frames
08h 8 micro-frames
10h 16 micro-frames
20h 32 micro-frames
40h 64 micro-frames</desc>
<sw_param offset="0xe0002140" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_USBCMD_FS2">
<name>FS2</name>
<desc>MSB bit of FS field.</desc>
<sw_param offset="0xe0002140" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_usb0_USBCMD_ATDTW">
<name>ATDTW</name>
<desc>This bit is used as a semaphore to ensure the proper addition of a new dTD to an active (primed) endpoint's linked list.</desc>
<sw_param offset="0xe0002140" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_usb0_USBCMD_SUTW">
<name>SUTW</name>
<desc>Setup TripWir. This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is
extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (See USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists.
Used only in device Mode</desc>
<sw_param offset="0xe0002140" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_usb0_USBCMD_reserved">
<name>reserved</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0002140" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_usb0_USBCMD_ASPE">
<name>ASPE</name>
<desc>If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1b and is R/W. Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled.
This field is set to '1'b in this implementation. Only used in host mode.</desc>
<sw_param offset="0xe0002140" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_usb0_USBCMD_reserved_1">
<name>reserved_1</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0002140" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_usb0_USBCMD_ASP">
<name>ASP</name>
<desc>If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is RO. It contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before
continuing traversal of the Asynchronous schedule.
This field is set to 3h in this implementation.
Only used in host mode.</desc>
<sw_param offset="0xe0002140" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_usb0_USBCMD_LR">
<name>LR</name>
<desc>Light Host/Device Controller Reset. This field will always be '0b'.</desc>
<sw_param offset="0xe0002140" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb0_USBCMD_IAA">
<name>IAA</name>
<desc>This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances the asynchronous schedule. Software must write a '1b' to this bit to ring the doorbell. This is used only in Host mode</desc>
<sw_param offset="0xe0002140" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb0_USBCMD_ASE">
<name>ASE</name>
<desc>This bit controls whether the host controller skips processing the Asynchronous Schedule.
Values Meaning :
0- Do not process the Asynchronous Schedule.
1- Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
Only used in host mode.</desc>
<sw_param offset="0xe0002140" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb0_USBCMD_PSE">
<name>PSE</name>
<desc>This bit controls whether the host controller skips processing the Periodic Schedule. Values Meaning
0 -&gt; Do not process the Periodic Schedule
1 -&gt; Use the PERIODICLISTBASE register to access the Periodic Schedule.
Only used in host mode.</desc>
<sw_param offset="0xe0002140" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb0_USBCMD_FS0">
<name>FS0</name>
<desc>reserved
0 -&gt; 1024 elements (4096 bytes)
1 -&gt; 512 elements (2048 bytes)
2 -&gt; 256 elements (1024 bytes)
3 -&gt; 128 elements (512 bytes)
4 -&gt; 64 elements (256 bytes)
5 -&gt; 32 elements (128 bytes)
6 -&gt;16 elements (64 bytes)
7 -&gt; 8 elements (32 bytes)</desc>
<sw_param offset="0xe0002140" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_usb0_USBCMD_RST">
<name>RST</name>
<desc>Software uses this bit to reset the controller. This bit is set to zero by the Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.</desc>
<sw_param offset="0xe0002140" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb0_USBCMD_RS">
<name>RS</name>
<desc>Run/Stop bit , When set to a 1, the Controller proceeds with the execution of the schedule.</desc>
<sw_param offset="0xe0002140" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_USBSTS_TI1">
<name>TI1</name>
<desc>This bit is set when the counter in the GPTIMER1CTRL register transitions to zero. Writing a one to this bit will clear it.</desc>
<sw_param offset="0xe0002144" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_usb0_USBSTS_TI0">
<name>TI0</name>
<desc>This bit is set when the counter in the GPTIMER0CTRL register transitions to zero.
Writing a one to this bit will clear it.</desc>
<sw_param offset="0xe0002144" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_usb0_USBSTS_reserved">
<name>reserved</name>
<desc>T</desc>
<sw_param offset="0xe0002144" start="23" end="20" />
</parameter>
<parameter uniqueid="ps7_usb0_USBSTS_UPI">
<name>UPI</name>
<desc>This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule.
This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than expected.
This bit is not used by the device controller and will always be zero.</desc>
<sw_param offset="0xe0002144" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_usb0_USBSTS_UAI">
<name>UAI</name>
<desc>USB Host Asynchronous Interrupt . This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule.
This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than expected.
This bit is not used by the device controller and will always be zero.</desc>
<sw_param offset="0xe0002144" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_usb0_USBSTS_reserved_1">
<name>reserved_1</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0002144" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb0_USBSTS_NAKI">
<name>NAKI</name>
<desc>NAK Interrupt. This bit is read-only. It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared. This bit is not used by the host controller and will always be zero.</desc>
<sw_param offset="0xe0002144" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_USBSTS_AS">
<name>AS</name>
<desc>This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled.
The Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0).
Only used in host mode.</desc>
<sw_param offset="0xe0002144" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_usb0_USBSTS_PS">
<name>PS</name>
<desc>Periodic Schedule Status. This bit reports the current real status of the Periodic Schedule. When set to zero the
periodic schedule is disabled, and if set to one the status is enabled. The Controller is not required to immediately disable or enable the Periodic Schedule when software
transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0).
Only used in host mode.</desc>
<sw_param offset="0xe0002144" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_usb0_USBSTS_RCL">
<name>RCL</name>
<desc>Reclamation. This is a read-only status bit used to detect an empty asynchronous schedule. Used in Host mode only</desc>
<sw_param offset="0xe0002144" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_usb0_USBSTS_HCH">
<name>HCH</name>
<desc>HCHaIted. This bit is a zero whenever the Run/Stop bit is a one. The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Controller hardware (e.g. internal error).
Only used in host mode.</desc>
<sw_param offset="0xe0002144" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_usb0_USBSTS_reserved_2">
<name>reserved_2</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0002144" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_usb0_USBSTS_ULPII">
<name>ULPII</name>
<desc>ULPI Interrupt. When the ULPI Viewport is present in the design, an event completion will set this interrupt.</desc>
<sw_param offset="0xe0002144" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_usb0_USBSTS_reserved_3">
<name>reserved_3</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0002144" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_usb0_USBSTS_SLI">
<name>SLI</name>
<desc>DCSuspend. When a device controller enters a suspend state from an active state, this bit will be set to a one. This bit is only cleared by software writing a 1 to it.
Only used in device mode.</desc>
<sw_param offset="0xe0002144" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_usb0_USBSTS_SRI">
<name>SRI</name>
<desc>SOF Received. When the device controller detects a Start Of (u)Frame, this bit will be set to a one.
When a SOF is extremely late, the Controller, when in device mode, will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1ms in FS mode and every 125us in HS mode and will be synchronized to the actual SOF that is received.
Since the Controller when in device mode is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp.
In host mode, this bit will be set every 125us and can be used by host controller driver as a time base.
Software writes a 1 to this bit to clear it.</desc>
<sw_param offset="0xe0002144" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb0_USBSTS_URI">
<name>URI</name>
<desc>USB Reset Received. When the Controller detects a USB Reset and enters the default state, this bit will be set to a one. Software can write a 1 to this bit to clear the USB Reset Received status bit.
Only used in device mode.</desc>
<sw_param offset="0xe0002144" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb0_USBSTS_AAI">
<name>AAI</name>
<desc>Interrupt on Async Advance. System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the
assertion of that interrupt source.
Only used in host mode.</desc>
<sw_param offset="0xe0002144" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb0_USBSTS_SEI">
<name>SEI</name>
<desc>System Error. In the BVCI implementation of the USBHS core, this bit is not used, and will always be
cleared to '0b'. In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface</desc>
<sw_param offset="0xe0002144" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb0_USBSTS_FRI">
<name>FRI</name>
<desc>Frame List Rollover
The Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX[13] toggles. Similarly, if the size is 512, the Controller sets this bit to a one every time FRINDEX[12] toggles. Only used in host mode.</desc>
<sw_param offset="0xe0002144" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_usb0_USBSTS_PCI">
<name>PCI</name>
<desc>Port Change Detect. The Controller in host mode sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port.
The Controller in device mode sets this bit to a one when it detects resume signaling or the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit and the DCSuspend bits respectively.</desc>
<sw_param offset="0xe0002144" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_usb0_USBSTS_UEI">
<name>UEI</name>
<desc>USB Error Interrupt. When completion of a USB transaction results in an error condition, this bit is set by the Controller</desc>
<sw_param offset="0xe0002144" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb0_USBSTS_UI">
<name>UI</name>
<desc>This bit is set by the Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set.
This bit is also set by the Host Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than expected.</desc>
<sw_param offset="0xe0002144" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_USBINTR_TIE1">
<name>TIE1</name>
<desc>General Purpose Timer Interrupt Enable 1
When this bit is a one, and the TI1 bit in the EXTSTS register is a one, the controller will issue an interrupt. The interrupt is acknowledged by software clearing the TI1 bit.</desc>
<sw_param offset="0xe0002148" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_usb0_USBINTR_TIE0">
<name>TIE0</name>
<desc>General Purpose Timer Interrupt Enable 0
When this bit is a one, and the TI1 bit in the EXTSTS register is a one, the controller will issue an interrupt. The interrupt is acknowledged by software clearing the TI0 bit.</desc>
<sw_param offset="0xe0002148" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_usb0_USBINTR_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0002148" start="23" end="20" />
</parameter>
<parameter uniqueid="ps7_usb0_USBINTR_UPEI">
<name>UPEI</name>
<desc>USB Host Periodic Interrupt Enable.
When this bit is a one, and the UPI bit in the EXTSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the UPI bit.</desc>
<sw_param offset="0xe0002148" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_usb0_USBINTR_UAEI">
<name>UAEI</name>
<desc>USB Host Asynchronous Interrupt Enable
When this bit is a one, and the UAI bit in the EXTSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the UAI bit.</desc>
<sw_param offset="0xe0002148" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_usb0_USBINTR_reserved_1">
<name>reserved_1</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0002148" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb0_USBINTR_NAKEI">
<name>NAKEI</name>
<desc>NAK Interrupt Enable
when this bit is a one, and the NAKI bit in the EXTSTS register is a one, the controller will issue an interrupt. The interrupt is acknowledged by software clearing the NAKI bit.</desc>
<sw_param offset="0xe0002148" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_USBINTR_reserved_2">
<name>reserved_2</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0002148" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_usb0_USBINTR_ULPIE">
<name>ULPIE</name>
<desc>ULPI Interrupt enable. When this bit is a one, and the ULPI Interrupt bit in the USBSTS register transitions, the Controller will issue and interrupt. The interrupt is acknowledged by software writing a one to the ULPI Interrupt bit.</desc>
<sw_param offset="0xe0002148" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_usb0_USBINTR_reserved_3">
<name>reserved_3</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0002148" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_usb0_USBINTR_SLE">
<name>SLE</name>
<desc>DCSuspend Interrupt Enable.
When this bit is a one, and the SLI bit in the USBSTS register transitions, the Controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the SLI bit.
Only used in device mode.</desc>
<sw_param offset="0xe0002148" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_usb0_USBINTR_SRE">
<name>SRE</name>
<desc>USB Reset Received Interrupt Enable
When this bit is a one, and the SRI bit in the USBSTS register is a one, the Controller will issue an interrupt. The interrupt is acknowledged by software clearing the SRI bit.</desc>
<sw_param offset="0xe0002148" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb0_USBINTR_URE">
<name>URE</name>
<desc>USB Reset Received. When the Controller detects a USB Reset and enters the default state, this bit will be set to a one. Software can write a 1 to this bit to clear the USB Reset Received status bit.
Only used in device mode.</desc>
<sw_param offset="0xe0002148" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb0_USBINTR_AAE">
<name>AAE</name>
<desc>Interrupt on Async Advance Enable. When this bit is a one, and the AAI bit in the USBSTS register is a one, the Controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on AAI bit.
Only used in host mode.</desc>
<sw_param offset="0xe0002148" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb0_USBINTR_SEE">
<name>SEE</name>
<desc>System Error Interrupt Enable. When this bit is a one, and the SEI bit in the USBSTS register is a one, the Controller will issue an interrupt. The interrupt is acknowledged by software clearing the SSI bit.</desc>
<sw_param offset="0xe0002148" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb0_USBINTR_FRE">
<name>FRE</name>
<desc>Frame List Rollover Interrupt Enable
When this bit is a one, and the FRI bit in the USBSTS register is a one, the Controller will issue an interrupt. The interrupt is acknowledged by software clearing the FRI bit. Only used in host mode.</desc>
<sw_param offset="0xe0002148" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_usb0_USBINTR_PCE">
<name>PCE</name>
<desc>Port Change Detect Interrupt Enable
When this bit is a one, and the PCI bit in the USBSTS register is a one, the Controller will issue an interrupt. The interrupt is acknowledged by software clearing the PCI bit.</desc>
<sw_param offset="0xe0002148" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_usb0_USBINTR_UEE">
<name>UEE</name>
<desc>USB Error Interrupt
When this bit is a one, and the UEI bit in the USBSTS register is a one, the Controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by
software clearing the UEI bit in the USBSTS register.</desc>
<sw_param offset="0xe0002148" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb0_USBINTR_UE">
<name>UE</name>
<desc>When this bit is a one, and the UI bit in the USBSTS register is a one, the Controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by
software clearing the UI bit.</desc>
<sw_param offset="0xe0002148" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_FRINDEX_FRINDEX">
<name>FRINDEX</name>
<desc>The value, in this register, increments at the end of each time frame (e.g. micro-frame). Bits [N:3] are used for the Frame List current index. This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode.
usbcmd-&gt; FrameList-&gt; Size
000b -&gt;(1024) -&gt; 12
001b -&gt;(512) -&gt;11
010b -&gt;(256)-&gt;10
011b -&gt;(128) -&gt; 9
100b -&gt;(64) -&gt; 8
101b -&gt;(32) -&gt; 7
110b -&gt;(16) -&gt;6
111b -&gt;(8) -&gt;5
In device mode the value is the current frame number of the last frame transmitted. It is not used as an index.
This register is read-only in device mode.</desc>
<sw_param offset="0xe000214c" start="13" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_PERIODICLISTBASE_DEVICEADDR_PERBASE_USBADRA">
<name>PERBASE_USBADRA</name>
<desc>In host mode: Periodic List Base Address:
These bits correspond to memory address signals [31:12], respectively.
In Device Mode:
Device address advance
When this bit is '0b', any writes to USBADR are instantaneous. When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the hidden register.
Hardware will automatically clear this bit on the following conditions:
1) IN is ACKed to endpoint 0. (USBADR is updated from hidden register).
2) OUT/SETUP occur to endpoint 0. (USBADR is not updated).
3) Device Reset occurs (USBADR is reset to 0).</desc>
<sw_param offset="0xe0002154" start="31" end="25" />
</parameter>
<parameter uniqueid="ps7_usb0_PERIODICLISTBASE_DEVICEADDR_PERBASE_USBADR">
<name>PERBASE_USBADR</name>
<desc>In host mode: Periodic List Base Address:
These bits correspond to memory address signals [31:12], respectively.
In device Mode: USB Device address
These bits correspond to the USB device address</desc>
<sw_param offset="0xe0002154" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_usb0_PERIODICLISTBASE_DEVICEADDR_PERBASE_Reserved">
<name>PERBASE_Reserved</name>
<desc>In host mode: Periodic List Base Address:
These bits correspond to memory address signals [31:12], respectively.
In Device Mode: Reserved</desc>
<sw_param offset="0xe0002154" start="23" end="12" />
</parameter>
<parameter uniqueid="ps7_usb0_PERIODICLISTBASE_DEVICEADDR_reserved">
<name>reserved</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0002154" start="11" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_ASYNCLISTADDR_ENDPOINTLISTADDR_ASYBASE_EPBASE">
<name>ASYBASE_EPBASE</name>
<desc>In host mode: Asynchronous List Base Address:
These bits correspond to memory address signals [31:5], respectively. This field may only reference a Queue Head (QH).
In Device Mode:
Endpoint List Base Address
These bits correspond to memory address signals [31:11], respectively. This field will reference a list of up to 32 Queue Heads (QH). (i.e. one queue head per endpoint ANDdirection).</desc>
<sw_param offset="0xe0002158" start="31" end="11" />
</parameter>
<parameter uniqueid="ps7_usb0_ASYNCLISTADDR_ENDPOINTLISTADDR_ASYBASE">
<name>ASYBASE</name>
<desc>In host mode: Asynchronous List Base Address:
These bits correspond to memory address signals [31:5], respectively. This field may only reference a Queue Head (QH).
In Device Mode: Reserved</desc>
<sw_param offset="0xe0002158" start="10" end="5" />
</parameter>
<parameter uniqueid="ps7_usb0_ASYNCLISTADDR_ENDPOINTLISTADDR_reserved">
<name>reserved</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0002158" start="4" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_TTCTRL_reserved">
<name>reserved</name>
<desc>RESERVED</desc>
<sw_param offset="0xe000215c" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_usb0_TTCTRL_TTHA">
<name>TTHA</name>
<desc>Internal TT Hub Address Representation.
This field is used to match against the Hub Address field in QH AND siTD to determine if the packet is routed to the internal TT for directly attached FS/LS devices. If the Hub
Address in the QH or siTD does not match this address then the packet will be broadcast on the High Speed ports destined for a downstream High Speed hub with the
address in the QH/siTD.</desc>
<sw_param offset="0xe000215c" start="30" end="24" />
</parameter>
<parameter uniqueid="ps7_usb0_TTCTRL_reserved_1">
<name>reserved_1</name>
<desc>RESERVED</desc>
<sw_param offset="0xe000215c" start="23" end="2" />
</parameter>
<parameter uniqueid="ps7_usb0_TTCTRL_TTAS">
<name>TTAS</name>
<desc>Embedded TT Asynchronous Buffers Clear. This field will clear all pending transactions in the embedded TT Asynchronous Buffer(s). The clear will take as much time as necessary to clear buffer without
interfering with a transaction in progress. TTAC will return to zero after being set by software only after the actual clear occurs.</desc>
<sw_param offset="0xe000215c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb0_TTCTRL_TTAC">
<name>TTAC</name>
<desc>Embedded TT Async Buffers Status. This read only bit will be '1' if one or more transactions are being held in the embedded TT Asynchronous Buffers. When this bit is a zero, then all outstanding transactions in the embedded TT have been flushed.</desc>
<sw_param offset="0xe000215c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_BURSTSIZE_TXPBURST">
<name>TXPBURST</name>
<desc>Programmable TX Burst Length.
Default is the constant VUSB_HS_TX_BURST. This register represents the maximum length of a the burst in 32-bit words while moving data from system memory to the USB bus.
If field AHBBRST of register SBUSCFG is different from zero, this field TXPBRUST will return the value of the INCRx length.
Supported values are integer values from 4 to 128. It is recommended to set this value to a integer sub-multiple of VUSB_HS_TX_CHAN. Different values will not use all the available buffer space, preventing proper TX endpoint priming in stream disable mode (SDIS bit of USBMODE register set to '1').</desc>
<sw_param offset="0xe0002160" start="16" end="8" />
</parameter>
<parameter uniqueid="ps7_usb0_BURSTSIZE_RXPBURST">
<name>RXPBURST</name>
<desc>Programmable RX Burst Length. Default is the constant VUSB_HS_RX_BURST. This register represents the maximum length of a the burst in 32-bit words while moving data from the USB bus to system memory. If field AHBBRST of register SBUSCFG is different from zero, this field RXPBRUST will return the value of the INCRx length.
The supported values are integer values from 4 to 128. It is recommended to set this value to a integer sub-multiple of VUSB_HS_RX_DEPTH.</desc>
<sw_param offset="0xe0002160" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_TXFILLTUNING_TXFIFOTHRES">
<name>TXFIFOTHRES</name>
<desc>FIFO Burst Threshold:
This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth, where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set (SDIS).</desc>
<sw_param offset="0xe0002164" start="21" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_TXFILLTUNING_reserved">
<name>reserved</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0002164" start="15" end="13" />
</parameter>
<parameter uniqueid="ps7_usb0_TXFILLTUNING_TXSCHEALTH">
<name>TXSCHEALTH</name>
<desc>Scheduler Health Counter.
This register increments when the Controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame.
This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. This counter will max. at 31.</desc>
<sw_param offset="0xe0002164" start="12" end="8" />
</parameter>
<parameter uniqueid="ps7_usb0_TXFILLTUNING_reserved_1">
<name>reserved_1</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0002164" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb0_TXFILLTUNING_TXSCHOH">
<name>TXSCHOH</name>
<desc>Scheduler Overhead.
This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization.
The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode for OTG(on the go) AND SPH(single port host) implementations.
The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode for OTG AND SPH implementations. The time unit represented in this register is always 1.267us for the MPH implementation</desc>
<sw_param offset="0xe0002164" start="6" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_TXTTFILLTUNING_TXTTSCHHEALTH">
<name>TXTTSCHHEALTH</name>
<desc>TT Scheduler Health Counter
Same description as TXSCHHEALTH</desc>
<sw_param offset="0xe0002168" start="12" end="8" />
</parameter>
<parameter uniqueid="ps7_usb0_TXTTFILLTUNING_reserved">
<name>reserved</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0002168" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_usb0_TXTTFILLTUNING_TXTTSCHOH">
<name>TXTTSCHOH</name>
<desc>TT Scheduler Overhead
Same description as TXSCHOH.
The time unit represented in this register is 6.333us.</desc>
<sw_param offset="0xe0002168" start="4" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_IC_USB_IC8">
<name>IC8</name>
<desc>Inter-Chip transceiver enable 8. These bits enables the Inter-Chip transceiver for each port (for the MPH case). To enable the interface, the bits PTS must be set to '011b' in the PORTSC8. Writing a '1' to each bit selects the IC_USB interface for that port.</desc>
<sw_param offset="0xe000216c" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_usb0_IC_USB_IC_VDD8">
<name>IC_VDD8</name>
<desc>Inter-Chip voltage selection 8
It selects which voltage is being supplied to the peripheral through each port This field is read-only and set to '000b' in case of device mode operation.
This field is read-only and set to '000b' in case of Single port host controller.</desc>
<sw_param offset="0xe000216c" start="30" end="28" />
</parameter>
<parameter uniqueid="ps7_usb0_IC_USB_IC7">
<name>IC7</name>
<desc>Inter-Chip transceiver enable 7. These bits enables the Inter-Chip transceiver for each port (for the MPH case). To enable the interface, the bits PTS must be set to '011b' in the PORTSC7. Writing a '1' to each bit selects the IC_USB interface for that port.</desc>
<sw_param offset="0xe000216c" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_usb0_IC_USB_IC_VDD7">
<name>IC_VDD7</name>
<desc>Inter-Chip voltage selection 7
It selects which voltage is being supplied to the peripheral through each port This field is read-only and set to '000b' in case of device mode operation.
This field is read-only and set to '000b' in case of Single port host controller.</desc>
<sw_param offset="0xe000216c" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_usb0_IC_USB_IC6">
<name>IC6</name>
<desc>Inter-Chip transceiver enable 6. These bits enables the Inter-Chip transceiver for each port (for the MPH case). To enable the interface, the bits PTS must be set to '011b' in the PORTSC6. Writing a '1' to each bit selects the IC_USB interface for that port.</desc>
<sw_param offset="0xe000216c" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb0_IC_USB_IC_VDD6">
<name>IC_VDD6</name>
<desc>Inter-Chip voltage selection 6
It selects which voltage is being supplied to the peripheral through each port This field is read-only and set to '000b' in case of device mode operation.
This field is read-only and set to '000b' in case of Single port host controller.</desc>
<sw_param offset="0xe000216c" start="22" end="20" />
</parameter>
<parameter uniqueid="ps7_usb0_IC_USB_IC5">
<name>IC5</name>
<desc>Inter-Chip transceiver enable 5. These bits enables the Inter-Chip transceiver for each port (for the MPH case). To enable the interface, the bits PTS must be set to '011b' in the PORTSC5. Writing a '1' to each bit selects the IC_USB interface for that port.</desc>
<sw_param offset="0xe000216c" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_usb0_IC_USB_IC_VDD5">
<name>IC_VDD5</name>
<desc>Inter-Chip voltage selection 5
It selects which voltage is being supplied to the peripheral through each port This field is read-only and set to '000b' in case of device mode operation.
This field is read-only and set to '000b' in case of Single port host controller.</desc>
<sw_param offset="0xe000216c" start="18" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_IC_USB_IC4">
<name>IC4</name>
<desc>Inter-Chip transceiver enable 4. These bits enables the Inter-Chip transceiver for each port (for the MPH case). To enable the interface, the bits PTS must be set to '011b' in the PORTSC4. Writing a '1' to each bit selects the IC_USB interface for that port.</desc>
<sw_param offset="0xe000216c" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_usb0_IC_USB_IC_VDD4">
<name>IC_VDD4</name>
<desc>Inter-Chip voltage selection 4
It selects which voltage is being supplied to the peripheral through each port This field is read-only and set to '000b' in case of device mode operation.
This field is read-only and set to '000b' in case of Single port host controller.</desc>
<sw_param offset="0xe000216c" start="14" end="12" />
</parameter>
<parameter uniqueid="ps7_usb0_IC_USB_IC3">
<name>IC3</name>
<desc>Inter-Chip transceiver enable 3. These bits enables the Inter-Chip transceiver for each port (for the MPH case). To enable the interface, the bits PTS must be set to '011b' in the PORTSC3. Writing a '1' to each bit selects the IC_USB interface for that port.</desc>
<sw_param offset="0xe000216c" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_usb0_IC_USB_IC_VDD3">
<name>IC_VDD3</name>
<desc>Inter-Chip voltage selection 3
It selects which voltage is being supplied to the peripheral through each port. This field is read-only and set to '000b' in case of device mode operation.
This field is read-only and set to '000b' in case of Single port host controller.</desc>
<sw_param offset="0xe000216c" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_usb0_IC_USB_IC2">
<name>IC2</name>
<desc>Inter-Chip transceiver enable 2. These bits enables the Inter-Chip transceiver for each port (for the MPH case). To enable the interface, the bits PTS must be set to '011b' in the PORTSC2. Writing a '1' to each bit selects the IC_USB interface for that port.</desc>
<sw_param offset="0xe000216c" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb0_IC_USB_IC_VDD2">
<name>IC_VDD2</name>
<desc>Inter-Chip voltage selection 2
It selects which voltage is being supplied to the peripheral through each port. This field is read-only and set to '000b' in case of device mode operation.
This field is read-only and set to '000b' in case of Single port host controller.</desc>
<sw_param offset="0xe000216c" start="6" end="4" />
</parameter>
<parameter uniqueid="ps7_usb0_IC_USB_IC1">
<name>IC1</name>
<desc>Inter-Chip transceiver enable 1. These bits enables the Inter-Chip transceiver for each port (for the MPH case). To enable the interface, the bits PTS must be set to '011b' in the PORTSC1. Writing a '1' to each bit selects the IC_USB interface for that port. If the Controller is not a MPH
implementation, IC8 to IC2 will be '0' and Read-Only.</desc>
<sw_param offset="0xe000216c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_usb0_IC_USB_IC_VDD1">
<name>IC_VDD1</name>
<desc>Inter-Chip voltage selection 1
It selects which voltage is being supplied to the peripheral through each port
000 - No voltage
001 - 1.0V
010 - 1.2V
011 - 1.5V
100 - 1.8V
101 - 3.0V
110 - Reserved
111 - Reserved
This field is read-only and set to '000b' in case of device mode operation.
The voltage negotiation should happen between enabling port power (PP) in PORTSC1 register and asserting the run/stop bit in USBCMD register.</desc>
<sw_param offset="0xe000216c" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_ULPI_VIEWPORT_ULPIWU">
<name>ULPIWU</name>
<desc>ULPI Wakeup.
Writing the '1' to this bit will begin the wakeup operation. The bit will automatically transition to '0' after the wakeup is complete. Once this bit is set, the driver can not set it back to '0'.
Note: The driver must never execute a wakeup and a read/write operation at the same time.</desc>
<sw_param offset="0xe0002170" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_usb0_ULPI_VIEWPORT_ULPIRUN">
<name>ULPIRUN</name>
<desc>ULPIRUN
Writing the '1' to this bit will begin the read/write operation. The bit will automatically transition to '0' after the read/write is complete. Once this bit is set, the driver can not set it back to '0'.
Note: The driver must never execute a wakeup and a read/write operation at the same time.</desc>
<sw_param offset="0xe0002170" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_usb0_ULPI_VIEWPORT_ULPIRW">
<name>ULPIRW</name>
<desc>ULPI Read/Write Control'0' - Read.'1' - Write.
This bit selects between running a read or write operation.</desc>
<sw_param offset="0xe0002170" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_usb0_ULPI_VIEWPORT_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0002170" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_usb0_ULPI_VIEWPORT_ULPISS">
<name>ULPISS</name>
<desc>ULPI Data Address. When a read or write operation is commanded, the address of the operation is written to this field.</desc>
<sw_param offset="0xe0002170" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_usb0_ULPI_VIEWPORT_ULPIPORT">
<name>ULPIPORT</name>
<desc>ULPI Port Number.
For the wakeup or read/write operation to be executed, this value selects the port number to which a ULPI PHY is attached. The range is 0 to 7. This field should always be written '000b' for non MPH implementations.</desc>
<sw_param offset="0xe0002170" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_usb0_ULPI_VIEWPORT_ULPIADDR">
<name>ULPIADDR</name>
<desc>ULPI Data Address. When a read or write operation is commanded, the address of the operation is written to this field.</desc>
<sw_param offset="0xe0002170" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_ULPI_VIEWPORT_ULPIDATRD">
<name>ULPIDATRD</name>
<desc>ULPI Data Read.
After a read operation completes, the result is placed in this field.</desc>
<sw_param offset="0xe0002170" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb0_ULPI_VIEWPORT_ULPIDATWR">
<name>ULPIDATWR</name>
<desc>ULPI Data Write. When a write operation is commanded, the data to be sent is written to this field</desc>
<sw_param offset="0xe0002170" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTNAK_EPTN">
<name>EPTN</name>
<desc>TX Endpoint NAK
Each TX endpoint has 1 bit in this field. The bit is set when the Controller sends a NAK handshake on a received IN token for the corresponding endpoint.
Bit 15 - Endpoint #15
...
Bit 1 - Endpoint #1
Bit 0 - Endpoint #0
Only used in device mode.</desc>
<sw_param offset="0xe0002178" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTNAK_EPRN">
<name>EPRN</name>
<desc>RX Endpoint NAK
Each RX endpoint has 1 bit in this field. The bit is set when the Controller sends a NAK handshake on a received OUT or PING token for the corresponding endpoint.
Bit 15 - Endpoint #15
...
Bit 1 - Endpoint #1
Bit 0 - Endpoint #0
Only used in device mode.</desc>
<sw_param offset="0xe0002178" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTNAKEN_EPTNE">
<name>EPTNE</name>
<desc>TX Endpoint NAK enable
Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set.
Bit 15 - Endpoint #15
...
Bit 1 - Endpoint #1
Bit 0 - Endpoint #0
Only used in device mode.</desc>
<sw_param offset="0xe000217c" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTNAKEN_EPRNE">
<name>EPRNE</name>
<desc>RX Endpoint NAK enable
Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set.
Bit 15 - Endpoint #15
...
Bit 1 - Endpoint #1
Bit 0 - Endpoint #0
Only used in device mode.</desc>
<sw_param offset="0xe000217c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_CONFIGFLAG_reserved">
<name>reserved</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0002180" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_PORTSC1_PTS">
<name>PTS</name>
<desc>This register bit pair is used in conjunction with the configuration constant VUSB_HS_PHY_TYPE to control which parallel transceiver interface is selected'010b' -&gt; 2, 6 - ULPI
Note that this field is made up from PORTSCx bits 25, 30 and 31.</desc>
<sw_param offset="0xe0002184" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_usb0_PORTSC1_STS">
<name>STS</name>
<desc>Serial Transceiver Select
This register bit is used in conjunction with the configuration constant VUSB_HS_PHY_SERIAL to control whether the parallel or serial transceiver interface is selected for FS and LS operation. The Serial Interface Engine can be used in
combination with the UTMI+ physical interface to provide FS/LS signaling instead of the parallel interface. If VUSB_HS_PHY_SERIAL is set for 0 or 1 then this bit is read only. If VUSB_HS_PHY_SERIAL is 2 or 3 then this bit is read/write.
This bit has no effect unless Parallel Transceiver Select is set to UTMI+. The Serial/1.1 and IC_USB physical interface will use the Serial Interface Engine for FS/LS signaling
regardless of this bit value.</desc>
<sw_param offset="0xe0002184" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_usb0_PORTSC1_PTW">
<name>PTW</name>
<desc>Parallel Transceiver Width. Writing this bit to '0' selects the 8-bit [60MHz] UTMI+ interface.</desc>
<sw_param offset="0xe0002184" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_usb0_PORTSC1_PSPD">
<name>PSPD</name>
<desc>Port Speed - RO. Default = 11b.
This register field indicates the speed at which the port is operating.'00b' -&gt; Full Speed'01b' -&gt; Low Speed'10b' -&gt; High Speed'11b' -&gt; Not connected</desc>
<sw_param offset="0xe0002184" start="27" end="26" />
</parameter>
<parameter uniqueid="ps7_usb0_PORTSC1_PTS2">
<name>PTS2</name>
<desc>Parallel Transceiver Select - RW. Default = Implementation dependent.
MSB bit of PTS field.</desc>
<sw_param offset="0xe0002184" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_usb0_PORTSC1_PFSC">
<name>PFSC</name>
<desc>Port Force Full Speed Connect - RW. Default = 0b.
Writing this bit to a '1b' will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device. This bit is for debugging purposes.</desc>
<sw_param offset="0xe0002184" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_usb0_PORTSC1_PHCD">
<name>PHCD</name>
<desc>PHY Low Power Clock Disable - RW. Default = 0b.
Writing this bit to a '1b' will disable the PHY clock. Writing a '0b' enables it. Reading this bit will indicate the status of the PHY clock. NOTE: The PHY clock cannot be disabled if it is being used as the system clock. In device mode, the PHY can be put into Low Power Clock Disable when the device is not running (USBCMD RS=0b) or the host has signaled suspend (PORTSCx SUSP=1b).
Low Power Clock Disable will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the Controller driver must clear this bit.
In host mode, the PHY can be put into Low Power Suspend Clock Disable when the downstream device has been put into suspend mode or when no downstream device is
connected. Low Power Clock Disable is completely under the control of software.</desc>
<sw_param offset="0xe0002184" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb0_PORTSC1_WKOC">
<name>WKOC</name>
<desc>Wake on Over-current Enable
Writing '1' to this bit enables the port to be sensitive to over-current conditions as wakeup events.
This field is zero if Port Power (PP) is '0' or in device mode.
This bit is output from the controller as signal pwrctl_wake_ovrcurr_en for use by an external power control circuit. Only used in host mode.</desc>
<sw_param offset="0xe0002184" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_usb0_PORTSC1_WKDS">
<name>WKDS</name>
<desc>Wake on Disconnect Enable
Writing this bit to a one enables the port to be sensitive to device disconnects as wakeup events. This field is zero if Port Power (PP) is '0' or in device mode. This bit is output from the controller as signal pwrctl_wake_dscnnt_en for use by an external power control circuit.</desc>
<sw_param offset="0xe0002184" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_usb0_PORTSC1_WKCN">
<name>WKCN</name>
<desc>Wake on Connect Enable
Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. This field is zero if Port Power(PP) is '0' or in device mode. This bit is output from the controller as signal pwrctl_wake_cnnt_en for use by an external power control circuit. Only used in host mode.</desc>
<sw_param offset="0xe0002184" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_usb0_PORTSC1_PTC">
<name>PTC</name>
<desc>Port Test Control
Any other value than zero indicates that the port is operating in test mode.
Value Specific Test
0000b -&gt; TEST_MODE_DISABLE
0001b -&gt; J_ STATE
0010b -&gt; K_STATE
0011b -&gt; SE0 (host) / NAK (device)
0100b -&gt; Packet
0101b -&gt; FORCE_ENABLE_HS
0110b -&gt; FORCE_ENABLE_FS
0111b -&gt; FORCE_ENABLE_LS
1000b -&gt; Reserved
... Reserved
1111b
-&gt; Reserved</desc>
<sw_param offset="0xe0002184" start="19" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_PORTSC1_PIC">
<name>PIC</name>
<desc>Port Indicator Control
Writing to this field has no effect if the P_INDICATOR bit in the HCSPARAMS register is
a zero. If P_INDICATOR bit is a one, then the bits are:
Value Meaning
00b -&gt; Port indicators are off
01b -&gt; Amber
10b -&gt; Green
11b -&gt; Undefined
Refer to the USB Specification Revision 2.0 for a description on how these bits are to be used.This field is output from the controller as signals port_ind_ctl_1 and port_ind_ctl_0 for</desc>
<sw_param offset="0xe0002184" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_usb0_PORTSC1_PO">
<name>PO</name>
<desc>Port Owner
Port owner hand off is not implemented in this design, therefore this bit will always read
back as 0b.</desc>
<sw_param offset="0xe0002184" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_usb0_PORTSC1_PP">
<name>PP</name>
<desc>Port Power
The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows:
PPC -&gt; PP -&gt; Operation
0b -&gt; 0b -&gt; Read Only. A Controller in device mode does not have port power control switches.
1b -&gt; 1b/0b -&gt; Read/Write. A Controller in host mode requires port power control switches.
This bit represents the current setting of the switch ('0'=off, '1'=on). When power is not available on a port (i.e. PP equals to '0'), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the Controller driver from '1' to '0'(removing power from the port).
In device mode port power control is not necessary, thus PPC and PP = 0.</desc>
<sw_param offset="0xe0002184" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_usb0_PORTSC1_LS">
<name>LS</name>
<desc>Line Status
These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines.
The encoding of the bits are:
00b -&gt; SE0
10b -&gt; J-state
01b -&gt; K-state
11b -&gt; Undefined
In host mode, the use of linestate by the Controller driver is not necessary (unlike EHCI), because the port controller state machine and the port routing manage the connection of LS and FS.
In device mode, the use of linestate by the Controller driver is not necessary.</desc>
<sw_param offset="0xe0002184" start="11" end="10" />
</parameter>
<parameter uniqueid="ps7_usb0_PORTSC1_HSP">
<name>HSP</name>
<desc>High-Speed Port
When the bit is one, the port is in high-speed mode and if set to zero, the port is not in a high-speed mode.
Note: HSP is redundant with PSPD but will remain in the design for compatibility.</desc>
<sw_param offset="0xe0002184" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_usb0_PORTSC1_PR">
<name>PR</name>
<desc>Port Reset - RW. Default = 0b.
This field is zero if Port Power(PP) is '0'.
Host mode: 1=Port is in Reset. 0=Port is not in Reset.
Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register</desc>
<sw_param offset="0xe0002184" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_usb0_PORTSC1_SUSP">
<name>SUSP</name>
<desc>Suspend
Host mode: 1=Port in suspend state. 0=Port not in suspend state. Port Enabled bit and Suspend bit of this register define the port states as follows:
Bits [Port Enabled, Suspend] Port State
0x Disable
10 Enable
11 Suspend
Device mode: Read Only. 1=Port in suspend state. 0=Port not in suspend state. In device mode this bit is a read only status bit.</desc>
<sw_param offset="0xe0002184" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb0_PORTSC1_FPR">
<name>FPR</name>
<desc>Force Port Resume
1= Resume detected/driven on port.
0=No resume (K-state) detected/driven on port.</desc>
<sw_param offset="0xe0002184" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb0_PORTSC1_OCC">
<name>OCC</name>
<desc>Over-current Change
This bit gets set to '1' when there is a change to Over-current Active. Software clears this bit by writing a '1' to this bit position.
When in host mode implementations the user can provide over-current detection to the vbus_pwr_fault input for this condition.
For device mode this bit shall always be '0'.</desc>
<sw_param offset="0xe0002184" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb0_PORTSC1_OCA">
<name>OCA</name>
<desc>Over-current Active
Value Meaning'1b' -&gt; This port currently has an over-current condition.'0b' -&gt; This port does not have an over-current condition.
This bit will automatically transition from '1' to '0' when the over current condition is removed.
For host mode implementations the user can provide over-current detection to the vbus_pwr_fault input for this condition.
For device mode implementations this bit shall always be '0'.</desc>
<sw_param offset="0xe0002184" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb0_PORTSC1_PEC">
<name>PEC</name>
<desc>Port Enabled Change
If set to '1' indicates a Port Enabled/Disabled status change.
Host mode:
For the root hub, this bit gets set to a '1' only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a '1' to it. This field is '0' if Port Power(PP) is '0'.
Device mode:
The device port is always enabled. (This bit will be '0').</desc>
<sw_param offset="0xe0002184" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_usb0_PORTSC1_PE">
<name>PE</name>
<desc>Port Enabled
1 -&gt; Enable
0-&gt; Disable
Host mode:
Ports can only be enabled by Controller as a part of the reset and enable. Software cannot enable a port by writing a '1' to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the software.This field is '0' if Port Power(PP) is '0' in host mode.
Device mode:
The device port is always enabled. (This bit will be always '1').</desc>
<sw_param offset="0xe0002184" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_usb0_PORTSC1_CSC">
<name>CSC</name>
<desc>Connect Status Change
If set to '1' indicates a change in Current Connect Status (CCS).
Host mode:
Indicates a change has occurred in the port's Current Connect Status. The Controller sets this bit for all changes to the port device connect status, even if system software
has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be 'setting' an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a '1' to it. This field is '0' if Port Power(PP) is '0' in host mode.
Device mode:
This bit is undefined in device mode.</desc>
<sw_param offset="0xe0002184" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb0_PORTSC1_CCS">
<name>CCS</name>
<desc>Current Connect Status.
Host mode:
1 -&gt; Device is present on port.
0 -&gt; No device is present.
Device mode:
1 -&gt; Attached.
0 -&gt; Not Attached.</desc>
<sw_param offset="0xe0002184" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021a4" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_DPIE">
<name>DPIE</name>
<desc>Data Pulse Interrupt Enable
This bit enables the generation of an interrupt if bit DPIS is set.</desc>
<sw_param offset="0xe00021a4" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_n1msE">
<name>n1msE</name>
<desc>1 millisecond timer Interrupt Enable
This bit enables the generation of an interrupt if bit 1msS is set.</desc>
<sw_param offset="0xe00021a4" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_BSEIE">
<name>BSEIE</name>
<desc>B Session End Interrupt Enable
This bit enables the generation of an interrupt if bit BSEIS is set</desc>
<sw_param offset="0xe00021a4" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_BSVIE">
<name>BSVIE</name>
<desc>B Session Valid Interrupt Enable
This bit enables the generation of an interrupt if bit BSVIS is set.</desc>
<sw_param offset="0xe00021a4" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_ASVIE">
<name>ASVIE</name>
<desc>A Session Valid Interrupt Enable
This bit enables the generation of an interrupt if bit ASVIS is set.</desc>
<sw_param offset="0xe00021a4" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_AVVIE">
<name>AVVIE</name>
<desc>A VBus Valid Interrupt Enable
This bit enables the generation of an interrupt if bit AVVIS is set.</desc>
<sw_param offset="0xe00021a4" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_IDIE">
<name>IDIE</name>
<desc>USB ID Interrupt Enable
This bit enables the generation of an interrupt if bit IDIS is set.</desc>
<sw_param offset="0xe00021a4" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021a4" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_DPIS">
<name>DPIS</name>
<desc>Data Pulse Interrupt Status
This bit is set when data bus pulsing occurs on DP or DM. Data bus pulsing is only detected when USBMODE.CM = Host ('11b') and PORTSC0.PP = Off ('0b').
Software must write a '1' to clear this bit.</desc>
<sw_param offset="0xe00021a4" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_n1msS">
<name>n1msS</name>
<desc>1 millisecond timer Interrupt Status.
This bit is set once every millisecond. Software must write a '1' to clear this bit.</desc>
<sw_param offset="0xe00021a4" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_BSEIS">
<name>BSEIS</name>
<desc>B Session End Interrupt Status
This bit is set when VBus has fallen below the B session end threshold. Software must write a '1' to clear this bit.</desc>
<sw_param offset="0xe00021a4" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_BSVIS">
<name>BSVIS</name>
<desc>B Session Valid Interrupt Status
This bit is set when VBus has either risen above or fallen below the B session valid threshold (0.8 VDC).
Software must write a '1' to clear this bit.</desc>
<sw_param offset="0xe00021a4" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_ASVIS">
<name>ASVIS</name>
<desc>A Session Valid Interrupt Status
This bit is set when VBus has either risen above or fallen below the A session valid threshold (0.8 VDC).
Software must write a '1' to clear this bit.</desc>
<sw_param offset="0xe00021a4" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_AVVIS">
<name>AVVIS</name>
<desc>Frame IndexThis bit is set when VBus has either risen above or fallen below the VBus valid threshold
(4.4 VDC) on an A device. Software must write a '1' to clear this bit.</desc>
<sw_param offset="0xe00021a4" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_IDIS">
<name>IDIS</name>
<desc>USB ID Interrupt Status
This bit is set when a change on the ID input has been detected. Software must write a '1' to clear this bit.</desc>
<sw_param offset="0xe00021a4" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021a4" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_DPS">
<name>DPS</name>
<desc>Data Bus Pulsing Status
A '1' indicates data bus pulsing is being detected on the port.</desc>
<sw_param offset="0xe00021a4" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_n1msT">
<name>n1msT</name>
<desc>1 millisecond timer toggle
This bit toggles once per millisecond.</desc>
<sw_param offset="0xe00021a4" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_BSE">
<name>BSE</name>
<desc>B Session End
Indicates VBus is below the B session end threshold.</desc>
<sw_param offset="0xe00021a4" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_BSV">
<name>BSV</name>
<desc>B Session Valid
Indicates VBus is above the B session valid threshold.</desc>
<sw_param offset="0xe00021a4" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_ASV">
<name>ASV</name>
<desc>A Session Valid
Indicates VBus is above the A session valid threshold.</desc>
<sw_param offset="0xe00021a4" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_AVV">
<name>AVV</name>
<desc>A VBus Valid.
Indicates VBus is above the A VBus valid threshold.</desc>
<sw_param offset="0xe00021a4" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_ID">
<name>ID</name>
<desc>USB ID'0' = A device, '1' = B device.</desc>
<sw_param offset="0xe00021a4" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_HABA">
<name>HABA</name>
<desc>Hardware Assist B-Disconnect to A-connect'0' = Disabled, '1' = Enable automatic B-disconnect to A-connect sequence.</desc>
<sw_param offset="0xe00021a4" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_HADP">
<name>HADP</name>
<desc>Hardware Assist Data-Pulse
If set, the hardware assist data pulsing sequence starts.</desc>
<sw_param offset="0xe00021a4" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_IDPU">
<name>IDPU</name>
<desc>ID Pullup
This bit provide control over the ID pull-up resister.'0' = off, '1' = on. When this bit is '0' the ID input will not be sampled.</desc>
<sw_param offset="0xe00021a4" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_DP">
<name>DP</name>
<desc>Data Pulsing
Setting this bit causes the pullup on DP to be asserted for data pulsing during SRP.</desc>
<sw_param offset="0xe00021a4" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_OT">
<name>OT</name>
<desc>OTG Termination
This bit must be set when the Controller is in device mode. It controls the pulldown on DM.</desc>
<sw_param offset="0xe00021a4" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_HAAR">
<name>HAAR</name>
<desc>Hardware Assist Auto-Reset'0' = Disabled, '1' = Enable automatic reset after connect on host port.</desc>
<sw_param offset="0xe00021a4" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_VC">
<name>VC</name>
<desc>VBUS Charge
Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP.</desc>
<sw_param offset="0xe00021a4" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb0_OTGSC_VD">
<name>VD</name>
<desc>VBUS Discharge.
Setting this bit causes VBus to discharge through a resistor.</desc>
<sw_param offset="0xe00021a4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_USBMODE_SRT">
<name>SRT</name>
<desc>Shorten Reset Time
When the Controller is in host mode, this bit enables a bypass of the Chirp J/K reset handshake, saving 6-7ms in simulation time for each reset sequence. This bit should only be used for initial system integration simulations, and should always be set to 0 for
normal operation.</desc>
<sw_param offset="0xe00021a8" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_usb0_USBMODE_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021a8" start="14" end="6" />
</parameter>
<parameter uniqueid="ps7_usb0_USBMODE_VBPS">
<name>VBPS</name>
<desc>Vbus Power Select'0' -&gt; Output is '0''1' -&gt; Output is '1'This bit is connected to the vbus_pwr_select output and can be used for any generic control but is named to be used by logic that selects between an on-chip Vbus power source (charge pump) and an off-chip source in systems when both are available.
Only used in host mode.</desc>
<sw_param offset="0xe00021a8" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb0_USBMODE_SDIS">
<name>SDIS</name>
<desc>Stream Disable Mode'0' -&gt; Inactive'1' -&gt; Active
Device mode:
Setting to a '1' disables double priming on both RX and TX for low bandwidth systems.
Host Mode:
Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet.</desc>
<sw_param offset="0xe00021a8" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb0_USBMODE_SLOM">
<name>SLOM</name>
<desc>Setup Lockout Mode
This bit controls behavior of the setup lock mechanism.'0' -&gt; Setup Lockouts On.'1' -&gt; Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMD).
Only used in device mode</desc>
<sw_param offset="0xe00021a8" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_usb0_USBMODE_ES">
<name>ES</name>
<desc>Endian Select
This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.'0' Little Endian -&gt; first byte referenced in least significant byte of 32-bit word.'1' Big Endian -&gt; first byte referenced in most significant byte of 32-bit word.</desc>
<sw_param offset="0xe00021a8" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_usb0_USBMODE_CM">
<name>CM</name>
<desc>Controller Mode
Controller mode is defaulted to the proper mode for host only and device only implementations. For those designs that contain both host AND device capability (OTG),
the Controller will default to an idle state and will need to be initialized to the desired operating mode after reset. For combination host/device controllers, this register can
only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RST bit in the USBCMD register before reprogramming
this register.
Value Meaning'00b' -&gt; Idle (Default for combination host/device).'01b' -&gt; Reserved.'10b' -&gt; Controller in device mode (Default for device only controller).'11b' -&gt; Controller in host mode (Default for host only controller).</desc>
<sw_param offset="0xe00021a8" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTSETUPSTAT_ENDPTSETUPSTAT">
<name>ENDPTSETUPSTAT</name>
<desc>ENDPTSETUPSTATSetup Endpoint Status
For every setup transaction that is received, the corresponding bit in this register is set to '1'. Software must clear to acknowledge the setup transfer by writing a '1' to the respective bit after it has read the setup data from Queue Head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus timeouts if the setup lockout mechanism is engaged.
Only used in device mode.</desc>
<sw_param offset="0xe00021ac" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTPRIME_PETB">
<name>PETB</name>
<desc>Prime Endpoint Transmit Buffer - RWS. Default = 0000h.
For each endpoint a corresponding bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software
should write a '1' to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer
descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.
Note: These bits will be momentarily set by hardware during hardware re-priming operations when a dTD is retired, and the dQH is updated.
Bit 15 - Endpoint #15
...
Bit 1 - Endpoint #1
Bit 0 - Endpoint #0
Only used in device mode.</desc>
<sw_param offset="0xe00021b0" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTPRIME_PERB">
<name>PERB</name>
<desc>Prime Endpoint Receive Buffer
For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a '1' to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.
Note: These bits will be momentarily set by hardware during hardware re-priming operations when a dTD is retired, and the dQH is updated.
Bit 15 - Endpoint #15
...
Bit 1 - Endpoint #1
Bit 0 - Endpoint #0
Only used in device mode.</desc>
<sw_param offset="0xe00021b0" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTFLUSH_FETB">
<name>FETB</name>
<desc>Flush Endpoint Transmit Buffer
Writing a '1' to a bit(s) in this register will cause the associated endpoint(s) to clear any primed buffers. If a packet is in progress for one of the associated endpoints, then that
transfer will continue until completion. Hardware will clear this register after the endpoint flush operation is successful.
Bit 15 - Endpoint #15
...
Bit 1 - Endpoint #1
Bit 0 - Endpoint #0
Only used in device mode.</desc>
<sw_param offset="0xe00021b4" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTFLUSH_FERB">
<name>FERB</name>
<desc>Flush Endpoint Receive Buffer
Writing a '1' to a bit(s) will cause the associated endpoint(s) to clear any primed buffers. If a packet is in progress for one of the associated endpoints, then that transfer will
continue until completion. Hardware will clear this register after the endpoint flush operation is successful.
Bit 15 - Endpoint #15
...
Bit 1 - Endpoint #1
Bit 0 - Endpoint #0
Only used in device mode.</desc>
<sw_param offset="0xe00021b4" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTSTAT_ETBR">
<name>ETBR</name>
<desc>Endpoint Transmit Buffer Ready
One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a '1' by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay time varies based upon the current USB traffic and the number of bits set in the
ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register.
Note: These bits will be momentarily cleared by hardware during hardware endpoint repriming operations when a dTD is retired, and the dQH is updated.
Bit 15 - Endpoint #15
...
Bit 1 - Endpoint #1
Bit 0 - Endpoint #0
Only used in device mode.</desc>
<sw_param offset="0xe00021b8" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTSTAT_ERBR">
<name>ERBR</name>
<desc>Endpoint Receive Buffer Ready
One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a '1' by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay time varies based upon the current USB traffic and the number of bits set in the
ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register.
Note: These bits will be momentarily cleared by hardware during hardware endpoint repriming operations when a dTD is retired, and the dQH is updated.
Bit 15 - Endpoint #15
...
Bit 1 - Endpoint #1
Bit 0 - Endpoint #0
Only used in device mode.</desc>
<sw_param offset="0xe00021b8" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCOMPLETE_ETCE">
<name>ETCE</name>
<desc>Endpoint Transmit Complete Event
Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the
corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a '1' will clear the corresponding bit in this register.
Bit 15 - Endpoint #15
...
Bit 1 - Endpoint #1
Bit 0 - Endpoint #0
Only used in device mode.</desc>
<sw_param offset="0xe00021bc" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCOMPLETE_ERCE">
<name>ERCE</name>
<desc>Endpoint Receive Complete Event
Each bit indicates a received event (OUT) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a '1' will clear the corresponding bit in this register.
Bit 15 - Endpoint #15
...
Bit 1 - Endpoint #1
Bit 0 - Endpoint #0
Only used in device mode.</desc>
<sw_param offset="0xe00021bc" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL0_TXE">
<name>TXE</name>
<desc>TX Endpoint Enable
Endpoint0 is always enabled and this bit always set to '1'.</desc>
<sw_param offset="0xe00021c0" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL0_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021c0" start="22" end="20" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL0_TXT">
<name>TXT</name>
<desc>TX Endpoint Type
Endpoint0 is fixed as a Control End Point and this field always set to '00'.</desc>
<sw_param offset="0xe00021c0" start="19" end="18" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL0_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021c0" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL0_TXS">
<name>TXS</name>
<desc>TX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled</desc>
<sw_param offset="0xe00021c0" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL0_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021c0" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL0_RXE">
<name>RXE</name>
<desc>RX Endpoint Enable
Endpoint0 is always enabled and this bit always set to '1'.</desc>
<sw_param offset="0xe00021c0" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL0_reserved_3">
<name>reserved_3</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021c0" start="6" end="4" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL0_RXT">
<name>RXT</name>
<desc>RX Endpoint Type
Endpoint0 is fixed as a Control End Point and this field always set to '00'.</desc>
<sw_param offset="0xe00021c0" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL0_reserved_4">
<name>reserved_4</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021c0" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL0_RXS">
<name>RXS</name>
<desc>RX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled
Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request.</desc>
<sw_param offset="0xe00021c0" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL1_TXE">
<name>TXE</name>
<desc>TX Endpoint Enable
Value Meaning'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00021c4" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL1_TXR">
<name>TXR</name>
<desc>TX Data Toggle Reset
Write '1' will reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00021c4" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL1_TXI">
<name>TXI</name>
<desc>TX Data Toggle Inhibit
Value Meaning'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00021c4" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL1_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021c4" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL1_TXT">
<name>TXT</name>
<desc>TX Endpoint Type'00' -&gt; Control'01' -&gt; Isochronous'10' -&gt; Bulk'11' -&gt; Interrupt</desc>
<sw_param offset="0xe00021c4" start="19" end="18" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL1_TXD">
<name>TXD</name>
<desc>TX Endpoint Data
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00021c4" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL1_TXS">
<name>TXS</name>
<desc>TX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled</desc>
<sw_param offset="0xe00021c4" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL1_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021c4" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL1_RXE">
<name>RXE</name>
<desc>RX Endpoint Enable'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00021c4" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL1_RXR">
<name>RXR</name>
<desc>RX Data Toggle Reset
Write '1' will reset the PID sequence.
Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00021c4" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL1_RXI">
<name>RXI</name>
<desc>RX Data Toggle Inhibit'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00021c4" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL1_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021c4" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL1_RXT">
<name>RXT</name>
<desc>RX Endpoint Type
Endpoint0 is fixed as a Control End Point and this field always set to '00'.</desc>
<sw_param offset="0xe00021c4" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL1_RXD">
<name>RXD</name>
<desc>RX Endpoint Data Sink
Value Meaning
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00021c4" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL1_RXS">
<name>RXS</name>
<desc>RX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled
Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request.</desc>
<sw_param offset="0xe00021c4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL2_TXE">
<name>TXE</name>
<desc>TX Endpoint Enable
Value Meaning'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00021c8" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL2_TXR">
<name>TXR</name>
<desc>TX Data Toggle Reset
Write '1' will reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00021c8" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL2_TXI">
<name>TXI</name>
<desc>TX Data Toggle Inhibit
Value Meaning'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00021c8" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL2_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021c8" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL2_TXT">
<name>TXT</name>
<desc>TX Endpoint Type'00' -&gt; Control'01' -&gt; Isochronous'10' -&gt; Bulk'11' -&gt; Interrupt</desc>
<sw_param offset="0xe00021c8" start="19" end="18" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL2_TXD">
<name>TXD</name>
<desc>TX Endpoint Data
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00021c8" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL2_TXS">
<name>TXS</name>
<desc>TX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled</desc>
<sw_param offset="0xe00021c8" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL2_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021c8" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL2_RXE">
<name>RXE</name>
<desc>RX Endpoint Enable'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00021c8" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL2_RXR">
<name>RXR</name>
<desc>RX Data Toggle Reset
Write '1' will reset the PID sequence.
Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00021c8" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL2_RXI">
<name>RXI</name>
<desc>RX Data Toggle Inhibit'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00021c8" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL2_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021c8" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL2_RXT">
<name>RXT</name>
<desc>RX Endpoint Type
Endpoint0 is fixed as a Control End Point and this field always set to '00'.</desc>
<sw_param offset="0xe00021c8" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL2_RXD">
<name>RXD</name>
<desc>RX Endpoint Data Sink
Value Meaning
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00021c8" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL2_RXS">
<name>RXS</name>
<desc>RX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled
Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request.</desc>
<sw_param offset="0xe00021c8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL3_TXE">
<name>TXE</name>
<desc>TX Endpoint Enable
Value Meaning'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00021cc" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL3_TXR">
<name>TXR</name>
<desc>TX Data Toggle Reset
Write '1' will reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00021cc" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL3_TXI">
<name>TXI</name>
<desc>TX Data Toggle Inhibit
Value Meaning'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00021cc" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL3_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021cc" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL3_TXT">
<name>TXT</name>
<desc>TX Endpoint Type'00' -&gt; Control'01' -&gt; Isochronous'10' -&gt; Bulk'11' -&gt; Interrupt</desc>
<sw_param offset="0xe00021cc" start="19" end="18" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL3_TXD">
<name>TXD</name>
<desc>TX Endpoint Data
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00021cc" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL3_TXS">
<name>TXS</name>
<desc>TX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled</desc>
<sw_param offset="0xe00021cc" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL3_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021cc" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL3_RXE">
<name>RXE</name>
<desc>RX Endpoint Enable'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00021cc" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL3_RXR">
<name>RXR</name>
<desc>RX Data Toggle Reset
Write '1' will reset the PID sequence.
Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00021cc" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL3_RXI">
<name>RXI</name>
<desc>RX Data Toggle Inhibit'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00021cc" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL3_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021cc" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL3_RXT">
<name>RXT</name>
<desc>RX Endpoint Type
Endpoint0 is fixed as a Control End Point and this field always set to '00'.</desc>
<sw_param offset="0xe00021cc" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL3_RXD">
<name>RXD</name>
<desc>RX Endpoint Data Sink
Value Meaning
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00021cc" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL3_RXS">
<name>RXS</name>
<desc>RX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled
Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request.</desc>
<sw_param offset="0xe00021cc" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL4_TXE">
<name>TXE</name>
<desc>TX Endpoint Enable
Value Meaning'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00021d0" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL4_TXR">
<name>TXR</name>
<desc>TX Data Toggle Reset
Write '1' will reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00021d0" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL4_TXI">
<name>TXI</name>
<desc>TX Data Toggle Inhibit
Value Meaning'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00021d0" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL4_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021d0" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL4_TXT">
<name>TXT</name>
<desc>TX Endpoint Type'00' -&gt; Control'01' -&gt; Isochronous'10' -&gt; Bulk'11' -&gt; Interrupt</desc>
<sw_param offset="0xe00021d0" start="19" end="18" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL4_TXD">
<name>TXD</name>
<desc>TX Endpoint Data
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00021d0" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL4_TXS">
<name>TXS</name>
<desc>TX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled</desc>
<sw_param offset="0xe00021d0" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL4_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021d0" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL4_RXE">
<name>RXE</name>
<desc>RX Endpoint Enable'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00021d0" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL4_RXR">
<name>RXR</name>
<desc>RX Data Toggle Reset
Write '1' will reset the PID sequence.
Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00021d0" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL4_RXI">
<name>RXI</name>
<desc>RX Data Toggle Inhibit'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00021d0" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL4_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021d0" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL4_RXT">
<name>RXT</name>
<desc>RX Endpoint Type
Endpoint0 is fixed as a Control End Point and this field always set to '00'.</desc>
<sw_param offset="0xe00021d0" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL4_RXD">
<name>RXD</name>
<desc>RX Endpoint Data Sink
Value Meaning
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00021d0" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL4_RXS">
<name>RXS</name>
<desc>RX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled
Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request.</desc>
<sw_param offset="0xe00021d0" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL5_TXE">
<name>TXE</name>
<desc>TX Endpoint Enable
Value Meaning'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00021d4" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL5_TXR">
<name>TXR</name>
<desc>TX Data Toggle Reset
Write '1' will reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00021d4" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL5_TXI">
<name>TXI</name>
<desc>TX Data Toggle Inhibit
Value Meaning'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00021d4" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL5_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021d4" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL5_TXT">
<name>TXT</name>
<desc>TX Endpoint Type'00' -&gt; Control'01' -&gt; Isochronous'10' -&gt; Bulk'11' -&gt; Interrupt</desc>
<sw_param offset="0xe00021d4" start="19" end="18" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL5_TXD">
<name>TXD</name>
<desc>TX Endpoint Data
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00021d4" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL5_TXS">
<name>TXS</name>
<desc>TX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled</desc>
<sw_param offset="0xe00021d4" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL5_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021d4" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL5_RXE">
<name>RXE</name>
<desc>RX Endpoint Enable'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00021d4" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL5_RXR">
<name>RXR</name>
<desc>RX Data Toggle Reset
Write '1' will reset the PID sequence.
Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00021d4" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL5_RXI">
<name>RXI</name>
<desc>RX Data Toggle Inhibit'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00021d4" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL5_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021d4" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL5_RXT">
<name>RXT</name>
<desc>RX Endpoint Type
Endpoint0 is fixed as a Control End Point and this field always set to '00'.</desc>
<sw_param offset="0xe00021d4" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL5_RXD">
<name>RXD</name>
<desc>RX Endpoint Data Sink
Value Meaning
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00021d4" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL5_RXS">
<name>RXS</name>
<desc>RX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled
Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request.</desc>
<sw_param offset="0xe00021d4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL6_TXE">
<name>TXE</name>
<desc>TX Endpoint Enable
Value Meaning'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00021d8" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL6_TXR">
<name>TXR</name>
<desc>TX Data Toggle Reset
Write '1' will reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00021d8" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL6_TXI">
<name>TXI</name>
<desc>TX Data Toggle Inhibit
Value Meaning'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00021d8" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL6_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021d8" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL6_TXT">
<name>TXT</name>
<desc>TX Endpoint Type'00' -&gt; Control'01' -&gt; Isochronous'10' -&gt; Bulk'11' -&gt; Interrupt</desc>
<sw_param offset="0xe00021d8" start="19" end="18" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL6_TXD">
<name>TXD</name>
<desc>TX Endpoint Data
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00021d8" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL6_TXS">
<name>TXS</name>
<desc>TX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled</desc>
<sw_param offset="0xe00021d8" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL6_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021d8" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL6_RXE">
<name>RXE</name>
<desc>RX Endpoint Enable'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00021d8" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL6_RXR">
<name>RXR</name>
<desc>RX Data Toggle Reset
Write '1' will reset the PID sequence.
Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00021d8" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL6_RXI">
<name>RXI</name>
<desc>RX Data Toggle Inhibit'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00021d8" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL6_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021d8" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL6_RXT">
<name>RXT</name>
<desc>RX Endpoint Type
Endpoint0 is fixed as a Control End Point and this field always set to '00'.</desc>
<sw_param offset="0xe00021d8" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL6_RXD">
<name>RXD</name>
<desc>RX Endpoint Data Sink
Value Meaning
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00021d8" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL6_RXS">
<name>RXS</name>
<desc>RX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled
Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request.</desc>
<sw_param offset="0xe00021d8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL7_TXE">
<name>TXE</name>
<desc>TX Endpoint Enable
Value Meaning'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00021dc" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL7_TXR">
<name>TXR</name>
<desc>TX Data Toggle Reset
Write '1' will reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00021dc" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL7_TXI">
<name>TXI</name>
<desc>TX Data Toggle Inhibit
Value Meaning'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00021dc" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL7_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021dc" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL7_TXT">
<name>TXT</name>
<desc>TX Endpoint Type'00' -&gt; Control'01' -&gt; Isochronous'10' -&gt; Bulk'11' -&gt; Interrupt</desc>
<sw_param offset="0xe00021dc" start="19" end="18" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL7_TXD">
<name>TXD</name>
<desc>TX Endpoint Data
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00021dc" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL7_TXS">
<name>TXS</name>
<desc>TX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled</desc>
<sw_param offset="0xe00021dc" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL7_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021dc" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL7_RXE">
<name>RXE</name>
<desc>RX Endpoint Enable'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00021dc" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL7_RXR">
<name>RXR</name>
<desc>RX Data Toggle Reset
Write '1' will reset the PID sequence.
Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00021dc" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL7_RXI">
<name>RXI</name>
<desc>RX Data Toggle Inhibit'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00021dc" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL7_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021dc" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL7_RXT">
<name>RXT</name>
<desc>RX Endpoint Type
Endpoint0 is fixed as a Control End Point and this field always set to '00'.</desc>
<sw_param offset="0xe00021dc" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL7_RXD">
<name>RXD</name>
<desc>RX Endpoint Data Sink
Value Meaning
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00021dc" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL7_RXS">
<name>RXS</name>
<desc>RX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled
Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request.</desc>
<sw_param offset="0xe00021dc" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL8_TXE">
<name>TXE</name>
<desc>TX Endpoint Enable
Value Meaning'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00021e0" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL8_TXR">
<name>TXR</name>
<desc>TX Data Toggle Reset
Write '1' will reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00021e0" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL8_TXI">
<name>TXI</name>
<desc>TX Data Toggle Inhibit
Value Meaning'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00021e0" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL8_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021e0" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL8_TXT">
<name>TXT</name>
<desc>TX Endpoint Type'00' -&gt; Control'01' -&gt; Isochronous'10' -&gt; Bulk'11' -&gt; Interrupt</desc>
<sw_param offset="0xe00021e0" start="19" end="18" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL8_TXD">
<name>TXD</name>
<desc>TX Endpoint Data
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00021e0" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL8_TXS">
<name>TXS</name>
<desc>TX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled</desc>
<sw_param offset="0xe00021e0" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL8_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021e0" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL8_RXE">
<name>RXE</name>
<desc>RX Endpoint Enable'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00021e0" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL8_RXR">
<name>RXR</name>
<desc>RX Data Toggle Reset
Write '1' will reset the PID sequence.
Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00021e0" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL8_RXI">
<name>RXI</name>
<desc>RX Data Toggle Inhibit'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00021e0" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL8_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021e0" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL8_RXT">
<name>RXT</name>
<desc>RX Endpoint Type
Endpoint0 is fixed as a Control End Point and this field always set to '00'.</desc>
<sw_param offset="0xe00021e0" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL8_RXD">
<name>RXD</name>
<desc>RX Endpoint Data Sink
Value Meaning
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00021e0" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL8_RXS">
<name>RXS</name>
<desc>RX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled
Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request.</desc>
<sw_param offset="0xe00021e0" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL9_TXE">
<name>TXE</name>
<desc>TX Endpoint Enable
Value Meaning'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00021e4" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL9_TXR">
<name>TXR</name>
<desc>TX Data Toggle Reset
Write '1' will reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00021e4" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL9_TXI">
<name>TXI</name>
<desc>TX Data Toggle Inhibit
Value Meaning'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00021e4" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL9_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021e4" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL9_TXT">
<name>TXT</name>
<desc>TX Endpoint Type'00' -&gt; Control'01' -&gt; Isochronous'10' -&gt; Bulk'11' -&gt; Interrupt</desc>
<sw_param offset="0xe00021e4" start="19" end="18" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL9_TXD">
<name>TXD</name>
<desc>TX Endpoint Data
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00021e4" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL9_TXS">
<name>TXS</name>
<desc>TX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled</desc>
<sw_param offset="0xe00021e4" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL9_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021e4" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL9_RXE">
<name>RXE</name>
<desc>RX Endpoint Enable'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00021e4" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL9_RXR">
<name>RXR</name>
<desc>RX Data Toggle Reset
Write '1' will reset the PID sequence.
Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00021e4" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL9_RXI">
<name>RXI</name>
<desc>RX Data Toggle Inhibit'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00021e4" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL9_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021e4" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL9_RXT">
<name>RXT</name>
<desc>RX Endpoint Type
Endpoint0 is fixed as a Control End Point and this field always set to '00'.</desc>
<sw_param offset="0xe00021e4" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL9_RXD">
<name>RXD</name>
<desc>RX Endpoint Data Sink
Value Meaning
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00021e4" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL9_RXS">
<name>RXS</name>
<desc>RX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled
Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request.</desc>
<sw_param offset="0xe00021e4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL10_TXE">
<name>TXE</name>
<desc>TX Endpoint Enable
Value Meaning'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00021e8" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL10_TXR">
<name>TXR</name>
<desc>TX Data Toggle Reset
Write '1' will reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00021e8" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL10_TXI">
<name>TXI</name>
<desc>TX Data Toggle Inhibit
Value Meaning'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00021e8" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL10_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021e8" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL10_TXT">
<name>TXT</name>
<desc>TX Endpoint Type'00' -&gt; Control'01' -&gt; Isochronous'10' -&gt; Bulk'11' -&gt; Interrupt</desc>
<sw_param offset="0xe00021e8" start="19" end="18" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL10_TXD">
<name>TXD</name>
<desc>TX Endpoint Data
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00021e8" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL10_TXS">
<name>TXS</name>
<desc>TX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled</desc>
<sw_param offset="0xe00021e8" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL10_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021e8" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL10_RXE">
<name>RXE</name>
<desc>RX Endpoint Enable'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00021e8" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL10_RXR">
<name>RXR</name>
<desc>RX Data Toggle Reset
Write '1' will reset the PID sequence.
Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00021e8" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL10_RXI">
<name>RXI</name>
<desc>RX Data Toggle Inhibit'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00021e8" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL10_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021e8" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL10_RXT">
<name>RXT</name>
<desc>RX Endpoint Type
Endpoint0 is fixed as a Control End Point and this field always set to '00'.</desc>
<sw_param offset="0xe00021e8" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL10_RXD">
<name>RXD</name>
<desc>RX Endpoint Data Sink
Value Meaning
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00021e8" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL10_RXS">
<name>RXS</name>
<desc>RX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled
Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request.</desc>
<sw_param offset="0xe00021e8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL11_TXE">
<name>TXE</name>
<desc>TX Endpoint Enable
Value Meaning'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00021ec" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL11_TXR">
<name>TXR</name>
<desc>TX Data Toggle Reset
Write '1' will reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00021ec" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL11_TXI">
<name>TXI</name>
<desc>TX Data Toggle Inhibit
Value Meaning'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00021ec" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL11_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021ec" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL11_TXT">
<name>TXT</name>
<desc>TX Endpoint Type'00' -&gt; Control'01' -&gt; Isochronous'10' -&gt; Bulk'11' -&gt; Interrupt</desc>
<sw_param offset="0xe00021ec" start="19" end="18" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL11_TXD">
<name>TXD</name>
<desc>TX Endpoint Data
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00021ec" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL11_TXS">
<name>TXS</name>
<desc>TX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled</desc>
<sw_param offset="0xe00021ec" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL11_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021ec" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL11_RXE">
<name>RXE</name>
<desc>RX Endpoint Enable'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00021ec" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL11_RXR">
<name>RXR</name>
<desc>RX Data Toggle Reset
Write '1' will reset the PID sequence.
Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00021ec" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL11_RXI">
<name>RXI</name>
<desc>RX Data Toggle Inhibit'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00021ec" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL11_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021ec" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL11_RXT">
<name>RXT</name>
<desc>RX Endpoint Type
Endpoint0 is fixed as a Control End Point and this field always set to '00'.</desc>
<sw_param offset="0xe00021ec" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL11_RXD">
<name>RXD</name>
<desc>RX Endpoint Data Sink
Value Meaning
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00021ec" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL11_RXS">
<name>RXS</name>
<desc>RX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled
Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request.</desc>
<sw_param offset="0xe00021ec" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL12_TXE">
<name>TXE</name>
<desc>TX Endpoint Enable
Value Meaning'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00021f0" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL12_TXR">
<name>TXR</name>
<desc>TX Data Toggle Reset
Write '1' will reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00021f0" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL12_TXI">
<name>TXI</name>
<desc>TX Data Toggle Inhibit
Value Meaning'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00021f0" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL12_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021f0" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL12_TXT">
<name>TXT</name>
<desc>TX Endpoint Type'00' -&gt; Control'01' -&gt; Isochronous'10' -&gt; Bulk'11' -&gt; Interrupt</desc>
<sw_param offset="0xe00021f0" start="19" end="18" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL12_TXD">
<name>TXD</name>
<desc>TX Endpoint Data
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00021f0" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL12_TXS">
<name>TXS</name>
<desc>TX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled</desc>
<sw_param offset="0xe00021f0" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL12_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021f0" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL12_RXE">
<name>RXE</name>
<desc>RX Endpoint Enable'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00021f0" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL12_RXR">
<name>RXR</name>
<desc>RX Data Toggle Reset
Write '1' will reset the PID sequence.
Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00021f0" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL12_RXI">
<name>RXI</name>
<desc>RX Data Toggle Inhibit'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00021f0" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL12_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe00021f0" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL12_RXT">
<name>RXT</name>
<desc>RX Endpoint Type
Endpoint0 is fixed as a Control End Point and this field always set to '00'.</desc>
<sw_param offset="0xe00021f0" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL12_RXD">
<name>RXD</name>
<desc>RX Endpoint Data Sink
Value Meaning
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00021f0" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb0_ENDPTCTRL12_RXS">
<name>RXS</name>
<desc>RX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled
Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request.</desc>
<sw_param offset="0xe00021f0" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_ID_CIVERSION">
<name>CIVERSION</name>
<desc>Identifies the CI version</desc>
<sw_param offset="0xe0003000" start="31" end="29" />
</parameter>
<parameter uniqueid="ps7_usb1_ID_VERSION">
<name>VERSION</name>
<desc>Identifies the version of the core</desc>
<sw_param offset="0xe0003000" start="28" end="25" />
</parameter>
<parameter uniqueid="ps7_usb1_ID_REVISION">
<name>REVISION</name>
<desc>Revision number of the core</desc>
<sw_param offset="0xe0003000" start="24" end="21" />
</parameter>
<parameter uniqueid="ps7_usb1_ID_TAG">
<name>TAG</name>
<desc>Identifies the tag of the core ; Current 2.20a version</desc>
<sw_param offset="0xe0003000" start="20" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_ID_reserved">
<name>reserved</name>
<desc>RESERVED. Writes are ignored</desc>
<sw_param offset="0xe0003000" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_usb1_ID_NID">
<name>NID</name>
<desc>NID Complement of ID; Ones complement version of ID</desc>
<sw_param offset="0xe0003000" start="13" end="8" />
</parameter>
<parameter uniqueid="ps7_usb1_ID_reserved_1">
<name>reserved_1</name>
<desc>RESERVED. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xe0003000" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_usb1_ID_ID">
<name>ID</name>
<desc>ID Configuration number ; This number indicates the type of the USB-HS 2.0 core.</desc>
<sw_param offset="0xe0003000" start="5" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_HWGENERAL_SM">
<name>SM</name>
<desc>VUSB_HS_PHY_SERIAL - This constant selects that the serial engine is used or not.
0 - No Serial Engine- Always use parallel signalling</desc>
<sw_param offset="0xe0003004" start="11" end="10" />
</parameter>
<parameter uniqueid="ps7_usb1_HWGENERAL_PHYM">
<name>PHYM</name>
<desc>VUSB_HS_PHY_TYPE
- PHY interface type.
2 = ULPI</desc>
<sw_param offset="0xe0003004" start="9" end="6" />
</parameter>
<parameter uniqueid="ps7_usb1_HWGENERAL_PHYW">
<name>PHYW</name>
<desc>VUSB_HS_PHY16_8 - This constant selects which phy is being used.
0 = 8 bit wide data bus [60MHz clock from the transciever]</desc>
<sw_param offset="0xe0003004" start="5" end="4" />
</parameter>
<parameter uniqueid="ps7_usb1_HWGENERAL_BWT">
<name>BWT</name>
<desc>RESERVED.</desc>
<sw_param offset="0xe0003004" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_usb1_HWGENERAL_CLKC">
<name>CLKC</name>
<desc>VUSB_HS_CLOCK_CONFIGURATION - constant determines the clocking used in the core.
1 = xcvr_clk_0 &lt; pe_clk = clk</desc>
<sw_param offset="0xe0003004" start="2" end="1" />
</parameter>
<parameter uniqueid="ps7_usb1_HWGENERAL_RT">
<name>RT</name>
<desc>VUSB_HS_RESET_TYPE - Reset Type.
1 = Use Asynchronous Resets</desc>
<sw_param offset="0xe0003004" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_HWHOST_TTPER">
<name>TTPER</name>
<desc>VUSB_HS_TT_PERIODIC_CONTEXTS</desc>
<sw_param offset="0xe0003008" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_usb1_HWHOST_TTASY">
<name>TTASY</name>
<desc>VUSB_HS_TT_ASYNC_CONTEXTS</desc>
<sw_param offset="0xe0003008" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_HWHOST_a">
<name>a</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0003008" start="15" end="4" />
</parameter>
<parameter uniqueid="ps7_usb1_HWHOST_NPORT">
<name>NPORT</name>
<desc>VUSB_HS_NUM_PORT-1.
1- The VUSB_HS_NUM_PORT constant specifies the number of downstream ports by host port</desc>
<sw_param offset="0xe0003008" start="3" end="1" />
</parameter>
<parameter uniqueid="ps7_usb1_HWHOST_HC">
<name>HC</name>
<desc>VUSB_HS_HOST</desc>
<sw_param offset="0xe0003008" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_HWDEVICE_DEVEP">
<name>DEVEP</name>
<desc>VUSB_HS_DEV_EP - Number of endpoints.
12 = VUSB_HS_DEV_EP constant represents the 12 number of endpoints</desc>
<sw_param offset="0xe000300c" start="5" end="1" />
</parameter>
<parameter uniqueid="ps7_usb1_HWDEVICE_DC">
<name>DC</name>
<desc>Device capable</desc>
<sw_param offset="0xe000300c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_HWTXBUF_reserved_1">
<name>reserved_1</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0003010" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_usb1_HWTXBUF_reserved">
<name>reserved</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0003010" start="30" end="24" />
</parameter>
<parameter uniqueid="ps7_usb1_HWTXBUF_TXCHANADD">
<name>TXCHANADD</name>
<desc>VUSB_HS_TX_CHAN_ADD - Address bits for each Endpoint; 64 words buffer for each end point.
6 - To address 64 depth TX buffer for each end point</desc>
<sw_param offset="0xe0003010" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_HWTXBUF_TXADD">
<name>TXADD</name>
<desc>VUSB_HS_TX_ADD ; 768 Depth TX buffer.
10- Address of the depoth of TX buffer</desc>
<sw_param offset="0xe0003010" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb1_HWTXBUF_TXBURST">
<name>TXBURST</name>
<desc>VUSB_HS_TX_BURST. Burst size for Memory To TX Buffer Transfers</desc>
<sw_param offset="0xe0003010" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_HWRXBUF_a">
<name>a</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0003014" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_usb1_HWRXBUF_RXADD">
<name>RXADD</name>
<desc>VUSB_HS_RX_ADD ; 768 Depth TX buffer.
10- Address of the depoth of TX buffer</desc>
<sw_param offset="0xe0003014" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb1_HWRXBUF_RXBURST">
<name>RXBURST</name>
<desc>VUSB_HS_RX_BURST.
16 = Burst size of 16 for Memory To TX Buffer Transfers</desc>
<sw_param offset="0xe0003014" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_GPTIMER0LD_GPTLD">
<name>GPTLD</name>
<desc>General Purpose Timer Load Value register.
This field is the value to be loaded into the GPTCNT countdown timer on a reset action. The value in this register represents the time in microseconds minus 1 for the timer duration.
Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7.
Note: Max value is 0xFFFFFF or 16.777215 seconds</desc>
<sw_param offset="0xe0003080" start="23" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_GPTIMER0CTRL_GPTRUN">
<name>GPTRUN</name>
<desc>General Purpose Timer Run. This bit enables the general-purpose timer to run. Setting or clearing this bit will not have an effect on the GPTCNT counter value.</desc>
<sw_param offset="0xe0003084" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_usb1_GPTIMER0CTRL_GPTRST">
<name>GPTRST</name>
<desc>General Purpose Timer Reset. Writing a one to this bit will reload the GPTCNT with the value in GPTLD.</desc>
<sw_param offset="0xe0003084" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_usb1_GPTIMER0CTRL_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xe0003084" start="29" end="25" />
</parameter>
<parameter uniqueid="ps7_usb1_GPTIMER0CTRL_GPTMODE">
<name>GPTMODE</name>
<desc>0b' - One Shot; '1b' - Repeat. This bit selects between a single timer countdown and a looped countdown. In one-shot mode, the timer will count down to zero, generate an interrupt and stop until the counter is reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the counter to begin again.</desc>
<sw_param offset="0xe0003084" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_usb1_GPTIMER0CTRL_GPTCNT">
<name>GPTCNT</name>
<desc>General Purpose Timer Counter.
This field is the value of the running timer.</desc>
<sw_param offset="0xe0003084" start="23" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_GPTIMER1LD_GPTLD">
<name>GPTLD</name>
<desc>General Purpose Timer Load Value register.
This field is the value to be loaded into the GPTCNT countdown timer on a reset action. The value in this register represents the time in microseconds minus 1 for the timer duration.
Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7.
Note: Max value is 0xFFFFFF or 16.777215 seconds</desc>
<sw_param offset="0xe0003088" start="23" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_GPTIMER1CTRL_GPTRUN">
<name>GPTRUN</name>
<desc>General Purpose Timer Run. This bit enables the general-purpose timer to run. Setting or clearing this bit will not have an effect on the GPTCNT counter value.</desc>
<sw_param offset="0xe000308c" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_usb1_GPTIMER1CTRL_GPTRST">
<name>GPTRST</name>
<desc>General Purpose Timer Reset. Writing a one to this bit will reload the GPTCNT with the value in GPTLD.</desc>
<sw_param offset="0xe000308c" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_usb1_GPTIMER1CTRL_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xe000308c" start="29" end="25" />
</parameter>
<parameter uniqueid="ps7_usb1_GPTIMER1CTRL_GPTMODE">
<name>GPTMODE</name>
<desc>0b' - One Shot; '1b' - Repeat. This bit selects between a single timer countdown and a looped countdown. In one-shot mode, the timer will count down to zero, generate an interrupt and stop until the counter is reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the counter to begin again.</desc>
<sw_param offset="0xe000308c" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_usb1_GPTIMER1CTRL_GPTCNT">
<name>GPTCNT</name>
<desc>General Purpose Timer Counter.
This field is the value of the running timer.</desc>
<sw_param offset="0xe000308c" start="23" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_SBUSCFG_AHBBRST">
<name>AHBBRST</name>
<desc>VUSB_HS_RX_BURST
0: incremental bursts of unspecified length
1: INCR4, non multiple transfers of 4 are decomposed to singles
2: INCR8, non multiple transfers of 8 are decomposed to INCR4 or singles
3: INCR16, non multiple transfers of 16 are decomposed to INCR8, INCR4 or singles
4: Do not use this value!
5: INCR4, non multiple transfers of 4 are decomposed to INCR of unspecifed length
6: INCR8, non multiple transfers of 8 are decomposed to INCR4 or INCR of unspecifed length
7: INCR16, non multiple transfers of 16 are decomposed to INCR8, INCR4 or INCR of unspecifed length</desc>
<sw_param offset="0xe0003090" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_CAPLENGTH_HCIVERSION_HCIVERSION">
<name>HCIVERSION</name>
<desc>This is a two-byte register containing a BCD encoding of the EHCI revision number supported by this host controller. The most significant byte of this register represents a major revision and the least significant byte is the minor revision.</desc>
<sw_param offset="0xe0003100" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_CAPLENGTH_HCIVERSION_CAPLENGTH">
<name>CAPLENGTH</name>
<desc>This register indicates capability register length. This register is used to indicate which offset to add to the register base address at the beginning of the Operational Register</desc>
<sw_param offset="0xe0003100" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_HCSPARAMS_N_TT">
<name>N_TT</name>
<desc>This field indicates the number of embedded transaction translators associated with the USB2.0 host controller. For Multi-Port Host this field will always be equal to '0001b'. For all other implementation, N_TT = '0000b'.
This field will always be '0'</desc>
<sw_param offset="0xe0003104" start="27" end="24" />
</parameter>
<parameter uniqueid="ps7_usb1_HCSPARAMS_N_PTT">
<name>N_PTT</name>
<desc>Number of Ports per Transaction Translator. This field indicates the number of ports assigned to each transaction translator within the USB2.0 host controller.
For Multi-Port Host this field will always equal N_PORTS. For all other implementations, N_PTT = '0000b'.
This in a non-EHCI field to support embedded TT.</desc>
<sw_param offset="0xe0003104" start="23" end="20" />
</parameter>
<parameter uniqueid="ps7_usb1_HCSPARAMS_reserved_1">
<name>reserved_1</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0003104" start="19" end="17" />
</parameter>
<parameter uniqueid="ps7_usb1_HCSPARAMS_PI">
<name>PI</name>
<desc>Port indicator. This bit indicates whether the ports support port indicator control. When set to one, the
port status and control registers include a read/writable field for controlling the state of
the port indicator. This field will always be '1'</desc>
<sw_param offset="0xe0003104" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_HCSPARAMS_N_CC">
<name>N_CC</name>
<desc>This field indicates the number of companion controllers associated with this USB2.0 host controller. A zero in this field indicates there are no internal Companion Controllers. Portownership
hand-off is not supported. A value larger than zero in this field indicates there are companion USB1.1 host controller(s). Port-ownership hand-offs are supported. High, Full and Low speed devices are supported on the host controller root ports.</desc>
<sw_param offset="0xe0003104" start="15" end="12" />
</parameter>
<parameter uniqueid="ps7_usb1_HCSPARAMS_N_PCC">
<name>N_PCC</name>
<desc>This field indicates the number of ports supported per internal Companion Controller. It is used to indicate the port routing configuration to the system software.</desc>
<sw_param offset="0xe0003104" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_usb1_HCSPARAMS_reserved">
<name>reserved</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0003104" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_usb1_HCSPARAMS_PPC">
<name>PPC</name>
<desc>Port Power Control. This field indicates whether the host controller implementation includes port power control.
1 =indicates the ports have port power switches.
0 = indicates the ports do not have port power switches.</desc>
<sw_param offset="0xe0003104" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb1_HCSPARAMS_N_PORTS">
<name>N_PORTS</name>
<desc>Number of downstream ports supported by the host controller</desc>
<sw_param offset="0xe0003104" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_HCCPARAMS_EECP">
<name>EECP</name>
<desc>No Description</desc>
<sw_param offset="0xe0003108" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb1_HCCPARAMS_IST">
<name>IST</name>
<desc>Isochronous Scheduling Threshold.
This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule. When bit [7] is zero, the value of the least significant 3 bits indicates the number of micro-frames a host controller can hold a set of isochronous data structures (one or more) before flushing the state. When bit [7] is a one, then host software assumes the host controller may cache an isochronous data structure for an entire frame.
This field will always be 4'b0</desc>
<sw_param offset="0xe0003108" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_usb1_HCCPARAMS_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xe0003108" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_usb1_HCCPARAMS_ASP">
<name>ASP</name>
<desc>Asynchronous Schedule Park Capability. If this bit is set to a one, then the host controller supports the park feature for highspeed queue heads in the Asynchronous Schedule. The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode
Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register.
This field will always be '1'</desc>
<sw_param offset="0xe0003108" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_usb1_HCCPARAMS_PFL">
<name>PFL</name>
<desc>If this bit is set to zero, then the system software must use a frame list length of 1024 elements with this host controller. The USBCMD register Frame List Size field is a read-only register and must be set to zero.
If set to a one, then the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K-page boundary. This field will always be '1'</desc>
<sw_param offset="0xe0003108" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb1_HCCPARAMS_ADC">
<name>ADC</name>
<desc>64-bit Addressing Capability. For thi scontroller its always 0</desc>
<sw_param offset="0xe0003108" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_DCIVERSION_DCIVERSION">
<name>DCIVERSION</name>
<desc>The device controller interface conforms to the two-byte BCD encoding of the interface version number
contained in this register</desc>
<sw_param offset="0xe0003120" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_DCCPARAMS_HC">
<name>HC</name>
<desc>Host Capable. When this bit is 1, this controller is capable of operating as an EHCI compatible USB
2.0 host controller
1= The controller is USB 2.0 host controller capable</desc>
<sw_param offset="0xe0003124" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_usb1_DCCPARAMS_DC">
<name>DC</name>
<desc>Device Capable register. When this bit is 1, this controller is capable of operating as a USB 2.0 device.
1= The controller is USB 2.0 device capable</desc>
<sw_param offset="0xe0003124" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb1_DCCPARAMS_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xe0003124" start="6" end="5" />
</parameter>
<parameter uniqueid="ps7_usb1_DCCPARAMS_DEN">
<name>DEN</name>
<desc>This field indicates the number of endpoints built into the device controller.
12 = 12 endpoints are supported</desc>
<sw_param offset="0xe0003124" start="4" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_USBCMD_ITC">
<name>ITC</name>
<desc>Interrupt Threshold Control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts.
00h Immediate (no threshold)
01h 1 micro-frame
02h 2 micro-frames
04h 4 micro-frames
08h 8 micro-frames
10h 16 micro-frames
20h 32 micro-frames
40h 64 micro-frames</desc>
<sw_param offset="0xe0003140" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_USBCMD_FS2">
<name>FS2</name>
<desc>MSB bit of FS field.</desc>
<sw_param offset="0xe0003140" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_usb1_USBCMD_ATDTW">
<name>ATDTW</name>
<desc>This bit is used as a semaphore to ensure the proper addition of a new dTD to an active (primed) endpoint's linked list.</desc>
<sw_param offset="0xe0003140" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_usb1_USBCMD_SUTW">
<name>SUTW</name>
<desc>Setup TripWir. This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is
extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (See USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists.
Used only in device Mode</desc>
<sw_param offset="0xe0003140" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_usb1_USBCMD_reserved">
<name>reserved</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0003140" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_usb1_USBCMD_ASPE">
<name>ASPE</name>
<desc>If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1b and is R/W. Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled.
This field is set to '1'b in this implementation. Only used in host mode.</desc>
<sw_param offset="0xe0003140" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_usb1_USBCMD_reserved_1">
<name>reserved_1</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0003140" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_usb1_USBCMD_ASP">
<name>ASP</name>
<desc>If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is RO. It contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before
continuing traversal of the Asynchronous schedule.
This field is set to 3h in this implementation.
Only used in host mode.</desc>
<sw_param offset="0xe0003140" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_usb1_USBCMD_LR">
<name>LR</name>
<desc>Light Host/Device Controller Reset. This field will always be '0b'.</desc>
<sw_param offset="0xe0003140" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb1_USBCMD_IAA">
<name>IAA</name>
<desc>This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances the asynchronous schedule. Software must write a '1b' to this bit to ring the doorbell. This is used only in Host mode</desc>
<sw_param offset="0xe0003140" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb1_USBCMD_ASE">
<name>ASE</name>
<desc>This bit controls whether the host controller skips processing the Asynchronous Schedule.
Values Meaning :
0- Do not process the Asynchronous Schedule.
1- Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
Only used in host mode.</desc>
<sw_param offset="0xe0003140" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb1_USBCMD_PSE">
<name>PSE</name>
<desc>This bit controls whether the host controller skips processing the Periodic Schedule. Values Meaning
0 -&gt; Do not process the Periodic Schedule
1 -&gt; Use the PERIODICLISTBASE register to access the Periodic Schedule.
Only used in host mode.</desc>
<sw_param offset="0xe0003140" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb1_USBCMD_FS0">
<name>FS0</name>
<desc>reserved
0 -&gt; 1024 elements (4096 bytes)
1 -&gt; 512 elements (2048 bytes)
2 -&gt; 256 elements (1024 bytes)
3 -&gt; 128 elements (512 bytes)
4 -&gt; 64 elements (256 bytes)
5 -&gt; 32 elements (128 bytes)
6 -&gt;16 elements (64 bytes)
7 -&gt; 8 elements (32 bytes)</desc>
<sw_param offset="0xe0003140" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_usb1_USBCMD_RST">
<name>RST</name>
<desc>Software uses this bit to reset the controller. This bit is set to zero by the Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.</desc>
<sw_param offset="0xe0003140" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb1_USBCMD_RS">
<name>RS</name>
<desc>Run/Stop bit , When set to a 1, the Controller proceeds with the execution of the schedule.</desc>
<sw_param offset="0xe0003140" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_USBSTS_TI1">
<name>TI1</name>
<desc>This bit is set when the counter in the GPTIMER1CTRL register transitions to zero. Writing a one to this bit will clear it.</desc>
<sw_param offset="0xe0003144" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_usb1_USBSTS_TI0">
<name>TI0</name>
<desc>This bit is set when the counter in the GPTIMER0CTRL register transitions to zero.
Writing a one to this bit will clear it.</desc>
<sw_param offset="0xe0003144" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_usb1_USBSTS_reserved">
<name>reserved</name>
<desc>T</desc>
<sw_param offset="0xe0003144" start="23" end="20" />
</parameter>
<parameter uniqueid="ps7_usb1_USBSTS_UPI">
<name>UPI</name>
<desc>This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule.
This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than expected.
This bit is not used by the device controller and will always be zero.</desc>
<sw_param offset="0xe0003144" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_usb1_USBSTS_UAI">
<name>UAI</name>
<desc>USB Host Asynchronous Interrupt . This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule.
This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than expected.
This bit is not used by the device controller and will always be zero.</desc>
<sw_param offset="0xe0003144" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_usb1_USBSTS_reserved_1">
<name>reserved_1</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0003144" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb1_USBSTS_NAKI">
<name>NAKI</name>
<desc>NAK Interrupt. This bit is read-only. It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared. This bit is not used by the host controller and will always be zero.</desc>
<sw_param offset="0xe0003144" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_USBSTS_AS">
<name>AS</name>
<desc>This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled.
The Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0).
Only used in host mode.</desc>
<sw_param offset="0xe0003144" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_usb1_USBSTS_PS">
<name>PS</name>
<desc>Periodic Schedule Status. This bit reports the current real status of the Periodic Schedule. When set to zero the
periodic schedule is disabled, and if set to one the status is enabled. The Controller is not required to immediately disable or enable the Periodic Schedule when software
transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0).
Only used in host mode.</desc>
<sw_param offset="0xe0003144" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_usb1_USBSTS_RCL">
<name>RCL</name>
<desc>Reclamation. This is a read-only status bit used to detect an empty asynchronous schedule. Used in Host mode only</desc>
<sw_param offset="0xe0003144" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_usb1_USBSTS_HCH">
<name>HCH</name>
<desc>HCHaIted. This bit is a zero whenever the Run/Stop bit is a one. The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Controller hardware (e.g. internal error).
Only used in host mode.</desc>
<sw_param offset="0xe0003144" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_usb1_USBSTS_reserved_2">
<name>reserved_2</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0003144" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_usb1_USBSTS_ULPII">
<name>ULPII</name>
<desc>ULPI Interrupt. When the ULPI Viewport is present in the design, an event completion will set this interrupt.</desc>
<sw_param offset="0xe0003144" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_usb1_USBSTS_reserved_3">
<name>reserved_3</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0003144" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_usb1_USBSTS_SLI">
<name>SLI</name>
<desc>DCSuspend. When a device controller enters a suspend state from an active state, this bit will be set to a one. This bit is only cleared by software writing a 1 to it.
Only used in device mode.</desc>
<sw_param offset="0xe0003144" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_usb1_USBSTS_SRI">
<name>SRI</name>
<desc>SOF Received. When the device controller detects a Start Of (u)Frame, this bit will be set to a one.
When a SOF is extremely late, the Controller, when in device mode, will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1ms in FS mode and every 125us in HS mode and will be synchronized to the actual SOF that is received.
Since the Controller when in device mode is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp.
In host mode, this bit will be set every 125us and can be used by host controller driver as a time base.
Software writes a 1 to this bit to clear it.</desc>
<sw_param offset="0xe0003144" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb1_USBSTS_URI">
<name>URI</name>
<desc>USB Reset Received. When the Controller detects a USB Reset and enters the default state, this bit will be set to a one. Software can write a 1 to this bit to clear the USB Reset Received status bit.
Only used in device mode.</desc>
<sw_param offset="0xe0003144" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb1_USBSTS_AAI">
<name>AAI</name>
<desc>Interrupt on Async Advance. System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the
assertion of that interrupt source.
Only used in host mode.</desc>
<sw_param offset="0xe0003144" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb1_USBSTS_SEI">
<name>SEI</name>
<desc>System Error. In the BVCI implementation of the USBHS core, this bit is not used, and will always be
cleared to '0b'. In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface</desc>
<sw_param offset="0xe0003144" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb1_USBSTS_FRI">
<name>FRI</name>
<desc>Frame List Rollover
The Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX[13] toggles. Similarly, if the size is 512, the Controller sets this bit to a one every time FRINDEX[12] toggles. Only used in host mode.</desc>
<sw_param offset="0xe0003144" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_usb1_USBSTS_PCI">
<name>PCI</name>
<desc>Port Change Detect. The Controller in host mode sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port.
The Controller in device mode sets this bit to a one when it detects resume signaling or the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit and the DCSuspend bits respectively.</desc>
<sw_param offset="0xe0003144" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_usb1_USBSTS_UEI">
<name>UEI</name>
<desc>USB Error Interrupt. When completion of a USB transaction results in an error condition, this bit is set by the Controller</desc>
<sw_param offset="0xe0003144" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb1_USBSTS_UI">
<name>UI</name>
<desc>This bit is set by the Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set.
This bit is also set by the Host Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than expected.</desc>
<sw_param offset="0xe0003144" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_USBINTR_TIE1">
<name>TIE1</name>
<desc>General Purpose Timer Interrupt Enable 1
When this bit is a one, and the TI1 bit in the EXTSTS register is a one, the controller will issue an interrupt. The interrupt is acknowledged by software clearing the TI1 bit.</desc>
<sw_param offset="0xe0003148" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_usb1_USBINTR_TIE0">
<name>TIE0</name>
<desc>General Purpose Timer Interrupt Enable 0
When this bit is a one, and the TI1 bit in the EXTSTS register is a one, the controller will issue an interrupt. The interrupt is acknowledged by software clearing the TI0 bit.</desc>
<sw_param offset="0xe0003148" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_usb1_USBINTR_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0003148" start="23" end="20" />
</parameter>
<parameter uniqueid="ps7_usb1_USBINTR_UPEI">
<name>UPEI</name>
<desc>USB Host Periodic Interrupt Enable.
When this bit is a one, and the UPI bit in the EXTSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the UPI bit.</desc>
<sw_param offset="0xe0003148" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_usb1_USBINTR_UAEI">
<name>UAEI</name>
<desc>USB Host Asynchronous Interrupt Enable
When this bit is a one, and the UAI bit in the EXTSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the UAI bit.</desc>
<sw_param offset="0xe0003148" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_usb1_USBINTR_reserved_1">
<name>reserved_1</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0003148" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb1_USBINTR_NAKEI">
<name>NAKEI</name>
<desc>NAK Interrupt Enable
when this bit is a one, and the NAKI bit in the EXTSTS register is a one, the controller will issue an interrupt. The interrupt is acknowledged by software clearing the NAKI bit.</desc>
<sw_param offset="0xe0003148" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_USBINTR_reserved_2">
<name>reserved_2</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0003148" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_usb1_USBINTR_ULPIE">
<name>ULPIE</name>
<desc>ULPI Interrupt enable. When this bit is a one, and the ULPI Interrupt bit in the USBSTS register transitions, the Controller will issue and interrupt. The interrupt is acknowledged by software writing a one to the ULPI Interrupt bit.</desc>
<sw_param offset="0xe0003148" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_usb1_USBINTR_reserved_3">
<name>reserved_3</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0003148" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_usb1_USBINTR_SLE">
<name>SLE</name>
<desc>DCSuspend Interrupt Enable.
When this bit is a one, and the SLI bit in the USBSTS register transitions, the Controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the SLI bit.
Only used in device mode.</desc>
<sw_param offset="0xe0003148" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_usb1_USBINTR_SRE">
<name>SRE</name>
<desc>USB Reset Received Interrupt Enable
When this bit is a one, and the SRI bit in the USBSTS register is a one, the Controller will issue an interrupt. The interrupt is acknowledged by software clearing the SRI bit.</desc>
<sw_param offset="0xe0003148" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb1_USBINTR_URE">
<name>URE</name>
<desc>USB Reset Received. When the Controller detects a USB Reset and enters the default state, this bit will be set to a one. Software can write a 1 to this bit to clear the USB Reset Received status bit.
Only used in device mode.</desc>
<sw_param offset="0xe0003148" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb1_USBINTR_AAE">
<name>AAE</name>
<desc>Interrupt on Async Advance Enable. When this bit is a one, and the AAI bit in the USBSTS register is a one, the Controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on AAI bit.
Only used in host mode.</desc>
<sw_param offset="0xe0003148" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb1_USBINTR_SEE">
<name>SEE</name>
<desc>System Error Interrupt Enable. When this bit is a one, and the SEI bit in the USBSTS register is a one, the Controller will issue an interrupt. The interrupt is acknowledged by software clearing the SSI bit.</desc>
<sw_param offset="0xe0003148" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb1_USBINTR_FRE">
<name>FRE</name>
<desc>Frame List Rollover Interrupt Enable
When this bit is a one, and the FRI bit in the USBSTS register is a one, the Controller will issue an interrupt. The interrupt is acknowledged by software clearing the FRI bit. Only used in host mode.</desc>
<sw_param offset="0xe0003148" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_usb1_USBINTR_PCE">
<name>PCE</name>
<desc>Port Change Detect Interrupt Enable
When this bit is a one, and the PCI bit in the USBSTS register is a one, the Controller will issue an interrupt. The interrupt is acknowledged by software clearing the PCI bit.</desc>
<sw_param offset="0xe0003148" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_usb1_USBINTR_UEE">
<name>UEE</name>
<desc>USB Error Interrupt
When this bit is a one, and the UEI bit in the USBSTS register is a one, the Controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by
software clearing the UEI bit in the USBSTS register.</desc>
<sw_param offset="0xe0003148" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb1_USBINTR_UE">
<name>UE</name>
<desc>When this bit is a one, and the UI bit in the USBSTS register is a one, the Controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by
software clearing the UI bit.</desc>
<sw_param offset="0xe0003148" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_FRINDEX_FRINDEX">
<name>FRINDEX</name>
<desc>The value, in this register, increments at the end of each time frame (e.g. micro-frame). Bits [N:3] are used for the Frame List current index. This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode.
usbcmd-&gt; FrameList-&gt; Size
000b -&gt;(1024) -&gt; 12
001b -&gt;(512) -&gt;11
010b -&gt;(256)-&gt;10
011b -&gt;(128) -&gt; 9
100b -&gt;(64) -&gt; 8
101b -&gt;(32) -&gt; 7
110b -&gt;(16) -&gt;6
111b -&gt;(8) -&gt;5
In device mode the value is the current frame number of the last frame transmitted. It is not used as an index.
This register is read-only in device mode.</desc>
<sw_param offset="0xe000314c" start="13" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_PERIODICLISTBASE_DEVICEADDR_PERBASE_USBADRA">
<name>PERBASE_USBADRA</name>
<desc>In host mode: Periodic List Base Address:
These bits correspond to memory address signals [31:12], respectively.
In Device Mode:
Device address advance
When this bit is '0b', any writes to USBADR are instantaneous. When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the hidden register.
Hardware will automatically clear this bit on the following conditions:
1) IN is ACKed to endpoint 0. (USBADR is updated from hidden register).
2) OUT/SETUP occur to endpoint 0. (USBADR is not updated).
3) Device Reset occurs (USBADR is reset to 0).</desc>
<sw_param offset="0xe0003154" start="31" end="25" />
</parameter>
<parameter uniqueid="ps7_usb1_PERIODICLISTBASE_DEVICEADDR_PERBASE_USBADR">
<name>PERBASE_USBADR</name>
<desc>In host mode: Periodic List Base Address:
These bits correspond to memory address signals [31:12], respectively.
In device Mode: USB Device address
These bits correspond to the USB device address</desc>
<sw_param offset="0xe0003154" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_usb1_PERIODICLISTBASE_DEVICEADDR_PERBASE_Reserved">
<name>PERBASE_Reserved</name>
<desc>In host mode: Periodic List Base Address:
These bits correspond to memory address signals [31:12], respectively.
In Device Mode: Reserved</desc>
<sw_param offset="0xe0003154" start="23" end="12" />
</parameter>
<parameter uniqueid="ps7_usb1_PERIODICLISTBASE_DEVICEADDR_reserved">
<name>reserved</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0003154" start="11" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_ASYNCLISTADDR_ENDPOINTLISTADDR_ASYBASE_EPBASE">
<name>ASYBASE_EPBASE</name>
<desc>In host mode: Asynchronous List Base Address:
These bits correspond to memory address signals [31:5], respectively. This field may only reference a Queue Head (QH).
In Device Mode:
Endpoint List Base Address
These bits correspond to memory address signals [31:11], respectively. This field will reference a list of up to 32 Queue Heads (QH). (i.e. one queue head per endpoint ANDdirection).</desc>
<sw_param offset="0xe0003158" start="31" end="11" />
</parameter>
<parameter uniqueid="ps7_usb1_ASYNCLISTADDR_ENDPOINTLISTADDR_ASYBASE">
<name>ASYBASE</name>
<desc>In host mode: Asynchronous List Base Address:
These bits correspond to memory address signals [31:5], respectively. This field may only reference a Queue Head (QH).
In Device Mode: Reserved</desc>
<sw_param offset="0xe0003158" start="10" end="5" />
</parameter>
<parameter uniqueid="ps7_usb1_ASYNCLISTADDR_ENDPOINTLISTADDR_reserved">
<name>reserved</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0003158" start="4" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_TTCTRL_reserved">
<name>reserved</name>
<desc>RESERVED</desc>
<sw_param offset="0xe000315c" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_usb1_TTCTRL_TTHA">
<name>TTHA</name>
<desc>Internal TT Hub Address Representation.
This field is used to match against the Hub Address field in QH AND siTD to determine if the packet is routed to the internal TT for directly attached FS/LS devices. If the Hub
Address in the QH or siTD does not match this address then the packet will be broadcast on the High Speed ports destined for a downstream High Speed hub with the
address in the QH/siTD.</desc>
<sw_param offset="0xe000315c" start="30" end="24" />
</parameter>
<parameter uniqueid="ps7_usb1_TTCTRL_reserved_1">
<name>reserved_1</name>
<desc>RESERVED</desc>
<sw_param offset="0xe000315c" start="23" end="2" />
</parameter>
<parameter uniqueid="ps7_usb1_TTCTRL_TTAS">
<name>TTAS</name>
<desc>Embedded TT Asynchronous Buffers Clear. This field will clear all pending transactions in the embedded TT Asynchronous Buffer(s). The clear will take as much time as necessary to clear buffer without
interfering with a transaction in progress. TTAC will return to zero after being set by software only after the actual clear occurs.</desc>
<sw_param offset="0xe000315c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb1_TTCTRL_TTAC">
<name>TTAC</name>
<desc>Embedded TT Async Buffers Status. This read only bit will be '1' if one or more transactions are being held in the embedded TT Asynchronous Buffers. When this bit is a zero, then all outstanding transactions in the embedded TT have been flushed.</desc>
<sw_param offset="0xe000315c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_BURSTSIZE_TXPBURST">
<name>TXPBURST</name>
<desc>Programmable TX Burst Length.
Default is the constant VUSB_HS_TX_BURST. This register represents the maximum length of a the burst in 32-bit words while moving data from system memory to the USB bus.
If field AHBBRST of register SBUSCFG is different from zero, this field TXPBRUST will return the value of the INCRx length.
Supported values are integer values from 4 to 128. It is recommended to set this value to a integer sub-multiple of VUSB_HS_TX_CHAN. Different values will not use all the available buffer space, preventing proper TX endpoint priming in stream disable mode (SDIS bit of USBMODE register set to '1').</desc>
<sw_param offset="0xe0003160" start="16" end="8" />
</parameter>
<parameter uniqueid="ps7_usb1_BURSTSIZE_RXPBURST">
<name>RXPBURST</name>
<desc>Programmable RX Burst Length. Default is the constant VUSB_HS_RX_BURST. This register represents the maximum length of a the burst in 32-bit words while moving data from the USB bus to system memory. If field AHBBRST of register SBUSCFG is different from zero, this field RXPBRUST will return the value of the INCRx length.
The supported values are integer values from 4 to 128. It is recommended to set this value to a integer sub-multiple of VUSB_HS_RX_DEPTH.</desc>
<sw_param offset="0xe0003160" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_TXFILLTUNING_TXFIFOTHRES">
<name>TXFIFOTHRES</name>
<desc>FIFO Burst Threshold:
This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth, where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set (SDIS).</desc>
<sw_param offset="0xe0003164" start="21" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_TXFILLTUNING_reserved">
<name>reserved</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0003164" start="15" end="13" />
</parameter>
<parameter uniqueid="ps7_usb1_TXFILLTUNING_TXSCHEALTH">
<name>TXSCHEALTH</name>
<desc>Scheduler Health Counter.
This register increments when the Controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame.
This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. This counter will max. at 31.</desc>
<sw_param offset="0xe0003164" start="12" end="8" />
</parameter>
<parameter uniqueid="ps7_usb1_TXFILLTUNING_reserved_1">
<name>reserved_1</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0003164" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb1_TXFILLTUNING_TXSCHOH">
<name>TXSCHOH</name>
<desc>Scheduler Overhead.
This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization.
The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode for OTG(on the go) AND SPH(single port host) implementations.
The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode for OTG AND SPH implementations. The time unit represented in this register is always 1.267us for the MPH implementation</desc>
<sw_param offset="0xe0003164" start="6" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_TXTTFILLTUNING_TXTTSCHHEALTH">
<name>TXTTSCHHEALTH</name>
<desc>TT Scheduler Health Counter
Same description as TXSCHHEALTH</desc>
<sw_param offset="0xe0003168" start="12" end="8" />
</parameter>
<parameter uniqueid="ps7_usb1_TXTTFILLTUNING_reserved">
<name>reserved</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0003168" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_usb1_TXTTFILLTUNING_TXTTSCHOH">
<name>TXTTSCHOH</name>
<desc>TT Scheduler Overhead
Same description as TXSCHOH.
The time unit represented in this register is 6.333us.</desc>
<sw_param offset="0xe0003168" start="4" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_IC_USB_IC8">
<name>IC8</name>
<desc>Inter-Chip transceiver enable 8. These bits enables the Inter-Chip transceiver for each port (for the MPH case). To enable the interface, the bits PTS must be set to '011b' in the PORTSC8. Writing a '1' to each bit selects the IC_USB interface for that port.</desc>
<sw_param offset="0xe000316c" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_usb1_IC_USB_IC_VDD8">
<name>IC_VDD8</name>
<desc>Inter-Chip voltage selection 8
It selects which voltage is being supplied to the peripheral through each port This field is read-only and set to '000b' in case of device mode operation.
This field is read-only and set to '000b' in case of Single port host controller.</desc>
<sw_param offset="0xe000316c" start="30" end="28" />
</parameter>
<parameter uniqueid="ps7_usb1_IC_USB_IC7">
<name>IC7</name>
<desc>Inter-Chip transceiver enable 7. These bits enables the Inter-Chip transceiver for each port (for the MPH case). To enable the interface, the bits PTS must be set to '011b' in the PORTSC7. Writing a '1' to each bit selects the IC_USB interface for that port.</desc>
<sw_param offset="0xe000316c" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_usb1_IC_USB_IC_VDD7">
<name>IC_VDD7</name>
<desc>Inter-Chip voltage selection 7
It selects which voltage is being supplied to the peripheral through each port This field is read-only and set to '000b' in case of device mode operation.
This field is read-only and set to '000b' in case of Single port host controller.</desc>
<sw_param offset="0xe000316c" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_usb1_IC_USB_IC6">
<name>IC6</name>
<desc>Inter-Chip transceiver enable 6. These bits enables the Inter-Chip transceiver for each port (for the MPH case). To enable the interface, the bits PTS must be set to '011b' in the PORTSC6. Writing a '1' to each bit selects the IC_USB interface for that port.</desc>
<sw_param offset="0xe000316c" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb1_IC_USB_IC_VDD6">
<name>IC_VDD6</name>
<desc>Inter-Chip voltage selection 6
It selects which voltage is being supplied to the peripheral through each port This field is read-only and set to '000b' in case of device mode operation.
This field is read-only and set to '000b' in case of Single port host controller.</desc>
<sw_param offset="0xe000316c" start="22" end="20" />
</parameter>
<parameter uniqueid="ps7_usb1_IC_USB_IC5">
<name>IC5</name>
<desc>Inter-Chip transceiver enable 5. These bits enables the Inter-Chip transceiver for each port (for the MPH case). To enable the interface, the bits PTS must be set to '011b' in the PORTSC5. Writing a '1' to each bit selects the IC_USB interface for that port.</desc>
<sw_param offset="0xe000316c" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_usb1_IC_USB_IC_VDD5">
<name>IC_VDD5</name>
<desc>Inter-Chip voltage selection 5
It selects which voltage is being supplied to the peripheral through each port This field is read-only and set to '000b' in case of device mode operation.
This field is read-only and set to '000b' in case of Single port host controller.</desc>
<sw_param offset="0xe000316c" start="18" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_IC_USB_IC4">
<name>IC4</name>
<desc>Inter-Chip transceiver enable 4. These bits enables the Inter-Chip transceiver for each port (for the MPH case). To enable the interface, the bits PTS must be set to '011b' in the PORTSC4. Writing a '1' to each bit selects the IC_USB interface for that port.</desc>
<sw_param offset="0xe000316c" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_usb1_IC_USB_IC_VDD4">
<name>IC_VDD4</name>
<desc>Inter-Chip voltage selection 4
It selects which voltage is being supplied to the peripheral through each port This field is read-only and set to '000b' in case of device mode operation.
This field is read-only and set to '000b' in case of Single port host controller.</desc>
<sw_param offset="0xe000316c" start="14" end="12" />
</parameter>
<parameter uniqueid="ps7_usb1_IC_USB_IC3">
<name>IC3</name>
<desc>Inter-Chip transceiver enable 3. These bits enables the Inter-Chip transceiver for each port (for the MPH case). To enable the interface, the bits PTS must be set to '011b' in the PORTSC3. Writing a '1' to each bit selects the IC_USB interface for that port.</desc>
<sw_param offset="0xe000316c" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_usb1_IC_USB_IC_VDD3">
<name>IC_VDD3</name>
<desc>Inter-Chip voltage selection 3
It selects which voltage is being supplied to the peripheral through each port. This field is read-only and set to '000b' in case of device mode operation.
This field is read-only and set to '000b' in case of Single port host controller.</desc>
<sw_param offset="0xe000316c" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_usb1_IC_USB_IC2">
<name>IC2</name>
<desc>Inter-Chip transceiver enable 2. These bits enables the Inter-Chip transceiver for each port (for the MPH case). To enable the interface, the bits PTS must be set to '011b' in the PORTSC2. Writing a '1' to each bit selects the IC_USB interface for that port.</desc>
<sw_param offset="0xe000316c" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb1_IC_USB_IC_VDD2">
<name>IC_VDD2</name>
<desc>Inter-Chip voltage selection 2
It selects which voltage is being supplied to the peripheral through each port. This field is read-only and set to '000b' in case of device mode operation.
This field is read-only and set to '000b' in case of Single port host controller.</desc>
<sw_param offset="0xe000316c" start="6" end="4" />
</parameter>
<parameter uniqueid="ps7_usb1_IC_USB_IC1">
<name>IC1</name>
<desc>Inter-Chip transceiver enable 1. These bits enables the Inter-Chip transceiver for each port (for the MPH case). To enable the interface, the bits PTS must be set to '011b' in the PORTSC1. Writing a '1' to each bit selects the IC_USB interface for that port. If the Controller is not a MPH
implementation, IC8 to IC2 will be '0' and Read-Only.</desc>
<sw_param offset="0xe000316c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_usb1_IC_USB_IC_VDD1">
<name>IC_VDD1</name>
<desc>Inter-Chip voltage selection 1
It selects which voltage is being supplied to the peripheral through each port
000 - No voltage
001 - 1.0V
010 - 1.2V
011 - 1.5V
100 - 1.8V
101 - 3.0V
110 - Reserved
111 - Reserved
This field is read-only and set to '000b' in case of device mode operation.
The voltage negotiation should happen between enabling port power (PP) in PORTSC1 register and asserting the run/stop bit in USBCMD register.</desc>
<sw_param offset="0xe000316c" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_ULPI_VIEWPORT_ULPIWU">
<name>ULPIWU</name>
<desc>ULPI Wakeup.
Writing the '1' to this bit will begin the wakeup operation. The bit will automatically transition to '0' after the wakeup is complete. Once this bit is set, the driver can not set it back to '0'.
Note: The driver must never execute a wakeup and a read/write operation at the same time.</desc>
<sw_param offset="0xe0003170" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_usb1_ULPI_VIEWPORT_ULPIRUN">
<name>ULPIRUN</name>
<desc>ULPIRUN
Writing the '1' to this bit will begin the read/write operation. The bit will automatically transition to '0' after the read/write is complete. Once this bit is set, the driver can not set it back to '0'.
Note: The driver must never execute a wakeup and a read/write operation at the same time.</desc>
<sw_param offset="0xe0003170" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_usb1_ULPI_VIEWPORT_ULPIRW">
<name>ULPIRW</name>
<desc>ULPI Read/Write Control'0' - Read.'1' - Write.
This bit selects between running a read or write operation.</desc>
<sw_param offset="0xe0003170" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_usb1_ULPI_VIEWPORT_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0003170" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_usb1_ULPI_VIEWPORT_ULPISS">
<name>ULPISS</name>
<desc>ULPI Data Address. When a read or write operation is commanded, the address of the operation is written to this field.</desc>
<sw_param offset="0xe0003170" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_usb1_ULPI_VIEWPORT_ULPIPORT">
<name>ULPIPORT</name>
<desc>ULPI Port Number.
For the wakeup or read/write operation to be executed, this value selects the port number to which a ULPI PHY is attached. The range is 0 to 7. This field should always be written '000b' for non MPH implementations.</desc>
<sw_param offset="0xe0003170" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_usb1_ULPI_VIEWPORT_ULPIADDR">
<name>ULPIADDR</name>
<desc>ULPI Data Address. When a read or write operation is commanded, the address of the operation is written to this field.</desc>
<sw_param offset="0xe0003170" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_ULPI_VIEWPORT_ULPIDATRD">
<name>ULPIDATRD</name>
<desc>ULPI Data Read.
After a read operation completes, the result is placed in this field.</desc>
<sw_param offset="0xe0003170" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb1_ULPI_VIEWPORT_ULPIDATWR">
<name>ULPIDATWR</name>
<desc>ULPI Data Write. When a write operation is commanded, the data to be sent is written to this field</desc>
<sw_param offset="0xe0003170" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTNAK_EPTN">
<name>EPTN</name>
<desc>TX Endpoint NAK
Each TX endpoint has 1 bit in this field. The bit is set when the Controller sends a NAK handshake on a received IN token for the corresponding endpoint.
Bit 15 - Endpoint #15
...
Bit 1 - Endpoint #1
Bit 0 - Endpoint #0
Only used in device mode.</desc>
<sw_param offset="0xe0003178" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTNAK_EPRN">
<name>EPRN</name>
<desc>RX Endpoint NAK
Each RX endpoint has 1 bit in this field. The bit is set when the Controller sends a NAK handshake on a received OUT or PING token for the corresponding endpoint.
Bit 15 - Endpoint #15
...
Bit 1 - Endpoint #1
Bit 0 - Endpoint #0
Only used in device mode.</desc>
<sw_param offset="0xe0003178" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTNAKEN_EPTNE">
<name>EPTNE</name>
<desc>TX Endpoint NAK enable
Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set.
Bit 15 - Endpoint #15
...
Bit 1 - Endpoint #1
Bit 0 - Endpoint #0
Only used in device mode.</desc>
<sw_param offset="0xe000317c" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTNAKEN_EPRNE">
<name>EPRNE</name>
<desc>RX Endpoint NAK enable
Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set.
Bit 15 - Endpoint #15
...
Bit 1 - Endpoint #1
Bit 0 - Endpoint #0
Only used in device mode.</desc>
<sw_param offset="0xe000317c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_CONFIGFLAG_reserved">
<name>reserved</name>
<desc>RESERVED</desc>
<sw_param offset="0xe0003180" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_PORTSC1_PTS">
<name>PTS</name>
<desc>This register bit pair is used in conjunction with the configuration constant VUSB_HS_PHY_TYPE to control which parallel transceiver interface is selected'010b' -&gt; 2, 6 - ULPI
Note that this field is made up from PORTSCx bits 25, 30 and 31.</desc>
<sw_param offset="0xe0003184" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_usb1_PORTSC1_STS">
<name>STS</name>
<desc>Serial Transceiver Select
This register bit is used in conjunction with the configuration constant VUSB_HS_PHY_SERIAL to control whether the parallel or serial transceiver interface is selected for FS and LS operation. The Serial Interface Engine can be used in
combination with the UTMI+ physical interface to provide FS/LS signaling instead of the parallel interface. If VUSB_HS_PHY_SERIAL is set for 0 or 1 then this bit is read only. If VUSB_HS_PHY_SERIAL is 2 or 3 then this bit is read/write.
This bit has no effect unless Parallel Transceiver Select is set to UTMI+. The Serial/1.1 and IC_USB physical interface will use the Serial Interface Engine for FS/LS signaling
regardless of this bit value.</desc>
<sw_param offset="0xe0003184" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_usb1_PORTSC1_PTW">
<name>PTW</name>
<desc>Parallel Transceiver Width. Writing this bit to '0' selects the 8-bit [60MHz] UTMI+ interface.</desc>
<sw_param offset="0xe0003184" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_usb1_PORTSC1_PSPD">
<name>PSPD</name>
<desc>Port Speed - RO. Default = 11b.
This register field indicates the speed at which the port is operating.'00b' -&gt; Full Speed'01b' -&gt; Low Speed'10b' -&gt; High Speed'11b' -&gt; Not connected</desc>
<sw_param offset="0xe0003184" start="27" end="26" />
</parameter>
<parameter uniqueid="ps7_usb1_PORTSC1_PTS2">
<name>PTS2</name>
<desc>Parallel Transceiver Select - RW. Default = Implementation dependent.
MSB bit of PTS field.</desc>
<sw_param offset="0xe0003184" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_usb1_PORTSC1_PFSC">
<name>PFSC</name>
<desc>Port Force Full Speed Connect - RW. Default = 0b.
Writing this bit to a '1b' will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device. This bit is for debugging purposes.</desc>
<sw_param offset="0xe0003184" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_usb1_PORTSC1_PHCD">
<name>PHCD</name>
<desc>PHY Low Power Clock Disable - RW. Default = 0b.
Writing this bit to a '1b' will disable the PHY clock. Writing a '0b' enables it. Reading this bit will indicate the status of the PHY clock. NOTE: The PHY clock cannot be disabled if it is being used as the system clock. In device mode, the PHY can be put into Low Power Clock Disable when the device is not running (USBCMD RS=0b) or the host has signaled suspend (PORTSCx SUSP=1b).
Low Power Clock Disable will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the Controller driver must clear this bit.
In host mode, the PHY can be put into Low Power Suspend Clock Disable when the downstream device has been put into suspend mode or when no downstream device is
connected. Low Power Clock Disable is completely under the control of software.</desc>
<sw_param offset="0xe0003184" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb1_PORTSC1_WKOC">
<name>WKOC</name>
<desc>Wake on Over-current Enable
Writing '1' to this bit enables the port to be sensitive to over-current conditions as wakeup events.
This field is zero if Port Power (PP) is '0' or in device mode.
This bit is output from the controller as signal pwrctl_wake_ovrcurr_en for use by an external power control circuit. Only used in host mode.</desc>
<sw_param offset="0xe0003184" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_usb1_PORTSC1_WKDS">
<name>WKDS</name>
<desc>Wake on Disconnect Enable
Writing this bit to a one enables the port to be sensitive to device disconnects as wakeup events. This field is zero if Port Power (PP) is '0' or in device mode. This bit is output from the controller as signal pwrctl_wake_dscnnt_en for use by an external power control circuit.</desc>
<sw_param offset="0xe0003184" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_usb1_PORTSC1_WKCN">
<name>WKCN</name>
<desc>Wake on Connect Enable
Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. This field is zero if Port Power(PP) is '0' or in device mode. This bit is output from the controller as signal pwrctl_wake_cnnt_en for use by an external power control circuit. Only used in host mode.</desc>
<sw_param offset="0xe0003184" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_usb1_PORTSC1_PTC">
<name>PTC</name>
<desc>Port Test Control
Any other value than zero indicates that the port is operating in test mode.
Value Specific Test
0000b -&gt; TEST_MODE_DISABLE
0001b -&gt; J_ STATE
0010b -&gt; K_STATE
0011b -&gt; SE0 (host) / NAK (device)
0100b -&gt; Packet
0101b -&gt; FORCE_ENABLE_HS
0110b -&gt; FORCE_ENABLE_FS
0111b -&gt; FORCE_ENABLE_LS
1000b -&gt; Reserved
... Reserved
1111b
-&gt; Reserved</desc>
<sw_param offset="0xe0003184" start="19" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_PORTSC1_PIC">
<name>PIC</name>
<desc>Port Indicator Control
Writing to this field has no effect if the P_INDICATOR bit in the HCSPARAMS register is
a zero. If P_INDICATOR bit is a one, then the bits are:
Value Meaning
00b -&gt; Port indicators are off
01b -&gt; Amber
10b -&gt; Green
11b -&gt; Undefined
Refer to the USB Specification Revision 2.0 for a description on how these bits are to be used.This field is output from the controller as signals port_ind_ctl_1 and port_ind_ctl_0 for</desc>
<sw_param offset="0xe0003184" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_usb1_PORTSC1_PO">
<name>PO</name>
<desc>Port Owner
Port owner hand off is not implemented in this design, therefore this bit will always read
back as 0b.</desc>
<sw_param offset="0xe0003184" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_usb1_PORTSC1_PP">
<name>PP</name>
<desc>Port Power
The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows:
PPC -&gt; PP -&gt; Operation
0b -&gt; 0b -&gt; Read Only. A Controller in device mode does not have port power control switches.
1b -&gt; 1b/0b -&gt; Read/Write. A Controller in host mode requires port power control switches.
This bit represents the current setting of the switch ('0'=off, '1'=on). When power is not available on a port (i.e. PP equals to '0'), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the Controller driver from '1' to '0'(removing power from the port).
In device mode port power control is not necessary, thus PPC and PP = 0.</desc>
<sw_param offset="0xe0003184" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_usb1_PORTSC1_LS">
<name>LS</name>
<desc>Line Status
These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines.
The encoding of the bits are:
00b -&gt; SE0
10b -&gt; J-state
01b -&gt; K-state
11b -&gt; Undefined
In host mode, the use of linestate by the Controller driver is not necessary (unlike EHCI), because the port controller state machine and the port routing manage the connection of LS and FS.
In device mode, the use of linestate by the Controller driver is not necessary.</desc>
<sw_param offset="0xe0003184" start="11" end="10" />
</parameter>
<parameter uniqueid="ps7_usb1_PORTSC1_HSP">
<name>HSP</name>
<desc>High-Speed Port
When the bit is one, the port is in high-speed mode and if set to zero, the port is not in a high-speed mode.
Note: HSP is redundant with PSPD but will remain in the design for compatibility.</desc>
<sw_param offset="0xe0003184" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_usb1_PORTSC1_PR">
<name>PR</name>
<desc>Port Reset - RW. Default = 0b.
This field is zero if Port Power(PP) is '0'.
Host mode: 1=Port is in Reset. 0=Port is not in Reset.
Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register</desc>
<sw_param offset="0xe0003184" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_usb1_PORTSC1_SUSP">
<name>SUSP</name>
<desc>Suspend
Host mode: 1=Port in suspend state. 0=Port not in suspend state. Port Enabled bit and Suspend bit of this register define the port states as follows:
Bits [Port Enabled, Suspend] Port State
0x Disable
10 Enable
11 Suspend
Device mode: Read Only. 1=Port in suspend state. 0=Port not in suspend state. In device mode this bit is a read only status bit.</desc>
<sw_param offset="0xe0003184" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb1_PORTSC1_FPR">
<name>FPR</name>
<desc>Force Port Resume
1= Resume detected/driven on port.
0=No resume (K-state) detected/driven on port.</desc>
<sw_param offset="0xe0003184" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb1_PORTSC1_OCC">
<name>OCC</name>
<desc>Over-current Change
This bit gets set to '1' when there is a change to Over-current Active. Software clears this bit by writing a '1' to this bit position.
When in host mode implementations the user can provide over-current detection to the vbus_pwr_fault input for this condition.
For device mode this bit shall always be '0'.</desc>
<sw_param offset="0xe0003184" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb1_PORTSC1_OCA">
<name>OCA</name>
<desc>Over-current Active
Value Meaning'1b' -&gt; This port currently has an over-current condition.'0b' -&gt; This port does not have an over-current condition.
This bit will automatically transition from '1' to '0' when the over current condition is removed.
For host mode implementations the user can provide over-current detection to the vbus_pwr_fault input for this condition.
For device mode implementations this bit shall always be '0'.</desc>
<sw_param offset="0xe0003184" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb1_PORTSC1_PEC">
<name>PEC</name>
<desc>Port Enabled Change
If set to '1' indicates a Port Enabled/Disabled status change.
Host mode:
For the root hub, this bit gets set to a '1' only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a '1' to it. This field is '0' if Port Power(PP) is '0'.
Device mode:
The device port is always enabled. (This bit will be '0').</desc>
<sw_param offset="0xe0003184" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_usb1_PORTSC1_PE">
<name>PE</name>
<desc>Port Enabled
1 -&gt; Enable
0-&gt; Disable
Host mode:
Ports can only be enabled by Controller as a part of the reset and enable. Software cannot enable a port by writing a '1' to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the software.This field is '0' if Port Power(PP) is '0' in host mode.
Device mode:
The device port is always enabled. (This bit will be always '1').</desc>
<sw_param offset="0xe0003184" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_usb1_PORTSC1_CSC">
<name>CSC</name>
<desc>Connect Status Change
If set to '1' indicates a change in Current Connect Status (CCS).
Host mode:
Indicates a change has occurred in the port's Current Connect Status. The Controller sets this bit for all changes to the port device connect status, even if system software
has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be 'setting' an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a '1' to it. This field is '0' if Port Power(PP) is '0' in host mode.
Device mode:
This bit is undefined in device mode.</desc>
<sw_param offset="0xe0003184" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb1_PORTSC1_CCS">
<name>CCS</name>
<desc>Current Connect Status.
Host mode:
1 -&gt; Device is present on port.
0 -&gt; No device is present.
Device mode:
1 -&gt; Attached.
0 -&gt; Not Attached.</desc>
<sw_param offset="0xe0003184" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031a4" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_DPIE">
<name>DPIE</name>
<desc>Data Pulse Interrupt Enable
This bit enables the generation of an interrupt if bit DPIS is set.</desc>
<sw_param offset="0xe00031a4" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_n1msE">
<name>n1msE</name>
<desc>1 millisecond timer Interrupt Enable
This bit enables the generation of an interrupt if bit 1msS is set.</desc>
<sw_param offset="0xe00031a4" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_BSEIE">
<name>BSEIE</name>
<desc>B Session End Interrupt Enable
This bit enables the generation of an interrupt if bit BSEIS is set</desc>
<sw_param offset="0xe00031a4" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_BSVIE">
<name>BSVIE</name>
<desc>B Session Valid Interrupt Enable
This bit enables the generation of an interrupt if bit BSVIS is set.</desc>
<sw_param offset="0xe00031a4" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_ASVIE">
<name>ASVIE</name>
<desc>A Session Valid Interrupt Enable
This bit enables the generation of an interrupt if bit ASVIS is set.</desc>
<sw_param offset="0xe00031a4" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_AVVIE">
<name>AVVIE</name>
<desc>A VBus Valid Interrupt Enable
This bit enables the generation of an interrupt if bit AVVIS is set.</desc>
<sw_param offset="0xe00031a4" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_IDIE">
<name>IDIE</name>
<desc>USB ID Interrupt Enable
This bit enables the generation of an interrupt if bit IDIS is set.</desc>
<sw_param offset="0xe00031a4" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031a4" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_DPIS">
<name>DPIS</name>
<desc>Data Pulse Interrupt Status
This bit is set when data bus pulsing occurs on DP or DM. Data bus pulsing is only detected when USBMODE.CM = Host ('11b') and PORTSC0.PP = Off ('0b').
Software must write a '1' to clear this bit.</desc>
<sw_param offset="0xe00031a4" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_n1msS">
<name>n1msS</name>
<desc>1 millisecond timer Interrupt Status.
This bit is set once every millisecond. Software must write a '1' to clear this bit.</desc>
<sw_param offset="0xe00031a4" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_BSEIS">
<name>BSEIS</name>
<desc>B Session End Interrupt Status
This bit is set when VBus has fallen below the B session end threshold. Software must write a '1' to clear this bit.</desc>
<sw_param offset="0xe00031a4" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_BSVIS">
<name>BSVIS</name>
<desc>B Session Valid Interrupt Status
This bit is set when VBus has either risen above or fallen below the B session valid threshold (0.8 VDC).
Software must write a '1' to clear this bit.</desc>
<sw_param offset="0xe00031a4" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_ASVIS">
<name>ASVIS</name>
<desc>A Session Valid Interrupt Status
This bit is set when VBus has either risen above or fallen below the A session valid threshold (0.8 VDC).
Software must write a '1' to clear this bit.</desc>
<sw_param offset="0xe00031a4" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_AVVIS">
<name>AVVIS</name>
<desc>Frame IndexThis bit is set when VBus has either risen above or fallen below the VBus valid threshold
(4.4 VDC) on an A device. Software must write a '1' to clear this bit.</desc>
<sw_param offset="0xe00031a4" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_IDIS">
<name>IDIS</name>
<desc>USB ID Interrupt Status
This bit is set when a change on the ID input has been detected. Software must write a '1' to clear this bit.</desc>
<sw_param offset="0xe00031a4" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031a4" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_DPS">
<name>DPS</name>
<desc>Data Bus Pulsing Status
A '1' indicates data bus pulsing is being detected on the port.</desc>
<sw_param offset="0xe00031a4" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_n1msT">
<name>n1msT</name>
<desc>1 millisecond timer toggle
This bit toggles once per millisecond.</desc>
<sw_param offset="0xe00031a4" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_BSE">
<name>BSE</name>
<desc>B Session End
Indicates VBus is below the B session end threshold.</desc>
<sw_param offset="0xe00031a4" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_BSV">
<name>BSV</name>
<desc>B Session Valid
Indicates VBus is above the B session valid threshold.</desc>
<sw_param offset="0xe00031a4" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_ASV">
<name>ASV</name>
<desc>A Session Valid
Indicates VBus is above the A session valid threshold.</desc>
<sw_param offset="0xe00031a4" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_AVV">
<name>AVV</name>
<desc>A VBus Valid.
Indicates VBus is above the A VBus valid threshold.</desc>
<sw_param offset="0xe00031a4" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_ID">
<name>ID</name>
<desc>USB ID'0' = A device, '1' = B device.</desc>
<sw_param offset="0xe00031a4" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_HABA">
<name>HABA</name>
<desc>Hardware Assist B-Disconnect to A-connect'0' = Disabled, '1' = Enable automatic B-disconnect to A-connect sequence.</desc>
<sw_param offset="0xe00031a4" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_HADP">
<name>HADP</name>
<desc>Hardware Assist Data-Pulse
If set, the hardware assist data pulsing sequence starts.</desc>
<sw_param offset="0xe00031a4" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_IDPU">
<name>IDPU</name>
<desc>ID Pullup
This bit provide control over the ID pull-up resister.'0' = off, '1' = on. When this bit is '0' the ID input will not be sampled.</desc>
<sw_param offset="0xe00031a4" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_DP">
<name>DP</name>
<desc>Data Pulsing
Setting this bit causes the pullup on DP to be asserted for data pulsing during SRP.</desc>
<sw_param offset="0xe00031a4" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_OT">
<name>OT</name>
<desc>OTG Termination
This bit must be set when the Controller is in device mode. It controls the pulldown on DM.</desc>
<sw_param offset="0xe00031a4" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_HAAR">
<name>HAAR</name>
<desc>Hardware Assist Auto-Reset'0' = Disabled, '1' = Enable automatic reset after connect on host port.</desc>
<sw_param offset="0xe00031a4" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_VC">
<name>VC</name>
<desc>VBUS Charge
Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP.</desc>
<sw_param offset="0xe00031a4" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb1_OTGSC_VD">
<name>VD</name>
<desc>VBUS Discharge.
Setting this bit causes VBus to discharge through a resistor.</desc>
<sw_param offset="0xe00031a4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_USBMODE_SRT">
<name>SRT</name>
<desc>Shorten Reset Time
When the Controller is in host mode, this bit enables a bypass of the Chirp J/K reset handshake, saving 6-7ms in simulation time for each reset sequence. This bit should only be used for initial system integration simulations, and should always be set to 0 for
normal operation.</desc>
<sw_param offset="0xe00031a8" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_usb1_USBMODE_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031a8" start="14" end="6" />
</parameter>
<parameter uniqueid="ps7_usb1_USBMODE_VBPS">
<name>VBPS</name>
<desc>Vbus Power Select'0' -&gt; Output is '0''1' -&gt; Output is '1'This bit is connected to the vbus_pwr_select output and can be used for any generic control but is named to be used by logic that selects between an on-chip Vbus power source (charge pump) and an off-chip source in systems when both are available.
Only used in host mode.</desc>
<sw_param offset="0xe00031a8" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb1_USBMODE_SDIS">
<name>SDIS</name>
<desc>Stream Disable Mode'0' -&gt; Inactive'1' -&gt; Active
Device mode:
Setting to a '1' disables double priming on both RX and TX for low bandwidth systems.
Host Mode:
Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet.</desc>
<sw_param offset="0xe00031a8" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb1_USBMODE_SLOM">
<name>SLOM</name>
<desc>Setup Lockout Mode
This bit controls behavior of the setup lock mechanism.'0' -&gt; Setup Lockouts On.'1' -&gt; Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMD).
Only used in device mode</desc>
<sw_param offset="0xe00031a8" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_usb1_USBMODE_ES">
<name>ES</name>
<desc>Endian Select
This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.'0' Little Endian -&gt; first byte referenced in least significant byte of 32-bit word.'1' Big Endian -&gt; first byte referenced in most significant byte of 32-bit word.</desc>
<sw_param offset="0xe00031a8" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_usb1_USBMODE_CM">
<name>CM</name>
<desc>Controller Mode
Controller mode is defaulted to the proper mode for host only and device only implementations. For those designs that contain both host AND device capability (OTG),
the Controller will default to an idle state and will need to be initialized to the desired operating mode after reset. For combination host/device controllers, this register can
only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RST bit in the USBCMD register before reprogramming
this register.
Value Meaning'00b' -&gt; Idle (Default for combination host/device).'01b' -&gt; Reserved.'10b' -&gt; Controller in device mode (Default for device only controller).'11b' -&gt; Controller in host mode (Default for host only controller).</desc>
<sw_param offset="0xe00031a8" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTSETUPSTAT_ENDPTSETUPSTAT">
<name>ENDPTSETUPSTAT</name>
<desc>ENDPTSETUPSTATSetup Endpoint Status
For every setup transaction that is received, the corresponding bit in this register is set to '1'. Software must clear to acknowledge the setup transfer by writing a '1' to the respective bit after it has read the setup data from Queue Head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus timeouts if the setup lockout mechanism is engaged.
Only used in device mode.</desc>
<sw_param offset="0xe00031ac" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTPRIME_PETB">
<name>PETB</name>
<desc>Prime Endpoint Transmit Buffer - RWS. Default = 0000h.
For each endpoint a corresponding bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software
should write a '1' to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer
descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.
Note: These bits will be momentarily set by hardware during hardware re-priming operations when a dTD is retired, and the dQH is updated.
Bit 15 - Endpoint #15
...
Bit 1 - Endpoint #1
Bit 0 - Endpoint #0
Only used in device mode.</desc>
<sw_param offset="0xe00031b0" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTPRIME_PERB">
<name>PERB</name>
<desc>Prime Endpoint Receive Buffer
For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a '1' to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.
Note: These bits will be momentarily set by hardware during hardware re-priming operations when a dTD is retired, and the dQH is updated.
Bit 15 - Endpoint #15
...
Bit 1 - Endpoint #1
Bit 0 - Endpoint #0
Only used in device mode.</desc>
<sw_param offset="0xe00031b0" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTFLUSH_FETB">
<name>FETB</name>
<desc>Flush Endpoint Transmit Buffer
Writing a '1' to a bit(s) in this register will cause the associated endpoint(s) to clear any primed buffers. If a packet is in progress for one of the associated endpoints, then that
transfer will continue until completion. Hardware will clear this register after the endpoint flush operation is successful.
Bit 15 - Endpoint #15
...
Bit 1 - Endpoint #1
Bit 0 - Endpoint #0
Only used in device mode.</desc>
<sw_param offset="0xe00031b4" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTFLUSH_FERB">
<name>FERB</name>
<desc>Flush Endpoint Receive Buffer
Writing a '1' to a bit(s) will cause the associated endpoint(s) to clear any primed buffers. If a packet is in progress for one of the associated endpoints, then that transfer will
continue until completion. Hardware will clear this register after the endpoint flush operation is successful.
Bit 15 - Endpoint #15
...
Bit 1 - Endpoint #1
Bit 0 - Endpoint #0
Only used in device mode.</desc>
<sw_param offset="0xe00031b4" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTSTAT_ETBR">
<name>ETBR</name>
<desc>Endpoint Transmit Buffer Ready
One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a '1' by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay time varies based upon the current USB traffic and the number of bits set in the
ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register.
Note: These bits will be momentarily cleared by hardware during hardware endpoint repriming operations when a dTD is retired, and the dQH is updated.
Bit 15 - Endpoint #15
...
Bit 1 - Endpoint #1
Bit 0 - Endpoint #0
Only used in device mode.</desc>
<sw_param offset="0xe00031b8" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTSTAT_ERBR">
<name>ERBR</name>
<desc>Endpoint Receive Buffer Ready
One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a '1' by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay time varies based upon the current USB traffic and the number of bits set in the
ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register.
Note: These bits will be momentarily cleared by hardware during hardware endpoint repriming operations when a dTD is retired, and the dQH is updated.
Bit 15 - Endpoint #15
...
Bit 1 - Endpoint #1
Bit 0 - Endpoint #0
Only used in device mode.</desc>
<sw_param offset="0xe00031b8" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCOMPLETE_ETCE">
<name>ETCE</name>
<desc>Endpoint Transmit Complete Event
Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the
corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a '1' will clear the corresponding bit in this register.
Bit 15 - Endpoint #15
...
Bit 1 - Endpoint #1
Bit 0 - Endpoint #0
Only used in device mode.</desc>
<sw_param offset="0xe00031bc" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCOMPLETE_ERCE">
<name>ERCE</name>
<desc>Endpoint Receive Complete Event
Each bit indicates a received event (OUT) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a '1' will clear the corresponding bit in this register.
Bit 15 - Endpoint #15
...
Bit 1 - Endpoint #1
Bit 0 - Endpoint #0
Only used in device mode.</desc>
<sw_param offset="0xe00031bc" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL0_TXE">
<name>TXE</name>
<desc>TX Endpoint Enable
Endpoint0 is always enabled and this bit always set to '1'.</desc>
<sw_param offset="0xe00031c0" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL0_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031c0" start="22" end="20" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL0_TXT">
<name>TXT</name>
<desc>TX Endpoint Type
Endpoint0 is fixed as a Control End Point and this field always set to '00'.</desc>
<sw_param offset="0xe00031c0" start="19" end="18" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL0_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031c0" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL0_TXS">
<name>TXS</name>
<desc>TX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled</desc>
<sw_param offset="0xe00031c0" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL0_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031c0" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL0_RXE">
<name>RXE</name>
<desc>RX Endpoint Enable
Endpoint0 is always enabled and this bit always set to '1'.</desc>
<sw_param offset="0xe00031c0" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL0_reserved_3">
<name>reserved_3</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031c0" start="6" end="4" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL0_RXT">
<name>RXT</name>
<desc>RX Endpoint Type
Endpoint0 is fixed as a Control End Point and this field always set to '00'.</desc>
<sw_param offset="0xe00031c0" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL0_reserved_4">
<name>reserved_4</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031c0" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL0_RXS">
<name>RXS</name>
<desc>RX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled
Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request.</desc>
<sw_param offset="0xe00031c0" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL1_TXE">
<name>TXE</name>
<desc>TX Endpoint Enable
Value Meaning'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00031c4" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL1_TXR">
<name>TXR</name>
<desc>TX Data Toggle Reset
Write '1' will reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00031c4" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL1_TXI">
<name>TXI</name>
<desc>TX Data Toggle Inhibit
Value Meaning'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00031c4" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL1_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031c4" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL1_TXT">
<name>TXT</name>
<desc>TX Endpoint Type'00' -&gt; Control'01' -&gt; Isochronous'10' -&gt; Bulk'11' -&gt; Interrupt</desc>
<sw_param offset="0xe00031c4" start="19" end="18" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL1_TXD">
<name>TXD</name>
<desc>TX Endpoint Data
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00031c4" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL1_TXS">
<name>TXS</name>
<desc>TX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled</desc>
<sw_param offset="0xe00031c4" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL1_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031c4" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL1_RXE">
<name>RXE</name>
<desc>RX Endpoint Enable'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00031c4" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL1_RXR">
<name>RXR</name>
<desc>RX Data Toggle Reset
Write '1' will reset the PID sequence.
Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00031c4" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL1_RXI">
<name>RXI</name>
<desc>RX Data Toggle Inhibit'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00031c4" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL1_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031c4" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL1_RXT">
<name>RXT</name>
<desc>RX Endpoint Type
Endpoint0 is fixed as a Control End Point and this field always set to '00'.</desc>
<sw_param offset="0xe00031c4" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL1_RXD">
<name>RXD</name>
<desc>RX Endpoint Data Sink
Value Meaning
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00031c4" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL1_RXS">
<name>RXS</name>
<desc>RX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled
Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request.</desc>
<sw_param offset="0xe00031c4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL2_TXE">
<name>TXE</name>
<desc>TX Endpoint Enable
Value Meaning'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00031c8" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL2_TXR">
<name>TXR</name>
<desc>TX Data Toggle Reset
Write '1' will reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00031c8" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL2_TXI">
<name>TXI</name>
<desc>TX Data Toggle Inhibit
Value Meaning'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00031c8" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL2_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031c8" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL2_TXT">
<name>TXT</name>
<desc>TX Endpoint Type'00' -&gt; Control'01' -&gt; Isochronous'10' -&gt; Bulk'11' -&gt; Interrupt</desc>
<sw_param offset="0xe00031c8" start="19" end="18" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL2_TXD">
<name>TXD</name>
<desc>TX Endpoint Data
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00031c8" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL2_TXS">
<name>TXS</name>
<desc>TX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled</desc>
<sw_param offset="0xe00031c8" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL2_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031c8" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL2_RXE">
<name>RXE</name>
<desc>RX Endpoint Enable'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00031c8" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL2_RXR">
<name>RXR</name>
<desc>RX Data Toggle Reset
Write '1' will reset the PID sequence.
Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00031c8" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL2_RXI">
<name>RXI</name>
<desc>RX Data Toggle Inhibit'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00031c8" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL2_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031c8" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL2_RXT">
<name>RXT</name>
<desc>RX Endpoint Type
Endpoint0 is fixed as a Control End Point and this field always set to '00'.</desc>
<sw_param offset="0xe00031c8" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL2_RXD">
<name>RXD</name>
<desc>RX Endpoint Data Sink
Value Meaning
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00031c8" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL2_RXS">
<name>RXS</name>
<desc>RX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled
Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request.</desc>
<sw_param offset="0xe00031c8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL3_TXE">
<name>TXE</name>
<desc>TX Endpoint Enable
Value Meaning'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00031cc" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL3_TXR">
<name>TXR</name>
<desc>TX Data Toggle Reset
Write '1' will reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00031cc" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL3_TXI">
<name>TXI</name>
<desc>TX Data Toggle Inhibit
Value Meaning'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00031cc" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL3_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031cc" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL3_TXT">
<name>TXT</name>
<desc>TX Endpoint Type'00' -&gt; Control'01' -&gt; Isochronous'10' -&gt; Bulk'11' -&gt; Interrupt</desc>
<sw_param offset="0xe00031cc" start="19" end="18" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL3_TXD">
<name>TXD</name>
<desc>TX Endpoint Data
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00031cc" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL3_TXS">
<name>TXS</name>
<desc>TX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled</desc>
<sw_param offset="0xe00031cc" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL3_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031cc" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL3_RXE">
<name>RXE</name>
<desc>RX Endpoint Enable'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00031cc" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL3_RXR">
<name>RXR</name>
<desc>RX Data Toggle Reset
Write '1' will reset the PID sequence.
Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00031cc" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL3_RXI">
<name>RXI</name>
<desc>RX Data Toggle Inhibit'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00031cc" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL3_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031cc" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL3_RXT">
<name>RXT</name>
<desc>RX Endpoint Type
Endpoint0 is fixed as a Control End Point and this field always set to '00'.</desc>
<sw_param offset="0xe00031cc" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL3_RXD">
<name>RXD</name>
<desc>RX Endpoint Data Sink
Value Meaning
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00031cc" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL3_RXS">
<name>RXS</name>
<desc>RX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled
Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request.</desc>
<sw_param offset="0xe00031cc" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL4_TXE">
<name>TXE</name>
<desc>TX Endpoint Enable
Value Meaning'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00031d0" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL4_TXR">
<name>TXR</name>
<desc>TX Data Toggle Reset
Write '1' will reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00031d0" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL4_TXI">
<name>TXI</name>
<desc>TX Data Toggle Inhibit
Value Meaning'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00031d0" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL4_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031d0" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL4_TXT">
<name>TXT</name>
<desc>TX Endpoint Type'00' -&gt; Control'01' -&gt; Isochronous'10' -&gt; Bulk'11' -&gt; Interrupt</desc>
<sw_param offset="0xe00031d0" start="19" end="18" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL4_TXD">
<name>TXD</name>
<desc>TX Endpoint Data
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00031d0" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL4_TXS">
<name>TXS</name>
<desc>TX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled</desc>
<sw_param offset="0xe00031d0" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL4_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031d0" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL4_RXE">
<name>RXE</name>
<desc>RX Endpoint Enable'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00031d0" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL4_RXR">
<name>RXR</name>
<desc>RX Data Toggle Reset
Write '1' will reset the PID sequence.
Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00031d0" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL4_RXI">
<name>RXI</name>
<desc>RX Data Toggle Inhibit'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00031d0" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL4_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031d0" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL4_RXT">
<name>RXT</name>
<desc>RX Endpoint Type
Endpoint0 is fixed as a Control End Point and this field always set to '00'.</desc>
<sw_param offset="0xe00031d0" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL4_RXD">
<name>RXD</name>
<desc>RX Endpoint Data Sink
Value Meaning
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00031d0" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL4_RXS">
<name>RXS</name>
<desc>RX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled
Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request.</desc>
<sw_param offset="0xe00031d0" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL5_TXE">
<name>TXE</name>
<desc>TX Endpoint Enable
Value Meaning'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00031d4" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL5_TXR">
<name>TXR</name>
<desc>TX Data Toggle Reset
Write '1' will reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00031d4" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL5_TXI">
<name>TXI</name>
<desc>TX Data Toggle Inhibit
Value Meaning'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00031d4" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL5_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031d4" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL5_TXT">
<name>TXT</name>
<desc>TX Endpoint Type'00' -&gt; Control'01' -&gt; Isochronous'10' -&gt; Bulk'11' -&gt; Interrupt</desc>
<sw_param offset="0xe00031d4" start="19" end="18" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL5_TXD">
<name>TXD</name>
<desc>TX Endpoint Data
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00031d4" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL5_TXS">
<name>TXS</name>
<desc>TX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled</desc>
<sw_param offset="0xe00031d4" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL5_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031d4" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL5_RXE">
<name>RXE</name>
<desc>RX Endpoint Enable'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00031d4" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL5_RXR">
<name>RXR</name>
<desc>RX Data Toggle Reset
Write '1' will reset the PID sequence.
Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00031d4" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL5_RXI">
<name>RXI</name>
<desc>RX Data Toggle Inhibit'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00031d4" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL5_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031d4" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL5_RXT">
<name>RXT</name>
<desc>RX Endpoint Type
Endpoint0 is fixed as a Control End Point and this field always set to '00'.</desc>
<sw_param offset="0xe00031d4" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL5_RXD">
<name>RXD</name>
<desc>RX Endpoint Data Sink
Value Meaning
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00031d4" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL5_RXS">
<name>RXS</name>
<desc>RX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled
Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request.</desc>
<sw_param offset="0xe00031d4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL6_TXE">
<name>TXE</name>
<desc>TX Endpoint Enable
Value Meaning'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00031d8" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL6_TXR">
<name>TXR</name>
<desc>TX Data Toggle Reset
Write '1' will reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00031d8" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL6_TXI">
<name>TXI</name>
<desc>TX Data Toggle Inhibit
Value Meaning'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00031d8" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL6_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031d8" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL6_TXT">
<name>TXT</name>
<desc>TX Endpoint Type'00' -&gt; Control'01' -&gt; Isochronous'10' -&gt; Bulk'11' -&gt; Interrupt</desc>
<sw_param offset="0xe00031d8" start="19" end="18" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL6_TXD">
<name>TXD</name>
<desc>TX Endpoint Data
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00031d8" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL6_TXS">
<name>TXS</name>
<desc>TX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled</desc>
<sw_param offset="0xe00031d8" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL6_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031d8" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL6_RXE">
<name>RXE</name>
<desc>RX Endpoint Enable'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00031d8" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL6_RXR">
<name>RXR</name>
<desc>RX Data Toggle Reset
Write '1' will reset the PID sequence.
Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00031d8" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL6_RXI">
<name>RXI</name>
<desc>RX Data Toggle Inhibit'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00031d8" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL6_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031d8" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL6_RXT">
<name>RXT</name>
<desc>RX Endpoint Type
Endpoint0 is fixed as a Control End Point and this field always set to '00'.</desc>
<sw_param offset="0xe00031d8" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL6_RXD">
<name>RXD</name>
<desc>RX Endpoint Data Sink
Value Meaning
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00031d8" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL6_RXS">
<name>RXS</name>
<desc>RX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled
Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request.</desc>
<sw_param offset="0xe00031d8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL7_TXE">
<name>TXE</name>
<desc>TX Endpoint Enable
Value Meaning'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00031dc" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL7_TXR">
<name>TXR</name>
<desc>TX Data Toggle Reset
Write '1' will reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00031dc" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL7_TXI">
<name>TXI</name>
<desc>TX Data Toggle Inhibit
Value Meaning'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00031dc" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL7_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031dc" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL7_TXT">
<name>TXT</name>
<desc>TX Endpoint Type'00' -&gt; Control'01' -&gt; Isochronous'10' -&gt; Bulk'11' -&gt; Interrupt</desc>
<sw_param offset="0xe00031dc" start="19" end="18" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL7_TXD">
<name>TXD</name>
<desc>TX Endpoint Data
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00031dc" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL7_TXS">
<name>TXS</name>
<desc>TX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled</desc>
<sw_param offset="0xe00031dc" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL7_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031dc" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL7_RXE">
<name>RXE</name>
<desc>RX Endpoint Enable'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00031dc" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL7_RXR">
<name>RXR</name>
<desc>RX Data Toggle Reset
Write '1' will reset the PID sequence.
Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00031dc" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL7_RXI">
<name>RXI</name>
<desc>RX Data Toggle Inhibit'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00031dc" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL7_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031dc" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL7_RXT">
<name>RXT</name>
<desc>RX Endpoint Type
Endpoint0 is fixed as a Control End Point and this field always set to '00'.</desc>
<sw_param offset="0xe00031dc" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL7_RXD">
<name>RXD</name>
<desc>RX Endpoint Data Sink
Value Meaning
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00031dc" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL7_RXS">
<name>RXS</name>
<desc>RX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled
Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request.</desc>
<sw_param offset="0xe00031dc" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL8_TXE">
<name>TXE</name>
<desc>TX Endpoint Enable
Value Meaning'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00031e0" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL8_TXR">
<name>TXR</name>
<desc>TX Data Toggle Reset
Write '1' will reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00031e0" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL8_TXI">
<name>TXI</name>
<desc>TX Data Toggle Inhibit
Value Meaning'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00031e0" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL8_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031e0" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL8_TXT">
<name>TXT</name>
<desc>TX Endpoint Type'00' -&gt; Control'01' -&gt; Isochronous'10' -&gt; Bulk'11' -&gt; Interrupt</desc>
<sw_param offset="0xe00031e0" start="19" end="18" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL8_TXD">
<name>TXD</name>
<desc>TX Endpoint Data
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00031e0" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL8_TXS">
<name>TXS</name>
<desc>TX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled</desc>
<sw_param offset="0xe00031e0" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL8_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031e0" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL8_RXE">
<name>RXE</name>
<desc>RX Endpoint Enable'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00031e0" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL8_RXR">
<name>RXR</name>
<desc>RX Data Toggle Reset
Write '1' will reset the PID sequence.
Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00031e0" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL8_RXI">
<name>RXI</name>
<desc>RX Data Toggle Inhibit'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00031e0" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL8_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031e0" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL8_RXT">
<name>RXT</name>
<desc>RX Endpoint Type
Endpoint0 is fixed as a Control End Point and this field always set to '00'.</desc>
<sw_param offset="0xe00031e0" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL8_RXD">
<name>RXD</name>
<desc>RX Endpoint Data Sink
Value Meaning
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00031e0" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL8_RXS">
<name>RXS</name>
<desc>RX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled
Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request.</desc>
<sw_param offset="0xe00031e0" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL9_TXE">
<name>TXE</name>
<desc>TX Endpoint Enable
Value Meaning'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00031e4" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL9_TXR">
<name>TXR</name>
<desc>TX Data Toggle Reset
Write '1' will reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00031e4" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL9_TXI">
<name>TXI</name>
<desc>TX Data Toggle Inhibit
Value Meaning'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00031e4" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL9_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031e4" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL9_TXT">
<name>TXT</name>
<desc>TX Endpoint Type'00' -&gt; Control'01' -&gt; Isochronous'10' -&gt; Bulk'11' -&gt; Interrupt</desc>
<sw_param offset="0xe00031e4" start="19" end="18" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL9_TXD">
<name>TXD</name>
<desc>TX Endpoint Data
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00031e4" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL9_TXS">
<name>TXS</name>
<desc>TX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled</desc>
<sw_param offset="0xe00031e4" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL9_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031e4" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL9_RXE">
<name>RXE</name>
<desc>RX Endpoint Enable'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00031e4" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL9_RXR">
<name>RXR</name>
<desc>RX Data Toggle Reset
Write '1' will reset the PID sequence.
Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00031e4" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL9_RXI">
<name>RXI</name>
<desc>RX Data Toggle Inhibit'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00031e4" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL9_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031e4" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL9_RXT">
<name>RXT</name>
<desc>RX Endpoint Type
Endpoint0 is fixed as a Control End Point and this field always set to '00'.</desc>
<sw_param offset="0xe00031e4" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL9_RXD">
<name>RXD</name>
<desc>RX Endpoint Data Sink
Value Meaning
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00031e4" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL9_RXS">
<name>RXS</name>
<desc>RX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled
Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request.</desc>
<sw_param offset="0xe00031e4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL10_TXE">
<name>TXE</name>
<desc>TX Endpoint Enable
Value Meaning'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00031e8" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL10_TXR">
<name>TXR</name>
<desc>TX Data Toggle Reset
Write '1' will reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00031e8" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL10_TXI">
<name>TXI</name>
<desc>TX Data Toggle Inhibit
Value Meaning'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00031e8" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL10_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031e8" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL10_TXT">
<name>TXT</name>
<desc>TX Endpoint Type'00' -&gt; Control'01' -&gt; Isochronous'10' -&gt; Bulk'11' -&gt; Interrupt</desc>
<sw_param offset="0xe00031e8" start="19" end="18" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL10_TXD">
<name>TXD</name>
<desc>TX Endpoint Data
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00031e8" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL10_TXS">
<name>TXS</name>
<desc>TX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled</desc>
<sw_param offset="0xe00031e8" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL10_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031e8" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL10_RXE">
<name>RXE</name>
<desc>RX Endpoint Enable'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00031e8" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL10_RXR">
<name>RXR</name>
<desc>RX Data Toggle Reset
Write '1' will reset the PID sequence.
Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00031e8" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL10_RXI">
<name>RXI</name>
<desc>RX Data Toggle Inhibit'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00031e8" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL10_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031e8" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL10_RXT">
<name>RXT</name>
<desc>RX Endpoint Type
Endpoint0 is fixed as a Control End Point and this field always set to '00'.</desc>
<sw_param offset="0xe00031e8" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL10_RXD">
<name>RXD</name>
<desc>RX Endpoint Data Sink
Value Meaning
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00031e8" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL10_RXS">
<name>RXS</name>
<desc>RX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled
Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request.</desc>
<sw_param offset="0xe00031e8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL11_TXE">
<name>TXE</name>
<desc>TX Endpoint Enable
Value Meaning'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00031ec" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL11_TXR">
<name>TXR</name>
<desc>TX Data Toggle Reset
Write '1' will reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00031ec" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL11_TXI">
<name>TXI</name>
<desc>TX Data Toggle Inhibit
Value Meaning'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00031ec" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL11_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031ec" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL11_TXT">
<name>TXT</name>
<desc>TX Endpoint Type'00' -&gt; Control'01' -&gt; Isochronous'10' -&gt; Bulk'11' -&gt; Interrupt</desc>
<sw_param offset="0xe00031ec" start="19" end="18" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL11_TXD">
<name>TXD</name>
<desc>TX Endpoint Data
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00031ec" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL11_TXS">
<name>TXS</name>
<desc>TX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled</desc>
<sw_param offset="0xe00031ec" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL11_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031ec" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL11_RXE">
<name>RXE</name>
<desc>RX Endpoint Enable'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00031ec" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL11_RXR">
<name>RXR</name>
<desc>RX Data Toggle Reset
Write '1' will reset the PID sequence.
Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00031ec" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL11_RXI">
<name>RXI</name>
<desc>RX Data Toggle Inhibit'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00031ec" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL11_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031ec" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL11_RXT">
<name>RXT</name>
<desc>RX Endpoint Type
Endpoint0 is fixed as a Control End Point and this field always set to '00'.</desc>
<sw_param offset="0xe00031ec" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL11_RXD">
<name>RXD</name>
<desc>RX Endpoint Data Sink
Value Meaning
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00031ec" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL11_RXS">
<name>RXS</name>
<desc>RX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled
Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request.</desc>
<sw_param offset="0xe00031ec" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL12_TXE">
<name>TXE</name>
<desc>TX Endpoint Enable
Value Meaning'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00031f0" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL12_TXR">
<name>TXR</name>
<desc>TX Data Toggle Reset
Write '1' will reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00031f0" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL12_TXI">
<name>TXI</name>
<desc>TX Data Toggle Inhibit
Value Meaning'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00031f0" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL12_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031f0" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL12_TXT">
<name>TXT</name>
<desc>TX Endpoint Type'00' -&gt; Control'01' -&gt; Isochronous'10' -&gt; Bulk'11' -&gt; Interrupt</desc>
<sw_param offset="0xe00031f0" start="19" end="18" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL12_TXD">
<name>TXD</name>
<desc>TX Endpoint Data
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00031f0" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL12_TXS">
<name>TXS</name>
<desc>TX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled</desc>
<sw_param offset="0xe00031f0" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL12_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031f0" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL12_RXE">
<name>RXE</name>
<desc>RX Endpoint Enable'0' -&gt; Disabled'1' -&gt; Enabled
An endpoint should be enabled only after it has been configured.</desc>
<sw_param offset="0xe00031f0" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL12_RXR">
<name>RXR</name>
<desc>RX Data Toggle Reset
Write '1' will reset the PID sequence.
Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.</desc>
<sw_param offset="0xe00031f0" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL12_RXI">
<name>RXI</name>
<desc>RX Data Toggle Inhibit'0' -&gt; PID Sequencing Enabled'1' -&gt; PID Sequencing Disabled</desc>
<sw_param offset="0xe00031f0" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL12_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xe00031f0" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL12_RXT">
<name>RXT</name>
<desc>RX Endpoint Type
Endpoint0 is fixed as a Control End Point and this field always set to '00'.</desc>
<sw_param offset="0xe00031f0" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL12_RXD">
<name>RXD</name>
<desc>RX Endpoint Data Sink
Value Meaning
0 Dual Port Memory Buffer/DMA Engine
Should always be written as '0'.</desc>
<sw_param offset="0xe00031f0" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_usb1_ENDPTCTRL12_RXS">
<name>RXS</name>
<desc>RX Endpoint Stall
Value Meaning'0' -&gt; Endpoint OK.'1' -&gt; Endpoint Stalled
Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request.</desc>
<sw_param offset="0xe00031f0" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort00_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf8805000" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort01_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf8805004" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort02_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf8805008" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort03_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf880500c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort04_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf8805010" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort05_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf8805014" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort06_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf8805018" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort07_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf880501c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort08_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf8805020" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort09_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf8805024" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort10_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf8805028" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort11_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf880502c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort12_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf8805030" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort13_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf8805034" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort14_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf8805038" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort15_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf880503c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort16_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf8805040" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort17_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf8805044" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort18_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf8805048" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort19_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf880504c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort20_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf8805050" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort21_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf8805054" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort22_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf8805058" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort23_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf880505c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort24_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf8805060" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort25_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf8805064" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort26_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf8805068" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort27_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf880506c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort28_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf8805070" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort29_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf8805074" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort30_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf8805078" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_StimPort31_a">
<name>a</name>
<desc>Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and
low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.</desc>
<sw_param offset="0xf880507c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_TER_a">
<name>a</name>
<desc>Bit mask to enable tracing on ITM stimulus ports.</desc>
<sw_param offset="0xf8805e00" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_TTR_a">
<name>a</name>
<desc>Bit mask to enable trigger generation, TRIGOUT, on selected writes to the Stimulus Registers.</desc>
<sw_param offset="0xf8805e20" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_CR_ITMBusy">
<name>ITMBusy</name>
<desc>ITM is transmitting trace and FIFO is not empty</desc>
<sw_param offset="0xf8805e80" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_debug_itm_CR_TraceID">
<name>TraceID</name>
<desc>ATIDM[6:0] value</desc>
<sw_param offset="0xf8805e80" start="22" end="16" />
</parameter>
<parameter uniqueid="ps7_debug_itm_CR_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8805e80" start="15" end="10" />
</parameter>
<parameter uniqueid="ps7_debug_itm_CR_TSPrescale">
<name>TSPrescale</name>
<desc>Timestamp Prescaler</desc>
<sw_param offset="0xf8805e80" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_itm_CR_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xf8805e80" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_itm_CR_DWTEn">
<name>DWTEn</name>
<desc>Enable DWT input port</desc>
<sw_param offset="0xf8805e80" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_itm_CR_SYNCEn">
<name>SYNCEn</name>
<desc>Enable sync packets</desc>
<sw_param offset="0xf8805e80" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_itm_CR_TSSEn">
<name>TSSEn</name>
<desc>Enable timestamps, delta</desc>
<sw_param offset="0xf8805e80" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_itm_CR_ITMEn">
<name>ITMEn</name>
<desc>Enable ITM Stimulus, also acts as a global enable</desc>
<sw_param offset="0xf8805e80" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_SCR_SyncCount">
<name>SyncCount</name>
<desc>Counter value for time between synchronization markers</desc>
<sw_param offset="0xf8805e90" start="11" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_ITTRIGOUTACK_ITTRIGOUTACK">
<name>ITTRIGOUTACK</name>
<desc>Read the value of TRIGOUTACK</desc>
<sw_param offset="0xf8805ee4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_ITTRIGOUT_ITTRIGOUT">
<name>ITTRIGOUT</name>
<desc>Set the value of TRIGOUT</desc>
<sw_param offset="0xf8805ee8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_ITATBDATA0_ITATDATAM7">
<name>ITATDATAM7</name>
<desc>Set the value of ATDATAM[7]</desc>
<sw_param offset="0xf8805eec" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_itm_ITATBDATA0_ITATDATAM0">
<name>ITATDATAM0</name>
<desc>Set the value of ATDATAM[0]</desc>
<sw_param offset="0xf8805eec" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_ITATBCTR2_ITATREADYM">
<name>ITATREADYM</name>
<desc>Read the value of ATREADYM</desc>
<sw_param offset="0xf8805ef0" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_ITATABCTR1_ITATIDM">
<name>ITATIDM</name>
<desc>Set the value of ATIDM[6:0]</desc>
<sw_param offset="0xf8805ef4" start="6" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_ITATBCTR0_ITAFREADYM">
<name>ITAFREADYM</name>
<desc>Set the value of AFREADYM</desc>
<sw_param offset="0xf8805ef8" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_itm_ITATBCTR0_ITATVALIDM">
<name>ITATVALIDM</name>
<desc>Set the value of ATVALIDM</desc>
<sw_param offset="0xf8805ef8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_IMCR_a">
<name>a</name>
<desc>Enable Integration Test registers.</desc>
<sw_param offset="0xf8805f00" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_CTSR_a">
<name>a</name>
<desc>The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed.
Read:
1= Claim tag is implemented, 0 = Claim tag is not implemented
Write:
1= Set claim tag bit, 0= No effect</desc>
<sw_param offset="0xf8805fa0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_CTCR_a">
<name>a</name>
<desc>The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed.
Read: Current value of claim tag.
Write: 1= Clear claim tag bit, 0= No effect</desc>
<sw_param offset="0xf8805fa4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_LAR_a">
<name>a</name>
<desc>Write Access Code.
Write behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
After reset (via PRESETDBGn), ITM is locked, i.e., writes to all other registers using lower 2GB addresses are ignored.
To unlock, 0xC5ACCE55 must be written this register.
After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register.
- PADDRDBG31=1 (upper 2GB):
ITM is unlocked when upper 2GB addresses are used to write to all the registers.
However, write to this register is ignored using a upper 2GB address!
Note: read from this register always returns 0, regardless of PADDRDBG31.</desc>
<sw_param offset="0xf8805fb0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_LSR_n8BIT">
<name>n8BIT</name>
<desc>Set to 0 since ITM implements a 32-bit lock access register</desc>
<sw_param offset="0xf8805fb4" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_itm_LSR_STATUS">
<name>STATUS</name>
<desc>Read behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
When a lower 2GB address is used to read this register, this bit indicates whether ITM is in locked state
(1= locked, 0= unlocked).
- PADDRDBG31=1 (upper 2GB):
always returns 0.</desc>
<sw_param offset="0xf8805fb4" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_itm_LSR_IMP">
<name>IMP</name>
<desc>Read behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
always returns 1, meaning lock mechanism are implemented.
- PADDRDBG31=1 (upper 2GB):
always returns 0, meaning lock mechanism is NOT implemented.</desc>
<sw_param offset="0xf8805fb4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_ASR_a">
<name>a</name>
<desc>Value is 0b1S001N00 where S is secure non-invasive debug state and N is non-secure, non-invasive debug.</desc>
<sw_param offset="0xf8805fb8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_DEVID_NumStimRegs">
<name>NumStimRegs</name>
<desc>Number of stimulus registers</desc>
<sw_param offset="0xf8805fc8" start="12" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_DTIR_a">
<name>a</name>
<desc>Indicates a Trace Source and the stimulus is devifed from bus activity</desc>
<sw_param offset="0xf8805fcc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_PERIPHID4_n4KB_count">
<name>n4KB_count</name>
<desc>4KB Count, set to 0</desc>
<sw_param offset="0xf8805fd0" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_itm_PERIPHID4_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 continuation code</desc>
<sw_param offset="0xf8805fd0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_PERIPHID5_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf8805fd4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_PERIPHID6_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf8805fd8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_PERIPHID7_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf8805fdc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_PERIPHID0_a">
<name>a</name>
<desc>PartNumber0</desc>
<sw_param offset="0xf8805fe0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_PERIPHID1_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 Identity Code [3:0]</desc>
<sw_param offset="0xf8805fe4" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_itm_PERIPHID1_PartNumber1">
<name>PartNumber1</name>
<desc>PartNumber1</desc>
<sw_param offset="0xf8805fe4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_PERIPHID2_RevNum">
<name>RevNum</name>
<desc>Revision number of Peripheral</desc>
<sw_param offset="0xf8805fe8" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_itm_PERIPHID2_JEDEC">
<name>JEDEC</name>
<desc>Indicates that a JEDEC assigned value is used</desc>
<sw_param offset="0xf8805fe8" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_itm_PERIPHID2_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 Identity Code [6:4]</desc>
<sw_param offset="0xf8805fe8" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_PERIPHID3_RevAnd">
<name>RevAnd</name>
<desc>RevAnd, at top level</desc>
<sw_param offset="0xf8805fec" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_itm_PERIPHID3_CustMod">
<name>CustMod</name>
<desc>Customer Modified</desc>
<sw_param offset="0xf8805fec" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_COMPID0_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8805ff0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_COMPID1_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8805ff4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_COMPID2_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8805ff8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_itm_COMPID3_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8805ffc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY00_AddressOffset">
<name>AddressOffset</name>
<desc>Base address of the component, relative to the ROM address.
Negative values are permitted using two's complement.
ComponentAddress = ROMAddress + (AddressOffset SHL 12)</desc>
<sw_param offset="0xf8800000" start="31" end="12" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY00_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8800000" start="11" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY00_Format">
<name>Format</name>
<desc>Format of ROM entry</desc>
<sw_param offset="0xf8800000" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY00_EntryPresent">
<name>EntryPresent</name>
<desc>Set HIGH to indicate an entry is present.</desc>
<sw_param offset="0xf8800000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY01_AddressOffset">
<name>AddressOffset</name>
<desc>Base address of the component, relative to the ROM address.
Negative values are permitted using two's complement.
ComponentAddress = ROMAddress + (AddressOffset SHL 12)</desc>
<sw_param offset="0xf8800004" start="31" end="12" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY01_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8800004" start="11" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY01_Format">
<name>Format</name>
<desc>Format of ROM entry</desc>
<sw_param offset="0xf8800004" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY01_EntryPresent">
<name>EntryPresent</name>
<desc>Set HIGH to indicate an entry is present.</desc>
<sw_param offset="0xf8800004" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY02_AddressOffset">
<name>AddressOffset</name>
<desc>Base address of the component, relative to the ROM address.
Negative values are permitted using two's complement.
ComponentAddress = ROMAddress + (AddressOffset SHL 12)</desc>
<sw_param offset="0xf8800008" start="31" end="12" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY02_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8800008" start="11" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY02_Format">
<name>Format</name>
<desc>Format of ROM entry</desc>
<sw_param offset="0xf8800008" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY02_EntryPresent">
<name>EntryPresent</name>
<desc>Set HIGH to indicate an entry is present.</desc>
<sw_param offset="0xf8800008" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY03_AddressOffset">
<name>AddressOffset</name>
<desc>Base address of the component, relative to the ROM address.
Negative values are permitted using two's complement.
ComponentAddress = ROMAddress + (AddressOffset SHL 12)</desc>
<sw_param offset="0xf880000c" start="31" end="12" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY03_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf880000c" start="11" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY03_Format">
<name>Format</name>
<desc>Format of ROM entry</desc>
<sw_param offset="0xf880000c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY03_EntryPresent">
<name>EntryPresent</name>
<desc>Set HIGH to indicate an entry is present.</desc>
<sw_param offset="0xf880000c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY04_AddressOffset">
<name>AddressOffset</name>
<desc>Base address of the component, relative to the ROM address.
Negative values are permitted using two's complement.
ComponentAddress = ROMAddress + (AddressOffset SHL 12)</desc>
<sw_param offset="0xf8800010" start="31" end="12" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY04_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8800010" start="11" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY04_Format">
<name>Format</name>
<desc>Format of ROM entry</desc>
<sw_param offset="0xf8800010" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY04_EntryPresent">
<name>EntryPresent</name>
<desc>Set HIGH to indicate an entry is present.</desc>
<sw_param offset="0xf8800010" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY05_AddressOffset">
<name>AddressOffset</name>
<desc>Base address of the component, relative to the ROM address.
Negative values are permitted using two's complement.
ComponentAddress = ROMAddress + (AddressOffset SHL 12)</desc>
<sw_param offset="0xf8800014" start="31" end="12" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY05_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8800014" start="11" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY05_Format">
<name>Format</name>
<desc>Format of ROM entry</desc>
<sw_param offset="0xf8800014" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY05_EntryPresent">
<name>EntryPresent</name>
<desc>Set HIGH to indicate an entry is present.</desc>
<sw_param offset="0xf8800014" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY06_AddressOffset">
<name>AddressOffset</name>
<desc>Base address of the component, relative to the ROM address.
Negative values are permitted using two's complement.
ComponentAddress = ROMAddress + (AddressOffset SHL 12)</desc>
<sw_param offset="0xf8800018" start="31" end="12" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY06_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8800018" start="11" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY06_Format">
<name>Format</name>
<desc>Format of ROM entry</desc>
<sw_param offset="0xf8800018" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY06_EntryPresent">
<name>EntryPresent</name>
<desc>Set HIGH to indicate an entry is present.</desc>
<sw_param offset="0xf8800018" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY07_AddressOffset">
<name>AddressOffset</name>
<desc>Base address of the component, relative to the ROM address.
Negative values are permitted using two's complement.
ComponentAddress = ROMAddress + (AddressOffset SHL 12)</desc>
<sw_param offset="0xf880001c" start="31" end="12" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY07_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf880001c" start="11" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY07_Format">
<name>Format</name>
<desc>Format of ROM entry</desc>
<sw_param offset="0xf880001c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY07_EntryPresent">
<name>EntryPresent</name>
<desc>Set HIGH to indicate an entry is present.</desc>
<sw_param offset="0xf880001c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY08_AddressOffset">
<name>AddressOffset</name>
<desc>Base address of the component, relative to the ROM address.
Negative values are permitted using two's complement.
ComponentAddress = ROMAddress + (AddressOffset SHL 12)</desc>
<sw_param offset="0xf8800020" start="31" end="12" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY08_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8800020" start="11" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY08_Format">
<name>Format</name>
<desc>Format of ROM entry</desc>
<sw_param offset="0xf8800020" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY08_EntryPresent">
<name>EntryPresent</name>
<desc>Set HIGH to indicate an entry is present.</desc>
<sw_param offset="0xf8800020" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY09_AddressOffset">
<name>AddressOffset</name>
<desc>Base address of the component, relative to the ROM address.
Negative values are permitted using two's complement.
ComponentAddress = ROMAddress + (AddressOffset SHL 12)</desc>
<sw_param offset="0xf8800024" start="31" end="12" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY09_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8800024" start="11" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY09_Format">
<name>Format</name>
<desc>Format of ROM entry</desc>
<sw_param offset="0xf8800024" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY09_EntryPresent">
<name>EntryPresent</name>
<desc>Set HIGH to indicate an entry is present.</desc>
<sw_param offset="0xf8800024" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY10_a">
<name>a</name>
<desc>Invalid entry</desc>
<sw_param offset="0xf8800028" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY11_a">
<name>a</name>
<desc>Invalid entry</desc>
<sw_param offset="0xf880002c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY12_a">
<name>a</name>
<desc>Invalid entry</desc>
<sw_param offset="0xf8800030" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY13_a">
<name>a</name>
<desc>Invalid entry</desc>
<sw_param offset="0xf8800034" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY14_a">
<name>a</name>
<desc>Invalid entry</desc>
<sw_param offset="0xf8800038" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_ROMENTRY15_a">
<name>a</name>
<desc>Invalid entry</desc>
<sw_param offset="0xf880003c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_PERIPHID4_n4KB_count">
<name>n4KB_count</name>
<desc>4KB Count, set to 0</desc>
<sw_param offset="0xf8800fd0" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_PERIPHID4_a">
<name>a</name>
<desc>JEP106 continuation code</desc>
<sw_param offset="0xf8800fd0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_PERIPHID5_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8800fd4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_PERIPHID6_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8800fd8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_PERIPHID7_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8800fdc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_PERIPHID0_PartNumber0">
<name>PartNumber0</name>
<desc>PartNumber0</desc>
<sw_param offset="0xf8800fe0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_PERIPHID1_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 Identity Code [3:0]</desc>
<sw_param offset="0xf8800fe4" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_PERIPHID1_PartNumber1">
<name>PartNumber1</name>
<desc>PartNumber1</desc>
<sw_param offset="0xf8800fe4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_PERIPHID2_RevNum">
<name>RevNum</name>
<desc>Revision number of Peripheral</desc>
<sw_param offset="0xf8800fe8" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_PERIPHID2_JEDEC">
<name>JEDEC</name>
<desc>Indicates that a JEDEC assigned value is used</desc>
<sw_param offset="0xf8800fe8" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_PERIPHID2_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 Identity Code [6:4]</desc>
<sw_param offset="0xf8800fe8" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_PERIPHID3_RevAnd">
<name>RevAnd</name>
<desc>RevAnd, at top level</desc>
<sw_param offset="0xf8800fec" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_PERIPHID3_CustMod">
<name>CustMod</name>
<desc>Customer Modified</desc>
<sw_param offset="0xf8800fec" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_COMPID0_Preamble">
<name>Preamble</name>
<desc>Preamble</desc>
<sw_param offset="0xf8800ff0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_COMPID1_Preamble">
<name>Preamble</name>
<desc>Preamble</desc>
<sw_param offset="0xf8800ff4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_COMPID2_Preamble">
<name>Preamble</name>
<desc>Preamble</desc>
<sw_param offset="0xf8800ff8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_dap_rom_COMPID3_Preamble">
<name>Preamble</name>
<desc>Preamble</desc>
<sw_param offset="0xf8800ffc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_CTICONTROL_GLBEN">
<name>GLBEN</name>
<desc>Enables or disables the ECT. When disabled, all cross triggering mapping logic functionality is disabled for this processor.</desc>
<sw_param offset="0xf880a000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_CTIINTACK_INTACK">
<name>INTACK</name>
<desc>Acknowledges the corresponding CTITRIGOUT output:
1 = CTITRIGOUT is acknowledged and is cleared when MAPTRIGOUT is LOW.
0 = no effect
There is one bit of the register for each CTITRIGOUT output.</desc>
<sw_param offset="0xf880a010" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_CTIAPPSET_APPSET">
<name>APPSET</name>
<desc>Setting a bit HIGH generates a channel event for the selected channel.
Read:
0 = application trigger inactive (reset)
1 = application trigger active.
Write:
0 = no effect
1 = generate channel event.
There is one bit of the register for each channel.</desc>
<sw_param offset="0xf880a014" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_CTIAPPCLEAR_APPCLEAR">
<name>APPCLEAR</name>
<desc>Clears corresponding bits in the CTIAPPSET register.
1 = application trigger disabled in the CTIAPPSET register
0 = no effect.
There is one bit of the register for each channel.</desc>
<sw_param offset="0xf880a018" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_CTIAPPPULSE_APPULSE">
<name>APPULSE</name>
<desc>Setting a bit HIGH generates a channel event pulse for the selected channel.
Write:
1 = channel event pulse generated for one CTICLK period
0 = no effect.
There is one bit of the register for each channel.</desc>
<sw_param offset="0xf880a01c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_CTIINEN0_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf880a020" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_CTIINEN1_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf880a024" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_CTIINEN2_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf880a028" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_CTIINEN3_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf880a02c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_CTIINEN4_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf880a030" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_CTIINEN5_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf880a034" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_CTIINEN6_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf880a038" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_CTIINEN7_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf880a03c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_CTIOUTEN0_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf880a0a0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_CTIOUTEN1_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf880a0a4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_CTIOUTEN2_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf880a0a8" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_CTIOUTEN3_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf880a0ac" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_CTIOUTEN4_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf880a0b0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_CTIOUTEN5_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf880a0b4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_CTIOUTEN6_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf880a0b8" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_CTIOUTEN7_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf880a0bc" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_CTITRIGINSTATUS_TRIGINSTATUS">
<name>TRIGINSTATUS</name>
<desc>Shows the status of the CTITRIGIN inputs:
1 = CTITRIGIN is active
0 = CTITRIGIN is inactive.
Because the register provides a view of the raw CTITRIGIN inputs, the reset value is
unknown. There is one bit of the register for each trigger input.</desc>
<sw_param offset="0xf880a130" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_CTITRIGOUTSTATUS_TRIGOUTSTATUS">
<name>TRIGOUTSTATUS</name>
<desc>Shows the status of the CTITRIGOUT outputs.
1 = CTITRIGOUT is active
0 = CTITRIGOUT is inactive (reset).
There is one bit of the register for each trigger output.</desc>
<sw_param offset="0xf880a134" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_CTICHINSTATUS_CTCHINSTATUS">
<name>CTCHINSTATUS</name>
<desc>Shows the status of the CTICHIN inputs:
1 = CTICHIN is active
0 = CTICHIN is inactive.
Because the register provides a view of the raw CTICHIN inputs from the CTM, the reset
value is unknown. There is one bit of the register for each channel input.</desc>
<sw_param offset="0xf880a138" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_CTICHOUTSTATUS_CTCHOUTSTATUS">
<name>CTCHOUTSTATUS</name>
<desc>Shows the status of the CTICHOUT outputs.
1 = CTICHOUT is active
0 = CTICHOUT is inactive (reset).
There is one bit of the register for each channel output.</desc>
<sw_param offset="0xf880a13c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_CTIGATE_CTIGATEEN3">
<name>CTIGATEEN3</name>
<desc>Enable CTICHOUT3.</desc>
<sw_param offset="0xf880a140" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_CTIGATE_CTIGATEEN2">
<name>CTIGATEEN2</name>
<desc>Enable CTICHOUT2.</desc>
<sw_param offset="0xf880a140" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_CTIGATE_CTIGATEEN1">
<name>CTIGATEEN1</name>
<desc>Enable CTICHOUT1.</desc>
<sw_param offset="0xf880a140" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_CTIGATE_CTIGATEEN0">
<name>CTIGATEEN0</name>
<desc>Enable CTICHOUT0.</desc>
<sw_param offset="0xf880a140" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_ASICCTL_ASICCTL">
<name>ASICCTL</name>
<desc>Implementation defined ASIC control, value written to the register is output on ASICCTL[7:0].</desc>
<sw_param offset="0xf880a144" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_ITCHINACK_CTCHINACK">
<name>CTCHINACK</name>
<desc>Set the value of the CTCHINACK outputs</desc>
<sw_param offset="0xf880aedc" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_ITTRIGINACK_CTTRIGINACK">
<name>CTTRIGINACK</name>
<desc>Set the value of the CTTRIGINACK outputs</desc>
<sw_param offset="0xf880aee0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_ITCHOUT_CTCHOUT">
<name>CTCHOUT</name>
<desc>Set the value of the CTCHOUT outputs</desc>
<sw_param offset="0xf880aee4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_ITTRIGOUT_CTTRIGOUT">
<name>CTTRIGOUT</name>
<desc>Set the value of the CTTRIGOUT outputs</desc>
<sw_param offset="0xf880aee8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_ITCHOUTACK_CTCHOUTACK">
<name>CTCHOUTACK</name>
<desc>Read the values of the CTCHOUTACK inputs</desc>
<sw_param offset="0xf880aeec" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_ITTRIGOUTACK_CTTRIGOUTACK">
<name>CTTRIGOUTACK</name>
<desc>Read the values of the CTTRIGOUTACK inputs</desc>
<sw_param offset="0xf880aef0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_ITCHIN_CTCHIN">
<name>CTCHIN</name>
<desc>Read the values of the CTCHIN inputs</desc>
<sw_param offset="0xf880aef4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_ITTRIGIN_CTTRIGIN">
<name>CTTRIGIN</name>
<desc>Read the values of the CTTRIGIN inputs</desc>
<sw_param offset="0xf880aef8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_ITCTRL_a">
<name>a</name>
<desc>Enable IT Registers</desc>
<sw_param offset="0xf880af00" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_CTSR_SET">
<name>SET</name>
<desc>The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed.
Read:
1= Claim tag is implemented, 0 = Claim tag is not implemented
Write:
1= Set claim tag bit, 0= No effect</desc>
<sw_param offset="0xf880afa0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_CTCR_CLEAR">
<name>CLEAR</name>
<desc>The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed.
Read: Current value of claim tag.
Write: 1= Clear claim tag bit, 0= No effect</desc>
<sw_param offset="0xf880afa4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_LAR_KEY">
<name>KEY</name>
<desc>Write Access Code.
Write behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored.
To unlock, 0xC5ACCE55 must be written this register.
After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register.
- PADDRDBG31=1 (upper 2GB):
CTI is unlocked when upper 2GB addresses are used to write to all the registers.
However, write to this register is ignored using a upper 2GB address!
Note: read from this register always returns 0, regardless of PADDRDBG31.</desc>
<sw_param offset="0xf880afb0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_LSR_n8BIT">
<name>n8BIT</name>
<desc>Set to 0 since CTI implements a 32-bit lock access register</desc>
<sw_param offset="0xf880afb4" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_LSR_STATUS">
<name>STATUS</name>
<desc>Read behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
When a lower 2GB address is used to read this register, this bit indicates whether CTI is in locked state
(1= locked, 0= unlocked).
- PADDRDBG31=1 (upper 2GB):
always returns 0.</desc>
<sw_param offset="0xf880afb4" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_LSR_IMP">
<name>IMP</name>
<desc>Read behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
always returns 1, meaning lock mechanism are implemented.
- PADDRDBG31=1 (upper 2GB):
always returns 0, meaning lock mechanism is NOT implemented.</desc>
<sw_param offset="0xf880afb4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_ASR_NIDEN">
<name>NIDEN</name>
<desc>Current value of noninvasive debug enable signals</desc>
<sw_param offset="0xf880afb8" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_ASR_NIDEN_CTL">
<name>NIDEN_CTL</name>
<desc>Non-invasive debug controlled</desc>
<sw_param offset="0xf880afb8" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_ASR_IDEN">
<name>IDEN</name>
<desc>Current value of invasive debug enable signals</desc>
<sw_param offset="0xf880afb8" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_ASR_IDEN_CTL">
<name>IDEN_CTL</name>
<desc>Invasive debug controlled</desc>
<sw_param offset="0xf880afb8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_DEVID_NumChan">
<name>NumChan</name>
<desc>Number of channels available</desc>
<sw_param offset="0xf880afc8" start="19" end="16" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_DEVID_NumTrig">
<name>NumTrig</name>
<desc>Number of triggers available</desc>
<sw_param offset="0xf880afc8" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_DEVID_res">
<name>res</name>
<desc>reserved</desc>
<sw_param offset="0xf880afc8" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_DEVID_ExtMux">
<name>ExtMux</name>
<desc>no external muxing</desc>
<sw_param offset="0xf880afc8" start="4" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_DTIR_a">
<name>a</name>
<desc>major type is a debug control logic component, sub-type is cross trigger</desc>
<sw_param offset="0xf880afcc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_PERIPHID4_n4KB_count">
<name>n4KB_count</name>
<desc>4KB Count, set to 0</desc>
<sw_param offset="0xf880afd0" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_PERIPHID4_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 continuation code</desc>
<sw_param offset="0xf880afd0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_PERIPHID5_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf880afd4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_PERIPHID6_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf880afd8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_PERIPHID7_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf880afdc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_PERIPHID0_a">
<name>a</name>
<desc>PartNumber0</desc>
<sw_param offset="0xf880afe0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_PERIPHID1_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 Identity Code [3:0]</desc>
<sw_param offset="0xf880afe4" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_PERIPHID1_PartNumber1">
<name>PartNumber1</name>
<desc>PartNumber1</desc>
<sw_param offset="0xf880afe4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_PERIPHID2_RevNum">
<name>RevNum</name>
<desc>Revision number of Peripheral</desc>
<sw_param offset="0xf880afe8" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_PERIPHID2_JEDEC">
<name>JEDEC</name>
<desc>Indicates that a JEDEC assigned value is used</desc>
<sw_param offset="0xf880afe8" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_PERIPHID2_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 Identity Code [6:4]</desc>
<sw_param offset="0xf880afe8" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_PERIPHID3_RevAnd">
<name>RevAnd</name>
<desc>RevAnd, at top level</desc>
<sw_param offset="0xf880afec" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_PERIPHID3_CustMod">
<name>CustMod</name>
<desc>Customer Modified</desc>
<sw_param offset="0xf880afec" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_COMPID0_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf880aff0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_COMPID1_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf880aff4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_COMPID2_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf880aff8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_axim_COMPID3_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf880affc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_CTICONTROL_GLBEN">
<name>GLBEN</name>
<desc>Enables or disables the ECT. When disabled, all cross triggering mapping logic functionality is disabled for this processor.</desc>
<sw_param offset="0xf8899000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_CTIINTACK_INTACK">
<name>INTACK</name>
<desc>Acknowledges the corresponding CTITRIGOUT output:
1 = CTITRIGOUT is acknowledged and is cleared when MAPTRIGOUT is LOW.
0 = no effect
There is one bit of the register for each CTITRIGOUT output.</desc>
<sw_param offset="0xf8899010" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_CTIAPPSET_APPSET">
<name>APPSET</name>
<desc>Setting a bit HIGH generates a channel event for the selected channel.
Read:
0 = application trigger inactive (reset)
1 = application trigger active.
Write:
0 = no effect
1 = generate channel event.
There is one bit of the register for each channel.</desc>
<sw_param offset="0xf8899014" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_CTIAPPCLEAR_APPCLEAR">
<name>APPCLEAR</name>
<desc>Clears corresponding bits in the CTIAPPSET register.
1 = application trigger disabled in the CTIAPPSET register
0 = no effect.
There is one bit of the register for each channel.</desc>
<sw_param offset="0xf8899018" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_CTIAPPPULSE_APPULSE">
<name>APPULSE</name>
<desc>Setting a bit HIGH generates a channel event pulse for the selected channel.
Write:
1 = channel event pulse generated for one CTICLK period
0 = no effect.
There is one bit of the register for each channel.</desc>
<sw_param offset="0xf889901c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_CTIINEN0_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf8899020" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_CTIINEN1_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf8899024" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_CTIINEN2_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf8899028" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_CTIINEN3_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf889902c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_CTIINEN4_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf8899030" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_CTIINEN5_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf8899034" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_CTIINEN6_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf8899038" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_CTIINEN7_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf889903c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_CTIOUTEN0_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88990a0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_CTIOUTEN1_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88990a4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_CTIOUTEN2_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88990a8" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_CTIOUTEN3_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88990ac" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_CTIOUTEN4_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88990b0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_CTIOUTEN5_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88990b4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_CTIOUTEN6_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88990b8" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_CTIOUTEN7_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88990bc" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_CTITRIGINSTATUS_TRIGINSTATUS">
<name>TRIGINSTATUS</name>
<desc>Shows the status of the CTITRIGIN inputs:
1 = CTITRIGIN is active
0 = CTITRIGIN is inactive.
Because the register provides a view of the raw CTITRIGIN inputs, the reset value is
unknown. There is one bit of the register for each trigger input.</desc>
<sw_param offset="0xf8899130" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_CTITRIGOUTSTATUS_TRIGOUTSTATUS">
<name>TRIGOUTSTATUS</name>
<desc>Shows the status of the CTITRIGOUT outputs.
1 = CTITRIGOUT is active
0 = CTITRIGOUT is inactive (reset).
There is one bit of the register for each trigger output.</desc>
<sw_param offset="0xf8899134" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_CTICHINSTATUS_CTCHINSTATUS">
<name>CTCHINSTATUS</name>
<desc>Shows the status of the CTICHIN inputs:
1 = CTICHIN is active
0 = CTICHIN is inactive.
Because the register provides a view of the raw CTICHIN inputs from the CTM, the reset
value is unknown. There is one bit of the register for each channel input.</desc>
<sw_param offset="0xf8899138" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_CTICHOUTSTATUS_CTCHOUTSTATUS">
<name>CTCHOUTSTATUS</name>
<desc>Shows the status of the CTICHOUT outputs.
1 = CTICHOUT is active
0 = CTICHOUT is inactive (reset).
There is one bit of the register for each channel output.</desc>
<sw_param offset="0xf889913c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_CTIGATE_CTIGATEEN3">
<name>CTIGATEEN3</name>
<desc>Enable CTICHOUT3.</desc>
<sw_param offset="0xf8899140" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_CTIGATE_CTIGATEEN2">
<name>CTIGATEEN2</name>
<desc>Enable CTICHOUT2.</desc>
<sw_param offset="0xf8899140" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_CTIGATE_CTIGATEEN1">
<name>CTIGATEEN1</name>
<desc>Enable CTICHOUT1.</desc>
<sw_param offset="0xf8899140" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_CTIGATE_CTIGATEEN0">
<name>CTIGATEEN0</name>
<desc>Enable CTICHOUT0.</desc>
<sw_param offset="0xf8899140" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_ASICCTL_ASICCTL">
<name>ASICCTL</name>
<desc>Implementation defined ASIC control, value written to the register is output on ASICCTL[7:0].</desc>
<sw_param offset="0xf8899144" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_ITCHINACK_CTCHINACK">
<name>CTCHINACK</name>
<desc>Set the value of the CTCHINACK outputs</desc>
<sw_param offset="0xf8899edc" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_ITTRIGINACK_CTTRIGINACK">
<name>CTTRIGINACK</name>
<desc>Set the value of the CTTRIGINACK outputs</desc>
<sw_param offset="0xf8899ee0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_ITCHOUT_CTCHOUT">
<name>CTCHOUT</name>
<desc>Set the value of the CTCHOUT outputs</desc>
<sw_param offset="0xf8899ee4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_ITTRIGOUT_CTTRIGOUT">
<name>CTTRIGOUT</name>
<desc>Set the value of the CTTRIGOUT outputs</desc>
<sw_param offset="0xf8899ee8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_ITCHOUTACK_CTCHOUTACK">
<name>CTCHOUTACK</name>
<desc>Read the values of the CTCHOUTACK inputs</desc>
<sw_param offset="0xf8899eec" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_ITTRIGOUTACK_CTTRIGOUTACK">
<name>CTTRIGOUTACK</name>
<desc>Read the values of the CTTRIGOUTACK inputs</desc>
<sw_param offset="0xf8899ef0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_ITCHIN_CTCHIN">
<name>CTCHIN</name>
<desc>Read the values of the CTCHIN inputs</desc>
<sw_param offset="0xf8899ef4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_ITTRIGIN_CTTRIGIN">
<name>CTTRIGIN</name>
<desc>Read the values of the CTTRIGIN inputs</desc>
<sw_param offset="0xf8899ef8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_ITCTRL_a">
<name>a</name>
<desc>Enable IT Registers</desc>
<sw_param offset="0xf8899f00" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_CTSR_SET">
<name>SET</name>
<desc>The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed.
Read:
1= Claim tag is implemented, 0 = Claim tag is not implemented
Write:
1= Set claim tag bit, 0= No effect</desc>
<sw_param offset="0xf8899fa0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_CTCR_CLEAR">
<name>CLEAR</name>
<desc>The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed.
Read: Current value of claim tag.
Write: 1= Clear claim tag bit, 0= No effect</desc>
<sw_param offset="0xf8899fa4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_LAR_KEY">
<name>KEY</name>
<desc>Write Access Code.
Write behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored.
To unlock, 0xC5ACCE55 must be written this register.
After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register.
- PADDRDBG31=1 (upper 2GB):
CTI is unlocked when upper 2GB addresses are used to write to all the registers.
However, write to this register is ignored using a upper 2GB address!
Note: read from this register always returns 0, regardless of PADDRDBG31.</desc>
<sw_param offset="0xf8899fb0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_LSR_n8BIT">
<name>n8BIT</name>
<desc>Set to 0 since CTI implements a 32-bit lock access register</desc>
<sw_param offset="0xf8899fb4" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_LSR_STATUS">
<name>STATUS</name>
<desc>Read behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
When a lower 2GB address is used to read this register, this bit indicates whether CTI is in locked state
(1= locked, 0= unlocked).
- PADDRDBG31=1 (upper 2GB):
always returns 0.</desc>
<sw_param offset="0xf8899fb4" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_LSR_IMP">
<name>IMP</name>
<desc>Read behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
always returns 1, meaning lock mechanism are implemented.
- PADDRDBG31=1 (upper 2GB):
always returns 0, meaning lock mechanism is NOT implemented.</desc>
<sw_param offset="0xf8899fb4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_ASR_NIDEN">
<name>NIDEN</name>
<desc>Current value of noninvasive debug enable signals</desc>
<sw_param offset="0xf8899fb8" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_ASR_NIDEN_CTL">
<name>NIDEN_CTL</name>
<desc>Non-invasive debug controlled</desc>
<sw_param offset="0xf8899fb8" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_ASR_IDEN">
<name>IDEN</name>
<desc>Current value of invasive debug enable signals</desc>
<sw_param offset="0xf8899fb8" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_ASR_IDEN_CTL">
<name>IDEN_CTL</name>
<desc>Invasive debug controlled</desc>
<sw_param offset="0xf8899fb8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_DEVID_NumChan">
<name>NumChan</name>
<desc>Number of channels available</desc>
<sw_param offset="0xf8899fc8" start="19" end="16" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_DEVID_NumTrig">
<name>NumTrig</name>
<desc>Number of triggers available</desc>
<sw_param offset="0xf8899fc8" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_DEVID_res">
<name>res</name>
<desc>reserved</desc>
<sw_param offset="0xf8899fc8" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_DEVID_ExtMux">
<name>ExtMux</name>
<desc>no external muxing</desc>
<sw_param offset="0xf8899fc8" start="4" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_DTIR_a">
<name>a</name>
<desc>major type is a debug control logic component, sub-type is cross trigger</desc>
<sw_param offset="0xf8899fcc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_PERIPHID4_n4KB_count">
<name>n4KB_count</name>
<desc>4KB Count, set to 0</desc>
<sw_param offset="0xf8899fd0" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_PERIPHID4_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 continuation code</desc>
<sw_param offset="0xf8899fd0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_PERIPHID5_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf8899fd4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_PERIPHID6_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf8899fd8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_PERIPHID7_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf8899fdc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_PERIPHID0_a">
<name>a</name>
<desc>PartNumber0</desc>
<sw_param offset="0xf8899fe0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_PERIPHID1_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 Identity Code [3:0]</desc>
<sw_param offset="0xf8899fe4" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_PERIPHID1_PartNumber1">
<name>PartNumber1</name>
<desc>PartNumber1</desc>
<sw_param offset="0xf8899fe4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_PERIPHID2_RevNum">
<name>RevNum</name>
<desc>Revision number of Peripheral</desc>
<sw_param offset="0xf8899fe8" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_PERIPHID2_JEDEC">
<name>JEDEC</name>
<desc>Indicates that a JEDEC assigned value is used</desc>
<sw_param offset="0xf8899fe8" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_PERIPHID2_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 Identity Code [6:4]</desc>
<sw_param offset="0xf8899fe8" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_PERIPHID3_RevAnd">
<name>RevAnd</name>
<desc>RevAnd, at top level</desc>
<sw_param offset="0xf8899fec" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_PERIPHID3_CustMod">
<name>CustMod</name>
<desc>Customer Modified</desc>
<sw_param offset="0xf8899fec" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_COMPID0_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8899ff0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_COMPID1_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8899ff4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_COMPID2_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8899ff8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti1_COMPID3_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8899ffc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_CTICONTROL_GLBEN">
<name>GLBEN</name>
<desc>Enables or disables the ECT. When disabled, all cross triggering mapping logic functionality is disabled for this processor.</desc>
<sw_param offset="0xf8898000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_CTIINTACK_INTACK">
<name>INTACK</name>
<desc>Acknowledges the corresponding CTITRIGOUT output:
1 = CTITRIGOUT is acknowledged and is cleared when MAPTRIGOUT is LOW.
0 = no effect
There is one bit of the register for each CTITRIGOUT output.</desc>
<sw_param offset="0xf8898010" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_CTIAPPSET_APPSET">
<name>APPSET</name>
<desc>Setting a bit HIGH generates a channel event for the selected channel.
Read:
0 = application trigger inactive (reset)
1 = application trigger active.
Write:
0 = no effect
1 = generate channel event.
There is one bit of the register for each channel.</desc>
<sw_param offset="0xf8898014" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_CTIAPPCLEAR_APPCLEAR">
<name>APPCLEAR</name>
<desc>Clears corresponding bits in the CTIAPPSET register.
1 = application trigger disabled in the CTIAPPSET register
0 = no effect.
There is one bit of the register for each channel.</desc>
<sw_param offset="0xf8898018" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_CTIAPPPULSE_APPULSE">
<name>APPULSE</name>
<desc>Setting a bit HIGH generates a channel event pulse for the selected channel.
Write:
1 = channel event pulse generated for one CTICLK period
0 = no effect.
There is one bit of the register for each channel.</desc>
<sw_param offset="0xf889801c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_CTIINEN0_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf8898020" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_CTIINEN1_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf8898024" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_CTIINEN2_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf8898028" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_CTIINEN3_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf889802c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_CTIINEN4_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf8898030" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_CTIINEN5_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf8898034" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_CTIINEN6_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf8898038" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_CTIINEN7_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf889803c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_CTIOUTEN0_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88980a0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_CTIOUTEN1_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88980a4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_CTIOUTEN2_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88980a8" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_CTIOUTEN3_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88980ac" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_CTIOUTEN4_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88980b0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_CTIOUTEN5_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88980b4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_CTIOUTEN6_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88980b8" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_CTIOUTEN7_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88980bc" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_CTITRIGINSTATUS_TRIGINSTATUS">
<name>TRIGINSTATUS</name>
<desc>Shows the status of the CTITRIGIN inputs:
1 = CTITRIGIN is active
0 = CTITRIGIN is inactive.
Because the register provides a view of the raw CTITRIGIN inputs, the reset value is
unknown. There is one bit of the register for each trigger input.</desc>
<sw_param offset="0xf8898130" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_CTITRIGOUTSTATUS_TRIGOUTSTATUS">
<name>TRIGOUTSTATUS</name>
<desc>Shows the status of the CTITRIGOUT outputs.
1 = CTITRIGOUT is active
0 = CTITRIGOUT is inactive (reset).
There is one bit of the register for each trigger output.</desc>
<sw_param offset="0xf8898134" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_CTICHINSTATUS_CTCHINSTATUS">
<name>CTCHINSTATUS</name>
<desc>Shows the status of the CTICHIN inputs:
1 = CTICHIN is active
0 = CTICHIN is inactive.
Because the register provides a view of the raw CTICHIN inputs from the CTM, the reset
value is unknown. There is one bit of the register for each channel input.</desc>
<sw_param offset="0xf8898138" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_CTICHOUTSTATUS_CTCHOUTSTATUS">
<name>CTCHOUTSTATUS</name>
<desc>Shows the status of the CTICHOUT outputs.
1 = CTICHOUT is active
0 = CTICHOUT is inactive (reset).
There is one bit of the register for each channel output.</desc>
<sw_param offset="0xf889813c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_CTIGATE_CTIGATEEN3">
<name>CTIGATEEN3</name>
<desc>Enable CTICHOUT3.</desc>
<sw_param offset="0xf8898140" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_CTIGATE_CTIGATEEN2">
<name>CTIGATEEN2</name>
<desc>Enable CTICHOUT2.</desc>
<sw_param offset="0xf8898140" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_CTIGATE_CTIGATEEN1">
<name>CTIGATEEN1</name>
<desc>Enable CTICHOUT1.</desc>
<sw_param offset="0xf8898140" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_CTIGATE_CTIGATEEN0">
<name>CTIGATEEN0</name>
<desc>Enable CTICHOUT0.</desc>
<sw_param offset="0xf8898140" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_ASICCTL_ASICCTL">
<name>ASICCTL</name>
<desc>Implementation defined ASIC control, value written to the register is output on ASICCTL[7:0].</desc>
<sw_param offset="0xf8898144" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_ITCHINACK_CTCHINACK">
<name>CTCHINACK</name>
<desc>Set the value of the CTCHINACK outputs</desc>
<sw_param offset="0xf8898edc" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_ITTRIGINACK_CTTRIGINACK">
<name>CTTRIGINACK</name>
<desc>Set the value of the CTTRIGINACK outputs</desc>
<sw_param offset="0xf8898ee0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_ITCHOUT_CTCHOUT">
<name>CTCHOUT</name>
<desc>Set the value of the CTCHOUT outputs</desc>
<sw_param offset="0xf8898ee4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_ITTRIGOUT_CTTRIGOUT">
<name>CTTRIGOUT</name>
<desc>Set the value of the CTTRIGOUT outputs</desc>
<sw_param offset="0xf8898ee8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_ITCHOUTACK_CTCHOUTACK">
<name>CTCHOUTACK</name>
<desc>Read the values of the CTCHOUTACK inputs</desc>
<sw_param offset="0xf8898eec" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_ITTRIGOUTACK_CTTRIGOUTACK">
<name>CTTRIGOUTACK</name>
<desc>Read the values of the CTTRIGOUTACK inputs</desc>
<sw_param offset="0xf8898ef0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_ITCHIN_CTCHIN">
<name>CTCHIN</name>
<desc>Read the values of the CTCHIN inputs</desc>
<sw_param offset="0xf8898ef4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_ITTRIGIN_CTTRIGIN">
<name>CTTRIGIN</name>
<desc>Read the values of the CTTRIGIN inputs</desc>
<sw_param offset="0xf8898ef8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_ITCTRL_a">
<name>a</name>
<desc>Enable IT Registers</desc>
<sw_param offset="0xf8898f00" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_CTSR_SET">
<name>SET</name>
<desc>The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed.
Read:
1= Claim tag is implemented, 0 = Claim tag is not implemented
Write:
1= Set claim tag bit, 0= No effect</desc>
<sw_param offset="0xf8898fa0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_CTCR_CLEAR">
<name>CLEAR</name>
<desc>The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed.
Read: Current value of claim tag.
Write: 1= Clear claim tag bit, 0= No effect</desc>
<sw_param offset="0xf8898fa4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_LAR_KEY">
<name>KEY</name>
<desc>Write Access Code.
Write behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored.
To unlock, 0xC5ACCE55 must be written this register.
After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register.
- PADDRDBG31=1 (upper 2GB):
CTI is unlocked when upper 2GB addresses are used to write to all the registers.
However, write to this register is ignored using a upper 2GB address!
Note: read from this register always returns 0, regardless of PADDRDBG31.</desc>
<sw_param offset="0xf8898fb0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_LSR_n8BIT">
<name>n8BIT</name>
<desc>Set to 0 since CTI implements a 32-bit lock access register</desc>
<sw_param offset="0xf8898fb4" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_LSR_STATUS">
<name>STATUS</name>
<desc>Read behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
When a lower 2GB address is used to read this register, this bit indicates whether CTI is in locked state
(1= locked, 0= unlocked).
- PADDRDBG31=1 (upper 2GB):
always returns 0.</desc>
<sw_param offset="0xf8898fb4" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_LSR_IMP">
<name>IMP</name>
<desc>Read behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
always returns 1, meaning lock mechanism are implemented.
- PADDRDBG31=1 (upper 2GB):
always returns 0, meaning lock mechanism is NOT implemented.</desc>
<sw_param offset="0xf8898fb4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_ASR_NIDEN">
<name>NIDEN</name>
<desc>Current value of noninvasive debug enable signals</desc>
<sw_param offset="0xf8898fb8" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_ASR_NIDEN_CTL">
<name>NIDEN_CTL</name>
<desc>Non-invasive debug controlled</desc>
<sw_param offset="0xf8898fb8" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_ASR_IDEN">
<name>IDEN</name>
<desc>Current value of invasive debug enable signals</desc>
<sw_param offset="0xf8898fb8" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_ASR_IDEN_CTL">
<name>IDEN_CTL</name>
<desc>Invasive debug controlled</desc>
<sw_param offset="0xf8898fb8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_DEVID_NumChan">
<name>NumChan</name>
<desc>Number of channels available</desc>
<sw_param offset="0xf8898fc8" start="19" end="16" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_DEVID_NumTrig">
<name>NumTrig</name>
<desc>Number of triggers available</desc>
<sw_param offset="0xf8898fc8" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_DEVID_res">
<name>res</name>
<desc>reserved</desc>
<sw_param offset="0xf8898fc8" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_DEVID_ExtMux">
<name>ExtMux</name>
<desc>no external muxing</desc>
<sw_param offset="0xf8898fc8" start="4" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_DTIR_a">
<name>a</name>
<desc>major type is a debug control logic component, sub-type is cross trigger</desc>
<sw_param offset="0xf8898fcc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_PERIPHID4_n4KB_count">
<name>n4KB_count</name>
<desc>4KB Count, set to 0</desc>
<sw_param offset="0xf8898fd0" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_PERIPHID4_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 continuation code</desc>
<sw_param offset="0xf8898fd0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_PERIPHID5_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf8898fd4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_PERIPHID6_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf8898fd8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_PERIPHID7_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf8898fdc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_PERIPHID0_a">
<name>a</name>
<desc>PartNumber0</desc>
<sw_param offset="0xf8898fe0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_PERIPHID1_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 Identity Code [3:0]</desc>
<sw_param offset="0xf8898fe4" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_PERIPHID1_PartNumber1">
<name>PartNumber1</name>
<desc>PartNumber1</desc>
<sw_param offset="0xf8898fe4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_PERIPHID2_RevNum">
<name>RevNum</name>
<desc>Revision number of Peripheral</desc>
<sw_param offset="0xf8898fe8" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_PERIPHID2_JEDEC">
<name>JEDEC</name>
<desc>Indicates that a JEDEC assigned value is used</desc>
<sw_param offset="0xf8898fe8" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_PERIPHID2_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 Identity Code [6:4]</desc>
<sw_param offset="0xf8898fe8" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_PERIPHID3_RevAnd">
<name>RevAnd</name>
<desc>RevAnd, at top level</desc>
<sw_param offset="0xf8898fec" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_PERIPHID3_CustMod">
<name>CustMod</name>
<desc>Customer Modified</desc>
<sw_param offset="0xf8898fec" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_COMPID0_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8898ff0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_COMPID1_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8898ff4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_COMPID2_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8898ff8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_cti0_COMPID3_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8898ffc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_CTICONTROL_GLBEN">
<name>GLBEN</name>
<desc>Enables or disables the ECT. When disabled, all cross triggering mapping logic functionality is disabled for this processor.</desc>
<sw_param offset="0xf8809000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_CTIINTACK_INTACK">
<name>INTACK</name>
<desc>Acknowledges the corresponding CTITRIGOUT output:
1 = CTITRIGOUT is acknowledged and is cleared when MAPTRIGOUT is LOW.
0 = no effect
There is one bit of the register for each CTITRIGOUT output.</desc>
<sw_param offset="0xf8809010" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_CTIAPPSET_APPSET">
<name>APPSET</name>
<desc>Setting a bit HIGH generates a channel event for the selected channel.
Read:
0 = application trigger inactive (reset)
1 = application trigger active.
Write:
0 = no effect
1 = generate channel event.
There is one bit of the register for each channel.</desc>
<sw_param offset="0xf8809014" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_CTIAPPCLEAR_APPCLEAR">
<name>APPCLEAR</name>
<desc>Clears corresponding bits in the CTIAPPSET register.
1 = application trigger disabled in the CTIAPPSET register
0 = no effect.
There is one bit of the register for each channel.</desc>
<sw_param offset="0xf8809018" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_CTIAPPPULSE_APPULSE">
<name>APPULSE</name>
<desc>Setting a bit HIGH generates a channel event pulse for the selected channel.
Write:
1 = channel event pulse generated for one CTICLK period
0 = no effect.
There is one bit of the register for each channel.</desc>
<sw_param offset="0xf880901c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_CTIINEN0_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf8809020" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_CTIINEN1_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf8809024" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_CTIINEN2_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf8809028" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_CTIINEN3_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf880902c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_CTIINEN4_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf8809030" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_CTIINEN5_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf8809034" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_CTIINEN6_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf8809038" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_CTIINEN7_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf880903c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_CTIOUTEN0_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88090a0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_CTIOUTEN1_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88090a4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_CTIOUTEN2_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88090a8" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_CTIOUTEN3_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88090ac" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_CTIOUTEN4_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88090b0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_CTIOUTEN5_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88090b4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_CTIOUTEN6_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88090b8" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_CTIOUTEN7_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88090bc" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_CTITRIGINSTATUS_TRIGINSTATUS">
<name>TRIGINSTATUS</name>
<desc>Shows the status of the CTITRIGIN inputs:
1 = CTITRIGIN is active
0 = CTITRIGIN is inactive.
Because the register provides a view of the raw CTITRIGIN inputs, the reset value is
unknown. There is one bit of the register for each trigger input.</desc>
<sw_param offset="0xf8809130" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_CTITRIGOUTSTATUS_TRIGOUTSTATUS">
<name>TRIGOUTSTATUS</name>
<desc>Shows the status of the CTITRIGOUT outputs.
1 = CTITRIGOUT is active
0 = CTITRIGOUT is inactive (reset).
There is one bit of the register for each trigger output.</desc>
<sw_param offset="0xf8809134" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_CTICHINSTATUS_CTCHINSTATUS">
<name>CTCHINSTATUS</name>
<desc>Shows the status of the CTICHIN inputs:
1 = CTICHIN is active
0 = CTICHIN is inactive.
Because the register provides a view of the raw CTICHIN inputs from the CTM, the reset
value is unknown. There is one bit of the register for each channel input.</desc>
<sw_param offset="0xf8809138" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_CTICHOUTSTATUS_CTCHOUTSTATUS">
<name>CTCHOUTSTATUS</name>
<desc>Shows the status of the CTICHOUT outputs.
1 = CTICHOUT is active
0 = CTICHOUT is inactive (reset).
There is one bit of the register for each channel output.</desc>
<sw_param offset="0xf880913c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_CTIGATE_CTIGATEEN3">
<name>CTIGATEEN3</name>
<desc>Enable CTICHOUT3.</desc>
<sw_param offset="0xf8809140" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_CTIGATE_CTIGATEEN2">
<name>CTIGATEEN2</name>
<desc>Enable CTICHOUT2.</desc>
<sw_param offset="0xf8809140" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_CTIGATE_CTIGATEEN1">
<name>CTIGATEEN1</name>
<desc>Enable CTICHOUT1.</desc>
<sw_param offset="0xf8809140" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_CTIGATE_CTIGATEEN0">
<name>CTIGATEEN0</name>
<desc>Enable CTICHOUT0.</desc>
<sw_param offset="0xf8809140" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_ASICCTL_ASICCTL">
<name>ASICCTL</name>
<desc>Implementation defined ASIC control, value written to the register is output on ASICCTL[7:0].</desc>
<sw_param offset="0xf8809144" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_ITCHINACK_CTCHINACK">
<name>CTCHINACK</name>
<desc>Set the value of the CTCHINACK outputs</desc>
<sw_param offset="0xf8809edc" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_ITTRIGINACK_CTTRIGINACK">
<name>CTTRIGINACK</name>
<desc>Set the value of the CTTRIGINACK outputs</desc>
<sw_param offset="0xf8809ee0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_ITCHOUT_CTCHOUT">
<name>CTCHOUT</name>
<desc>Set the value of the CTCHOUT outputs</desc>
<sw_param offset="0xf8809ee4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_ITTRIGOUT_CTTRIGOUT">
<name>CTTRIGOUT</name>
<desc>Set the value of the CTTRIGOUT outputs</desc>
<sw_param offset="0xf8809ee8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_ITCHOUTACK_CTCHOUTACK">
<name>CTCHOUTACK</name>
<desc>Read the values of the CTCHOUTACK inputs</desc>
<sw_param offset="0xf8809eec" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_ITTRIGOUTACK_CTTRIGOUTACK">
<name>CTTRIGOUTACK</name>
<desc>Read the values of the CTTRIGOUTACK inputs</desc>
<sw_param offset="0xf8809ef0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_ITCHIN_CTCHIN">
<name>CTCHIN</name>
<desc>Read the values of the CTCHIN inputs</desc>
<sw_param offset="0xf8809ef4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_ITTRIGIN_CTTRIGIN">
<name>CTTRIGIN</name>
<desc>Read the values of the CTTRIGIN inputs</desc>
<sw_param offset="0xf8809ef8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_ITCTRL_a">
<name>a</name>
<desc>Enable IT Registers</desc>
<sw_param offset="0xf8809f00" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_CTSR_SET">
<name>SET</name>
<desc>The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed.
Read:
1= Claim tag is implemented, 0 = Claim tag is not implemented
Write:
1= Set claim tag bit, 0= No effect</desc>
<sw_param offset="0xf8809fa0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_CTCR_CLEAR">
<name>CLEAR</name>
<desc>The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed.
Read: Current value of claim tag.
Write: 1= Clear claim tag bit, 0= No effect</desc>
<sw_param offset="0xf8809fa4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_LAR_KEY">
<name>KEY</name>
<desc>Write Access Code.
Write behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored.
To unlock, 0xC5ACCE55 must be written this register.
After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register.
- PADDRDBG31=1 (upper 2GB):
CTI is unlocked when upper 2GB addresses are used to write to all the registers.
However, write to this register is ignored using a upper 2GB address!
Note: read from this register always returns 0, regardless of PADDRDBG31.</desc>
<sw_param offset="0xf8809fb0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_LSR_n8BIT">
<name>n8BIT</name>
<desc>Set to 0 since CTI implements a 32-bit lock access register</desc>
<sw_param offset="0xf8809fb4" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_LSR_STATUS">
<name>STATUS</name>
<desc>Read behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
When a lower 2GB address is used to read this register, this bit indicates whether CTI is in locked state
(1= locked, 0= unlocked).
- PADDRDBG31=1 (upper 2GB):
always returns 0.</desc>
<sw_param offset="0xf8809fb4" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_LSR_IMP">
<name>IMP</name>
<desc>Read behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
always returns 1, meaning lock mechanism are implemented.
- PADDRDBG31=1 (upper 2GB):
always returns 0, meaning lock mechanism is NOT implemented.</desc>
<sw_param offset="0xf8809fb4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_ASR_NIDEN">
<name>NIDEN</name>
<desc>Current value of noninvasive debug enable signals</desc>
<sw_param offset="0xf8809fb8" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_ASR_NIDEN_CTL">
<name>NIDEN_CTL</name>
<desc>Non-invasive debug controlled</desc>
<sw_param offset="0xf8809fb8" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_ASR_IDEN">
<name>IDEN</name>
<desc>Current value of invasive debug enable signals</desc>
<sw_param offset="0xf8809fb8" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_ASR_IDEN_CTL">
<name>IDEN_CTL</name>
<desc>Invasive debug controlled</desc>
<sw_param offset="0xf8809fb8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_DEVID_NumChan">
<name>NumChan</name>
<desc>Number of channels available</desc>
<sw_param offset="0xf8809fc8" start="19" end="16" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_DEVID_NumTrig">
<name>NumTrig</name>
<desc>Number of triggers available</desc>
<sw_param offset="0xf8809fc8" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_DEVID_res">
<name>res</name>
<desc>reserved</desc>
<sw_param offset="0xf8809fc8" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_DEVID_ExtMux">
<name>ExtMux</name>
<desc>no external muxing</desc>
<sw_param offset="0xf8809fc8" start="4" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_DTIR_a">
<name>a</name>
<desc>major type is a debug control logic component, sub-type is cross trigger</desc>
<sw_param offset="0xf8809fcc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_PERIPHID4_n4KB_count">
<name>n4KB_count</name>
<desc>4KB Count, set to 0</desc>
<sw_param offset="0xf8809fd0" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_PERIPHID4_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 continuation code</desc>
<sw_param offset="0xf8809fd0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_PERIPHID5_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf8809fd4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_PERIPHID6_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf8809fd8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_PERIPHID7_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf8809fdc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_PERIPHID0_a">
<name>a</name>
<desc>PartNumber0</desc>
<sw_param offset="0xf8809fe0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_PERIPHID1_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 Identity Code [3:0]</desc>
<sw_param offset="0xf8809fe4" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_PERIPHID1_PartNumber1">
<name>PartNumber1</name>
<desc>PartNumber1</desc>
<sw_param offset="0xf8809fe4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_PERIPHID2_RevNum">
<name>RevNum</name>
<desc>Revision number of Peripheral</desc>
<sw_param offset="0xf8809fe8" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_PERIPHID2_JEDEC">
<name>JEDEC</name>
<desc>Indicates that a JEDEC assigned value is used</desc>
<sw_param offset="0xf8809fe8" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_PERIPHID2_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 Identity Code [6:4]</desc>
<sw_param offset="0xf8809fe8" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_PERIPHID3_RevAnd">
<name>RevAnd</name>
<desc>RevAnd, at top level</desc>
<sw_param offset="0xf8809fec" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_PERIPHID3_CustMod">
<name>CustMod</name>
<desc>Customer Modified</desc>
<sw_param offset="0xf8809fec" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_COMPID0_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8809ff0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_COMPID1_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8809ff4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_COMPID2_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8809ff8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_ftm_COMPID3_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8809ffc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_CTICONTROL_GLBEN">
<name>GLBEN</name>
<desc>Enables or disables the ECT. When disabled, all cross triggering mapping logic functionality is disabled for this processor.</desc>
<sw_param offset="0xf8802000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_CTIINTACK_INTACK">
<name>INTACK</name>
<desc>Acknowledges the corresponding CTITRIGOUT output:
1 = CTITRIGOUT is acknowledged and is cleared when MAPTRIGOUT is LOW.
0 = no effect
There is one bit of the register for each CTITRIGOUT output.</desc>
<sw_param offset="0xf8802010" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_CTIAPPSET_APPSET">
<name>APPSET</name>
<desc>Setting a bit HIGH generates a channel event for the selected channel.
Read:
0 = application trigger inactive (reset)
1 = application trigger active.
Write:
0 = no effect
1 = generate channel event.
There is one bit of the register for each channel.</desc>
<sw_param offset="0xf8802014" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_CTIAPPCLEAR_APPCLEAR">
<name>APPCLEAR</name>
<desc>Clears corresponding bits in the CTIAPPSET register.
1 = application trigger disabled in the CTIAPPSET register
0 = no effect.
There is one bit of the register for each channel.</desc>
<sw_param offset="0xf8802018" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_CTIAPPPULSE_APPULSE">
<name>APPULSE</name>
<desc>Setting a bit HIGH generates a channel event pulse for the selected channel.
Write:
1 = channel event pulse generated for one CTICLK period
0 = no effect.
There is one bit of the register for each channel.</desc>
<sw_param offset="0xf880201c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_CTIINEN0_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf8802020" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_CTIINEN1_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf8802024" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_CTIINEN2_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf8802028" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_CTIINEN3_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf880202c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_CTIINEN4_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf8802030" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_CTIINEN5_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf8802034" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_CTIINEN6_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf8802038" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_CTIINEN7_TRIGINEN">
<name>TRIGINEN</name>
<desc>Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated.
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example in register CTIINEN0,
TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM.</desc>
<sw_param offset="0xf880203c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_CTIOUTEN0_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88020a0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_CTIOUTEN1_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88020a4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_CTIOUTEN2_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88020a8" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_CTIOUTEN3_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88020ac" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_CTIOUTEN4_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88020b0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_CTIOUTEN5_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88020b4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_CTIOUTEN6_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88020b8" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_CTIOUTEN7_TRIGOUTEN">
<name>TRIGOUTEN</name>
<desc>Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding
channel to generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output
1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output.
There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling
bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.</desc>
<sw_param offset="0xf88020bc" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_CTITRIGINSTATUS_TRIGINSTATUS">
<name>TRIGINSTATUS</name>
<desc>Shows the status of the CTITRIGIN inputs:
1 = CTITRIGIN is active
0 = CTITRIGIN is inactive.
Because the register provides a view of the raw CTITRIGIN inputs, the reset value is
unknown. There is one bit of the register for each trigger input.</desc>
<sw_param offset="0xf8802130" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_CTITRIGOUTSTATUS_TRIGOUTSTATUS">
<name>TRIGOUTSTATUS</name>
<desc>Shows the status of the CTITRIGOUT outputs.
1 = CTITRIGOUT is active
0 = CTITRIGOUT is inactive (reset).
There is one bit of the register for each trigger output.</desc>
<sw_param offset="0xf8802134" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_CTICHINSTATUS_CTCHINSTATUS">
<name>CTCHINSTATUS</name>
<desc>Shows the status of the CTICHIN inputs:
1 = CTICHIN is active
0 = CTICHIN is inactive.
Because the register provides a view of the raw CTICHIN inputs from the CTM, the reset
value is unknown. There is one bit of the register for each channel input.</desc>
<sw_param offset="0xf8802138" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_CTICHOUTSTATUS_CTCHOUTSTATUS">
<name>CTCHOUTSTATUS</name>
<desc>Shows the status of the CTICHOUT outputs.
1 = CTICHOUT is active
0 = CTICHOUT is inactive (reset).
There is one bit of the register for each channel output.</desc>
<sw_param offset="0xf880213c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_CTIGATE_CTIGATEEN3">
<name>CTIGATEEN3</name>
<desc>Enable CTICHOUT3.</desc>
<sw_param offset="0xf8802140" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_CTIGATE_CTIGATEEN2">
<name>CTIGATEEN2</name>
<desc>Enable CTICHOUT2.</desc>
<sw_param offset="0xf8802140" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_CTIGATE_CTIGATEEN1">
<name>CTIGATEEN1</name>
<desc>Enable CTICHOUT1.</desc>
<sw_param offset="0xf8802140" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_CTIGATE_CTIGATEEN0">
<name>CTIGATEEN0</name>
<desc>Enable CTICHOUT0.</desc>
<sw_param offset="0xf8802140" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_ASICCTL_ASICCTL">
<name>ASICCTL</name>
<desc>Implementation defined ASIC control, value written to the register is output on ASICCTL[7:0].</desc>
<sw_param offset="0xf8802144" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_ITCHINACK_CTCHINACK">
<name>CTCHINACK</name>
<desc>Set the value of the CTCHINACK outputs</desc>
<sw_param offset="0xf8802edc" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_ITTRIGINACK_CTTRIGINACK">
<name>CTTRIGINACK</name>
<desc>Set the value of the CTTRIGINACK outputs</desc>
<sw_param offset="0xf8802ee0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_ITCHOUT_CTCHOUT">
<name>CTCHOUT</name>
<desc>Set the value of the CTCHOUT outputs</desc>
<sw_param offset="0xf8802ee4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_ITTRIGOUT_CTTRIGOUT">
<name>CTTRIGOUT</name>
<desc>Set the value of the CTTRIGOUT outputs</desc>
<sw_param offset="0xf8802ee8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_ITCHOUTACK_CTCHOUTACK">
<name>CTCHOUTACK</name>
<desc>Read the values of the CTCHOUTACK inputs</desc>
<sw_param offset="0xf8802eec" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_ITTRIGOUTACK_CTTRIGOUTACK">
<name>CTTRIGOUTACK</name>
<desc>Read the values of the CTTRIGOUTACK inputs</desc>
<sw_param offset="0xf8802ef0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_ITCHIN_CTCHIN">
<name>CTCHIN</name>
<desc>Read the values of the CTCHIN inputs</desc>
<sw_param offset="0xf8802ef4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_ITTRIGIN_CTTRIGIN">
<name>CTTRIGIN</name>
<desc>Read the values of the CTTRIGIN inputs</desc>
<sw_param offset="0xf8802ef8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_ITCTRL_a">
<name>a</name>
<desc>Enable IT Registers</desc>
<sw_param offset="0xf8802f00" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_CTSR_SET">
<name>SET</name>
<desc>The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed.
Read:
1= Claim tag is implemented, 0 = Claim tag is not implemented
Write:
1= Set claim tag bit, 0= No effect</desc>
<sw_param offset="0xf8802fa0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_CTCR_CLEAR">
<name>CLEAR</name>
<desc>The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed.
Read: Current value of claim tag.
Write: 1= Clear claim tag bit, 0= No effect</desc>
<sw_param offset="0xf8802fa4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_LAR_KEY">
<name>KEY</name>
<desc>Write Access Code.
Write behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored.
To unlock, 0xC5ACCE55 must be written this register.
After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register.
- PADDRDBG31=1 (upper 2GB):
CTI is unlocked when upper 2GB addresses are used to write to all the registers.
However, write to this register is ignored using a upper 2GB address!
Note: read from this register always returns 0, regardless of PADDRDBG31.</desc>
<sw_param offset="0xf8802fb0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_LSR_n8BIT">
<name>n8BIT</name>
<desc>Set to 0 since CTI implements a 32-bit lock access register</desc>
<sw_param offset="0xf8802fb4" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_LSR_STATUS">
<name>STATUS</name>
<desc>Read behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
When a lower 2GB address is used to read this register, this bit indicates whether CTI is in locked state
(1= locked, 0= unlocked).
- PADDRDBG31=1 (upper 2GB):
always returns 0.</desc>
<sw_param offset="0xf8802fb4" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_LSR_IMP">
<name>IMP</name>
<desc>Read behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
always returns 1, meaning lock mechanism are implemented.
- PADDRDBG31=1 (upper 2GB):
always returns 0, meaning lock mechanism is NOT implemented.</desc>
<sw_param offset="0xf8802fb4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_ASR_NIDEN">
<name>NIDEN</name>
<desc>Current value of noninvasive debug enable signals</desc>
<sw_param offset="0xf8802fb8" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_ASR_NIDEN_CTL">
<name>NIDEN_CTL</name>
<desc>Non-invasive debug controlled</desc>
<sw_param offset="0xf8802fb8" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_ASR_IDEN">
<name>IDEN</name>
<desc>Current value of invasive debug enable signals</desc>
<sw_param offset="0xf8802fb8" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_ASR_IDEN_CTL">
<name>IDEN_CTL</name>
<desc>Invasive debug controlled</desc>
<sw_param offset="0xf8802fb8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_DEVID_NumChan">
<name>NumChan</name>
<desc>Number of channels available</desc>
<sw_param offset="0xf8802fc8" start="19" end="16" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_DEVID_NumTrig">
<name>NumTrig</name>
<desc>Number of triggers available</desc>
<sw_param offset="0xf8802fc8" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_DEVID_res">
<name>res</name>
<desc>reserved</desc>
<sw_param offset="0xf8802fc8" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_DEVID_ExtMux">
<name>ExtMux</name>
<desc>no external muxing</desc>
<sw_param offset="0xf8802fc8" start="4" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_DTIR_a">
<name>a</name>
<desc>major type is a debug control logic component, sub-type is cross trigger</desc>
<sw_param offset="0xf8802fcc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_PERIPHID4_n4KB_count">
<name>n4KB_count</name>
<desc>4KB Count, set to 0</desc>
<sw_param offset="0xf8802fd0" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_PERIPHID4_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 continuation code</desc>
<sw_param offset="0xf8802fd0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_PERIPHID5_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf8802fd4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_PERIPHID6_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf8802fd8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_PERIPHID7_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf8802fdc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_PERIPHID0_a">
<name>a</name>
<desc>PartNumber0</desc>
<sw_param offset="0xf8802fe0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_PERIPHID1_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 Identity Code [3:0]</desc>
<sw_param offset="0xf8802fe4" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_PERIPHID1_PartNumber1">
<name>PartNumber1</name>
<desc>PartNumber1</desc>
<sw_param offset="0xf8802fe4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_PERIPHID2_RevNum">
<name>RevNum</name>
<desc>Revision number of Peripheral</desc>
<sw_param offset="0xf8802fe8" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_PERIPHID2_JEDEC">
<name>JEDEC</name>
<desc>Indicates that a JEDEC assigned value is used</desc>
<sw_param offset="0xf8802fe8" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_PERIPHID2_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 Identity Code [6:4]</desc>
<sw_param offset="0xf8802fe8" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_PERIPHID3_RevAnd">
<name>RevAnd</name>
<desc>RevAnd, at top level</desc>
<sw_param offset="0xf8802fec" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_PERIPHID3_CustMod">
<name>CustMod</name>
<desc>Customer Modified</desc>
<sw_param offset="0xf8802fec" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_COMPID0_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8802ff0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_COMPID1_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8802ff4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_COMPID2_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8802ff8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cti_etb_tpiu_COMPID3_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8802ffc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_uart1_Control_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0001000" start="31" end="9" />
</parameter>
<parameter uniqueid="ps7_uart1_Control_reg0_STPBRK">
<name>STPBRK</name>
<desc>Stop transmitter break.
1 = stop transmission of the break.</desc>
<sw_param offset="0xe0001000" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_uart1_Control_reg0_STTBRK">
<name>STTBRK</name>
<desc>Start transmitter break
1 = start to transmit a break. Can only be set if
STPBRK (Stop transmitter break) is not high.</desc>
<sw_param offset="0xe0001000" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_uart1_Control_reg0_RSTTO">
<name>RSTTO</name>
<desc>Restart receiver timeout counter
1 = receiver timeout counter is restarted</desc>
<sw_param offset="0xe0001000" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_uart1_Control_reg0_TXDIS">
<name>TXDIS</name>
<desc>Transmit disable.
1, the transmitter is disabled</desc>
<sw_param offset="0xe0001000" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_uart1_Control_reg0_TXEN">
<name>TXEN</name>
<desc>Transmit enable.
1, the transmitter is enabled, provided the TXDIS field is set to 0.</desc>
<sw_param offset="0xe0001000" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_uart1_Control_reg0_RXDIS">
<name>RXDIS</name>
<desc>Receive disable.
1= receiver is enabled</desc>
<sw_param offset="0xe0001000" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_uart1_Control_reg0_RXEN">
<name>RXEN</name>
<desc>Receive enable.
1=the receiver logic is enabled, provided RXDIS field is set to 0</desc>
<sw_param offset="0xe0001000" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_uart1_Control_reg0_TXRES">
<name>TXRES</name>
<desc>Software reset for TX data path.
1=the transmitter logic is reset and all pending transmitter data is discarded
self clear</desc>
<sw_param offset="0xe0001000" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_uart1_Control_reg0_RXRES">
<name>RXRES</name>
<desc>Software reset for RX data path
1=receiver logic is reset and all pending receiver data is discarded
self clear</desc>
<sw_param offset="0xe0001000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_uart1_mode_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0001004" start="31" end="12" />
</parameter>
<parameter uniqueid="ps7_uart1_mode_reg0_IRMODE">
<name>IRMODE</name>
<desc>Enable IrDA mode
0 : Default UART mode
1 : Enable IrDA mode</desc>
<sw_param offset="0xe0001004" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_uart1_mode_reg0_UCLKEN">
<name>UCLKEN</name>
<desc>External uart_clk source select
0 : APB clock, pclk
1 : a user-defined clock</desc>
<sw_param offset="0xe0001004" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_uart1_mode_reg0_CHMODE">
<name>CHMODE</name>
<desc>Channel mode
00 = normal
01 = automatic cho
10 = local loopback
11 = remote loopback</desc>
<sw_param offset="0xe0001004" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_uart1_mode_reg0_NBSTOP">
<name>NBSTOP</name>
<desc>Number of stop bits
00 = 1 stop bit
01 = 1.5 stop bits
10 = 2 stop bits
11 = reserved</desc>
<sw_param offset="0xe0001004" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_uart1_mode_reg0_PAR">
<name>PAR</name>
<desc>Parity type select.
000 = even parity
001 = odd parity
010 = forced to 0 parity (space)
011 = forced to 1 parity (mark)
1xx = no parity</desc>
<sw_param offset="0xe0001004" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_uart1_mode_reg0_CHRL">
<name>CHRL</name>
<desc>Character length select
11 = 6 bits
10 = 7 bits
01 / 00 = 8 bits</desc>
<sw_param offset="0xe0001004" start="2" end="1" />
</parameter>
<parameter uniqueid="ps7_uart1_mode_reg0_CLKS">
<name>CLKS</name>
<desc>clock source select
1 = clock source is uart_clk/8
0 = clock source is uart_clk</desc>
<sw_param offset="0xe0001004" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_en_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0001008" start="31" end="13" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_en_reg0_TOVR">
<name>TOVR</name>
<desc>Transmitter FIFO Overflow interrupt
1 = enable</desc>
<sw_param offset="0xe0001008" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_en_reg0_TNFUL">
<name>TNFUL</name>
<desc>Transmitter FIFO Nearly Full interrupt
1 = enable</desc>
<sw_param offset="0xe0001008" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_en_reg0_TTRIG">
<name>TTRIG</name>
<desc>Transmitter FIFO Trigger interrupt
1 = enable</desc>
<sw_param offset="0xe0001008" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_en_reg0_DMSI">
<name>DMSI</name>
<desc>Delta Modem Status Indicator interrupt
1 = enable</desc>
<sw_param offset="0xe0001008" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_en_reg0_TIMEOUT">
<name>TIMEOUT</name>
<desc>Receiver Timeout Error interrupt
1 = enable</desc>
<sw_param offset="0xe0001008" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_en_reg0_PARE">
<name>PARE</name>
<desc>Receiver Parity Error interrupt
1 = enable</desc>
<sw_param offset="0xe0001008" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_en_reg0_FRAME">
<name>FRAME</name>
<desc>Receiver Framing Error interrupt
1 = enable</desc>
<sw_param offset="0xe0001008" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_en_reg0_ROVR">
<name>ROVR</name>
<desc>Receiver Overflow Error interrupt
1 = enable</desc>
<sw_param offset="0xe0001008" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_en_reg0_TFUL">
<name>TFUL</name>
<desc>Transmitter FIFO Full interrupt
1 = enable</desc>
<sw_param offset="0xe0001008" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_en_reg0_TEMPTY">
<name>TEMPTY</name>
<desc>Transmitter FIFO Empty interrupt
1 = enable</desc>
<sw_param offset="0xe0001008" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_en_reg0_RFUL">
<name>RFUL</name>
<desc>Receiver FIFO Full interrupt
1 = enable</desc>
<sw_param offset="0xe0001008" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_en_reg0_REMPTY">
<name>REMPTY</name>
<desc>Receiver FIFO Empty interrupt
1 = enable</desc>
<sw_param offset="0xe0001008" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_en_reg0_RTRIG">
<name>RTRIG</name>
<desc>Receiver FIFO Trigger interrupt
1 = enable</desc>
<sw_param offset="0xe0001008" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_dis_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe000100c" start="31" end="13" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_dis_reg0_TOVR">
<name>TOVR</name>
<desc>Transmitter FIFO Overflow interrupt
1 = disable</desc>
<sw_param offset="0xe000100c" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_dis_reg0_TNFUL">
<name>TNFUL</name>
<desc>Transmitter FIFO Nearly Full interrupt
1 = disable</desc>
<sw_param offset="0xe000100c" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_dis_reg0_TTRIG">
<name>TTRIG</name>
<desc>Transmitter FIFO Trigger interrupt
1 = disable</desc>
<sw_param offset="0xe000100c" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_dis_reg0_DMSI">
<name>DMSI</name>
<desc>Delta Modem Status Indicator interrupt
1 = disable</desc>
<sw_param offset="0xe000100c" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_dis_reg0_TIMEOUT">
<name>TIMEOUT</name>
<desc>Receiver Timeout Error interrupt
1 = disable</desc>
<sw_param offset="0xe000100c" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_dis_reg0_PARE">
<name>PARE</name>
<desc>Receiver Parity Error interrupt
1 = disable</desc>
<sw_param offset="0xe000100c" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_dis_reg0_FRAME">
<name>FRAME</name>
<desc>Receiver Framing Error interrupt
1 = disable</desc>
<sw_param offset="0xe000100c" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_dis_reg0_ROVR">
<name>ROVR</name>
<desc>Receiver Overflow Error interrupt
1 = disable</desc>
<sw_param offset="0xe000100c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_dis_reg0_TFUL">
<name>TFUL</name>
<desc>Transmitter FIFO Full interrupt
1 = disable</desc>
<sw_param offset="0xe000100c" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_dis_reg0_TEMPTY">
<name>TEMPTY</name>
<desc>Transmitter FIFO Empty interrupt
1 = disable</desc>
<sw_param offset="0xe000100c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_dis_reg0_RFUL">
<name>RFUL</name>
<desc>Receiver FIFO Full interrupt
1 = disable</desc>
<sw_param offset="0xe000100c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_dis_reg0_REMPTY">
<name>REMPTY</name>
<desc>Receiver FIFO Empty interrupt
1 = disable</desc>
<sw_param offset="0xe000100c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_dis_reg0_RTRIG">
<name>RTRIG</name>
<desc>Receiver FIFO Trigger interrupt
1 = disable</desc>
<sw_param offset="0xe000100c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_mask_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0001010" start="31" end="13" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_mask_reg0_TOVR">
<name>TOVR</name>
<desc>Transmitter FIFO Overflow interrupt status
1 = interrupt is enabled
0 = interrupt is disabled</desc>
<sw_param offset="0xe0001010" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_mask_reg0_TNFUL">
<name>TNFUL</name>
<desc>Transmitter FIFO Nearly Full interrupt mask status
1 = interrupt is enabled
0 = interrupt is disabled</desc>
<sw_param offset="0xe0001010" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_mask_reg0_TTRIG">
<name>TTRIG</name>
<desc>Transmitter FIFO Trigger interrupt mask status
1 = interrupt is enabled
0 = interrupt is disabled</desc>
<sw_param offset="0xe0001010" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_mask_reg0_DMSI">
<name>DMSI</name>
<desc>Delta Modem Status Indicator interrupt mask status
1 = interrupt is enabled
0 = interrupt is disabled</desc>
<sw_param offset="0xe0001010" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_mask_reg0_TIMEOUT">
<name>TIMEOUT</name>
<desc>Receiver Timeout Error interrupt mask status
1 = interrupt is enabled
0 = interrupt is disabled</desc>
<sw_param offset="0xe0001010" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_mask_reg0_PARE">
<name>PARE</name>
<desc>Receiver Parity Error interrupt mask status
1 = interrupt is enabled
0 = interrupt is disabled</desc>
<sw_param offset="0xe0001010" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_mask_reg0_FRAME">
<name>FRAME</name>
<desc>Receiver Framing Error interrupt mask status
1 = interrupt is enabled
0 = interrupt is disabled</desc>
<sw_param offset="0xe0001010" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_mask_reg0_ROVR">
<name>ROVR</name>
<desc>Receiver Overflow Error interrupt mask status
1 = interrupt is enabled
0 = interrupt is disabled</desc>
<sw_param offset="0xe0001010" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_mask_reg0_TFUL">
<name>TFUL</name>
<desc>Transmitter FIFO Full interrupt mask status
1 = interrupt is enabled
0 = interrupt is disabled</desc>
<sw_param offset="0xe0001010" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_mask_reg0_TEMPTY">
<name>TEMPTY</name>
<desc>Transmitter FIFO Empty interrupt mask status
1 = interrupt is enabled
0 = interrupt is disabled</desc>
<sw_param offset="0xe0001010" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_mask_reg0_RFUL">
<name>RFUL</name>
<desc>Receiver FIFO Full interrupt mask status
1 = interrupt is enabled
0 = interrupt is disabled</desc>
<sw_param offset="0xe0001010" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_mask_reg0_REMPTY">
<name>REMPTY</name>
<desc>Receiver FIFO Empty interrupt
mask status
1 = interrupt is enabled
0 = interrupt is disabled</desc>
<sw_param offset="0xe0001010" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_uart1_Intrpt_mask_reg0_RTRIG">
<name>RTRIG</name>
<desc>Receiver FIFO Trigger interrupt mask status
1 = interrupt is enabled
0 = interrupt is disabled</desc>
<sw_param offset="0xe0001010" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_uart1_Chnl_int_sts_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0001014" start="31" end="13" />
</parameter>
<parameter uniqueid="ps7_uart1_Chnl_int_sts_reg0_TOVR">
<name>TOVR</name>
<desc>Transmitter FIFO Overflow interrupt mask status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe0001014" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_uart1_Chnl_int_sts_reg0_TNFUL">
<name>TNFUL</name>
<desc>Transmitter FIFO Nearly Full interrupt mask status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe0001014" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_uart1_Chnl_int_sts_reg0_TTRIG">
<name>TTRIG</name>
<desc>Transmitter FIFO Trigger interrupt mask status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe0001014" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_uart1_Chnl_int_sts_reg0_DMSI">
<name>DMSI</name>
<desc>Delta Modem Status Indicator interrupt mask status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe0001014" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_uart1_Chnl_int_sts_reg0_TIMEOUT">
<name>TIMEOUT</name>
<desc>Receiver Timeout Error interrupt mask status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe0001014" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_uart1_Chnl_int_sts_reg0_PARE">
<name>PARE</name>
<desc>Receiver Parity Error interrupt mask status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe0001014" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_uart1_Chnl_int_sts_reg0_FRAME">
<name>FRAME</name>
<desc>Receiver Framing Error interrupt mask status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe0001014" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_uart1_Chnl_int_sts_reg0_ROVR">
<name>ROVR</name>
<desc>Receiver Overflow Error interrupt mask status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe0001014" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_uart1_Chnl_int_sts_reg0_TFUL">
<name>TFUL</name>
<desc>Transmitter FIFO Full interrupt mask status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe0001014" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_uart1_Chnl_int_sts_reg0_TEMPTY">
<name>TEMPTY</name>
<desc>Transmitter FIFO Empty interrupt mask status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe0001014" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_uart1_Chnl_int_sts_reg0_RFUL">
<name>RFUL</name>
<desc>Receiver FIFO Full interrupt mask status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe0001014" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_uart1_Chnl_int_sts_reg0_REMPTY">
<name>REMPTY</name>
<desc>Receiver FIFO Empty interrupt
mask status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe0001014" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_uart1_Chnl_int_sts_reg0_RTRIG">
<name>RTRIG</name>
<desc>Receiver FIFO Trigger interrupt mask status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe0001014" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_uart1_Baud_rate_gen_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0001018" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_uart1_Baud_rate_gen_reg0_CD">
<name>CD</name>
<desc>Baud Rate Clock Divisor Value
0 = Disables baud_sample
1 = Clock divisor bypass
2 - 65535 = baud_sample value</desc>
<sw_param offset="0xe0001018" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_uart1_Rcvr_timeout_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe000101c" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_uart1_Rcvr_timeout_reg0_RTO">
<name>RTO</name>
<desc>Receiver timeout value
0 = Disables receiver timeout counter
1 - 255 = Receiver timeout</desc>
<sw_param offset="0xe000101c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_uart1_Rcvr_FIFO_trigger_level0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0001020" start="31" end="6" />
</parameter>
<parameter uniqueid="ps7_uart1_Rcvr_FIFO_trigger_level0_RTRIG">
<name>RTRIG</name>
<desc>Receiver FIFO trigger level value
0 = Disables receiver timeout counter
1 - 63 = Receiver timeout</desc>
<sw_param offset="0xe0001020" start="5" end="0" />
</parameter>
<parameter uniqueid="ps7_uart1_Modem_ctrl_reg0_reserved_1">
<name>reserved_1</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0001024" start="31" end="6" />
</parameter>
<parameter uniqueid="ps7_uart1_Modem_ctrl_reg0_FCM">
<name>FCM</name>
<desc>Automatic flow control mode
1 = enable
0 = disable</desc>
<sw_param offset="0xe0001024" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_uart1_Modem_ctrl_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0001024" start="4" end="2" />
</parameter>
<parameter uniqueid="ps7_uart1_Modem_ctrl_reg0_RTS">
<name>RTS</name>
<desc>Request to send output control
1 = forced to logic 0
0 = forced to logic 1</desc>
<sw_param offset="0xe0001024" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_uart1_Modem_ctrl_reg0_DTR">
<name>DTR</name>
<desc>Data Terminal Ready
1 = forced to logic 0
0 = forced to logic 1</desc>
<sw_param offset="0xe0001024" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_uart1_Modem_sts_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0001028" start="31" end="9" />
</parameter>
<parameter uniqueid="ps7_uart1_Modem_sts_reg0_FCMS">
<name>FCMS</name>
<desc>Flow Control Mode
1 = enabled
0 = disabled</desc>
<sw_param offset="0xe0001028" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_uart1_Modem_sts_reg0_DCD">
<name>DCD</name>
<desc>Data Carrier Detect Input Status
1 = ua_ndcd input is low
0 = ua_ndcd input is high</desc>
<sw_param offset="0xe0001028" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_uart1_Modem_sts_reg0_RI">
<name>RI</name>
<desc>Ring Indicator input status
1 = ua_nri input is low
0 = ua_nri input is high</desc>
<sw_param offset="0xe0001028" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_uart1_Modem_sts_reg0_DSR">
<name>DSR</name>
<desc>Data Set Ready input status
1 = ua_ndsr input is low
0 = ua_ndsr input is high</desc>
<sw_param offset="0xe0001028" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_uart1_Modem_sts_reg0_CTS">
<name>CTS</name>
<desc>Clear to Send input status
1 = ua_ncts input is low
0 = ua_ncts input is high</desc>
<sw_param offset="0xe0001028" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_uart1_Modem_sts_reg0_DDCD">
<name>DDCD</name>
<desc>Delta Data Carrier Detect Status
1 = Change has occurred
0 = No change has occurred</desc>
<sw_param offset="0xe0001028" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_uart1_Modem_sts_reg0_TERI">
<name>TERI</name>
<desc>Trailing Edge Ring Indicator Status
1 = Trailing edge has occurred
0 = No trailing edge has occurred</desc>
<sw_param offset="0xe0001028" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_uart1_Modem_sts_reg0_DDSR">
<name>DDSR</name>
<desc>Delta Data Set Ready status
1 = Change has occurred
0 = No change has occurred</desc>
<sw_param offset="0xe0001028" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_uart1_Modem_sts_reg0_DCTS">
<name>DCTS</name>
<desc>Delta Clear To Send Status
1 = Change has occurred
0 = No change has occurred</desc>
<sw_param offset="0xe0001028" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_uart1_Channel_sts_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe000102c" start="31" end="15" />
</parameter>
<parameter uniqueid="ps7_uart1_Channel_sts_reg0_TNFUL">
<name>TNFUL</name>
<desc>Transmitter FIFO Nearly Full continuous status
1 = Only one byte is free in the TX FIFO
0 = More than one byte is unused in the TX FIFO</desc>
<sw_param offset="0xe000102c" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_uart1_Channel_sts_reg0_TTRIG">
<name>TTRIG</name>
<desc>Transmitter FIFO Trigger continuous status
1 = TX FIFO fill level is greater than or equal to TTRIG
0 = TX FIFO fill level is less than TTRIG</desc>
<sw_param offset="0xe000102c" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_uart1_Channel_sts_reg0_FDELT">
<name>FDELT</name>
<desc>Receiver flow delay trigger continuous status.
1 = RX FIFO fill level is greater than or equal to FDEL
0 = RX FIFO fill level is less than FDEL</desc>
<sw_param offset="0xe000102c" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_uart1_Channel_sts_reg0_TACTIVE">
<name>TACTIVE</name>
<desc>Transmitter state machine active status.
1 = active state
0 = inactive state</desc>
<sw_param offset="0xe000102c" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_uart1_Channel_sts_reg0_RACTIVE">
<name>RACTIVE</name>
<desc>Receiver state machine active status.
1 = active state
0 = inactive state</desc>
<sw_param offset="0xe000102c" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_uart1_Channel_sts_reg0_DMSI">
<name>DMSI</name>
<desc>Delta Modem Status Indicator status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe000102c" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_uart1_Channel_sts_reg0_TIMEOUT">
<name>TIMEOUT</name>
<desc>Receiver Timeout status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe000102c" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_uart1_Channel_sts_reg0_PARE">
<name>PARE</name>
<desc>Receiver Parity Error status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe000102c" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_uart1_Channel_sts_reg0_FRAME">
<name>FRAME</name>
<desc>Receiver Frame Error status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe000102c" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_uart1_Channel_sts_reg0_ROVR">
<name>ROVR</name>
<desc>Receiver Overflow Error status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe000102c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_uart1_Channel_sts_reg0_TFUL">
<name>TFUL</name>
<desc>Transmitter FIFO Full continuous status
1= TX FIFO is full
0 = TX FIFO is not full</desc>
<sw_param offset="0xe000102c" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_uart1_Channel_sts_reg0_TEMPTY">
<name>TEMPTY</name>
<desc>Transmitter FIFO Empty continuous status
1 = TX FIFO is empty
0 = TX FIFO is not empty</desc>
<sw_param offset="0xe000102c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_uart1_Channel_sts_reg0_RFUL">
<name>RFUL</name>
<desc>Receiver FIFO Full continuous status
1 = RX FIFO is full
0 = RX FIFO is not full</desc>
<sw_param offset="0xe000102c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_uart1_Channel_sts_reg0_REMPTY">
<name>REMPTY</name>
<desc>Receiver FIFO Full continuous status.
1 : RX FIFO is empty
0 : RX FIFO is not empty</desc>
<sw_param offset="0xe000102c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_uart1_Channel_sts_reg0_RTRIG">
<name>RTRIG</name>
<desc>Receiver FIFO Trigger continuous status
1 : RX FIFO fill level is greater than or equal to RTRIG
0 : RX FIFO fill level is less than RTRIG</desc>
<sw_param offset="0xe000102c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_uart1_TX_RX_FIFO0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0001030" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_uart1_TX_RX_FIFO0_FIFO">
<name>FIFO</name>
<desc>operates as TX FIFO and RX FIFO</desc>
<sw_param offset="0xe0001030" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_uart1_Baud_rate_divider_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0001034" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_uart1_Baud_rate_divider_reg0_BDIV">
<name>BDIV</name>
<desc>Baud rate divider value
0 - 3: ignored
4 - 255: Baud rate</desc>
<sw_param offset="0xe0001034" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_uart1_Flow_delay_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0001038" start="31" end="6" />
</parameter>
<parameter uniqueid="ps7_uart1_Flow_delay_reg0_FDEL">
<name>FDEL</name>
<desc>RX FIFO trigger level for ua_nrts de-assertion
0 - 3 = disabled
4 to 65535 = ua_nrts is driven high when RX FIFO fill level equals FDEL</desc>
<sw_param offset="0xe0001038" start="5" end="0" />
</parameter>
<parameter uniqueid="ps7_uart1_IR_min_rcv_pulse_wdth0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe000103c" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_uart1_IR_min_rcv_pulse_wdth0_PMN">
<name>PMN</name>
<desc>Number of uart_clk periods
0 to 65535 : minimum width</desc>
<sw_param offset="0xe000103c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_uart1_IR_transmitted_pulse_wdth0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0001040" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_uart1_IR_transmitted_pulse_wdth0_PWID">
<name>PWID</name>
<desc>Pulse width
0 - 255 : width</desc>
<sw_param offset="0xe0001040" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_uart1_Tx_FIFO_trigger_level0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0001044" start="31" end="6" />
</parameter>
<parameter uniqueid="ps7_uart1_Tx_FIFO_trigger_level0_TTRIG">
<name>TTRIG</name>
<desc>Transmitter FIFO trigger level
0 = Disables transmitter FIFO trigger level function
1 - 63 = Trigger set when transmitter FIFO fills to TTRIG bytes</desc>
<sw_param offset="0xe0001044" start="5" end="0" />
</parameter>
<parameter uniqueid="ps7_uart0_Control_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0000000" start="31" end="9" />
</parameter>
<parameter uniqueid="ps7_uart0_Control_reg0_STPBRK">
<name>STPBRK</name>
<desc>Stop transmitter break.
1 = stop transmission of the break.</desc>
<sw_param offset="0xe0000000" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_uart0_Control_reg0_STTBRK">
<name>STTBRK</name>
<desc>Start transmitter break
1 = start to transmit a break. Can only be set if
STPBRK (Stop transmitter break) is not high.</desc>
<sw_param offset="0xe0000000" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_uart0_Control_reg0_RSTTO">
<name>RSTTO</name>
<desc>Restart receiver timeout counter
1 = receiver timeout counter is restarted</desc>
<sw_param offset="0xe0000000" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_uart0_Control_reg0_TXDIS">
<name>TXDIS</name>
<desc>Transmit disable.
1, the transmitter is disabled</desc>
<sw_param offset="0xe0000000" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_uart0_Control_reg0_TXEN">
<name>TXEN</name>
<desc>Transmit enable.
1, the transmitter is enabled, provided the TXDIS field is set to 0.</desc>
<sw_param offset="0xe0000000" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_uart0_Control_reg0_RXDIS">
<name>RXDIS</name>
<desc>Receive disable.
1= receiver is enabled</desc>
<sw_param offset="0xe0000000" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_uart0_Control_reg0_RXEN">
<name>RXEN</name>
<desc>Receive enable.
1=the receiver logic is enabled, provided RXDIS field is set to 0</desc>
<sw_param offset="0xe0000000" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_uart0_Control_reg0_TXRES">
<name>TXRES</name>
<desc>Software reset for TX data path.
1=the transmitter logic is reset and all pending transmitter data is discarded
self clear</desc>
<sw_param offset="0xe0000000" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_uart0_Control_reg0_RXRES">
<name>RXRES</name>
<desc>Software reset for RX data path
1=receiver logic is reset and all pending receiver data is discarded
self clear</desc>
<sw_param offset="0xe0000000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_uart0_mode_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0000004" start="31" end="12" />
</parameter>
<parameter uniqueid="ps7_uart0_mode_reg0_IRMODE">
<name>IRMODE</name>
<desc>Enable IrDA mode
0 : Default UART mode
1 : Enable IrDA mode</desc>
<sw_param offset="0xe0000004" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_uart0_mode_reg0_UCLKEN">
<name>UCLKEN</name>
<desc>External uart_clk source select
0 : APB clock, pclk
1 : a user-defined clock</desc>
<sw_param offset="0xe0000004" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_uart0_mode_reg0_CHMODE">
<name>CHMODE</name>
<desc>Channel mode
00 = normal
01 = automatic cho
10 = local loopback
11 = remote loopback</desc>
<sw_param offset="0xe0000004" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_uart0_mode_reg0_NBSTOP">
<name>NBSTOP</name>
<desc>Number of stop bits
00 = 1 stop bit
01 = 1.5 stop bits
10 = 2 stop bits
11 = reserved</desc>
<sw_param offset="0xe0000004" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_uart0_mode_reg0_PAR">
<name>PAR</name>
<desc>Parity type select.
000 = even parity
001 = odd parity
010 = forced to 0 parity (space)
011 = forced to 1 parity (mark)
1xx = no parity</desc>
<sw_param offset="0xe0000004" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_uart0_mode_reg0_CHRL">
<name>CHRL</name>
<desc>Character length select
11 = 6 bits
10 = 7 bits
01 / 00 = 8 bits</desc>
<sw_param offset="0xe0000004" start="2" end="1" />
</parameter>
<parameter uniqueid="ps7_uart0_mode_reg0_CLKS">
<name>CLKS</name>
<desc>clock source select
1 = clock source is uart_clk/8
0 = clock source is uart_clk</desc>
<sw_param offset="0xe0000004" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_en_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0000008" start="31" end="13" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_en_reg0_TOVR">
<name>TOVR</name>
<desc>Transmitter FIFO Overflow interrupt
1 = enable</desc>
<sw_param offset="0xe0000008" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_en_reg0_TNFUL">
<name>TNFUL</name>
<desc>Transmitter FIFO Nearly Full interrupt
1 = enable</desc>
<sw_param offset="0xe0000008" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_en_reg0_TTRIG">
<name>TTRIG</name>
<desc>Transmitter FIFO Trigger interrupt
1 = enable</desc>
<sw_param offset="0xe0000008" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_en_reg0_DMSI">
<name>DMSI</name>
<desc>Delta Modem Status Indicator interrupt
1 = enable</desc>
<sw_param offset="0xe0000008" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_en_reg0_TIMEOUT">
<name>TIMEOUT</name>
<desc>Receiver Timeout Error interrupt
1 = enable</desc>
<sw_param offset="0xe0000008" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_en_reg0_PARE">
<name>PARE</name>
<desc>Receiver Parity Error interrupt
1 = enable</desc>
<sw_param offset="0xe0000008" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_en_reg0_FRAME">
<name>FRAME</name>
<desc>Receiver Framing Error interrupt
1 = enable</desc>
<sw_param offset="0xe0000008" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_en_reg0_ROVR">
<name>ROVR</name>
<desc>Receiver Overflow Error interrupt
1 = enable</desc>
<sw_param offset="0xe0000008" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_en_reg0_TFUL">
<name>TFUL</name>
<desc>Transmitter FIFO Full interrupt
1 = enable</desc>
<sw_param offset="0xe0000008" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_en_reg0_TEMPTY">
<name>TEMPTY</name>
<desc>Transmitter FIFO Empty interrupt
1 = enable</desc>
<sw_param offset="0xe0000008" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_en_reg0_RFUL">
<name>RFUL</name>
<desc>Receiver FIFO Full interrupt
1 = enable</desc>
<sw_param offset="0xe0000008" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_en_reg0_REMPTY">
<name>REMPTY</name>
<desc>Receiver FIFO Empty interrupt
1 = enable</desc>
<sw_param offset="0xe0000008" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_en_reg0_RTRIG">
<name>RTRIG</name>
<desc>Receiver FIFO Trigger interrupt
1 = enable</desc>
<sw_param offset="0xe0000008" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_dis_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe000000c" start="31" end="13" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_dis_reg0_TOVR">
<name>TOVR</name>
<desc>Transmitter FIFO Overflow interrupt
1 = disable</desc>
<sw_param offset="0xe000000c" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_dis_reg0_TNFUL">
<name>TNFUL</name>
<desc>Transmitter FIFO Nearly Full interrupt
1 = disable</desc>
<sw_param offset="0xe000000c" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_dis_reg0_TTRIG">
<name>TTRIG</name>
<desc>Transmitter FIFO Trigger interrupt
1 = disable</desc>
<sw_param offset="0xe000000c" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_dis_reg0_DMSI">
<name>DMSI</name>
<desc>Delta Modem Status Indicator interrupt
1 = disable</desc>
<sw_param offset="0xe000000c" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_dis_reg0_TIMEOUT">
<name>TIMEOUT</name>
<desc>Receiver Timeout Error interrupt
1 = disable</desc>
<sw_param offset="0xe000000c" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_dis_reg0_PARE">
<name>PARE</name>
<desc>Receiver Parity Error interrupt
1 = disable</desc>
<sw_param offset="0xe000000c" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_dis_reg0_FRAME">
<name>FRAME</name>
<desc>Receiver Framing Error interrupt
1 = disable</desc>
<sw_param offset="0xe000000c" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_dis_reg0_ROVR">
<name>ROVR</name>
<desc>Receiver Overflow Error interrupt
1 = disable</desc>
<sw_param offset="0xe000000c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_dis_reg0_TFUL">
<name>TFUL</name>
<desc>Transmitter FIFO Full interrupt
1 = disable</desc>
<sw_param offset="0xe000000c" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_dis_reg0_TEMPTY">
<name>TEMPTY</name>
<desc>Transmitter FIFO Empty interrupt
1 = disable</desc>
<sw_param offset="0xe000000c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_dis_reg0_RFUL">
<name>RFUL</name>
<desc>Receiver FIFO Full interrupt
1 = disable</desc>
<sw_param offset="0xe000000c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_dis_reg0_REMPTY">
<name>REMPTY</name>
<desc>Receiver FIFO Empty interrupt
1 = disable</desc>
<sw_param offset="0xe000000c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_dis_reg0_RTRIG">
<name>RTRIG</name>
<desc>Receiver FIFO Trigger interrupt
1 = disable</desc>
<sw_param offset="0xe000000c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_mask_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0000010" start="31" end="13" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_mask_reg0_TOVR">
<name>TOVR</name>
<desc>Transmitter FIFO Overflow interrupt status
1 = interrupt is enabled
0 = interrupt is disabled</desc>
<sw_param offset="0xe0000010" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_mask_reg0_TNFUL">
<name>TNFUL</name>
<desc>Transmitter FIFO Nearly Full interrupt mask status
1 = interrupt is enabled
0 = interrupt is disabled</desc>
<sw_param offset="0xe0000010" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_mask_reg0_TTRIG">
<name>TTRIG</name>
<desc>Transmitter FIFO Trigger interrupt mask status
1 = interrupt is enabled
0 = interrupt is disabled</desc>
<sw_param offset="0xe0000010" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_mask_reg0_DMSI">
<name>DMSI</name>
<desc>Delta Modem Status Indicator interrupt mask status
1 = interrupt is enabled
0 = interrupt is disabled</desc>
<sw_param offset="0xe0000010" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_mask_reg0_TIMEOUT">
<name>TIMEOUT</name>
<desc>Receiver Timeout Error interrupt mask status
1 = interrupt is enabled
0 = interrupt is disabled</desc>
<sw_param offset="0xe0000010" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_mask_reg0_PARE">
<name>PARE</name>
<desc>Receiver Parity Error interrupt mask status
1 = interrupt is enabled
0 = interrupt is disabled</desc>
<sw_param offset="0xe0000010" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_mask_reg0_FRAME">
<name>FRAME</name>
<desc>Receiver Framing Error interrupt mask status
1 = interrupt is enabled
0 = interrupt is disabled</desc>
<sw_param offset="0xe0000010" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_mask_reg0_ROVR">
<name>ROVR</name>
<desc>Receiver Overflow Error interrupt mask status
1 = interrupt is enabled
0 = interrupt is disabled</desc>
<sw_param offset="0xe0000010" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_mask_reg0_TFUL">
<name>TFUL</name>
<desc>Transmitter FIFO Full interrupt mask status
1 = interrupt is enabled
0 = interrupt is disabled</desc>
<sw_param offset="0xe0000010" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_mask_reg0_TEMPTY">
<name>TEMPTY</name>
<desc>Transmitter FIFO Empty interrupt mask status
1 = interrupt is enabled
0 = interrupt is disabled</desc>
<sw_param offset="0xe0000010" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_mask_reg0_RFUL">
<name>RFUL</name>
<desc>Receiver FIFO Full interrupt mask status
1 = interrupt is enabled
0 = interrupt is disabled</desc>
<sw_param offset="0xe0000010" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_mask_reg0_REMPTY">
<name>REMPTY</name>
<desc>Receiver FIFO Empty interrupt
mask status
1 = interrupt is enabled
0 = interrupt is disabled</desc>
<sw_param offset="0xe0000010" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_uart0_Intrpt_mask_reg0_RTRIG">
<name>RTRIG</name>
<desc>Receiver FIFO Trigger interrupt mask status
1 = interrupt is enabled
0 = interrupt is disabled</desc>
<sw_param offset="0xe0000010" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_uart0_Chnl_int_sts_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0000014" start="31" end="13" />
</parameter>
<parameter uniqueid="ps7_uart0_Chnl_int_sts_reg0_TOVR">
<name>TOVR</name>
<desc>Transmitter FIFO Overflow interrupt mask status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe0000014" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_uart0_Chnl_int_sts_reg0_TNFUL">
<name>TNFUL</name>
<desc>Transmitter FIFO Nearly Full interrupt mask status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe0000014" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_uart0_Chnl_int_sts_reg0_TTRIG">
<name>TTRIG</name>
<desc>Transmitter FIFO Trigger interrupt mask status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe0000014" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_uart0_Chnl_int_sts_reg0_DMSI">
<name>DMSI</name>
<desc>Delta Modem Status Indicator interrupt mask status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe0000014" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_uart0_Chnl_int_sts_reg0_TIMEOUT">
<name>TIMEOUT</name>
<desc>Receiver Timeout Error interrupt mask status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe0000014" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_uart0_Chnl_int_sts_reg0_PARE">
<name>PARE</name>
<desc>Receiver Parity Error interrupt mask status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe0000014" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_uart0_Chnl_int_sts_reg0_FRAME">
<name>FRAME</name>
<desc>Receiver Framing Error interrupt mask status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe0000014" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_uart0_Chnl_int_sts_reg0_ROVR">
<name>ROVR</name>
<desc>Receiver Overflow Error interrupt mask status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe0000014" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_uart0_Chnl_int_sts_reg0_TFUL">
<name>TFUL</name>
<desc>Transmitter FIFO Full interrupt mask status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe0000014" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_uart0_Chnl_int_sts_reg0_TEMPTY">
<name>TEMPTY</name>
<desc>Transmitter FIFO Empty interrupt mask status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe0000014" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_uart0_Chnl_int_sts_reg0_RFUL">
<name>RFUL</name>
<desc>Receiver FIFO Full interrupt mask status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe0000014" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_uart0_Chnl_int_sts_reg0_REMPTY">
<name>REMPTY</name>
<desc>Receiver FIFO Empty interrupt
mask status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe0000014" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_uart0_Chnl_int_sts_reg0_RTRIG">
<name>RTRIG</name>
<desc>Receiver FIFO Trigger interrupt mask status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe0000014" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_uart0_Baud_rate_gen_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0000018" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_uart0_Baud_rate_gen_reg0_CD">
<name>CD</name>
<desc>Baud Rate Clock Divisor Value
0 = Disables baud_sample
1 = Clock divisor bypass
2 - 65535 = baud_sample value</desc>
<sw_param offset="0xe0000018" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_uart0_Rcvr_timeout_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe000001c" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_uart0_Rcvr_timeout_reg0_RTO">
<name>RTO</name>
<desc>Receiver timeout value
0 = Disables receiver timeout counter
1 - 255 = Receiver timeout</desc>
<sw_param offset="0xe000001c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_uart0_Rcvr_FIFO_trigger_level0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0000020" start="31" end="6" />
</parameter>
<parameter uniqueid="ps7_uart0_Rcvr_FIFO_trigger_level0_RTRIG">
<name>RTRIG</name>
<desc>Receiver FIFO trigger level value
0 = Disables receiver timeout counter
1 - 63 = Receiver timeout</desc>
<sw_param offset="0xe0000020" start="5" end="0" />
</parameter>
<parameter uniqueid="ps7_uart0_Modem_ctrl_reg0_reserved_1">
<name>reserved_1</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0000024" start="31" end="6" />
</parameter>
<parameter uniqueid="ps7_uart0_Modem_ctrl_reg0_FCM">
<name>FCM</name>
<desc>Automatic flow control mode
1 = enable
0 = disable</desc>
<sw_param offset="0xe0000024" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_uart0_Modem_ctrl_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0000024" start="4" end="2" />
</parameter>
<parameter uniqueid="ps7_uart0_Modem_ctrl_reg0_RTS">
<name>RTS</name>
<desc>Request to send output control
1 = forced to logic 0
0 = forced to logic 1</desc>
<sw_param offset="0xe0000024" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_uart0_Modem_ctrl_reg0_DTR">
<name>DTR</name>
<desc>Data Terminal Ready
1 = forced to logic 0
0 = forced to logic 1</desc>
<sw_param offset="0xe0000024" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_uart0_Modem_sts_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0000028" start="31" end="9" />
</parameter>
<parameter uniqueid="ps7_uart0_Modem_sts_reg0_FCMS">
<name>FCMS</name>
<desc>Flow Control Mode
1 = enabled
0 = disabled</desc>
<sw_param offset="0xe0000028" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_uart0_Modem_sts_reg0_DCD">
<name>DCD</name>
<desc>Data Carrier Detect Input Status
1 = ua_ndcd input is low
0 = ua_ndcd input is high</desc>
<sw_param offset="0xe0000028" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_uart0_Modem_sts_reg0_RI">
<name>RI</name>
<desc>Ring Indicator input status
1 = ua_nri input is low
0 = ua_nri input is high</desc>
<sw_param offset="0xe0000028" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_uart0_Modem_sts_reg0_DSR">
<name>DSR</name>
<desc>Data Set Ready input status
1 = ua_ndsr input is low
0 = ua_ndsr input is high</desc>
<sw_param offset="0xe0000028" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_uart0_Modem_sts_reg0_CTS">
<name>CTS</name>
<desc>Clear to Send input status
1 = ua_ncts input is low
0 = ua_ncts input is high</desc>
<sw_param offset="0xe0000028" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_uart0_Modem_sts_reg0_DDCD">
<name>DDCD</name>
<desc>Delta Data Carrier Detect Status
1 = Change has occurred
0 = No change has occurred</desc>
<sw_param offset="0xe0000028" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_uart0_Modem_sts_reg0_TERI">
<name>TERI</name>
<desc>Trailing Edge Ring Indicator Status
1 = Trailing edge has occurred
0 = No trailing edge has occurred</desc>
<sw_param offset="0xe0000028" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_uart0_Modem_sts_reg0_DDSR">
<name>DDSR</name>
<desc>Delta Data Set Ready status
1 = Change has occurred
0 = No change has occurred</desc>
<sw_param offset="0xe0000028" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_uart0_Modem_sts_reg0_DCTS">
<name>DCTS</name>
<desc>Delta Clear To Send Status
1 = Change has occurred
0 = No change has occurred</desc>
<sw_param offset="0xe0000028" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_uart0_Channel_sts_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe000002c" start="31" end="15" />
</parameter>
<parameter uniqueid="ps7_uart0_Channel_sts_reg0_TNFUL">
<name>TNFUL</name>
<desc>Transmitter FIFO Nearly Full continuous status
1 = Only one byte is free in the TX FIFO
0 = More than one byte is unused in the TX FIFO</desc>
<sw_param offset="0xe000002c" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_uart0_Channel_sts_reg0_TTRIG">
<name>TTRIG</name>
<desc>Transmitter FIFO Trigger continuous status
1 = TX FIFO fill level is greater than or equal to TTRIG
0 = TX FIFO fill level is less than TTRIG</desc>
<sw_param offset="0xe000002c" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_uart0_Channel_sts_reg0_FDELT">
<name>FDELT</name>
<desc>Receiver flow delay trigger continuous status.
1 = RX FIFO fill level is greater than or equal to FDEL
0 = RX FIFO fill level is less than FDEL</desc>
<sw_param offset="0xe000002c" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_uart0_Channel_sts_reg0_TACTIVE">
<name>TACTIVE</name>
<desc>Transmitter state machine active status.
1 = active state
0 = inactive state</desc>
<sw_param offset="0xe000002c" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_uart0_Channel_sts_reg0_RACTIVE">
<name>RACTIVE</name>
<desc>Receiver state machine active status.
1 = active state
0 = inactive state</desc>
<sw_param offset="0xe000002c" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_uart0_Channel_sts_reg0_DMSI">
<name>DMSI</name>
<desc>Delta Modem Status Indicator status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe000002c" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_uart0_Channel_sts_reg0_TIMEOUT">
<name>TIMEOUT</name>
<desc>Receiver Timeout status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe000002c" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_uart0_Channel_sts_reg0_PARE">
<name>PARE</name>
<desc>Receiver Parity Error status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe000002c" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_uart0_Channel_sts_reg0_FRAME">
<name>FRAME</name>
<desc>Receiver Frame Error status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe000002c" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_uart0_Channel_sts_reg0_ROVR">
<name>ROVR</name>
<desc>Receiver Overflow Error status
1 = interrupt occurred
0 = no interrupt occurred</desc>
<sw_param offset="0xe000002c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_uart0_Channel_sts_reg0_TFUL">
<name>TFUL</name>
<desc>Transmitter FIFO Full continuous status
1= TX FIFO is full
0 = TX FIFO is not full</desc>
<sw_param offset="0xe000002c" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_uart0_Channel_sts_reg0_TEMPTY">
<name>TEMPTY</name>
<desc>Transmitter FIFO Empty continuous status
1 = TX FIFO is empty
0 = TX FIFO is not empty</desc>
<sw_param offset="0xe000002c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_uart0_Channel_sts_reg0_RFUL">
<name>RFUL</name>
<desc>Receiver FIFO Full continuous status
1 = RX FIFO is full
0 = RX FIFO is not full</desc>
<sw_param offset="0xe000002c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_uart0_Channel_sts_reg0_REMPTY">
<name>REMPTY</name>
<desc>Receiver FIFO Full continuous status.
1 : RX FIFO is empty
0 : RX FIFO is not empty</desc>
<sw_param offset="0xe000002c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_uart0_Channel_sts_reg0_RTRIG">
<name>RTRIG</name>
<desc>Receiver FIFO Trigger continuous status
1 : RX FIFO fill level is greater than or equal to RTRIG
0 : RX FIFO fill level is less than RTRIG</desc>
<sw_param offset="0xe000002c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_uart0_TX_RX_FIFO0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0000030" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_uart0_TX_RX_FIFO0_FIFO">
<name>FIFO</name>
<desc>operates as TX FIFO and RX FIFO</desc>
<sw_param offset="0xe0000030" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_uart0_Baud_rate_divider_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0000034" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_uart0_Baud_rate_divider_reg0_BDIV">
<name>BDIV</name>
<desc>Baud rate divider value
0 - 3: ignored
4 - 255: Baud rate</desc>
<sw_param offset="0xe0000034" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_uart0_Flow_delay_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0000038" start="31" end="6" />
</parameter>
<parameter uniqueid="ps7_uart0_Flow_delay_reg0_FDEL">
<name>FDEL</name>
<desc>RX FIFO trigger level for ua_nrts de-assertion
0 - 3 = disabled
4 to 65535 = ua_nrts is driven high when RX FIFO fill level equals FDEL</desc>
<sw_param offset="0xe0000038" start="5" end="0" />
</parameter>
<parameter uniqueid="ps7_uart0_IR_min_rcv_pulse_wdth0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe000003c" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_uart0_IR_min_rcv_pulse_wdth0_PMN">
<name>PMN</name>
<desc>Number of uart_clk periods
0 to 65535 : minimum width</desc>
<sw_param offset="0xe000003c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_uart0_IR_transmitted_pulse_wdth0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0000040" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_uart0_IR_transmitted_pulse_wdth0_PWID">
<name>PWID</name>
<desc>Pulse width
0 - 255 : width</desc>
<sw_param offset="0xe0000040" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_uart0_Tx_FIFO_trigger_level0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0000044" start="31" end="6" />
</parameter>
<parameter uniqueid="ps7_uart0_Tx_FIFO_trigger_level0_TTRIG">
<name>TTRIG</name>
<desc>Transmitter FIFO trigger level
0 = Disables transmitter FIFO trigger level function
1 - 63 = Trigger set when transmitter FIFO fills to TTRIG bytes</desc>
<sw_param offset="0xe0000044" start="5" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_net_ctrl_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe000c000" start="31" end="19" />
</parameter>
<parameter uniqueid="ps7_gem1_net_ctrl_flush_next_rx_dpram_pkt">
<name>flush_next_rx_dpram_pkt</name>
<desc>Flush the next packet from the external RX DPRAM.
Writing one to this bit will only have an effect if the DMA is not currently writing a packet already stored in the DPRAM to memory.</desc>
<sw_param offset="0xe000c000" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_gem1_net_ctrl_tx_pfc_pri_pri_pause_frame">
<name>tx_pfc_pri_pri_pause_frame</name>
<desc>Transmit PFC Priority Based Pause Frame. Takes the values stored in the Transmit PFC Pause Register</desc>
<sw_param offset="0xe000c000" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_gem1_net_ctrl_en_pfc_pri_pause_rx">
<name>en_pfc_pri_pause_rx</name>
<desc>Enable PFC Priority Based Pause Reception capabilities.
Setting this bit will enable PFC negotiation and recognition of priority based pause frames.</desc>
<sw_param offset="0xe000c000" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_net_ctrl_str_rx_timestamp">
<name>str_rx_timestamp</name>
<desc>Store receive time stamp to memory. Setting this bit to one will cause the CRC of every received frame to be replaced with the value of the nanoseconds field of the 1588 timer that was captured as the receive frame passed the message time stamp point. Set to zero for normal operation.</desc>
<sw_param offset="0xe000c000" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_gem1_net_ctrl_reserved_rd_snapshot">
<name>reserved_rd_snapshot</name>
<desc>Reserved. Do not modify.</desc>
<sw_param offset="0xe000c000" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_gem1_net_ctrl_reserved_take_snapshot">
<name>reserved_take_snapshot</name>
<desc>Reserved. Do not modify.</desc>
<sw_param offset="0xe000c000" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_gem1_net_ctrl_tx_zeroq_pause_frame">
<name>tx_zeroq_pause_frame</name>
<desc>Transmit zero quantum pause frame - writing one to this bit causes a pause frame with zero quantum to be transmitted.</desc>
<sw_param offset="0xe000c000" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_gem1_net_ctrl_tx_pause_frame">
<name>tx_pause_frame</name>
<desc>Transmit pause frame - writing one to this bit causes a pause frame to be transmitted.</desc>
<sw_param offset="0xe000c000" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_gem1_net_ctrl_tx_halt">
<name>tx_halt</name>
<desc>Transmit halt - writing one to this bit halts transmission as soon as any ongoing frame transmission ends.</desc>
<sw_param offset="0xe000c000" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_gem1_net_ctrl_start_tx">
<name>start_tx</name>
<desc>Start transmission - writing one to this bit starts transmission.</desc>
<sw_param offset="0xe000c000" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_gem1_net_ctrl_back_pressure">
<name>back_pressure</name>
<desc>Back pressure - if set in 10M or 100M half duplex mode will force collisions on all received frames.
Ignored in gigabit half duplex mode.</desc>
<sw_param offset="0xe000c000" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_gem1_net_ctrl_wren_stat_regs">
<name>wren_stat_regs</name>
<desc>Write enable for statistics registers - setting this bit to one means the statistics registers can be written for functional test purposes.</desc>
<sw_param offset="0xe000c000" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_gem1_net_ctrl_incr_stat_regs">
<name>incr_stat_regs</name>
<desc>Incremental statistics registers - this bit is write only.
Writing a one increments all the statistics registers by one for test purposes.</desc>
<sw_param offset="0xe000c000" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_gem1_net_ctrl_clear_stat_regs">
<name>clear_stat_regs</name>
<desc>Clear statistics registers - this bit is write only.
Writing a one clears the statistics registers.</desc>
<sw_param offset="0xe000c000" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_gem1_net_ctrl_mgmt_port_en">
<name>mgmt_port_en</name>
<desc>Management port enable - set to one to enable the management port. When zero forces mdio to high impedance state and mdc low.</desc>
<sw_param offset="0xe000c000" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_gem1_net_ctrl_tx_en">
<name>tx_en</name>
<desc>Transmit enable - when set, it enables the GEM transmitter to send data. When reset transmission will stop immediately, the transmit pipeline and control registers will be cleared and the transmit queue pointer register will reset to point to the start of the transmit descriptor list.</desc>
<sw_param offset="0xe000c000" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_gem1_net_ctrl_rx_en">
<name>rx_en</name>
<desc>Receive enable - when set, it enables the GEM to receive data. When reset frame reception will stop immediately and the receive pipeline will be cleared.
The receive queue pointer register is unaffected.</desc>
<sw_param offset="0xe000c000" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_gem1_net_ctrl_loopback_local">
<name>loopback_local</name>
<desc>Loop back local - asserts the loopback_local signal to the system clock generator. Also connects txd to rxd, tx_en to rx_dv and forces full duplex mode. Bit 11 of the network configuration register must be set low to disable TBI mode when in internal loopback. rx_clk and tx_clk may malfunction as the GEM is switched into and out of internal loop back. It is important that receive and transmit circuits have already been disabled when making the switch into and out of internal loop back. Local loopback functionality isn't available in the EP107 Pele Emulation Platform, because the clocking doesn't map well into an FPGA.</desc>
<sw_param offset="0xe000c000" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_gem1_net_ctrl_reserved_loopback">
<name>reserved_loopback</name>
<desc>Reserved. Do not modify.</desc>
<sw_param offset="0xe000c000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_net_cfg_unidir_en">
<name>unidir_en</name>
<desc>Uni-direction-enable. When low the PCS will transmit idle symbols if the link goes down. When high the PCS can transmit frame data when the link is down.</desc>
<sw_param offset="0xe000c004" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_gem1_net_cfg_ignore_ipg_rx_er">
<name>ignore_ipg_rx_er</name>
<desc>Ignore IPG rx_er. When set rx_er has no effect on the GEM's operation when rx_dv is low. Set this when using the RGMII wrapper in half-duplex mode.</desc>
<sw_param offset="0xe000c004" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_gem1_net_cfg_rx_bad_preamble">
<name>rx_bad_preamble</name>
<desc>Receive bad preamble. When set frames with non-standard preamble are not rejected.</desc>
<sw_param offset="0xe000c004" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_gem1_net_cfg_ipg_stretch_en">
<name>ipg_stretch_en</name>
<desc>IPG stretch enable - when set the transmit IPG can be increased above 96 bit times depending on the previous frame length using the IPG stretch register.</desc>
<sw_param offset="0xe000c004" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_gem1_net_cfg_sgmii_en">
<name>sgmii_en</name>
<desc>SGMII mode enable - changes behaviour of the auto-negotiation advertisement and link partner ability registers to meet the requirements of SGMII and reduces the duration of the link timer from 10 ms to 1.6 ms</desc>
<sw_param offset="0xe000c004" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_gem1_net_cfg_ignore_rx_fcs">
<name>ignore_rx_fcs</name>
<desc>Ignore RX FCS - when set frames with FCS/CRC errors will not be rejected. FCS error statistics will still be collected for frames with bad FCS and FCS status will be recorded in frame's DMA descriptor.
For normal operation this bit must be set to zero.</desc>
<sw_param offset="0xe000c004" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_gem1_net_cfg_rx_hd_while_tx">
<name>rx_hd_while_tx</name>
<desc>Enable frames to be received in half-duplex mode while transmitting.</desc>
<sw_param offset="0xe000c004" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_gem1_net_cfg_rx_chksum_offld_en">
<name>rx_chksum_offld_en</name>
<desc>Receive checksum offload enable - when set, the receive checksum engine is enabled. Frames with bad IP, TCP or UDP checksums are discarded.</desc>
<sw_param offset="0xe000c004" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_gem1_net_cfg_dis_cp_pause_frame">
<name>dis_cp_pause_frame</name>
<desc>Disable copy of pause frames - set to one to prevent valid pause frames being copied to memory. When set, pause frames are not copied to memory regardless of the state of the copy all frames bit; whether a hash match is found or whether a type ID match is identified. If a destination address match is found the pause frame will be copied to memory.
Note that valid pause frames received will still increment pause statistics and pause the transmission of frames as required.</desc>
<sw_param offset="0xe000c004" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_gem1_net_cfg_dbus_width">
<name>dbus_width</name>
<desc>Data bus width - set according to AMBA AHB or external FIFO data bus width. The reset value for this can be changed by defining a new value for gem_dma_bus_width_def in gem_defs.v Only valid bus widths may be written if the system is configured to a maximum width less than 128-bits. Pele defines gem_dma_bus_width_def as 2'b00.
00: 32 bit AMBA AHB data bus width
01: 64 bit AMBA AHB data bus width
10: 128 bit AMBA AHB data bus width
11: 128 bit AMBA AHB data bus width</desc>
<sw_param offset="0xe000c004" start="22" end="21" />
</parameter>
<parameter uniqueid="ps7_gem1_net_cfg_mdc_clk_div">
<name>mdc_clk_div</name>
<desc>MDC clock division - set according to pclk speed.
These three bits determine the number pclk will be divided by to generate MDC. For conformance with the 802.3 specification, MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and write operations). The reset value for this can be changed by defining a new value for gem_mdc_clock_div in gem_defs.v. Pele defines gem_mdc_clock_div as 3'b010.
000: divide pclk by 8 (pclk up to 20 MHz)
001: divide pclk by 16 (pclk up to 40 MHz)
010: divide pclk by 32 (pclk up to 80 MHz)
011: divide pclk by 48 (pclk up to 120MHz)
100: divide pclk by 64 (pclk up to 160 MHz)
101: divide pclk by 96 (pclk up to 240 MHz)
110: divide pclk by 128 (pclk up to 320 MHz)
111: divide pclk by 224 (pclk up to 540 MHz)</desc>
<sw_param offset="0xe000c004" start="20" end="18" />
</parameter>
<parameter uniqueid="ps7_gem1_net_cfg_fcs_remove">
<name>fcs_remove</name>
<desc>FCS remove - setting this bit will cause received frames to be written to memory without their frame check sequence (last 4 bytes). The frame length indicated will be reduced by four bytes in this mode.</desc>
<sw_param offset="0xe000c004" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_gem1_net_cfg_len_err_frame_disc">
<name>len_err_frame_disc</name>
<desc>Length field error frame discard - setting this bit causes frames with a measured length shorter than the extracted length field (as indicated by bytes 13 and 14 in a non-VLAN tagged frame) to be discarded. This only applies to frames with a length field less than 0x0600.</desc>
<sw_param offset="0xe000c004" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_net_cfg_rx_buf_offset">
<name>rx_buf_offset</name>
<desc>Receive buffer offset - indicates the number of bytes by which the received data is offset from the start of the receive buffer.</desc>
<sw_param offset="0xe000c004" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_gem1_net_cfg_pause_en">
<name>pause_en</name>
<desc>Pause enable - when set, transmission will pause if a non zero 802.3 classic pause frame is received and PFC has not been negotiated.</desc>
<sw_param offset="0xe000c004" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_gem1_net_cfg_retry_test">
<name>retry_test</name>
<desc>Retry test - must be set to zero for normal operation.
If set to one the backoff between collisions will always be one slot time. Setting this bit to one helps test the too many retries condition. Also used in the pause frame tests to reduce the pause counter's decrement time from 512 bit times, to every rx_clk cycle.</desc>
<sw_param offset="0xe000c004" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_gem1_net_cfg_pcs_sel">
<name>pcs_sel</name>
<desc>PCS select - selects between MII/GMII and TBI.
Must be set for SGMII operation.
0: GMII/MII interface enabled, TBI disabled
1: TBI enabled, GMII/MII disabled</desc>
<sw_param offset="0xe000c004" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_gem1_net_cfg_gige_en">
<name>gige_en</name>
<desc>Gigabit mode enable - setting this bit configures the GEM for 1000 Mbps operation.
0: 10/100 operation using MII or TBI interface
1: Gigabit operation using GMII or TBI interface</desc>
<sw_param offset="0xe000c004" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_gem1_net_cfg_ext_addr_match_en">
<name>ext_addr_match_en</name>
<desc>External address match enable - when set the external address match interface can be used to copy frames to memory.</desc>
<sw_param offset="0xe000c004" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_gem1_net_cfg_reserved_rx_1536_byte_frames">
<name>reserved_rx_1536_byte_frames</name>
<desc>Reserved. Do not modify.</desc>
<sw_param offset="0xe000c004" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_gem1_net_cfg_uni_hash_en">
<name>uni_hash_en</name>
<desc>Unicast hash enable - when set, unicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register.</desc>
<sw_param offset="0xe000c004" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_gem1_net_cfg_multi_hash_en">
<name>multi_hash_en</name>
<desc>Multicast hash enable - when set, multicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register.</desc>
<sw_param offset="0xe000c004" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_gem1_net_cfg_no_broadcast">
<name>no_broadcast</name>
<desc>No broadcast - when set to logic one, frames addressed to the broadcast address of all ones will not be accepted.</desc>
<sw_param offset="0xe000c004" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_gem1_net_cfg_copy_all">
<name>copy_all</name>
<desc>Copy all frames - when set to logic one, all valid frames will be accepted.</desc>
<sw_param offset="0xe000c004" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_gem1_net_cfg_reserved_jumbo_en">
<name>reserved_jumbo_en</name>
<desc>Reserved. Do not modify.</desc>
<sw_param offset="0xe000c004" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_gem1_net_cfg_disc_non_vlan">
<name>disc_non_vlan</name>
<desc>Discard non-VLAN frames - when set only VLAN tagged frames will be passed to the address matching logic.</desc>
<sw_param offset="0xe000c004" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_gem1_net_cfg_full_duplex">
<name>full_duplex</name>
<desc>Full duplex - if set to logic one, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting. Also controls the half_duplex pin.</desc>
<sw_param offset="0xe000c004" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_gem1_net_cfg_speed">
<name>speed</name>
<desc>Speed - set to logic one to indicate 100Mbps operation, logic zero for 10Mbps. The value of this pin is reflected on the speed_mode[0] output pin.</desc>
<sw_param offset="0xe000c004" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_net_status_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write</desc>
<sw_param offset="0xe000c008" start="31" end="7" />
</parameter>
<parameter uniqueid="ps7_gem1_net_status_pfc_pri_pause_neg">
<name>pfc_pri_pause_neg</name>
<desc>Set when PFC Priority Based Pause has been negotiated.</desc>
<sw_param offset="0xe000c008" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_gem1_net_status_pcs_autoneg_pause_tx_res">
<name>pcs_autoneg_pause_tx_res</name>
<desc>PCS auto-negotiation pause transmit resolution.</desc>
<sw_param offset="0xe000c008" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_gem1_net_status_pcs_autoneg_pause_rx_res">
<name>pcs_autoneg_pause_rx_res</name>
<desc>PCS auto-negotiation pause receive resolution</desc>
<sw_param offset="0xe000c008" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_gem1_net_status_pcs_autoneg_dup_res">
<name>pcs_autoneg_dup_res</name>
<desc>PCS auto-negotiation duplex resolution. Set to one if the resolution function determines that both devices are capable of full duplex operation. If zero half-duplex operation is possible as long as bit 0 (PCS link state) is also one.</desc>
<sw_param offset="0xe000c008" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_gem1_net_status_phy_mgmt_idle">
<name>phy_mgmt_idle</name>
<desc>The PHY management logic is idle (i.e. has completed).</desc>
<sw_param offset="0xe000c008" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_gem1_net_status_mdio_in_pin_status">
<name>mdio_in_pin_status</name>
<desc>Returns status of the mdio_in pin</desc>
<sw_param offset="0xe000c008" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_gem1_net_status_pcs_link_state">
<name>pcs_link_state</name>
<desc>Returns status of PCS link state. If auto-negotiation is disabled this returns the synchronisation status. If auto-negotiation is enabled it is set in the LINK_OK state as long as a compatible duplex mode is resolved, it is always set in the LINK_OK state in SGMII mode.</desc>
<sw_param offset="0xe000c008" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_user_io_user_in">
<name>user_in</name>
<desc>User programmable inputs - the upper 16 bits of this register are used to monitor the state of the user inputs. A logic one read from a bit in this range will correspond to the input being in a high state. A logic zero read from a bit in this range will correspond to the input being in a low state. Any unused bits will be read as zero. Writing to any bits in this range will have no functional effect.</desc>
<sw_param offset="0xe000c00c" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_user_io_user_out">
<name>user_out</name>
<desc>User programmable outputs - the lower 16 bits of this register are used to control the state of the user outputs. A logic one written to a bit in this range will cause the corresponding output to be set high. A logic zero written to a bit in this range shall cause the corresponding output to be forced low. Any unused bits will be read as logic zero. Writing to any unused bits in this range will have no functional effect.</desc>
<sw_param offset="0xe000c00c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_dma_cfg_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe000c010" start="31" end="25" />
</parameter>
<parameter uniqueid="ps7_gem1_dma_cfg_disc_when_no_ahb">
<name>disc_when_no_ahb</name>
<desc>When set, the GEM DMA will automatically discard receive packets from the receiver packet buffer memory when no AHB resource is available.
When low, then received packets will remain to be stored in the SRAM based packet buffer until AHB buffer resource next becomes available.</desc>
<sw_param offset="0xe000c010" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_gem1_dma_cfg_ahb_mem_rx_buf_size">
<name>ahb_mem_rx_buf_size</name>
<desc>DMA receive buffer size in AHB system memory.
The value defined by these bits determines the size of buffer to use in main AHB system memory when writing received data.
The value is defined in multiples of 64 bytes such that a value of 0x01 corresponds to buffers of 64 bytes, 0x02 corresponds to 128 bytes etc.
For example:-
0x02: 128 byte
0x18: 1536 byte (1*max length frame/buffer)
0xA0: 10240 byte (1*10K jumbo frame/buffer)
Note that this value should never be written as zero.</desc>
<sw_param offset="0xe000c010" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_dma_cfg_reserved_1">
<name>reserved_1</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe000c010" start="15" end="12" />
</parameter>
<parameter uniqueid="ps7_gem1_dma_cfg_csum_gen_offload_en">
<name>csum_gen_offload_en</name>
<desc>Transmitter IP, TCP and UDP checksum generation offload enable. When set, the transmitter checksum generation engine is enabled, to calculate and substitute checksums for transmit frames. When clear, frame data is unaffected.
If the GEM is not configured to use the DMA packet buffer, this bit is not implemented and will be treated as reserved, read as zero, ignored on write.
Pele uses packet buffer.</desc>
<sw_param offset="0xe000c010" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_gem1_dma_cfg_tx_pktbuf_memsz_sel">
<name>tx_pktbuf_memsz_sel</name>
<desc>Transmitter packet buffer memory size select - Having this bit at zero halves the amount of memory used for the transmit packet buffer. This reduces the amount of memory used by the GEM. It is important to set this bit to one if the full configured physical memory is available. The value in brackets below represents the size that would result for the default maximum configured memory size of 4 Kbytes.
1: Use full configured addressable space (4 Kb)
0: Do not use top address bit (2 Kb)
If the GEM is not configured to use the DMA packet buffer, this bit is not implemented and will be treated as reserved, read as zero, ignored on write. Pele uses packet buffer</desc>
<sw_param offset="0xe000c010" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_gem1_dma_cfg_rx_pktbuf_memsz_sel">
<name>rx_pktbuf_memsz_sel</name>
<desc>Receiver packet buffer memory size select - Having these bits at less than 11 reduces the amount of memory used for the receive packet buffer. This reduces the amount of memory used by the GEM. It is important to set these bits both to one if the full configured physical memory is available. The value in brackets below represents the size that would result for the default maximum configured memory size of 8 Kbytes.
11: Use full configured addressable space (8 Kb)
10: Do not use top address bit (4 Kb)
01: Do not use top two address bits (2 Kb)
00: Do not use top three address bits (1 Kb)
If the GEM is not configured to use the DMA packet buffer, these bits are not implemented and will be treated as reserved, read as zero, ignored on write. Pele uses packet buffer.</desc>
<sw_param offset="0xe000c010" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_gem1_dma_cfg_ahb_endian_swp_pkt_en">
<name>ahb_endian_swp_pkt_en</name>
<desc>AHB endian swap mode enable for packet data accesses - When set, selects swapped endianism for AHB transfers. When clear, selects little endian mode.</desc>
<sw_param offset="0xe000c010" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_gem1_dma_cfg_ahb_endian_swp_mgmt_en">
<name>ahb_endian_swp_mgmt_en</name>
<desc>AHB endian swap mode enable for management descriptor accesses - When set, selects swapped endianism for AHB transfers. When clear, selects little endian mode.</desc>
<sw_param offset="0xe000c010" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_gem1_dma_cfg_reserved_2">
<name>reserved_2</name>
<desc>Reserved, read as zero, ignored on write</desc>
<sw_param offset="0xe000c010" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_gem1_dma_cfg_ahb_fixed_burst_len">
<name>ahb_fixed_burst_len</name>
<desc>AHB fixed burst length for DMA data operations - Selects the burst length to attempt to use on the AHB when transferring frame data. Not used for DMA management operations and only used where space and data size allow. Otherwise SINGLE type AHB transfers are used.
Upper bits become non-writeable if the configured DMA TX and RX FIFO sizes are smaller than required to support the selected burst size.
One-hot priority encoding enforced automatically on register writes as follows, where 'x' represents don't care:-
1xxxx: Attempt to use INCR16 AHB bursts
01xxx: Attempt to use INCR8 AHB bursts
001xx: Attempt to use INCR4 AHB bursts
0001x: Always use SINGLE AHB bursts
00001: Always use SINGLE AHB bursts
default: Attempt to use INCR4 AHB bursts</desc>
<sw_param offset="0xe000c010" start="4" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_tx_status_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe000c014" start="31" end="9" />
</parameter>
<parameter uniqueid="ps7_gem1_tx_status_hresp_not_ok">
<name>hresp_not_ok</name>
<desc>Hresp not OK - set when the DMA block sees hresp not OK. Cleared by writing a one to this bit.</desc>
<sw_param offset="0xe000c014" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_gem1_tx_status_late_collision">
<name>late_collision</name>
<desc>Late collision occurred - only set if the condition occurs in gigabit mode, as retry is not attempted.
Cleared by writing a one to this bit.</desc>
<sw_param offset="0xe000c014" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_gem1_tx_status_tx_under_run">
<name>tx_under_run</name>
<desc>Transmit under run - this bit is set if the transmitter was forced to terminate a frame that it had already began transmitting due to further data being unavailable.
This bit is set if a transmitter status write back has not completed when another status write back is attempted.
When using the DMA interface configured for internal FIFO mode, this bit is also set when the transmit DMA has written the SOP data into the FIFO and either the AHB bus was not granted in time for further data, or because an AHB not OK response was returned, or because a used bit was read.
When using the DMA interface configured for packet buffer mode, this bit will never be set.
When using the external FIFO interface, this bit is also set when the tx_r_underflow input is asserted during a frame transfer. Cleared by writing a 1.</desc>
<sw_param offset="0xe000c014" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_gem1_tx_status_tx_complete">
<name>tx_complete</name>
<desc>Transmit complete - set when a frame has been transmitted. Cleared by writing a one to this bit.</desc>
<sw_param offset="0xe000c014" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_gem1_tx_status_tx_corr_ahb_err">
<name>tx_corr_ahb_err</name>
<desc>Transmit frame corruption due to AHB error - set if an error occurs whilst midway through reading transmit frame from the AHB, including HRESP errors and buffers exhausted mid frame (if the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and tx_er asserted).
Also set in DMA packet buffer mode if single frame is too large for configured packet buffer memory size.
Cleared by writing a one to this bit.</desc>
<sw_param offset="0xe000c014" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_gem1_tx_status_tx_go">
<name>tx_go</name>
<desc>Transmit go - if high transmit is active.
When using the exposed FIFO interface, this bit represents bit 3 of the network control register.
When using the DMA interface this bit represents the tx_go variable as specified in the transmit buffer description.</desc>
<sw_param offset="0xe000c014" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_gem1_tx_status_retry_limit_exceeded">
<name>retry_limit_exceeded</name>
<desc>Retry limit exceeded - cleared by writing a one to this bit.</desc>
<sw_param offset="0xe000c014" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_gem1_tx_status_collision">
<name>collision</name>
<desc>Collision occurred - set by the assertion of collision.
Cleared by writing a one to this bit. When operating in 10/100 mode, this status indicates either a collision or a late collision. In gigabit mode, this status is not set for a late collision.</desc>
<sw_param offset="0xe000c014" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_gem1_tx_status_used_bit_read">
<name>used_bit_read</name>
<desc>Used bit read - set when a transmit buffer descriptor is read with its used bit set. Cleared by writing a one to this bit.</desc>
<sw_param offset="0xe000c014" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_rx_qbar_rx_q_baseaddr">
<name>rx_q_baseaddr</name>
<desc>Receive buffer queue base address - written with the
address of the start of the receive queue.</desc>
<sw_param offset="0xe000c018" start="31" end="2" />
</parameter>
<parameter uniqueid="ps7_gem1_rx_qbar_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c018" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_tx_qbar_tx_q_base_addr">
<name>tx_q_base_addr</name>
<desc>Transmit buffer queue base address - written with the address of the start of the transmit queue.</desc>
<sw_param offset="0xe000c01c" start="31" end="2" />
</parameter>
<parameter uniqueid="ps7_gem1_tx_qbar_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c01c" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_rx_status_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c020" start="31" end="4" />
</parameter>
<parameter uniqueid="ps7_gem1_rx_status_hresp_not_ok">
<name>hresp_not_ok</name>
<desc>Hresp not OK - set when the DMA block sees hresp not OK. Cleared by writing a one to this bit.</desc>
<sw_param offset="0xe000c020" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_gem1_rx_status_rx_overrun">
<name>rx_overrun</name>
<desc>Receive overrun - this bit is set if either the gem_dma RX FIFO or external RX FIFO were unable to store the receive frame due to a FIFO overflow, or if the receive status, reported by the gem_rx module to the gem_dma was not taken at end of frame. This bit is also set in DMA packet buffer mode if the packet buffer overflows. For DMA operation the buffer will be recovered if an overrun occurs. This bit is cleared by writing a one to it.</desc>
<sw_param offset="0xe000c020" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_gem1_rx_status_frame_recd">
<name>frame_recd</name>
<desc>Frame received - one or more frames have been received and placed in memory. Cleared by writing a one to this bit.</desc>
<sw_param offset="0xe000c020" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_gem1_rx_status_buffer_not_avail">
<name>buffer_not_avail</name>
<desc>Buffer not available - an attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA will reread the pointer each time an end of frame is received until a valid pointer is found. This bit is set following each descriptor read attempt that fails, even if consecutive pointers are unsuccessful and software has in the mean time cleared the status flag. Cleared by writing a one to this bit.</desc>
<sw_param offset="0xe000c020" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_status_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c024" start="31" end="27" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_status_tsu_sec_incr">
<name>tsu_sec_incr</name>
<desc>TSU seconds register increment - indicates the register has incremented.</desc>
<sw_param offset="0xe000c024" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_status_pdelay_resp_tx">
<name>pdelay_resp_tx</name>
<desc>PTP pdelay_resp frame transmitted - indicates a PTP pdelay_resp frame has been transmitted.</desc>
<sw_param offset="0xe000c024" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_status_pdelay_req_tx">
<name>pdelay_req_tx</name>
<desc>PTP pdelay_req frame transmitted - indicates a PTP pdelay_req frame has been transmitted.</desc>
<sw_param offset="0xe000c024" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_status_pdelay_resp_rx">
<name>pdelay_resp_rx</name>
<desc>PTP pdelay_resp frame received - indicates a PTP pdelay_resp frame has been received.</desc>
<sw_param offset="0xe000c024" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_status_pdelay_req_rx">
<name>pdelay_req_rx</name>
<desc>PTP pdelay_req frame received - indicates a PTP pdelay_req frame has been received.</desc>
<sw_param offset="0xe000c024" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_status_sync_tx">
<name>sync_tx</name>
<desc>PTP sync frame transmitted - indicates a PTP sync frame has been transmitted.</desc>
<sw_param offset="0xe000c024" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_status_delay_req_tx">
<name>delay_req_tx</name>
<desc>PTP delay_req frame transmitted - indicates a PTP delay_req frame has been transmitted.</desc>
<sw_param offset="0xe000c024" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_status_sync_rx">
<name>sync_rx</name>
<desc>PTP sync frame received - indicates a PTP sync frame has been received.</desc>
<sw_param offset="0xe000c024" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_status_delay_req_rx">
<name>delay_req_rx</name>
<desc>PTP delay_req frame received - indicates a PTP delay_req frame has been received.</desc>
<sw_param offset="0xe000c024" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_status_partner_pg_rx">
<name>partner_pg_rx</name>
<desc>PCS link partner page received - set when a new base page or next page is received from the link partner. The first time this interrupt is received, it will indicate base page received and subsequent reads will indicate next pages. The next page and base page registers should only be read when this interrupt is signalled. For next pages, the link partner next page register should be read first to avoid the register being over written. This interrupt also indicates when the host should write a new page into the next page register. If further next page exchange is only required by the link partner, this register should be written with a null message page (0x2001).</desc>
<sw_param offset="0xe000c024" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_status_autoneg_complete">
<name>autoneg_complete</name>
<desc>PCS auto-negotiation complete - set once the internal PCS layer has completed auto-negotiation.</desc>
<sw_param offset="0xe000c024" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_status_ext_intr">
<name>ext_intr</name>
<desc>External interrupt - set when a rising edge has been detected on the ext_interrupt_in input pin.</desc>
<sw_param offset="0xe000c024" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_status_pause_tx">
<name>pause_tx</name>
<desc>Pause frame transmitted - indicates a pause frame has been successfully transmitted after being initiated from the network control register or from the tx_pause control pin.</desc>
<sw_param offset="0xe000c024" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_status_pause_zero">
<name>pause_zero</name>
<desc>Pause time zero - set when either the pause time register at address 0x38 decrements to zero, or when a valid pause frame is received with a zero pause quantum field.</desc>
<sw_param offset="0xe000c024" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_status_pause_nonzeroq_rx">
<name>pause_nonzeroq_rx</name>
<desc>Pause frame with non-zero pause quantum received - indicates a valid pause has been received that has a non-zero pause quantum field.</desc>
<sw_param offset="0xe000c024" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_status_hresp_not_ok">
<name>hresp_not_ok</name>
<desc>Hresp not OK - set when the DMA block sees hresp not OK.</desc>
<sw_param offset="0xe000c024" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_status_rx_overrun">
<name>rx_overrun</name>
<desc>Receive overrun - set when the receive overrun status bit gets set.</desc>
<sw_param offset="0xe000c024" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_status_link_chng">
<name>link_chng</name>
<desc>Link change - set when the state of the link detected by the internal PCS changes state.</desc>
<sw_param offset="0xe000c024" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_status_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe000c024" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_status_tx_complete">
<name>tx_complete</name>
<desc>Transmit complete - set when a frame has been transmitted.</desc>
<sw_param offset="0xe000c024" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_status_tx_corrupt_ahb_err">
<name>tx_corrupt_ahb_err</name>
<desc>Transmit frame corruption due to AHB error - set if an error occurs whilst midway through reading transmit frame from the AHB, including HRESP errors and buffers exhausted mid frame (if the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and tx_er asserted).
Also set in DMA packet buffer mode if single frame is too large for configured packet buffer memory size.
Cleared on a read.</desc>
<sw_param offset="0xe000c024" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_status_retry_ex_late_collisn">
<name>retry_ex_late_collisn</name>
<desc>Retry limit exceeded or late collision - transmit error.
Late collision will only cause this status bit to be set in gigabit mode (as a retry is not attempted).</desc>
<sw_param offset="0xe000c024" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_status_reserved_tx_underrun">
<name>reserved_tx_underrun</name>
<desc>Reserved. Do not modify.</desc>
<sw_param offset="0xe000c024" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_status_tx_used_read">
<name>tx_used_read</name>
<desc>TX used bit read - set when a transmit buffer descriptor is read with its used bit set.</desc>
<sw_param offset="0xe000c024" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_status_rx_used_read">
<name>rx_used_read</name>
<desc>RX used bit read - set when a receive buffer descriptor is read with its used bit set.</desc>
<sw_param offset="0xe000c024" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_status_rx_complete">
<name>rx_complete</name>
<desc>Receive complete - a frame has been stored in memory.</desc>
<sw_param offset="0xe000c024" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_status_mgmt_sent">
<name>mgmt_sent</name>
<desc>Management frame sent - the PHY maintenance register has completed its operation.</desc>
<sw_param offset="0xe000c024" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_en_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe000c028" start="31" end="27" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_en_tsu_sec_incr">
<name>tsu_sec_incr</name>
<desc>Enable TSU seconds register increment interrupt</desc>
<sw_param offset="0xe000c028" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_en_pdelay_resp_tx">
<name>pdelay_resp_tx</name>
<desc>Enable PTP pdelay_resp frame transmitted interrupt</desc>
<sw_param offset="0xe000c028" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_en_pdelay_req_tx">
<name>pdelay_req_tx</name>
<desc>Enable PTP pdelay_req frame transmitted interrupt</desc>
<sw_param offset="0xe000c028" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_en_pdelay_resp_rx">
<name>pdelay_resp_rx</name>
<desc>Enable PTP pdelay_resp frame received interrupt</desc>
<sw_param offset="0xe000c028" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_en_pdelay_req_rx">
<name>pdelay_req_rx</name>
<desc>Enable PTP pdelay_req frame received interrupt</desc>
<sw_param offset="0xe000c028" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_en_sync_tx">
<name>sync_tx</name>
<desc>Enable PTP sync frame transmitted interrupt</desc>
<sw_param offset="0xe000c028" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_en_delay_req_tx">
<name>delay_req_tx</name>
<desc>Enable PTP delay_req frame transmitted interrupt</desc>
<sw_param offset="0xe000c028" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_en_sync_rx">
<name>sync_rx</name>
<desc>Enable PTP sync frame received interrupt</desc>
<sw_param offset="0xe000c028" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_en_delay_req_rx">
<name>delay_req_rx</name>
<desc>Enable PTP delay_req frame received interrupt</desc>
<sw_param offset="0xe000c028" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_en_partner_pg_rx">
<name>partner_pg_rx</name>
<desc>Enable PCS link partner page received interrupt</desc>
<sw_param offset="0xe000c028" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_en_autoneg_complete">
<name>autoneg_complete</name>
<desc>Enable PCS auto-negotiation complete interrupt</desc>
<sw_param offset="0xe000c028" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_en_ext_intr">
<name>ext_intr</name>
<desc>Enable external interrupt</desc>
<sw_param offset="0xe000c028" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_en_pause_tx">
<name>pause_tx</name>
<desc>Enable pause frame transmitted interrupt</desc>
<sw_param offset="0xe000c028" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_en_pause_zero">
<name>pause_zero</name>
<desc>Enable pause time zero interrupt</desc>
<sw_param offset="0xe000c028" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_en_pause_nonzeroq">
<name>pause_nonzeroq</name>
<desc>Enable pause frame with non-zero pause quantum interrupt</desc>
<sw_param offset="0xe000c028" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_en_hresp_not_ok">
<name>hresp_not_ok</name>
<desc>Enable hresp not OK interrupt</desc>
<sw_param offset="0xe000c028" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_en_rx_overrun">
<name>rx_overrun</name>
<desc>Enable receive overrun interrupt</desc>
<sw_param offset="0xe000c028" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_en_link_chng">
<name>link_chng</name>
<desc>Enable link change interrupt</desc>
<sw_param offset="0xe000c028" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_en_reserved_1">
<name>reserved_1</name>
<desc>Not used</desc>
<sw_param offset="0xe000c028" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_en_tx_complete">
<name>tx_complete</name>
<desc>Enable transmit complete interrupt</desc>
<sw_param offset="0xe000c028" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_en_tx_corrupt_ahb_err">
<name>tx_corrupt_ahb_err</name>
<desc>Enable transmit frame corruption due to AHB error interrupt</desc>
<sw_param offset="0xe000c028" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_en_retry_ex_late_collisn">
<name>retry_ex_late_collisn</name>
<desc>Enable retry limit exceeded or late collision interrupt</desc>
<sw_param offset="0xe000c028" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_en_tx_underrun">
<name>tx_underrun</name>
<desc>Enable transmit buffer under run interrupt</desc>
<sw_param offset="0xe000c028" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_en_tx_used_read">
<name>tx_used_read</name>
<desc>Enable transmit used bit read interrupt</desc>
<sw_param offset="0xe000c028" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_en_rx_used_read">
<name>rx_used_read</name>
<desc>Enable receive used bit read interrupt</desc>
<sw_param offset="0xe000c028" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_en_rx_complete">
<name>rx_complete</name>
<desc>Enable receive complete interrupt</desc>
<sw_param offset="0xe000c028" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_en_mgmt_done">
<name>mgmt_done</name>
<desc>Enable management done interrupt</desc>
<sw_param offset="0xe000c028" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_dis_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe000c02c" start="31" end="27" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_dis_tsu_sec_incr">
<name>tsu_sec_incr</name>
<desc>Disable TSU seconds register increment interrupt</desc>
<sw_param offset="0xe000c02c" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_dis_pdelay_resp_tx">
<name>pdelay_resp_tx</name>
<desc>Disable PTP pdelay_resp frame transmitted interrupt</desc>
<sw_param offset="0xe000c02c" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_dis_pdelay_req_tx">
<name>pdelay_req_tx</name>
<desc>Disable PTP pdelay_req frame transmitted interrupt</desc>
<sw_param offset="0xe000c02c" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_dis_pdelay_resp_rx">
<name>pdelay_resp_rx</name>
<desc>Disable PTP pdelay_resp frame received interrupt</desc>
<sw_param offset="0xe000c02c" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_dis_pdelay_req_rx">
<name>pdelay_req_rx</name>
<desc>Disable PTP pdelay_req frame received interrupt</desc>
<sw_param offset="0xe000c02c" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_dis_sync_tx">
<name>sync_tx</name>
<desc>Disable PTP sync frame transmitted interrupt</desc>
<sw_param offset="0xe000c02c" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_dis_delay_req_tx">
<name>delay_req_tx</name>
<desc>Disable PTP delay_req frame transmitted interrupt</desc>
<sw_param offset="0xe000c02c" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_dis_sync_rx">
<name>sync_rx</name>
<desc>Disable PTP sync frame received interrupt</desc>
<sw_param offset="0xe000c02c" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_dis_delay_req_rx">
<name>delay_req_rx</name>
<desc>Disable PTP delay_req frame received interrupt</desc>
<sw_param offset="0xe000c02c" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_dis_partner_pg_rx">
<name>partner_pg_rx</name>
<desc>Disable PCS link partner page received interrupt</desc>
<sw_param offset="0xe000c02c" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_dis_autoneg_complete">
<name>autoneg_complete</name>
<desc>Disable PCS auto-negotiation complete interrupt</desc>
<sw_param offset="0xe000c02c" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_dis_ext_intr">
<name>ext_intr</name>
<desc>Disable external interrupt</desc>
<sw_param offset="0xe000c02c" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_dis_pause_tx">
<name>pause_tx</name>
<desc>Disable pause frame transmitted interrupt</desc>
<sw_param offset="0xe000c02c" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_dis_pause_zero">
<name>pause_zero</name>
<desc>Disable pause time zero interrupt</desc>
<sw_param offset="0xe000c02c" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_dis_pause_nonzeroq">
<name>pause_nonzeroq</name>
<desc>Disable pause frame with non-zero pause quantum interrupt</desc>
<sw_param offset="0xe000c02c" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_dis_hresp_not_ok">
<name>hresp_not_ok</name>
<desc>Disable hresp not OK interrupt</desc>
<sw_param offset="0xe000c02c" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_dis_rx_overrun">
<name>rx_overrun</name>
<desc>Disable receive overrun interrupt</desc>
<sw_param offset="0xe000c02c" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_dis_link_chng">
<name>link_chng</name>
<desc>Disable link change interrupt</desc>
<sw_param offset="0xe000c02c" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_dis_reserved_1">
<name>reserved_1</name>
<desc>Not used</desc>
<sw_param offset="0xe000c02c" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_dis_tx_complete">
<name>tx_complete</name>
<desc>Disable transmit complete interrupt</desc>
<sw_param offset="0xe000c02c" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_dis_tx_corrupt_ahb_err">
<name>tx_corrupt_ahb_err</name>
<desc>Disable transmit frame corruption due to AHB error interrupt</desc>
<sw_param offset="0xe000c02c" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_dis_retry_ex_late_collisn">
<name>retry_ex_late_collisn</name>
<desc>Disable retry limit exceeded or late collision interrupt</desc>
<sw_param offset="0xe000c02c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_dis_tx_underrun">
<name>tx_underrun</name>
<desc>Disable transmit buffer under run interrupt</desc>
<sw_param offset="0xe000c02c" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_dis_tx_used_read">
<name>tx_used_read</name>
<desc>Disable transmit used bit read interrupt</desc>
<sw_param offset="0xe000c02c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_dis_rx_used_read">
<name>rx_used_read</name>
<desc>Disable receive used bit read interrupt</desc>
<sw_param offset="0xe000c02c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_dis_rx_complete">
<name>rx_complete</name>
<desc>Disable receive complete interrupt</desc>
<sw_param offset="0xe000c02c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_dis_mgmt_done">
<name>mgmt_done</name>
<desc>Disable management done interrupt</desc>
<sw_param offset="0xe000c02c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_mask_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe000c030" start="31" end="26" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_mask_pdelay_resp_tx">
<name>pdelay_resp_tx</name>
<desc>PTP pdelay_resp frame transmitted mask.</desc>
<sw_param offset="0xe000c030" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_mask_pdelay_req_tx">
<name>pdelay_req_tx</name>
<desc>PTP pdelay_req frame transmitted mask.</desc>
<sw_param offset="0xe000c030" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_mask_pdelay_resp_rx">
<name>pdelay_resp_rx</name>
<desc>PTP pdelay_resp frame received mask.</desc>
<sw_param offset="0xe000c030" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_mask_pdelay_req_rx">
<name>pdelay_req_rx</name>
<desc>PTP pdelay_req frame received mask.</desc>
<sw_param offset="0xe000c030" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_mask_sync_tx">
<name>sync_tx</name>
<desc>PTP sync frame transmitted mask.</desc>
<sw_param offset="0xe000c030" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_mask_delay_req_tx">
<name>delay_req_tx</name>
<desc>PTP delay_req frame transmitted mask.</desc>
<sw_param offset="0xe000c030" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_mask_sync_rx">
<name>sync_rx</name>
<desc>PTP sync frame received mask.</desc>
<sw_param offset="0xe000c030" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_mask_delay_req_rx">
<name>delay_req_rx</name>
<desc>PTP delay_req frame received mask.</desc>
<sw_param offset="0xe000c030" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_mask_partner_pg_rx">
<name>partner_pg_rx</name>
<desc>PCS link partner page mask.</desc>
<sw_param offset="0xe000c030" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_mask_autoneg_complete">
<name>autoneg_complete</name>
<desc>PCS auto-negotiation complete interrupt mask.</desc>
<sw_param offset="0xe000c030" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_mask_ext_intr">
<name>ext_intr</name>
<desc>External interrupt mask.</desc>
<sw_param offset="0xe000c030" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_mask_pause_tx">
<name>pause_tx</name>
<desc>Pause frame transmitted interrupt mask.</desc>
<sw_param offset="0xe000c030" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_mask_pause_zero">
<name>pause_zero</name>
<desc>Pause time zero interrupt mask.</desc>
<sw_param offset="0xe000c030" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_mask_pause_nonzeroq">
<name>pause_nonzeroq</name>
<desc>Pause frame with non-zero pause quantum interrupt mask.</desc>
<sw_param offset="0xe000c030" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_mask_hresp_not_ok">
<name>hresp_not_ok</name>
<desc>Hresp not OK interrupt mask.</desc>
<sw_param offset="0xe000c030" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_mask_rx_overrun">
<name>rx_overrun</name>
<desc>Receive overrun interrupt mask.</desc>
<sw_param offset="0xe000c030" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_mask_link_chng">
<name>link_chng</name>
<desc>Link change interrupt mask.</desc>
<sw_param offset="0xe000c030" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_mask_reserved_1">
<name>reserved_1</name>
<desc>Not used</desc>
<sw_param offset="0xe000c030" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_mask_tx_complete">
<name>tx_complete</name>
<desc>Transmit complete interrupt mask.</desc>
<sw_param offset="0xe000c030" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_mask_tx_corrupt_ahb_err">
<name>tx_corrupt_ahb_err</name>
<desc>Transmit frame corruption due to AHB error interrupt</desc>
<sw_param offset="0xe000c030" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_mask_retry_ex_late_collisn">
<name>retry_ex_late_collisn</name>
<desc>Retry limit exceeded or late collision (gigabit mode only)</desc>
<sw_param offset="0xe000c030" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_mask_tx_underrun">
<name>tx_underrun</name>
<desc>Transmit buffer under run interrupt mask.</desc>
<sw_param offset="0xe000c030" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_mask_tx_used_read">
<name>tx_used_read</name>
<desc>Transmit used bit read interrupt mask.</desc>
<sw_param offset="0xe000c030" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_mask_rx_used_read">
<name>rx_used_read</name>
<desc>Receive used bit read interrupt mask.</desc>
<sw_param offset="0xe000c030" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_mask_rx_complete">
<name>rx_complete</name>
<desc>Receive complete interrupt mask.</desc>
<sw_param offset="0xe000c030" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_gem1_intr_mask_mgmt_done">
<name>mgmt_done</name>
<desc>Management done interrupt mask.</desc>
<sw_param offset="0xe000c030" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_phy_maint_reserved">
<name>reserved</name>
<desc>Must be written with 0.</desc>
<sw_param offset="0xe000c034" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_gem1_phy_maint_clause_22">
<name>clause_22</name>
<desc>Must be written to 1 for Clause 22 operation.
Check you PHY's spec to see if it is clause 22 or clause 45 compliant.</desc>
<sw_param offset="0xe000c034" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_gem1_phy_maint_operation">
<name>operation</name>
<desc>Operation. 10 is read. 01 is write.</desc>
<sw_param offset="0xe000c034" start="29" end="28" />
</parameter>
<parameter uniqueid="ps7_gem1_phy_maint_phy_addr">
<name>phy_addr</name>
<desc>PHY address.</desc>
<sw_param offset="0xe000c034" start="27" end="23" />
</parameter>
<parameter uniqueid="ps7_gem1_phy_maint_reg_addr">
<name>reg_addr</name>
<desc>Register address - specifies the register in the PHY to access.</desc>
<sw_param offset="0xe000c034" start="22" end="18" />
</parameter>
<parameter uniqueid="ps7_gem1_phy_maint_must_10">
<name>must_10</name>
<desc>Must be written to 10.</desc>
<sw_param offset="0xe000c034" start="17" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_phy_maint_data">
<name>data</name>
<desc>For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY.</desc>
<sw_param offset="0xe000c034" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_rx_pauseq_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c038" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_rx_pauseq_rx_pauseq">
<name>rx_pauseq</name>
<desc>Received pause quantum - stores the current value of the received pause quantum register which is decremented every 512 bit times.</desc>
<sw_param offset="0xe000c038" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_tx_pauseq_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c03c" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_tx_pauseq_tx_pauseq">
<name>tx_pauseq</name>
<desc>Transmit pause quantum - written with the pause quantum value for pause frame transmission</desc>
<sw_param offset="0xe000c03c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_hash_bot_a">
<name>a</name>
<desc>The first 32 bits of the hash address register.</desc>
<sw_param offset="0xe000c080" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_hash_top_a">
<name>a</name>
<desc>The remaining 32 bits of the hash address register.</desc>
<sw_param offset="0xe000c084" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_spec_addr1_bot_a">
<name>a</name>
<desc>Least significant 32 bits of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.</desc>
<sw_param offset="0xe000c088" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_spec_addr1_top_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write</desc>
<sw_param offset="0xe000c08c" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_spec_addr1_top_addr_msbs">
<name>addr_msbs</name>
<desc>Specific address 1. The most significant bits of the destination address, that is bits 47:32.</desc>
<sw_param offset="0xe000c08c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_spec_addr2_bot_a">
<name>a</name>
<desc>Least significant 32 bits of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.</desc>
<sw_param offset="0xe000c090" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_spec_addr2_top_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write</desc>
<sw_param offset="0xe000c094" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_spec_addr2_top_addr_msbs">
<name>addr_msbs</name>
<desc>Specific address 2. The most significant bits of the destination address, that is bits 47:32.</desc>
<sw_param offset="0xe000c094" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_spec_addr3_bot_a">
<name>a</name>
<desc>Least significant 32 bits of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.</desc>
<sw_param offset="0xe000c098" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_spec_addr3_top_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write</desc>
<sw_param offset="0xe000c09c" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_spec_addr3_top_addr_msbs">
<name>addr_msbs</name>
<desc>Specific address 3. The most significant bits of the destination address, that is bits 47:32.</desc>
<sw_param offset="0xe000c09c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_spec_addr4_bot_a">
<name>a</name>
<desc>Least significant 32 bits of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.</desc>
<sw_param offset="0xe000c0a0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_spec_addr4_top_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write</desc>
<sw_param offset="0xe000c0a4" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_spec_addr4_top_addr_msbs">
<name>addr_msbs</name>
<desc>Specific address 4. The most significant bits of the destination address, that is bits 47:32.</desc>
<sw_param offset="0xe000c0a4" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_type_id_match1_copy_en">
<name>copy_en</name>
<desc>Enable copying of type ID match 1 matched frames</desc>
<sw_param offset="0xe000c0a8" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_gem1_type_id_match1_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write</desc>
<sw_param offset="0xe000c0a8" start="30" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_type_id_match1_type_id_match1">
<name>type_id_match1</name>
<desc>Type ID match 1. For use in comparisons with received frames type ID/length field.</desc>
<sw_param offset="0xe000c0a8" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_type_id_match2_copy_en">
<name>copy_en</name>
<desc>Enable copying of type ID match 2 matched frames</desc>
<sw_param offset="0xe000c0ac" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_gem1_type_id_match2_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write</desc>
<sw_param offset="0xe000c0ac" start="30" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_type_id_match2_type_id_match2">
<name>type_id_match2</name>
<desc>Type ID match 2. For use in comparisons with received frames type ID/length field.</desc>
<sw_param offset="0xe000c0ac" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_type_id_match3_copy_en">
<name>copy_en</name>
<desc>Enable copying of type ID match 3 matched frames</desc>
<sw_param offset="0xe000c0b0" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_gem1_type_id_match3_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write</desc>
<sw_param offset="0xe000c0b0" start="30" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_type_id_match3_type_id_match3">
<name>type_id_match3</name>
<desc>Type ID match 3. For use in comparisons with received frames type ID/length field.</desc>
<sw_param offset="0xe000c0b0" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_type_id_match4_copy_en">
<name>copy_en</name>
<desc>Enable copying of type ID match 4 matched frames</desc>
<sw_param offset="0xe000c0b4" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_gem1_type_id_match4_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write</desc>
<sw_param offset="0xe000c0b4" start="30" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_type_id_match4_type_id_match4">
<name>type_id_match4</name>
<desc>Type ID match 4. For use in comparisons with received frames type ID/length field.</desc>
<sw_param offset="0xe000c0b4" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_wake_on_lan_reserved">
<name>reserved</name>
<desc>Reserved - read 0, ignored when written</desc>
<sw_param offset="0xe000c0b8" start="31" end="20" />
</parameter>
<parameter uniqueid="ps7_gem1_wake_on_lan_multi_hash_en">
<name>multi_hash_en</name>
<desc>Wake on LAN multicast hash event enable. When set multicast hash events will cause the wol output to be asserted.</desc>
<sw_param offset="0xe000c0b8" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_gem1_wake_on_lan_spec_addr_reg1_en">
<name>spec_addr_reg1_en</name>
<desc>Wake on LAN specific address register 1 event enable. When set specific address 1 events will cause the wol output to be asserted.</desc>
<sw_param offset="0xe000c0b8" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_gem1_wake_on_lan_arp_req_en">
<name>arp_req_en</name>
<desc>Wake on LAN ARP request event enable. When set ARP request events will cause the wol output to be asserted.</desc>
<sw_param offset="0xe000c0b8" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_gem1_wake_on_lan_magic_pkt_en">
<name>magic_pkt_en</name>
<desc>Wake on LAN magic packet event enable. When set magic packet events will cause the wol output to be asserted.</desc>
<sw_param offset="0xe000c0b8" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_wake_on_lan_arp_req_ip_addr">
<name>arp_req_ip_addr</name>
<desc>Wake on LAN ARP request IP address. Written to define the least significant 16 bits of the target IP address that is matched to generate a Wake on LAN event. A value of zero will not generate an event, even if this is matched by the received frame.</desc>
<sw_param offset="0xe000c0b8" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_ipg_stretch_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c0bc" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_ipg_stretch_ipg_stretch">
<name>ipg_stretch</name>
<desc>Bits 7:0 are multiplied with the previously transmitted frame length (including preamble) bits 15:8 +1 divide the frame length. If the resulting number is greater than 96 and bit 28 is set in the network configuration register then the resulting number is used for the transmit inter-packet-gap. 1 is added to bits 15:8 to prevent a divide by zero.</desc>
<sw_param offset="0xe000c0bc" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_stacked_vlan_stacked_vlan_en">
<name>stacked_vlan_en</name>
<desc>Enable Stacked VLAN processing mode</desc>
<sw_param offset="0xe000c0c0" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_gem1_stacked_vlan_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c0c0" start="30" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_stacked_vlan_user_def_vlan_type">
<name>user_def_vlan_type</name>
<desc>User defined VLAN_TYPE field. When Stacked VLAN is enabled, the first VLAN tag in a received frame will only be accepted if the VLAN type field is equal to this user defined VLAN_TYPE OR equal to the standard VLAN type (0x8100). Note that the second VLAN tag of a Stacked VLAN packet will only be matched correctly if its VLAN_TYPE field equals 0x8100.</desc>
<sw_param offset="0xe000c0c0" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_tx_pfc_pause_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c0c4" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_tx_pfc_pause_pauseq_sel">
<name>pauseq_sel</name>
<desc>If bit 17 of the network control register is written with a one then for each entry equal to zero in the Transmit PFC Pause Register[15:8], the PFC pause frame's pause quantum field associated with that entry will be taken from the transmit pause quantum register. For each entry equal to one in the Transmit PFC Pause Register [15:8], the pause quantum associated with that entry will be zero.</desc>
<sw_param offset="0xe000c0c4" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_gem1_tx_pfc_pause_pri_en_vec_val">
<name>pri_en_vec_val</name>
<desc>If bit 17 of the network control register is written with a one then the priority enable vector of the PFC priority based pause frame will be set equal to the value stored in this register [7:0].</desc>
<sw_param offset="0xe000c0c4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_spec_addr1_mask_bot_mask_bits_bot">
<name>mask_bits_bot</name>
<desc>Setting a bit to one masks the corresponding bit in the specific address 1 register</desc>
<sw_param offset="0xe000c0c8" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_spec_addr1_mask_top_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c0cc" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_spec_addr1_mask_top_mask_bits_top">
<name>mask_bits_top</name>
<desc>Setting a bit to one masks the corresponding bit in the specific address 1 register</desc>
<sw_param offset="0xe000c0cc" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_module_id_module_id">
<name>module_id</name>
<desc>Module identification number - for the GEM, this value is fixed at 0x0002.</desc>
<sw_param offset="0xe000c0fc" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_module_id_module_rev">
<name>module_rev</name>
<desc>Module revision - fixed byte value specific to the revision of the design which is incremented after each release of the IP. Corresponds to Pele having GEM p23.</desc>
<sw_param offset="0xe000c0fc" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_octets_tx_bot_octets_tx_bot">
<name>octets_tx_bot</name>
<desc>Transmitted octets in frame without errors [31:0].
The number of octets transmitted in valid frames of any type. This counter is 48-bits, and is read through two registers. This count does not include octets from automatically generated pause frames.</desc>
<sw_param offset="0xe000c100" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_octets_tx_top_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c104" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_octets_tx_top_octets_tx_top">
<name>octets_tx_top</name>
<desc>Transmitted octets in frame without errors [47:32].
The number of octets transmitted in valid frames of
any type. This counter is 48-bits, and is read through
two registers. This count does not include octets
from automatically generated pause frames.</desc>
<sw_param offset="0xe000c104" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_frames_tx_a">
<name>a</name>
<desc>Frames transmitted without error. A 32 bit register
counting the number of frames successfully
transmitted, i.e. no under run and not too many
retries. Excludes pause frames.</desc>
<sw_param offset="0xe000c108" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_broadcast_frames_tx_a">
<name>a</name>
<desc>Broadcast frames transmitted without error. A 32 bit
register counting the number of broadcast frames
successfully transmitted without error, i.e. no under
run and not too many retries. Excludes pause
frames.</desc>
<sw_param offset="0xe000c10c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_multi_frames_tx_a">
<name>a</name>
<desc>Multicast frames transmitted without error. A 32 bit
register counting the number of multicast frames
successfully transmitted without error, i.e. no under
run and not too many retries. Excludes pause
frames.</desc>
<sw_param offset="0xe000c110" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_pause_frames_tx_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c114" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_pause_frames_tx_pause_frames_tx">
<name>pause_frames_tx</name>
<desc>Transmitted pause frames - a 16 bit register
counting the number of pause frames transmitted.
Only pause frames triggered by the register interface
or through the external pause pins are counted as
pause frames. Pause frames received through the
external FIFO interface are counted in the frames
transmitted counter.</desc>
<sw_param offset="0xe000c114" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_frames_64b_tx_a">
<name>a</name>
<desc>64 byte frames transmitted without error. A 32 bit
register counting the number of 64 byte frames
successfully transmitted without error, i.e. no under
run and not too many retries. Excludes pause
frames.</desc>
<sw_param offset="0xe000c118" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_frames_65to127b_tx_a">
<name>a</name>
<desc>65 to127 byte frames transmitted without error. A 32
bit register counting the number of 65 to127 byte
frames successfully transmitted without error, i.e. no
under run and not too many retries.</desc>
<sw_param offset="0xe000c11c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_frames_128to255b_tx_a">
<name>a</name>
<desc>128 to 255 byte frames transmitted without error. A
32 bit register counting the number of 128 to 255
byte frames successfully transmitted without error,
i.e. no under run and not too many retries.</desc>
<sw_param offset="0xe000c120" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_frames_256to511b_tx_a">
<name>a</name>
<desc>256 to 511 byte frames transmitted without error. A
32 bit register counting the number of 256 to 511
byte frames successfully transmitted without error,
i.e. no under run and not too many retries.</desc>
<sw_param offset="0xe000c124" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_frames_512to1023b_tx_a">
<name>a</name>
<desc>512 to 1023 byte frames transmitted without error. A
32 bit register counting the number of 512 to 1023
byte frames successfully transmitted without error,
i.e. no under run and not too many retries.</desc>
<sw_param offset="0xe000c128" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_frames_1024to1518b_tx_a">
<name>a</name>
<desc>1024 to 1518 byte frames transmitted without error.
A 32 bit register counting the number of 1024 to
1518 byte frames successfully transmitted without
error, i.e. no under run and not too many retries.</desc>
<sw_param offset="0xe000c12c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_tx_under_runs_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c134" start="31" end="10" />
</parameter>
<parameter uniqueid="ps7_gem1_tx_under_runs_tx_under_runs">
<name>tx_under_runs</name>
<desc>Transmit under runs - a 10 bit register counting the
number of frames not transmitted due to a transmit
under run. If this register is incremented then no
other statistics register is incremented.</desc>
<sw_param offset="0xe000c134" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_single_collisn_frames_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c138" start="31" end="18" />
</parameter>
<parameter uniqueid="ps7_gem1_single_collisn_frames_single_collisn">
<name>single_collisn</name>
<desc>Single collision frames - an 18 bit register counting
the number of frames experiencing a single collision
before being successfully transmitted, i.e. no under
run.</desc>
<sw_param offset="0xe000c138" start="17" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_multi_collisn_frames_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c13c" start="31" end="18" />
</parameter>
<parameter uniqueid="ps7_gem1_multi_collisn_frames_multi_collisn">
<name>multi_collisn</name>
<desc>Multiple collision frames - an 18 bit register counting
the number of frames experiencing between two and
fifteen collisions prior to being successfully
transmitted, i.e. no under run and not too many
retries.</desc>
<sw_param offset="0xe000c13c" start="17" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_excessive_collisns_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c140" start="31" end="10" />
</parameter>
<parameter uniqueid="ps7_gem1_excessive_collisns_excessive_collisns">
<name>excessive_collisns</name>
<desc>Excessive collisions - a 10 bit register counting the
number of frames that failed to be transmitted
because they experienced 16 collisions.</desc>
<sw_param offset="0xe000c140" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_late_collisns_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c144" start="31" end="10" />
</parameter>
<parameter uniqueid="ps7_gem1_late_collisns_late_collisns">
<name>late_collisns</name>
<desc>Late collisions - a 10 bit register counting the number
of late collision occurring after the slot time (512 bits)
has expired. In 10/100 mode, late collisions are
counted twice i.e. both as a collision and a late
collision. In gigabit mode, a late collision causes the
transmission to be aborted, thus the single and multi
collision registers are not updated.</desc>
<sw_param offset="0xe000c144" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_deferred_tx_frames_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c148" start="31" end="18" />
</parameter>
<parameter uniqueid="ps7_gem1_deferred_tx_frames_deferred_tx">
<name>deferred_tx</name>
<desc>Deferred transmission frames - an 18 bit register
counting the number of frames experiencing deferral
due to carrier sense being active on their first
attempt at transmission. Frames involved in any
collision are not counted nor are frames that
experienced a transmit under run.</desc>
<sw_param offset="0xe000c148" start="17" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_carrier_sense_errs_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c14c" start="31" end="10" />
</parameter>
<parameter uniqueid="ps7_gem1_carrier_sense_errs_carrier_sense_errs">
<name>carrier_sense_errs</name>
<desc>Carrier sense errors - a 10 bit register counting the
number of frames transmitted where carrier sense
was not seen during transmission or where carrier
sense was deasserted after being asserted in a
transmit frame without collision (no under run). Only
incremented in half duplex mode. The only effect of
a carrier sense error is to increment this register.
The behaviour of the other statistics registers is
unaffected by the detection of a carrier sense error.</desc>
<sw_param offset="0xe000c14c" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_octets_rx_bot_octets_rx_bot">
<name>octets_rx_bot</name>
<desc>Received octets in frame without errors [31:0]. The
number of octets received in valid frames of any
type. This counter is 48-bits and is read through two
registers. This count does not include octets from
pause frames, and is only incremented if the frame is
successfully filtered and copied to memory.</desc>
<sw_param offset="0xe000c150" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_octets_rx_top_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c154" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_octets_rx_top_octets_rx_top">
<name>octets_rx_top</name>
<desc>Received octets in frame without errors [47:32]. The
number of octets received in valid frames of any
type. This counter is 48-bits and is read through two
registers. This count does not include octets from
pause frames, and is only incremented if the frame is
successfully filtered and copied to memory.</desc>
<sw_param offset="0xe000c154" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_frames_rx_a">
<name>a</name>
<desc>Frames received without error. A 32 bit register
counting the number of frames successfully
received. Excludes pause frames, and is only
incremented if the frame is successfully filtered and
copied to memory.</desc>
<sw_param offset="0xe000c158" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_bdcast_fames_rx_a">
<name>a</name>
<desc>Broadcast frames received without error. A 32 bit
register counting the number of broadcast frames
successfully received without error. Excludes pause
frames, and is only incremented if the frame is
successfully filtered and copied to memory.</desc>
<sw_param offset="0xe000c15c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_multi_frames_rx_a">
<name>a</name>
<desc>Multicast frames received without error. A 32 bit
register counting the number of multicast frames
successfully received without error. Excludes pause
frames, and is only incremented if the frame is
successfully filtered and copied to memory.</desc>
<sw_param offset="0xe000c160" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_pause_rx_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c164" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_pause_rx_pause_rx">
<name>pause_rx</name>
<desc>Received pause frames - a 16 bit register counting
the number of pause frames received without error.</desc>
<sw_param offset="0xe000c164" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_frames_64b_rx_a">
<name>a</name>
<desc>64 byte frames received without error. A 32 bit
register counting the number of 64 byte frames
successfully received without error. Excludes pause
frames, and is only incremented if the frame is
successfully filtered and copied to memory.</desc>
<sw_param offset="0xe000c168" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_frames_65to127b_rx_a">
<name>a</name>
<desc>65 to 127 byte frames received without error. A 32 bit
register counting the number of 65 to 127 byte
frames successfully received without error. Excludes
pause frames, and is only incremented if the frame is
successfully filtered and copied to memory.</desc>
<sw_param offset="0xe000c16c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_frames_128to255b_rx_a">
<name>a</name>
<desc>128 to 255 byte frames received without error. A 32
bit register counting the number of 128 to 255 byte
frames successfully received without error. Excludes
pause frames, and is only incremented if the frame is
successfully filtered and copied to memory.</desc>
<sw_param offset="0xe000c170" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_frames_256to511b_rx_a">
<name>a</name>
<desc>256 to 511 byte frames received without error. A 32
bit register counting the number of 256 to 511 byte
frames successfully transmitted without error.
Excludes pause frames, and is only incremented if
the frame is successfully filtered and copied to
memory.</desc>
<sw_param offset="0xe000c174" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_frames_512to1023b_rx_a">
<name>a</name>
<desc>512 to 1023 byte frames received without error. A 32
bit register counting the number of 512 to 1023 byte
frames successfully received without error. Excludes
pause frames, and is only incremented if the frame is
successfully filtered and copied to memory.</desc>
<sw_param offset="0xe000c178" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_frames_1024to1518b_rx_a">
<name>a</name>
<desc>1024 to 1518 byte frames received without error. A
32 bit register counting the number of 1024 to 1518
byte frames successfully received without error.
Excludes pause frames, and is only incremented if
the frame is successfully filtered and copied to
memory.</desc>
<sw_param offset="0xe000c17c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_undersz_rx_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c184" start="31" end="10" />
</parameter>
<parameter uniqueid="ps7_gem1_undersz_rx_undersz_rx">
<name>undersz_rx</name>
<desc>Undersize frames received - a 10 bit register
counting the number of frames received less than 64
bytes in length (10/100 mode or gigabit mode, full
duplex) that do not have either a CRC error or an
alignment error. In gigabit mode, half duplex, this
register counts either frames not conforming to the
minimum slot time of 512 bytes or frames not
conforming to the minimum frame size once bursting
is active.</desc>
<sw_param offset="0xe000c184" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_fcs_errors_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c190" start="31" end="10" />
</parameter>
<parameter uniqueid="ps7_gem1_fcs_errors_fcs_errors">
<name>fcs_errors</name>
<desc>Frame check sequence errors - a 10 bit register
counting frames that are an integral number of
bytes, have bad CRC and are between 64 and 1518
bytes in length. This register is
also incremented if a symbol error is detected and
the frame is of valid length and has an integral
number of bytes.
This register is incremented for a frame with bad
FCS, regardless of whether it is copied to memory
due to ignore FCS mode being enabled in bit 26 of
the network configuration register.H524</desc>
<sw_param offset="0xe000c190" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_length_field_errors_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c194" start="31" end="10" />
</parameter>
<parameter uniqueid="ps7_gem1_length_field_errors_length_field_errors">
<name>length_field_errors</name>
<desc>Length field frame errors - this 10-bit register counts
the number of frames received that have a
measured length shorter than that extracted from the
length field (bytes 13 and 14). This condition is only
counted if the value of the length field is less than
0x0600, the frame is not of excessive length and
checking is enabled through bit 16 of the network
configuration register.</desc>
<sw_param offset="0xe000c194" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_rx_symbol_errors_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c198" start="31" end="10" />
</parameter>
<parameter uniqueid="ps7_gem1_rx_symbol_errors_rx_symbol_errors">
<name>rx_symbol_errors</name>
<desc>Receive symbol errors - a 10-bit register counting
the number of frames that had rx_er asserted
during reception. For 10/100 mode symbol errors
are counted regardless of frame length checks. For
gigabit mode the frame must satisfy slot time
requirements in order to count a symbol error.
Additionally, in gigabit half duplex mode, carrier
extension errors are also recorded. Receive symbol
errors will also be counted as an FCS or alignment
error if the frame is between 64 and 1518 bytes. If the frame is larger it will be
recorded as a jabber error.</desc>
<sw_param offset="0xe000c198" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_align_errors_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c19c" start="31" end="10" />
</parameter>
<parameter uniqueid="ps7_gem1_align_errors_align_errors">
<name>align_errors</name>
<desc>Alignment errors - a 10 bit register counting frames
that are not an integral number of bytes long and
have bad CRC when their length is truncated to an
integral number of bytes and are between 64 and
1518 bytes in length. This register is
also incremented if a symbol error is detected and
the frame is of valid length and does not have an
integral number of bytes.</desc>
<sw_param offset="0xe000c19c" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_rx_resource_errors_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c1a0" start="31" end="18" />
</parameter>
<parameter uniqueid="ps7_gem1_rx_resource_errors_rx_resource_errors">
<name>rx_resource_errors</name>
<desc>Receive resource errors - an 18 bit register counting
the number of frames that were successfully
received by the MAC (correct address matched
frame and adequate slot time) but could not be
copied to memory because no receive buffer was
available. This will be either because the AHB bus
was not granted in time or because a hresp not OK
was returned.</desc>
<sw_param offset="0xe000c1a0" start="17" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_rx_overrun_errors_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c1a4" start="31" end="10" />
</parameter>
<parameter uniqueid="ps7_gem1_rx_overrun_errors_rx_overrun_errors">
<name>rx_overrun_errors</name>
<desc>Receive overruns - a 10 bit register counting the
number of frames that are address recognized but
were not copied to memory due to a receive overrun.</desc>
<sw_param offset="0xe000c1a4" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_ip_hdr_csum_errors_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c1a8" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_gem1_ip_hdr_csum_errors_ip_hdr_csum_errors">
<name>ip_hdr_csum_errors</name>
<desc>0 IP header checksum errors - an 8-bit register
counting the number of frames discarded due to an
incorrect IP header checksum, but are between 64
and 1518 bytes and do not
have a CRC error, an alignment error, nor a symbol
error.</desc>
<sw_param offset="0xe000c1a8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_tcp_csum_errors_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c1ac" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_gem1_tcp_csum_errors_tcp_csum_errors">
<name>tcp_csum_errors</name>
<desc>TCP checksum errors - an 8-bit register counting the
number of frames discarded due to an incorrect TCP
checksum, but are between 64 and 1518 bytes and do not have a CRC error,
an alignment error, nor a symbol error.</desc>
<sw_param offset="0xe000c1ac" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_udp_csum_errors_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c1b0" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_gem1_udp_csum_errors_udp_csum_errors">
<name>udp_csum_errors</name>
<desc>UDP checksum errors - an 8-bit register counting the
number of frames discarded due to an incorrect UDP
checksum, but are between 64 and 1518 bytes and do not have a CRC error,
an alignment error, nor a symbol error.</desc>
<sw_param offset="0xe000c1b0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_timer_strobe_s_a">
<name>a</name>
<desc>The value of the Timer Seconds register captured
when gem_tsu_ms and gem_tsu_inc_ctrl are zero</desc>
<sw_param offset="0xe000c1c8" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_timer_strobe_ns_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c1cc" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_gem1_timer_strobe_ns_ns_reg_val">
<name>ns_reg_val</name>
<desc>The value of the Timer Nanoseconds register
captured when gem_tsu_ms and gem_tsu_inc_ctrl
are zero.</desc>
<sw_param offset="0xe000c1cc" start="29" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_timer_s_a">
<name>a</name>
<desc>Timer count in seconds. This register is writeable. It
increments by one when the 1588 nanoseconds
counter counts to one second. It may also be
incremented when the timer adjust register is
written.</desc>
<sw_param offset="0xe000c1d0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_timer_ns_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c1d4" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_gem1_timer_ns_timer_ct_ns">
<name>timer_ct_ns</name>
<desc>Timer count in nanoseconds. This register is
writeable. It can also be adjusted by writes to the
1588 timer adjust register. It increments by the value
of the 1588 timer increment register each clock
cycle.</desc>
<sw_param offset="0xe000c1d4" start="29" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_timer_adjust_add_subn">
<name>add_subn</name>
<desc>Write as one to subtract from the 1588 timer. Write
as zero to add to it.</desc>
<sw_param offset="0xe000c1d8" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_gem1_timer_adjust_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c1d8" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_gem1_timer_adjust_ns_delta">
<name>ns_delta</name>
<desc>The number of nanoseconds to increment or
decrement the 1588 timer nanoseconds register. If
necessary the 1588 seconds register will be
incremented or decremented.</desc>
<sw_param offset="0xe000c1d8" start="29" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_timer_incr_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c1dc" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_gem1_timer_incr_incr_b4_alt">
<name>incr_b4_alt</name>
<desc>The number of increments after which the alternative
increment is used</desc>
<sw_param offset="0xe000c1dc" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_timer_incr_alt_ct_ns_delta">
<name>alt_ct_ns_delta</name>
<desc>Alternative count of nanoseconds by which the 1588
timer nanoseconds register will be incremented
each clock cycle.</desc>
<sw_param offset="0xe000c1dc" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_gem1_timer_incr_ns_delta">
<name>ns_delta</name>
<desc>A count of nanoseconds by which the 1588 timer
nanoseconds register will be incremented each
clock cycle.</desc>
<sw_param offset="0xe000c1dc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_ptp_tx_s_a">
<name>a</name>
<desc>The register is updated with the value that the 1588
timer seconds register held when the SFD of a PTP
transmit primary event crosses the MII interface. The
actual update occurs when the GEM recognizes the
frame as a PTP sync or delay_req frame. An
interrupt is issued when the register is updated.</desc>
<sw_param offset="0xe000c1e0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_ptp_tx_ns_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c1e4" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_gem1_ptp_tx_ns_ns_reg_val">
<name>ns_reg_val</name>
<desc>The register is updated with the value that the 1588
timer nanoseconds register held when the SFD of a
PTP transmit primary event crosses the MII
interface. The actual update occurs when the GEM
recognizes the frame as a PTP sync or delay_req
frame. An interrupt is issued when the register is
updated.</desc>
<sw_param offset="0xe000c1e4" start="29" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_ptp_rx_s_a">
<name>a</name>
<desc>The register is updated with the value that the 1588
timer seconds register held when the SFD of a PTP
receive primary event crosses the MII interface. The
actual update occurs when the GEM recognizes the
frame as a PTP sync or delay_req frame. An
interrupt is issued when the register is updated.</desc>
<sw_param offset="0xe000c1e8" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_ptp_rx_ns_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c1ec" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_gem1_ptp_rx_ns_ns_reg_val">
<name>ns_reg_val</name>
<desc>The register is updated with the value that the 1588
timer nanoseconds register held when the SFD of a
PTP receive primary event crosses the MII interface.
The actual update occurs when the GEM recognizes
the frame as a PTP sync or delay_req frame. An
interrupt is issued when the register is updated.</desc>
<sw_param offset="0xe000c1ec" start="29" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_ptp_peer_tx_s_a">
<name>a</name>
<desc>The register is updated with the value that the 1588
timer seconds register held when the SFD of a PTP
transmit peer event crosses the MII interface. The
actual update occurs when the GEM recognizes the
frame as a PTP pdealy_req or pdelay_resp frame.
An interrupt is issued when the register is updated.</desc>
<sw_param offset="0xe000c1f0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_ptp_peer_tx_ns_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c1f4" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_gem1_ptp_peer_tx_ns_ns_reg_val">
<name>ns_reg_val</name>
<desc>The register is updated with the value that the 1588
timer nanoseconds register held when the SFD of a
PTP transmit peer event crosses the MII interface.
The actual update occurs when the GEM recognizes
the frame as a PTP pdelay_req or pdelay_resp
frame. An interrupt is issued when the register is
updated.</desc>
<sw_param offset="0xe000c1f4" start="29" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_ptp_peer_rx_s_a">
<name>a</name>
<desc>The register is updated with the value that the 1588
timer seconds register held when the SFD of a PTP
receive peer event crosses the MII interface. The
actual update occurs when the GEM recognizes the
frame as a PTP pdelay_req or pdelay_resp frame.
An interrupt is issued when the register is updated.</desc>
<sw_param offset="0xe000c1f8" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_ptp_peer_rx_ns_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000c1fc" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_gem1_ptp_peer_rx_ns_ns_reg_val">
<name>ns_reg_val</name>
<desc>The register is updated with the value that the 1588
timer nanoseconds register held when the SFD of a
PTP receive peer event crosses the MII interface.
The actual update occurs when the GEM recognizes
the frame as a PTP pdelay_req or pdelay_resp
frame. An interrupt is issued when the register is
updated.</desc>
<sw_param offset="0xe000c1fc" start="29" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg1_reserved">
<name>reserved</name>
<desc>Reserved. Set to 0</desc>
<sw_param offset="0xe000c280" start="31" end="28" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg1_gem_dma_bus_width">
<name>gem_dma_bus_width</name>
<desc>Takes the value of the `gem_dma_bus_width DEFINE
3'b001 : 32-bit
3'b010 : 64-bit
3'b100 : 128-bit</desc>
<sw_param offset="0xe000c280" start="27" end="25" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg1_extra_spec_add">
<name>extra_spec_add</name>
<desc>Takes the value of the `extra_spec_add DEFINE. Undefined in Pele</desc>
<sw_param offset="0xe000c280" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg1_gem_irq_read_clear">
<name>gem_irq_read_clear</name>
<desc>Takes the value of the `gem_irq_read_clear DEFINE. Undefined in Pele. Keeping undefined means interrupt status registers are write-one-to-clear rather than clearing when read.</desc>
<sw_param offset="0xe000c280" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg1_gem_no_snapshot">
<name>gem_no_snapshot</name>
<desc>Takes the value of the `gem_no_snapshot DEFINE. Defined for Pele. Remove statistics snapshot
(not supported by driver)</desc>
<sw_param offset="0xe000c280" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg1_gem_no_stats">
<name>gem_no_stats</name>
<desc>Takes the value of the `gem_no_stats DEFINE. Undefined for Pele.
Include statistics registers.</desc>
<sw_param offset="0xe000c280" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg1_gem_no_scan_pins">
<name>gem_no_scan_pins</name>
<desc>Takes the value of the `gem_no_scan_pins DEFINE. Defined for Pele. Remove placeholder scan pins from module.</desc>
<sw_param offset="0xe000c280" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg1_gem_user_in_width">
<name>gem_user_in_width</name>
<desc>Takes the value of the `gem_user_in_width DEFINE. Undefined for Pele. No requirement for user I/O.</desc>
<sw_param offset="0xe000c280" start="19" end="15" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg1_gem_user_out_width">
<name>gem_user_out_width</name>
<desc>Takes the value of the `gem_user_out_width DEFINE. Undefined for Pele. No requirement for user I/O.</desc>
<sw_param offset="0xe000c280" start="14" end="10" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg1_gem_user_io">
<name>gem_user_io</name>
<desc>Takes the value of the `gem_user_io DEFINE. Undefined for Pele. No requirement for user I/O.</desc>
<sw_param offset="0xe000c280" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg1_gem_apb_rev2">
<name>gem_apb_rev2</name>
<desc>Takes the value of the `gem_apb_rev2 DEFINE. Defined for Pele. Use AMBA 2.0 APB.</desc>
<sw_param offset="0xe000c280" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg1_gem_apb_rev1">
<name>gem_apb_rev1</name>
<desc>Takes the value of the `gem_apb_rev1 DEFINE. Undefined for Pele. Use AMBA 2.0 APB.</desc>
<sw_param offset="0xe000c280" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg1_gem_ext_fifo_interface">
<name>gem_ext_fifo_interface</name>
<desc>Takes the value of the `gem_ext_fifo_interface. Undefined for Pele. Use AHB DMA; External FIFO interface not implemented.</desc>
<sw_param offset="0xe000c280" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg1_gem_no_int_loopback">
<name>gem_no_int_loopback</name>
<desc>Takes the value of the `gem_no_int_loopback DEFINE. Undefined for Pele. Include loopback test mode</desc>
<sw_param offset="0xe000c280" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg1_gem_int_loopback">
<name>gem_int_loopback</name>
<desc>Takes the value of the `gem_int_loopback DEFINE. Defined for Pele. Include loopback test mode.</desc>
<sw_param offset="0xe000c280" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg1_TDC_50">
<name>TDC_50</name>
<desc>Takes the value of the `TDC_50 DEFINE. Undefined for Pele. Only used with PCS.</desc>
<sw_param offset="0xe000c280" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg1_RDC_50">
<name>RDC_50</name>
<desc>Takes the value of the `RDC_50 DEFINE. Undefined for Pele. Only used with PCS.</desc>
<sw_param offset="0xe000c280" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg1_gem_serdes">
<name>gem_serdes</name>
<desc>Takes the value of the `gem_serdes DEFINE. Undefined for Pele. Only used with PCS.</desc>
<sw_param offset="0xe000c280" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg1_gem_no_pcs">
<name>gem_no_pcs</name>
<desc>Takes the value of the `gem_no_pcs DEFINE. Defined for Pele. Use GEM without 1000-BASE-X PCS sublayer and Ten Bit Interface</desc>
<sw_param offset="0xe000c280" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg2_reserved">
<name>reserved</name>
<desc>Reserved. Set to zero.</desc>
<sw_param offset="0xe000c284" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg2_gem_tx_pbuf_addr">
<name>gem_tx_pbuf_addr</name>
<desc>Takes the value of the `gem_tx_pbuf_addr DEFINE. Max address bits for Tx packet buffer (10-bits for maximum 4 kB buffer)
Buffer size for Tx packet buffer mode will be 4kB.
This will allow one standard packet to be received while another is transferred to system memory by the DMA interface.</desc>
<sw_param offset="0xe000c284" start="29" end="26" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg2_gem_rx_pbuf_addr">
<name>gem_rx_pbuf_addr</name>
<desc>Takes the value of the `gem_rx_pbuf_addr DEFINE. Max address bits for Rx packet buffer (10-bits for maximum 4 kB buffer)
Buffer size for Rx packet buffer mode will be 4kB.
This will allow one standard packet to be received while another is transferred to system memory by the DMA interface.</desc>
<sw_param offset="0xe000c284" start="25" end="22" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg2_gem_tx_pkt_buffer">
<name>gem_tx_pkt_buffer</name>
<desc>Takes the value of the `gem_tx_pkt_buffer DEFINE. Defined for Pele. Includes the transmitter packet buffer</desc>
<sw_param offset="0xe000c284" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg2_gem_rx_pkt_buffer">
<name>gem_rx_pkt_buffer</name>
<desc>Takes the value of the `gem_rx_pkt_buffer DEFINE. Defined for Pele. Includes the receiver packet buffer</desc>
<sw_param offset="0xe000c284" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg2_gem_hprot_value">
<name>gem_hprot_value</name>
<desc>Takes the value of the `gem_hprot_value DEFINE. For Pele set the fixed AHB HPROT value used during transfers</desc>
<sw_param offset="0xe000c284" start="19" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg2_gem_jumbo_max_length">
<name>gem_jumbo_max_length</name>
<desc>Takes the value of the `gem_jumbo_max_length DEFINE. Maximum length of jumbo frames accepted by receiver.
This is set to the size of the smallest of the two packet buffer, minus a margin for packet headers. However, Pele will not support jumbo frames.</desc>
<sw_param offset="0xe000c284" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg3_gem_rx_base2_fifo_size">
<name>gem_rx_base2_fifo_size</name>
<desc>Takes the value of the `gem_rx_base2_fifo_size DEFINE. Base-2 equivalent of `gem_rx_fifo_size</desc>
<sw_param offset="0xe000c288" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg3_gem_rx_fifo_size">
<name>gem_rx_fifo_size</name>
<desc>Takes the value of the `gem_rx_fifo_size DEFINE. Set the size of the small Rx FIFO for grant latency. Extended to 16 deep to allow buffering of 64 byte maximum AHB burst size in Pele.</desc>
<sw_param offset="0xe000c288" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg4_gem_tx_base2_fifo_size">
<name>gem_tx_base2_fifo_size</name>
<desc>Takes the value of the `gem_tx_base2_fifo_size DEFINE. Base-2 equivalent of `gem_tx_fifo_size</desc>
<sw_param offset="0xe000c28c" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg4_gem_tx_fifo_size">
<name>gem_tx_fifo_size</name>
<desc>Takes the value of the `gem_tx_fifo_size DEFINE. Set the size of the small TX FIFO for grant latency</desc>
<sw_param offset="0xe000c28c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg5_reserved">
<name>reserved</name>
<desc>Reserved. Set to zero.</desc>
<sw_param offset="0xe000c290" start="31" end="29" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg5_gem_tsu_clk">
<name>gem_tsu_clk</name>
<desc>Takes the value of the `gem_tsu_clk DEFINE. Undefined in Pele. 1588 Time Stamp Unit clock sourced from pclk rather than independent tsu_clk.</desc>
<sw_param offset="0xe000c290" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg5_gem_rx_buffer_length_def">
<name>gem_rx_buffer_length_def</name>
<desc>Takes the value of the `gem_rx_buffer_length_def DEFINE. Set the default buffer length used by Rx DMA to 128 bytes in Pele</desc>
<sw_param offset="0xe000c290" start="27" end="20" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg5_gem_tx_pbuf_size_def">
<name>gem_tx_pbuf_size_def</name>
<desc>Takes the value of the `gem_tx_pbuf_size_def DEFINE. Full 4 kB Tx packet buffer size - dedicated memory resource in Pele.</desc>
<sw_param offset="0xe000c290" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg5_gem_rx_pbuf_size_def">
<name>gem_rx_pbuf_size_def</name>
<desc>Takes the value of the `gem_rx_pbuf_size_def DEFINE. Full
4 kB Rx packet buffer size - dedicated memory resource in Pele.</desc>
<sw_param offset="0xe000c290" start="18" end="17" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg5_gem_endian_swap_def">
<name>gem_endian_swap_def</name>
<desc>Takes the value of the `gem_endian_swap_def DEFINE. Set to big endian data, little endian management descriptors in Pele.</desc>
<sw_param offset="0xe000c290" start="16" end="15" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg5_gem_mdc_clock_div">
<name>gem_mdc_clock_div</name>
<desc>Takes the value of the `gem_mdc_clock_div DEFINE. Set default MDC clock divisor (can still be programmed) in Pele.</desc>
<sw_param offset="0xe000c290" start="14" end="12" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg5_gem_dma_bus_width">
<name>gem_dma_bus_width</name>
<desc>Takes the value of the `gem_dma_bus_width_def DEFINE. Limit to 32-bit AHB bus in Pele</desc>
<sw_param offset="0xe000c290" start="11" end="10" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg5_gem_phy_ident">
<name>gem_phy_ident</name>
<desc>Takes the value of the `gem_phy_ident DEFINE. Undefined in Pele. Only used in PCS.</desc>
<sw_param offset="0xe000c290" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg5_gem_tsu">
<name>gem_tsu</name>
<desc>Takes the value of the `gem_tsu DEFINE. Defined in Pele. Include support for 1588 Time Stamp Unit</desc>
<sw_param offset="0xe000c290" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg5_gem_tx_fifo_cnt_width">
<name>gem_tx_fifo_cnt_width</name>
<desc>Takes the value of the `gem_tx_fifo_cnt_width DEFINE. Width for `gem_tx_fifo_size</desc>
<sw_param offset="0xe000c290" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg5_gem_rx_fifo_cnt_width">
<name>gem_rx_fifo_cnt_width</name>
<desc>Takes the value of the `gem_rx_fifo_cnt_width DEFINE. Width for `gem_rx_fifo_size.</desc>
<sw_param offset="0xe000c290" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg6_reserved">
<name>reserved</name>
<desc>Reserved. Set to zero.</desc>
<sw_param offset="0xe000c294" start="31" end="12" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg6_gem_tx_pbufq_seg_sz">
<name>gem_tx_pbufq_seg_sz</name>
<desc>Takes the value of the `gem_tx_pbuf_queue_segment_size DEFINE. Uses default GEM value in Pele. Ignored, no priority dma.</desc>
<sw_param offset="0xe000c294" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg6_dma_priority_queue7">
<name>dma_priority_queue7</name>
<desc>Takes the value of the `dma_priority_queue7 DEFINE. Undefined. No priority DMA In Pele.</desc>
<sw_param offset="0xe000c294" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg6_dma_priority_queue6">
<name>dma_priority_queue6</name>
<desc>Takes the value of the `dma_priority_queue6 DEFINE. Undefined. No priority DMA In Pele.</desc>
<sw_param offset="0xe000c294" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg6_dma_priority_queue5">
<name>dma_priority_queue5</name>
<desc>Takes the value of the `dma_priority_queue5 DEFINE. Undefined. No priority DMA In Pele.</desc>
<sw_param offset="0xe000c294" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg6_dma_priority_queue4">
<name>dma_priority_queue4</name>
<desc>Takes the value of the `dma_priority_queue4 DEFINE. Undefined. No priority DMA In Pele.</desc>
<sw_param offset="0xe000c294" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg6_dma_priority_queue3">
<name>dma_priority_queue3</name>
<desc>Takes the value of the `dma_priority_queue3 DEFINE. Undefined. No priority DMA In Pele.</desc>
<sw_param offset="0xe000c294" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg6_dma_priority_queue2">
<name>dma_priority_queue2</name>
<desc>Takes the value of the `dma_priority_queue2 DEFINE. Undefined. No priority DMA In Pele.</desc>
<sw_param offset="0xe000c294" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg6_dma_priority_queue1">
<name>dma_priority_queue1</name>
<desc>Takes the value of the `dma_priority_queue1 DEFINE. Undefined. No priority DMA In Pele.</desc>
<sw_param offset="0xe000c294" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg6_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Set to zero.</desc>
<sw_param offset="0xe000c294" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg7_tx_pbuf_numseg_q7">
<name>tx_pbuf_numseg_q7</name>
<desc>Takes the value of the `gem_tx_pbuf_num_segments_q7 DEFINE. Undefined. No priority DMA In Pele.</desc>
<sw_param offset="0xe000c298" start="31" end="28" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg7_tx_pbuf_numseg_q6">
<name>tx_pbuf_numseg_q6</name>
<desc>Takes the value of the `gem_tx_pbuf_num_segments_q6 DEFINE. Undefined. No priority DMA In Pele.</desc>
<sw_param offset="0xe000c298" start="27" end="24" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg7_tx_pbuf_numseg_q5">
<name>tx_pbuf_numseg_q5</name>
<desc>Takes the value of the `gem_tx_pbuf_num_segments_q5 DEFINE. Undefined. No priority DMA In Pele.</desc>
<sw_param offset="0xe000c298" start="23" end="20" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg7_tx_pbuf_numseg_q4">
<name>tx_pbuf_numseg_q4</name>
<desc>Takes the value of the `gem_tx_pbuf_num_segments_q4 DEFINE. Undefined. No priority DMA In Pele.</desc>
<sw_param offset="0xe000c298" start="19" end="16" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg7_tx_pbuf_numseg_q3">
<name>tx_pbuf_numseg_q3</name>
<desc>Takes the value of the `gem_tx_pbuf_num_segments_q3 DEFINE. Undefined. No priority DMA In Pele.</desc>
<sw_param offset="0xe000c298" start="15" end="12" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg7_tx_pbuf_numseg_q2">
<name>tx_pbuf_numseg_q2</name>
<desc>Takes the value of the `gem_tx_pbuf_num_segments_q2 DEFINE. Undefined. No priority DMA In Pele.</desc>
<sw_param offset="0xe000c298" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg7_tx_pbuf_numseg_q1">
<name>tx_pbuf_numseg_q1</name>
<desc>Takes the value of the `gem_tx_pbuf_num_segments_q1 DEFINE. Undefined. No priority DMA In Pele.</desc>
<sw_param offset="0xe000c298" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_gem1_design_cfg7_tx_pbuf_numseg_q0">
<name>tx_pbuf_numseg_q0</name>
<desc>Takes the value of the `gem_tx_pbuf_num_segments_q0 DEFINE. Undefined. No priority DMA In Pele.</desc>
<sw_param offset="0xe000c298" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_net_ctrl_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe000b000" start="31" end="19" />
</parameter>
<parameter uniqueid="ps7_gem0_net_ctrl_flush_next_rx_dpram_pkt">
<name>flush_next_rx_dpram_pkt</name>
<desc>Flush the next packet from the external RX DPRAM.
Writing one to this bit will only have an effect if the DMA is not currently writing a packet already stored in the DPRAM to memory.</desc>
<sw_param offset="0xe000b000" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_gem0_net_ctrl_tx_pfc_pri_pri_pause_frame">
<name>tx_pfc_pri_pri_pause_frame</name>
<desc>Transmit PFC Priority Based Pause Frame. Takes the values stored in the Transmit PFC Pause Register</desc>
<sw_param offset="0xe000b000" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_gem0_net_ctrl_en_pfc_pri_pause_rx">
<name>en_pfc_pri_pause_rx</name>
<desc>Enable PFC Priority Based Pause Reception capabilities.
Setting this bit will enable PFC negotiation and recognition of priority based pause frames.</desc>
<sw_param offset="0xe000b000" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_net_ctrl_str_rx_timestamp">
<name>str_rx_timestamp</name>
<desc>Store receive time stamp to memory. Setting this bit to one will cause the CRC of every received frame to be replaced with the value of the nanoseconds field of the 1588 timer that was captured as the receive frame passed the message time stamp point. Set to zero for normal operation.</desc>
<sw_param offset="0xe000b000" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_gem0_net_ctrl_reserved_rd_snapshot">
<name>reserved_rd_snapshot</name>
<desc>Reserved. Do not modify.</desc>
<sw_param offset="0xe000b000" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_gem0_net_ctrl_reserved_take_snapshot">
<name>reserved_take_snapshot</name>
<desc>Reserved. Do not modify.</desc>
<sw_param offset="0xe000b000" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_gem0_net_ctrl_tx_zeroq_pause_frame">
<name>tx_zeroq_pause_frame</name>
<desc>Transmit zero quantum pause frame - writing one to this bit causes a pause frame with zero quantum to be transmitted.</desc>
<sw_param offset="0xe000b000" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_gem0_net_ctrl_tx_pause_frame">
<name>tx_pause_frame</name>
<desc>Transmit pause frame - writing one to this bit causes a pause frame to be transmitted.</desc>
<sw_param offset="0xe000b000" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_gem0_net_ctrl_tx_halt">
<name>tx_halt</name>
<desc>Transmit halt - writing one to this bit halts transmission as soon as any ongoing frame transmission ends.</desc>
<sw_param offset="0xe000b000" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_gem0_net_ctrl_start_tx">
<name>start_tx</name>
<desc>Start transmission - writing one to this bit starts transmission.</desc>
<sw_param offset="0xe000b000" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_gem0_net_ctrl_back_pressure">
<name>back_pressure</name>
<desc>Back pressure - if set in 10M or 100M half duplex mode will force collisions on all received frames.
Ignored in gigabit half duplex mode.</desc>
<sw_param offset="0xe000b000" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_gem0_net_ctrl_wren_stat_regs">
<name>wren_stat_regs</name>
<desc>Write enable for statistics registers - setting this bit to one means the statistics registers can be written for functional test purposes.</desc>
<sw_param offset="0xe000b000" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_gem0_net_ctrl_incr_stat_regs">
<name>incr_stat_regs</name>
<desc>Incremental statistics registers - this bit is write only.
Writing a one increments all the statistics registers by one for test purposes.</desc>
<sw_param offset="0xe000b000" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_gem0_net_ctrl_clear_stat_regs">
<name>clear_stat_regs</name>
<desc>Clear statistics registers - this bit is write only.
Writing a one clears the statistics registers.</desc>
<sw_param offset="0xe000b000" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_gem0_net_ctrl_mgmt_port_en">
<name>mgmt_port_en</name>
<desc>Management port enable - set to one to enable the management port. When zero forces mdio to high impedance state and mdc low.</desc>
<sw_param offset="0xe000b000" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_gem0_net_ctrl_tx_en">
<name>tx_en</name>
<desc>Transmit enable - when set, it enables the GEM transmitter to send data. When reset transmission will stop immediately, the transmit pipeline and control registers will be cleared and the transmit queue pointer register will reset to point to the start of the transmit descriptor list.</desc>
<sw_param offset="0xe000b000" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_gem0_net_ctrl_rx_en">
<name>rx_en</name>
<desc>Receive enable - when set, it enables the GEM to receive data. When reset frame reception will stop immediately and the receive pipeline will be cleared.
The receive queue pointer register is unaffected.</desc>
<sw_param offset="0xe000b000" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_gem0_net_ctrl_loopback_local">
<name>loopback_local</name>
<desc>Loop back local - asserts the loopback_local signal to the system clock generator. Also connects txd to rxd, tx_en to rx_dv and forces full duplex mode. Bit 11 of the network configuration register must be set low to disable TBI mode when in internal loopback. rx_clk and tx_clk may malfunction as the GEM is switched into and out of internal loop back. It is important that receive and transmit circuits have already been disabled when making the switch into and out of internal loop back. Local loopback functionality isn't available in the EP107 Pele Emulation Platform, because the clocking doesn't map well into an FPGA.</desc>
<sw_param offset="0xe000b000" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_gem0_net_ctrl_reserved_loopback">
<name>reserved_loopback</name>
<desc>Reserved. Do not modify.</desc>
<sw_param offset="0xe000b000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_net_cfg_unidir_en">
<name>unidir_en</name>
<desc>Uni-direction-enable. When low the PCS will transmit idle symbols if the link goes down. When high the PCS can transmit frame data when the link is down.</desc>
<sw_param offset="0xe000b004" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_gem0_net_cfg_ignore_ipg_rx_er">
<name>ignore_ipg_rx_er</name>
<desc>Ignore IPG rx_er. When set rx_er has no effect on the GEM's operation when rx_dv is low. Set this when using the RGMII wrapper in half-duplex mode.</desc>
<sw_param offset="0xe000b004" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_gem0_net_cfg_rx_bad_preamble">
<name>rx_bad_preamble</name>
<desc>Receive bad preamble. When set frames with non-standard preamble are not rejected.</desc>
<sw_param offset="0xe000b004" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_gem0_net_cfg_ipg_stretch_en">
<name>ipg_stretch_en</name>
<desc>IPG stretch enable - when set the transmit IPG can be increased above 96 bit times depending on the previous frame length using the IPG stretch register.</desc>
<sw_param offset="0xe000b004" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_gem0_net_cfg_sgmii_en">
<name>sgmii_en</name>
<desc>SGMII mode enable - changes behaviour of the auto-negotiation advertisement and link partner ability registers to meet the requirements of SGMII and reduces the duration of the link timer from 10 ms to 1.6 ms</desc>
<sw_param offset="0xe000b004" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_gem0_net_cfg_ignore_rx_fcs">
<name>ignore_rx_fcs</name>
<desc>Ignore RX FCS - when set frames with FCS/CRC errors will not be rejected. FCS error statistics will still be collected for frames with bad FCS and FCS status will be recorded in frame's DMA descriptor.
For normal operation this bit must be set to zero.</desc>
<sw_param offset="0xe000b004" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_gem0_net_cfg_rx_hd_while_tx">
<name>rx_hd_while_tx</name>
<desc>Enable frames to be received in half-duplex mode while transmitting.</desc>
<sw_param offset="0xe000b004" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_gem0_net_cfg_rx_chksum_offld_en">
<name>rx_chksum_offld_en</name>
<desc>Receive checksum offload enable - when set, the receive checksum engine is enabled. Frames with bad IP, TCP or UDP checksums are discarded.</desc>
<sw_param offset="0xe000b004" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_gem0_net_cfg_dis_cp_pause_frame">
<name>dis_cp_pause_frame</name>
<desc>Disable copy of pause frames - set to one to prevent valid pause frames being copied to memory. When set, pause frames are not copied to memory regardless of the state of the copy all frames bit; whether a hash match is found or whether a type ID match is identified. If a destination address match is found the pause frame will be copied to memory.
Note that valid pause frames received will still increment pause statistics and pause the transmission of frames as required.</desc>
<sw_param offset="0xe000b004" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_gem0_net_cfg_dbus_width">
<name>dbus_width</name>
<desc>Data bus width - set according to AMBA AHB or external FIFO data bus width. The reset value for this can be changed by defining a new value for gem_dma_bus_width_def in gem_defs.v Only valid bus widths may be written if the system is configured to a maximum width less than 128-bits. Pele defines gem_dma_bus_width_def as 2'b00.
00: 32 bit AMBA AHB data bus width
01: 64 bit AMBA AHB data bus width
10: 128 bit AMBA AHB data bus width
11: 128 bit AMBA AHB data bus width</desc>
<sw_param offset="0xe000b004" start="22" end="21" />
</parameter>
<parameter uniqueid="ps7_gem0_net_cfg_mdc_clk_div">
<name>mdc_clk_div</name>
<desc>MDC clock division - set according to pclk speed.
These three bits determine the number pclk will be divided by to generate MDC. For conformance with the 802.3 specification, MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and write operations). The reset value for this can be changed by defining a new value for gem_mdc_clock_div in gem_defs.v. Pele defines gem_mdc_clock_div as 3'b010.
000: divide pclk by 8 (pclk up to 20 MHz)
001: divide pclk by 16 (pclk up to 40 MHz)
010: divide pclk by 32 (pclk up to 80 MHz)
011: divide pclk by 48 (pclk up to 120MHz)
100: divide pclk by 64 (pclk up to 160 MHz)
101: divide pclk by 96 (pclk up to 240 MHz)
110: divide pclk by 128 (pclk up to 320 MHz)
111: divide pclk by 224 (pclk up to 540 MHz)</desc>
<sw_param offset="0xe000b004" start="20" end="18" />
</parameter>
<parameter uniqueid="ps7_gem0_net_cfg_fcs_remove">
<name>fcs_remove</name>
<desc>FCS remove - setting this bit will cause received frames to be written to memory without their frame check sequence (last 4 bytes). The frame length indicated will be reduced by four bytes in this mode.</desc>
<sw_param offset="0xe000b004" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_gem0_net_cfg_len_err_frame_disc">
<name>len_err_frame_disc</name>
<desc>Length field error frame discard - setting this bit causes frames with a measured length shorter than the extracted length field (as indicated by bytes 13 and 14 in a non-VLAN tagged frame) to be discarded. This only applies to frames with a length field less than 0x0600.</desc>
<sw_param offset="0xe000b004" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_net_cfg_rx_buf_offset">
<name>rx_buf_offset</name>
<desc>Receive buffer offset - indicates the number of bytes by which the received data is offset from the start of the receive buffer.</desc>
<sw_param offset="0xe000b004" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_gem0_net_cfg_pause_en">
<name>pause_en</name>
<desc>Pause enable - when set, transmission will pause if a non zero 802.3 classic pause frame is received and PFC has not been negotiated.</desc>
<sw_param offset="0xe000b004" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_gem0_net_cfg_retry_test">
<name>retry_test</name>
<desc>Retry test - must be set to zero for normal operation.
If set to one the backoff between collisions will always be one slot time. Setting this bit to one helps test the too many retries condition. Also used in the pause frame tests to reduce the pause counter's decrement time from 512 bit times, to every rx_clk cycle.</desc>
<sw_param offset="0xe000b004" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_gem0_net_cfg_pcs_sel">
<name>pcs_sel</name>
<desc>PCS select - selects between MII/GMII and TBI.
Must be set for SGMII operation.
0: GMII/MII interface enabled, TBI disabled
1: TBI enabled, GMII/MII disabled</desc>
<sw_param offset="0xe000b004" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_gem0_net_cfg_gige_en">
<name>gige_en</name>
<desc>Gigabit mode enable - setting this bit configures the GEM for 1000 Mbps operation.
0: 10/100 operation using MII or TBI interface
1: Gigabit operation using GMII or TBI interface</desc>
<sw_param offset="0xe000b004" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_gem0_net_cfg_ext_addr_match_en">
<name>ext_addr_match_en</name>
<desc>External address match enable - when set the external address match interface can be used to copy frames to memory.</desc>
<sw_param offset="0xe000b004" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_gem0_net_cfg_reserved_rx_1536_byte_frames">
<name>reserved_rx_1536_byte_frames</name>
<desc>Reserved. Do not modify.</desc>
<sw_param offset="0xe000b004" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_gem0_net_cfg_uni_hash_en">
<name>uni_hash_en</name>
<desc>Unicast hash enable - when set, unicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register.</desc>
<sw_param offset="0xe000b004" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_gem0_net_cfg_multi_hash_en">
<name>multi_hash_en</name>
<desc>Multicast hash enable - when set, multicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register.</desc>
<sw_param offset="0xe000b004" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_gem0_net_cfg_no_broadcast">
<name>no_broadcast</name>
<desc>No broadcast - when set to logic one, frames addressed to the broadcast address of all ones will not be accepted.</desc>
<sw_param offset="0xe000b004" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_gem0_net_cfg_copy_all">
<name>copy_all</name>
<desc>Copy all frames - when set to logic one, all valid frames will be accepted.</desc>
<sw_param offset="0xe000b004" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_gem0_net_cfg_reserved_jumbo_en">
<name>reserved_jumbo_en</name>
<desc>Reserved. Do not modify.</desc>
<sw_param offset="0xe000b004" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_gem0_net_cfg_disc_non_vlan">
<name>disc_non_vlan</name>
<desc>Discard non-VLAN frames - when set only VLAN tagged frames will be passed to the address matching logic.</desc>
<sw_param offset="0xe000b004" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_gem0_net_cfg_full_duplex">
<name>full_duplex</name>
<desc>Full duplex - if set to logic one, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting. Also controls the half_duplex pin.</desc>
<sw_param offset="0xe000b004" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_gem0_net_cfg_speed">
<name>speed</name>
<desc>Speed - set to logic one to indicate 100Mbps operation, logic zero for 10Mbps. The value of this pin is reflected on the speed_mode[0] output pin.</desc>
<sw_param offset="0xe000b004" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_net_status_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write</desc>
<sw_param offset="0xe000b008" start="31" end="7" />
</parameter>
<parameter uniqueid="ps7_gem0_net_status_pfc_pri_pause_neg">
<name>pfc_pri_pause_neg</name>
<desc>Set when PFC Priority Based Pause has been negotiated.</desc>
<sw_param offset="0xe000b008" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_gem0_net_status_pcs_autoneg_pause_tx_res">
<name>pcs_autoneg_pause_tx_res</name>
<desc>PCS auto-negotiation pause transmit resolution.</desc>
<sw_param offset="0xe000b008" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_gem0_net_status_pcs_autoneg_pause_rx_res">
<name>pcs_autoneg_pause_rx_res</name>
<desc>PCS auto-negotiation pause receive resolution</desc>
<sw_param offset="0xe000b008" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_gem0_net_status_pcs_autoneg_dup_res">
<name>pcs_autoneg_dup_res</name>
<desc>PCS auto-negotiation duplex resolution. Set to one if the resolution function determines that both devices are capable of full duplex operation. If zero half-duplex operation is possible as long as bit 0 (PCS link state) is also one.</desc>
<sw_param offset="0xe000b008" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_gem0_net_status_phy_mgmt_idle">
<name>phy_mgmt_idle</name>
<desc>The PHY management logic is idle (i.e. has completed).</desc>
<sw_param offset="0xe000b008" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_gem0_net_status_mdio_in_pin_status">
<name>mdio_in_pin_status</name>
<desc>Returns status of the mdio_in pin</desc>
<sw_param offset="0xe000b008" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_gem0_net_status_pcs_link_state">
<name>pcs_link_state</name>
<desc>Returns status of PCS link state. If auto-negotiation is disabled this returns the synchronisation status. If auto-negotiation is enabled it is set in the LINK_OK state as long as a compatible duplex mode is resolved, it is always set in the LINK_OK state in SGMII mode.</desc>
<sw_param offset="0xe000b008" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_user_io_user_in">
<name>user_in</name>
<desc>User programmable inputs - the upper 16 bits of this register are used to monitor the state of the user inputs. A logic one read from a bit in this range will correspond to the input being in a high state. A logic zero read from a bit in this range will correspond to the input being in a low state. Any unused bits will be read as zero. Writing to any bits in this range will have no functional effect.</desc>
<sw_param offset="0xe000b00c" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_user_io_user_out">
<name>user_out</name>
<desc>User programmable outputs - the lower 16 bits of this register are used to control the state of the user outputs. A logic one written to a bit in this range will cause the corresponding output to be set high. A logic zero written to a bit in this range shall cause the corresponding output to be forced low. Any unused bits will be read as logic zero. Writing to any unused bits in this range will have no functional effect.</desc>
<sw_param offset="0xe000b00c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_dma_cfg_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe000b010" start="31" end="25" />
</parameter>
<parameter uniqueid="ps7_gem0_dma_cfg_disc_when_no_ahb">
<name>disc_when_no_ahb</name>
<desc>When set, the GEM DMA will automatically discard receive packets from the receiver packet buffer memory when no AHB resource is available.
When low, then received packets will remain to be stored in the SRAM based packet buffer until AHB buffer resource next becomes available.</desc>
<sw_param offset="0xe000b010" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_gem0_dma_cfg_ahb_mem_rx_buf_size">
<name>ahb_mem_rx_buf_size</name>
<desc>DMA receive buffer size in AHB system memory.
The value defined by these bits determines the size of buffer to use in main AHB system memory when writing received data.
The value is defined in multiples of 64 bytes such that a value of 0x01 corresponds to buffers of 64 bytes, 0x02 corresponds to 128 bytes etc.
For example:-
0x02: 128 byte
0x18: 1536 byte (1*max length frame/buffer)
0xA0: 10240 byte (1*10K jumbo frame/buffer)
Note that this value should never be written as zero.</desc>
<sw_param offset="0xe000b010" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_dma_cfg_reserved_1">
<name>reserved_1</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe000b010" start="15" end="12" />
</parameter>
<parameter uniqueid="ps7_gem0_dma_cfg_csum_gen_offload_en">
<name>csum_gen_offload_en</name>
<desc>Transmitter IP, TCP and UDP checksum generation offload enable. When set, the transmitter checksum generation engine is enabled, to calculate and substitute checksums for transmit frames. When clear, frame data is unaffected.
If the GEM is not configured to use the DMA packet buffer, this bit is not implemented and will be treated as reserved, read as zero, ignored on write.
Pele uses packet buffer.</desc>
<sw_param offset="0xe000b010" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_gem0_dma_cfg_tx_pktbuf_memsz_sel">
<name>tx_pktbuf_memsz_sel</name>
<desc>Transmitter packet buffer memory size select - Having this bit at zero halves the amount of memory used for the transmit packet buffer. This reduces the amount of memory used by the GEM. It is important to set this bit to one if the full configured physical memory is available. The value in brackets below represents the size that would result for the default maximum configured memory size of 4 Kbytes.
1: Use full configured addressable space (4 Kb)
0: Do not use top address bit (2 Kb)
If the GEM is not configured to use the DMA packet buffer, this bit is not implemented and will be treated as reserved, read as zero, ignored on write. Pele uses packet buffer</desc>
<sw_param offset="0xe000b010" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_gem0_dma_cfg_rx_pktbuf_memsz_sel">
<name>rx_pktbuf_memsz_sel</name>
<desc>Receiver packet buffer memory size select - Having these bits at less than 11 reduces the amount of memory used for the receive packet buffer. This reduces the amount of memory used by the GEM. It is important to set these bits both to one if the full configured physical memory is available. The value in brackets below represents the size that would result for the default maximum configured memory size of 8 Kbytes.
11: Use full configured addressable space (8 Kb)
10: Do not use top address bit (4 Kb)
01: Do not use top two address bits (2 Kb)
00: Do not use top three address bits (1 Kb)
If the GEM is not configured to use the DMA packet buffer, these bits are not implemented and will be treated as reserved, read as zero, ignored on write. Pele uses packet buffer.</desc>
<sw_param offset="0xe000b010" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_gem0_dma_cfg_ahb_endian_swp_pkt_en">
<name>ahb_endian_swp_pkt_en</name>
<desc>AHB endian swap mode enable for packet data accesses - When set, selects swapped endianism for AHB transfers. When clear, selects little endian mode.</desc>
<sw_param offset="0xe000b010" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_gem0_dma_cfg_ahb_endian_swp_mgmt_en">
<name>ahb_endian_swp_mgmt_en</name>
<desc>AHB endian swap mode enable for management descriptor accesses - When set, selects swapped endianism for AHB transfers. When clear, selects little endian mode.</desc>
<sw_param offset="0xe000b010" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_gem0_dma_cfg_reserved_2">
<name>reserved_2</name>
<desc>Reserved, read as zero, ignored on write</desc>
<sw_param offset="0xe000b010" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_gem0_dma_cfg_ahb_fixed_burst_len">
<name>ahb_fixed_burst_len</name>
<desc>AHB fixed burst length for DMA data operations - Selects the burst length to attempt to use on the AHB when transferring frame data. Not used for DMA management operations and only used where space and data size allow. Otherwise SINGLE type AHB transfers are used.
Upper bits become non-writeable if the configured DMA TX and RX FIFO sizes are smaller than required to support the selected burst size.
One-hot priority encoding enforced automatically on register writes as follows, where 'x' represents don't care:-
1xxxx: Attempt to use INCR16 AHB bursts
01xxx: Attempt to use INCR8 AHB bursts
001xx: Attempt to use INCR4 AHB bursts
0001x: Always use SINGLE AHB bursts
00001: Always use SINGLE AHB bursts
default: Attempt to use INCR4 AHB bursts</desc>
<sw_param offset="0xe000b010" start="4" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_tx_status_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe000b014" start="31" end="9" />
</parameter>
<parameter uniqueid="ps7_gem0_tx_status_hresp_not_ok">
<name>hresp_not_ok</name>
<desc>Hresp not OK - set when the DMA block sees hresp not OK. Cleared by writing a one to this bit.</desc>
<sw_param offset="0xe000b014" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_gem0_tx_status_late_collision">
<name>late_collision</name>
<desc>Late collision occurred - only set if the condition occurs in gigabit mode, as retry is not attempted.
Cleared by writing a one to this bit.</desc>
<sw_param offset="0xe000b014" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_gem0_tx_status_tx_under_run">
<name>tx_under_run</name>
<desc>Transmit under run - this bit is set if the transmitter was forced to terminate a frame that it had already began transmitting due to further data being unavailable.
This bit is set if a transmitter status write back has not completed when another status write back is attempted.
When using the DMA interface configured for internal FIFO mode, this bit is also set when the transmit DMA has written the SOP data into the FIFO and either the AHB bus was not granted in time for further data, or because an AHB not OK response was returned, or because a used bit was read.
When using the DMA interface configured for packet buffer mode, this bit will never be set.
When using the external FIFO interface, this bit is also set when the tx_r_underflow input is asserted during a frame transfer. Cleared by writing a 1.</desc>
<sw_param offset="0xe000b014" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_gem0_tx_status_tx_complete">
<name>tx_complete</name>
<desc>Transmit complete - set when a frame has been transmitted. Cleared by writing a one to this bit.</desc>
<sw_param offset="0xe000b014" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_gem0_tx_status_tx_corr_ahb_err">
<name>tx_corr_ahb_err</name>
<desc>Transmit frame corruption due to AHB error - set if an error occurs whilst midway through reading transmit frame from the AHB, including HRESP errors and buffers exhausted mid frame (if the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and tx_er asserted).
Also set in DMA packet buffer mode if single frame is too large for configured packet buffer memory size.
Cleared by writing a one to this bit.</desc>
<sw_param offset="0xe000b014" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_gem0_tx_status_tx_go">
<name>tx_go</name>
<desc>Transmit go - if high transmit is active.
When using the exposed FIFO interface, this bit represents bit 3 of the network control register.
When using the DMA interface this bit represents the tx_go variable as specified in the transmit buffer description.</desc>
<sw_param offset="0xe000b014" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_gem0_tx_status_retry_limit_exceeded">
<name>retry_limit_exceeded</name>
<desc>Retry limit exceeded - cleared by writing a one to this bit.</desc>
<sw_param offset="0xe000b014" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_gem0_tx_status_collision">
<name>collision</name>
<desc>Collision occurred - set by the assertion of collision.
Cleared by writing a one to this bit. When operating in 10/100 mode, this status indicates either a collision or a late collision. In gigabit mode, this status is not set for a late collision.</desc>
<sw_param offset="0xe000b014" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_gem0_tx_status_used_bit_read">
<name>used_bit_read</name>
<desc>Used bit read - set when a transmit buffer descriptor is read with its used bit set. Cleared by writing a one to this bit.</desc>
<sw_param offset="0xe000b014" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_rx_qbar_rx_q_baseaddr">
<name>rx_q_baseaddr</name>
<desc>Receive buffer queue base address - written with the
address of the start of the receive queue.</desc>
<sw_param offset="0xe000b018" start="31" end="2" />
</parameter>
<parameter uniqueid="ps7_gem0_rx_qbar_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b018" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_tx_qbar_tx_q_base_addr">
<name>tx_q_base_addr</name>
<desc>Transmit buffer queue base address - written with the address of the start of the transmit queue.</desc>
<sw_param offset="0xe000b01c" start="31" end="2" />
</parameter>
<parameter uniqueid="ps7_gem0_tx_qbar_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b01c" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_rx_status_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b020" start="31" end="4" />
</parameter>
<parameter uniqueid="ps7_gem0_rx_status_hresp_not_ok">
<name>hresp_not_ok</name>
<desc>Hresp not OK - set when the DMA block sees hresp not OK. Cleared by writing a one to this bit.</desc>
<sw_param offset="0xe000b020" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_gem0_rx_status_rx_overrun">
<name>rx_overrun</name>
<desc>Receive overrun - this bit is set if either the gem_dma RX FIFO or external RX FIFO were unable to store the receive frame due to a FIFO overflow, or if the receive status, reported by the gem_rx module to the gem_dma was not taken at end of frame. This bit is also set in DMA packet buffer mode if the packet buffer overflows. For DMA operation the buffer will be recovered if an overrun occurs. This bit is cleared by writing a one to it.</desc>
<sw_param offset="0xe000b020" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_gem0_rx_status_frame_recd">
<name>frame_recd</name>
<desc>Frame received - one or more frames have been received and placed in memory. Cleared by writing a one to this bit.</desc>
<sw_param offset="0xe000b020" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_gem0_rx_status_buffer_not_avail">
<name>buffer_not_avail</name>
<desc>Buffer not available - an attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA will reread the pointer each time an end of frame is received until a valid pointer is found. This bit is set following each descriptor read attempt that fails, even if consecutive pointers are unsuccessful and software has in the mean time cleared the status flag. Cleared by writing a one to this bit.</desc>
<sw_param offset="0xe000b020" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_status_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b024" start="31" end="27" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_status_tsu_sec_incr">
<name>tsu_sec_incr</name>
<desc>TSU seconds register increment - indicates the register has incremented.</desc>
<sw_param offset="0xe000b024" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_status_pdelay_resp_tx">
<name>pdelay_resp_tx</name>
<desc>PTP pdelay_resp frame transmitted - indicates a PTP pdelay_resp frame has been transmitted.</desc>
<sw_param offset="0xe000b024" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_status_pdelay_req_tx">
<name>pdelay_req_tx</name>
<desc>PTP pdelay_req frame transmitted - indicates a PTP pdelay_req frame has been transmitted.</desc>
<sw_param offset="0xe000b024" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_status_pdelay_resp_rx">
<name>pdelay_resp_rx</name>
<desc>PTP pdelay_resp frame received - indicates a PTP pdelay_resp frame has been received.</desc>
<sw_param offset="0xe000b024" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_status_pdelay_req_rx">
<name>pdelay_req_rx</name>
<desc>PTP pdelay_req frame received - indicates a PTP pdelay_req frame has been received.</desc>
<sw_param offset="0xe000b024" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_status_sync_tx">
<name>sync_tx</name>
<desc>PTP sync frame transmitted - indicates a PTP sync frame has been transmitted.</desc>
<sw_param offset="0xe000b024" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_status_delay_req_tx">
<name>delay_req_tx</name>
<desc>PTP delay_req frame transmitted - indicates a PTP delay_req frame has been transmitted.</desc>
<sw_param offset="0xe000b024" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_status_sync_rx">
<name>sync_rx</name>
<desc>PTP sync frame received - indicates a PTP sync frame has been received.</desc>
<sw_param offset="0xe000b024" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_status_delay_req_rx">
<name>delay_req_rx</name>
<desc>PTP delay_req frame received - indicates a PTP delay_req frame has been received.</desc>
<sw_param offset="0xe000b024" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_status_partner_pg_rx">
<name>partner_pg_rx</name>
<desc>PCS link partner page received - set when a new base page or next page is received from the link partner. The first time this interrupt is received, it will indicate base page received and subsequent reads will indicate next pages. The next page and base page registers should only be read when this interrupt is signalled. For next pages, the link partner next page register should be read first to avoid the register being over written. This interrupt also indicates when the host should write a new page into the next page register. If further next page exchange is only required by the link partner, this register should be written with a null message page (0x2001).</desc>
<sw_param offset="0xe000b024" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_status_autoneg_complete">
<name>autoneg_complete</name>
<desc>PCS auto-negotiation complete - set once the internal PCS layer has completed auto-negotiation.</desc>
<sw_param offset="0xe000b024" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_status_ext_intr">
<name>ext_intr</name>
<desc>External interrupt - set when a rising edge has been detected on the ext_interrupt_in input pin.</desc>
<sw_param offset="0xe000b024" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_status_pause_tx">
<name>pause_tx</name>
<desc>Pause frame transmitted - indicates a pause frame has been successfully transmitted after being initiated from the network control register or from the tx_pause control pin.</desc>
<sw_param offset="0xe000b024" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_status_pause_zero">
<name>pause_zero</name>
<desc>Pause time zero - set when either the pause time register at address 0x38 decrements to zero, or when a valid pause frame is received with a zero pause quantum field.</desc>
<sw_param offset="0xe000b024" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_status_pause_nonzeroq_rx">
<name>pause_nonzeroq_rx</name>
<desc>Pause frame with non-zero pause quantum received - indicates a valid pause has been received that has a non-zero pause quantum field.</desc>
<sw_param offset="0xe000b024" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_status_hresp_not_ok">
<name>hresp_not_ok</name>
<desc>Hresp not OK - set when the DMA block sees hresp not OK.</desc>
<sw_param offset="0xe000b024" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_status_rx_overrun">
<name>rx_overrun</name>
<desc>Receive overrun - set when the receive overrun status bit gets set.</desc>
<sw_param offset="0xe000b024" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_status_link_chng">
<name>link_chng</name>
<desc>Link change - set when the state of the link detected by the internal PCS changes state.</desc>
<sw_param offset="0xe000b024" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_status_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe000b024" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_status_tx_complete">
<name>tx_complete</name>
<desc>Transmit complete - set when a frame has been transmitted.</desc>
<sw_param offset="0xe000b024" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_status_tx_corrupt_ahb_err">
<name>tx_corrupt_ahb_err</name>
<desc>Transmit frame corruption due to AHB error - set if an error occurs whilst midway through reading transmit frame from the AHB, including HRESP errors and buffers exhausted mid frame (if the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and tx_er asserted).
Also set in DMA packet buffer mode if single frame is too large for configured packet buffer memory size.
Cleared on a read.</desc>
<sw_param offset="0xe000b024" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_status_retry_ex_late_collisn">
<name>retry_ex_late_collisn</name>
<desc>Retry limit exceeded or late collision - transmit error.
Late collision will only cause this status bit to be set in gigabit mode (as a retry is not attempted).</desc>
<sw_param offset="0xe000b024" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_status_reserved_tx_underrun">
<name>reserved_tx_underrun</name>
<desc>Reserved. Do not modify.</desc>
<sw_param offset="0xe000b024" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_status_tx_used_read">
<name>tx_used_read</name>
<desc>TX used bit read - set when a transmit buffer descriptor is read with its used bit set.</desc>
<sw_param offset="0xe000b024" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_status_rx_used_read">
<name>rx_used_read</name>
<desc>RX used bit read - set when a receive buffer descriptor is read with its used bit set.</desc>
<sw_param offset="0xe000b024" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_status_rx_complete">
<name>rx_complete</name>
<desc>Receive complete - a frame has been stored in memory.</desc>
<sw_param offset="0xe000b024" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_status_mgmt_sent">
<name>mgmt_sent</name>
<desc>Management frame sent - the PHY maintenance register has completed its operation.</desc>
<sw_param offset="0xe000b024" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_en_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe000b028" start="31" end="27" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_en_tsu_sec_incr">
<name>tsu_sec_incr</name>
<desc>Enable TSU seconds register increment interrupt</desc>
<sw_param offset="0xe000b028" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_en_pdelay_resp_tx">
<name>pdelay_resp_tx</name>
<desc>Enable PTP pdelay_resp frame transmitted interrupt</desc>
<sw_param offset="0xe000b028" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_en_pdelay_req_tx">
<name>pdelay_req_tx</name>
<desc>Enable PTP pdelay_req frame transmitted interrupt</desc>
<sw_param offset="0xe000b028" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_en_pdelay_resp_rx">
<name>pdelay_resp_rx</name>
<desc>Enable PTP pdelay_resp frame received interrupt</desc>
<sw_param offset="0xe000b028" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_en_pdelay_req_rx">
<name>pdelay_req_rx</name>
<desc>Enable PTP pdelay_req frame received interrupt</desc>
<sw_param offset="0xe000b028" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_en_sync_tx">
<name>sync_tx</name>
<desc>Enable PTP sync frame transmitted interrupt</desc>
<sw_param offset="0xe000b028" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_en_delay_req_tx">
<name>delay_req_tx</name>
<desc>Enable PTP delay_req frame transmitted interrupt</desc>
<sw_param offset="0xe000b028" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_en_sync_rx">
<name>sync_rx</name>
<desc>Enable PTP sync frame received interrupt</desc>
<sw_param offset="0xe000b028" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_en_delay_req_rx">
<name>delay_req_rx</name>
<desc>Enable PTP delay_req frame received interrupt</desc>
<sw_param offset="0xe000b028" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_en_partner_pg_rx">
<name>partner_pg_rx</name>
<desc>Enable PCS link partner page received interrupt</desc>
<sw_param offset="0xe000b028" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_en_autoneg_complete">
<name>autoneg_complete</name>
<desc>Enable PCS auto-negotiation complete interrupt</desc>
<sw_param offset="0xe000b028" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_en_ext_intr">
<name>ext_intr</name>
<desc>Enable external interrupt</desc>
<sw_param offset="0xe000b028" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_en_pause_tx">
<name>pause_tx</name>
<desc>Enable pause frame transmitted interrupt</desc>
<sw_param offset="0xe000b028" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_en_pause_zero">
<name>pause_zero</name>
<desc>Enable pause time zero interrupt</desc>
<sw_param offset="0xe000b028" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_en_pause_nonzeroq">
<name>pause_nonzeroq</name>
<desc>Enable pause frame with non-zero pause quantum interrupt</desc>
<sw_param offset="0xe000b028" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_en_hresp_not_ok">
<name>hresp_not_ok</name>
<desc>Enable hresp not OK interrupt</desc>
<sw_param offset="0xe000b028" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_en_rx_overrun">
<name>rx_overrun</name>
<desc>Enable receive overrun interrupt</desc>
<sw_param offset="0xe000b028" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_en_link_chng">
<name>link_chng</name>
<desc>Enable link change interrupt</desc>
<sw_param offset="0xe000b028" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_en_reserved_1">
<name>reserved_1</name>
<desc>Not used</desc>
<sw_param offset="0xe000b028" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_en_tx_complete">
<name>tx_complete</name>
<desc>Enable transmit complete interrupt</desc>
<sw_param offset="0xe000b028" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_en_tx_corrupt_ahb_err">
<name>tx_corrupt_ahb_err</name>
<desc>Enable transmit frame corruption due to AHB error interrupt</desc>
<sw_param offset="0xe000b028" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_en_retry_ex_late_collisn">
<name>retry_ex_late_collisn</name>
<desc>Enable retry limit exceeded or late collision interrupt</desc>
<sw_param offset="0xe000b028" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_en_tx_underrun">
<name>tx_underrun</name>
<desc>Enable transmit buffer under run interrupt</desc>
<sw_param offset="0xe000b028" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_en_tx_used_read">
<name>tx_used_read</name>
<desc>Enable transmit used bit read interrupt</desc>
<sw_param offset="0xe000b028" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_en_rx_used_read">
<name>rx_used_read</name>
<desc>Enable receive used bit read interrupt</desc>
<sw_param offset="0xe000b028" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_en_rx_complete">
<name>rx_complete</name>
<desc>Enable receive complete interrupt</desc>
<sw_param offset="0xe000b028" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_en_mgmt_done">
<name>mgmt_done</name>
<desc>Enable management done interrupt</desc>
<sw_param offset="0xe000b028" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_dis_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe000b02c" start="31" end="27" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_dis_tsu_sec_incr">
<name>tsu_sec_incr</name>
<desc>Disable TSU seconds register increment interrupt</desc>
<sw_param offset="0xe000b02c" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_dis_pdelay_resp_tx">
<name>pdelay_resp_tx</name>
<desc>Disable PTP pdelay_resp frame transmitted interrupt</desc>
<sw_param offset="0xe000b02c" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_dis_pdelay_req_tx">
<name>pdelay_req_tx</name>
<desc>Disable PTP pdelay_req frame transmitted interrupt</desc>
<sw_param offset="0xe000b02c" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_dis_pdelay_resp_rx">
<name>pdelay_resp_rx</name>
<desc>Disable PTP pdelay_resp frame received interrupt</desc>
<sw_param offset="0xe000b02c" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_dis_pdelay_req_rx">
<name>pdelay_req_rx</name>
<desc>Disable PTP pdelay_req frame received interrupt</desc>
<sw_param offset="0xe000b02c" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_dis_sync_tx">
<name>sync_tx</name>
<desc>Disable PTP sync frame transmitted interrupt</desc>
<sw_param offset="0xe000b02c" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_dis_delay_req_tx">
<name>delay_req_tx</name>
<desc>Disable PTP delay_req frame transmitted interrupt</desc>
<sw_param offset="0xe000b02c" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_dis_sync_rx">
<name>sync_rx</name>
<desc>Disable PTP sync frame received interrupt</desc>
<sw_param offset="0xe000b02c" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_dis_delay_req_rx">
<name>delay_req_rx</name>
<desc>Disable PTP delay_req frame received interrupt</desc>
<sw_param offset="0xe000b02c" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_dis_partner_pg_rx">
<name>partner_pg_rx</name>
<desc>Disable PCS link partner page received interrupt</desc>
<sw_param offset="0xe000b02c" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_dis_autoneg_complete">
<name>autoneg_complete</name>
<desc>Disable PCS auto-negotiation complete interrupt</desc>
<sw_param offset="0xe000b02c" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_dis_ext_intr">
<name>ext_intr</name>
<desc>Disable external interrupt</desc>
<sw_param offset="0xe000b02c" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_dis_pause_tx">
<name>pause_tx</name>
<desc>Disable pause frame transmitted interrupt</desc>
<sw_param offset="0xe000b02c" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_dis_pause_zero">
<name>pause_zero</name>
<desc>Disable pause time zero interrupt</desc>
<sw_param offset="0xe000b02c" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_dis_pause_nonzeroq">
<name>pause_nonzeroq</name>
<desc>Disable pause frame with non-zero pause quantum interrupt</desc>
<sw_param offset="0xe000b02c" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_dis_hresp_not_ok">
<name>hresp_not_ok</name>
<desc>Disable hresp not OK interrupt</desc>
<sw_param offset="0xe000b02c" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_dis_rx_overrun">
<name>rx_overrun</name>
<desc>Disable receive overrun interrupt</desc>
<sw_param offset="0xe000b02c" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_dis_link_chng">
<name>link_chng</name>
<desc>Disable link change interrupt</desc>
<sw_param offset="0xe000b02c" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_dis_reserved_1">
<name>reserved_1</name>
<desc>Not used</desc>
<sw_param offset="0xe000b02c" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_dis_tx_complete">
<name>tx_complete</name>
<desc>Disable transmit complete interrupt</desc>
<sw_param offset="0xe000b02c" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_dis_tx_corrupt_ahb_err">
<name>tx_corrupt_ahb_err</name>
<desc>Disable transmit frame corruption due to AHB error interrupt</desc>
<sw_param offset="0xe000b02c" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_dis_retry_ex_late_collisn">
<name>retry_ex_late_collisn</name>
<desc>Disable retry limit exceeded or late collision interrupt</desc>
<sw_param offset="0xe000b02c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_dis_tx_underrun">
<name>tx_underrun</name>
<desc>Disable transmit buffer under run interrupt</desc>
<sw_param offset="0xe000b02c" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_dis_tx_used_read">
<name>tx_used_read</name>
<desc>Disable transmit used bit read interrupt</desc>
<sw_param offset="0xe000b02c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_dis_rx_used_read">
<name>rx_used_read</name>
<desc>Disable receive used bit read interrupt</desc>
<sw_param offset="0xe000b02c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_dis_rx_complete">
<name>rx_complete</name>
<desc>Disable receive complete interrupt</desc>
<sw_param offset="0xe000b02c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_dis_mgmt_done">
<name>mgmt_done</name>
<desc>Disable management done interrupt</desc>
<sw_param offset="0xe000b02c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_mask_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe000b030" start="31" end="26" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_mask_pdelay_resp_tx">
<name>pdelay_resp_tx</name>
<desc>PTP pdelay_resp frame transmitted mask.</desc>
<sw_param offset="0xe000b030" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_mask_pdelay_req_tx">
<name>pdelay_req_tx</name>
<desc>PTP pdelay_req frame transmitted mask.</desc>
<sw_param offset="0xe000b030" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_mask_pdelay_resp_rx">
<name>pdelay_resp_rx</name>
<desc>PTP pdelay_resp frame received mask.</desc>
<sw_param offset="0xe000b030" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_mask_pdelay_req_rx">
<name>pdelay_req_rx</name>
<desc>PTP pdelay_req frame received mask.</desc>
<sw_param offset="0xe000b030" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_mask_sync_tx">
<name>sync_tx</name>
<desc>PTP sync frame transmitted mask.</desc>
<sw_param offset="0xe000b030" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_mask_delay_req_tx">
<name>delay_req_tx</name>
<desc>PTP delay_req frame transmitted mask.</desc>
<sw_param offset="0xe000b030" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_mask_sync_rx">
<name>sync_rx</name>
<desc>PTP sync frame received mask.</desc>
<sw_param offset="0xe000b030" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_mask_delay_req_rx">
<name>delay_req_rx</name>
<desc>PTP delay_req frame received mask.</desc>
<sw_param offset="0xe000b030" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_mask_partner_pg_rx">
<name>partner_pg_rx</name>
<desc>PCS link partner page mask.</desc>
<sw_param offset="0xe000b030" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_mask_autoneg_complete">
<name>autoneg_complete</name>
<desc>PCS auto-negotiation complete interrupt mask.</desc>
<sw_param offset="0xe000b030" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_mask_ext_intr">
<name>ext_intr</name>
<desc>External interrupt mask.</desc>
<sw_param offset="0xe000b030" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_mask_pause_tx">
<name>pause_tx</name>
<desc>Pause frame transmitted interrupt mask.</desc>
<sw_param offset="0xe000b030" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_mask_pause_zero">
<name>pause_zero</name>
<desc>Pause time zero interrupt mask.</desc>
<sw_param offset="0xe000b030" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_mask_pause_nonzeroq">
<name>pause_nonzeroq</name>
<desc>Pause frame with non-zero pause quantum interrupt mask.</desc>
<sw_param offset="0xe000b030" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_mask_hresp_not_ok">
<name>hresp_not_ok</name>
<desc>Hresp not OK interrupt mask.</desc>
<sw_param offset="0xe000b030" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_mask_rx_overrun">
<name>rx_overrun</name>
<desc>Receive overrun interrupt mask.</desc>
<sw_param offset="0xe000b030" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_mask_link_chng">
<name>link_chng</name>
<desc>Link change interrupt mask.</desc>
<sw_param offset="0xe000b030" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_mask_reserved_1">
<name>reserved_1</name>
<desc>Not used</desc>
<sw_param offset="0xe000b030" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_mask_tx_complete">
<name>tx_complete</name>
<desc>Transmit complete interrupt mask.</desc>
<sw_param offset="0xe000b030" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_mask_tx_corrupt_ahb_err">
<name>tx_corrupt_ahb_err</name>
<desc>Transmit frame corruption due to AHB error interrupt</desc>
<sw_param offset="0xe000b030" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_mask_retry_ex_late_collisn">
<name>retry_ex_late_collisn</name>
<desc>Retry limit exceeded or late collision (gigabit mode only)</desc>
<sw_param offset="0xe000b030" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_mask_tx_underrun">
<name>tx_underrun</name>
<desc>Transmit buffer under run interrupt mask.</desc>
<sw_param offset="0xe000b030" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_mask_tx_used_read">
<name>tx_used_read</name>
<desc>Transmit used bit read interrupt mask.</desc>
<sw_param offset="0xe000b030" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_mask_rx_used_read">
<name>rx_used_read</name>
<desc>Receive used bit read interrupt mask.</desc>
<sw_param offset="0xe000b030" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_mask_rx_complete">
<name>rx_complete</name>
<desc>Receive complete interrupt mask.</desc>
<sw_param offset="0xe000b030" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_gem0_intr_mask_mgmt_done">
<name>mgmt_done</name>
<desc>Management done interrupt mask.</desc>
<sw_param offset="0xe000b030" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_phy_maint_reserved">
<name>reserved</name>
<desc>Must be written with 0.</desc>
<sw_param offset="0xe000b034" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_gem0_phy_maint_clause_22">
<name>clause_22</name>
<desc>Must be written to 1 for Clause 22 operation.
Check you PHY's spec to see if it is clause 22 or clause 45 compliant.</desc>
<sw_param offset="0xe000b034" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_gem0_phy_maint_operation">
<name>operation</name>
<desc>Operation. 10 is read. 01 is write.</desc>
<sw_param offset="0xe000b034" start="29" end="28" />
</parameter>
<parameter uniqueid="ps7_gem0_phy_maint_phy_addr">
<name>phy_addr</name>
<desc>PHY address.</desc>
<sw_param offset="0xe000b034" start="27" end="23" />
</parameter>
<parameter uniqueid="ps7_gem0_phy_maint_reg_addr">
<name>reg_addr</name>
<desc>Register address - specifies the register in the PHY to access.</desc>
<sw_param offset="0xe000b034" start="22" end="18" />
</parameter>
<parameter uniqueid="ps7_gem0_phy_maint_must_10">
<name>must_10</name>
<desc>Must be written to 10.</desc>
<sw_param offset="0xe000b034" start="17" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_phy_maint_data">
<name>data</name>
<desc>For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY.</desc>
<sw_param offset="0xe000b034" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_rx_pauseq_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b038" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_rx_pauseq_rx_pauseq">
<name>rx_pauseq</name>
<desc>Received pause quantum - stores the current value of the received pause quantum register which is decremented every 512 bit times.</desc>
<sw_param offset="0xe000b038" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_tx_pauseq_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b03c" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_tx_pauseq_tx_pauseq">
<name>tx_pauseq</name>
<desc>Transmit pause quantum - written with the pause quantum value for pause frame transmission</desc>
<sw_param offset="0xe000b03c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_hash_bot_a">
<name>a</name>
<desc>The first 32 bits of the hash address register.</desc>
<sw_param offset="0xe000b080" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_hash_top_a">
<name>a</name>
<desc>The remaining 32 bits of the hash address register.</desc>
<sw_param offset="0xe000b084" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_spec_addr1_bot_a">
<name>a</name>
<desc>Least significant 32 bits of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.</desc>
<sw_param offset="0xe000b088" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_spec_addr1_top_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write</desc>
<sw_param offset="0xe000b08c" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_spec_addr1_top_addr_msbs">
<name>addr_msbs</name>
<desc>Specific address 1. The most significant bits of the destination address, that is bits 47:32.</desc>
<sw_param offset="0xe000b08c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_spec_addr2_bot_a">
<name>a</name>
<desc>Least significant 32 bits of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.</desc>
<sw_param offset="0xe000b090" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_spec_addr2_top_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write</desc>
<sw_param offset="0xe000b094" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_spec_addr2_top_addr_msbs">
<name>addr_msbs</name>
<desc>Specific address 2. The most significant bits of the destination address, that is bits 47:32.</desc>
<sw_param offset="0xe000b094" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_spec_addr3_bot_a">
<name>a</name>
<desc>Least significant 32 bits of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.</desc>
<sw_param offset="0xe000b098" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_spec_addr3_top_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write</desc>
<sw_param offset="0xe000b09c" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_spec_addr3_top_addr_msbs">
<name>addr_msbs</name>
<desc>Specific address 3. The most significant bits of the destination address, that is bits 47:32.</desc>
<sw_param offset="0xe000b09c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_spec_addr4_bot_a">
<name>a</name>
<desc>Least significant 32 bits of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.</desc>
<sw_param offset="0xe000b0a0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_spec_addr4_top_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write</desc>
<sw_param offset="0xe000b0a4" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_spec_addr4_top_addr_msbs">
<name>addr_msbs</name>
<desc>Specific address 4. The most significant bits of the destination address, that is bits 47:32.</desc>
<sw_param offset="0xe000b0a4" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_type_id_match1_copy_en">
<name>copy_en</name>
<desc>Enable copying of type ID match 1 matched frames</desc>
<sw_param offset="0xe000b0a8" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_gem0_type_id_match1_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write</desc>
<sw_param offset="0xe000b0a8" start="30" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_type_id_match1_type_id_match1">
<name>type_id_match1</name>
<desc>Type ID match 1. For use in comparisons with received frames type ID/length field.</desc>
<sw_param offset="0xe000b0a8" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_type_id_match2_copy_en">
<name>copy_en</name>
<desc>Enable copying of type ID match 2 matched frames</desc>
<sw_param offset="0xe000b0ac" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_gem0_type_id_match2_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write</desc>
<sw_param offset="0xe000b0ac" start="30" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_type_id_match2_type_id_match2">
<name>type_id_match2</name>
<desc>Type ID match 2. For use in comparisons with received frames type ID/length field.</desc>
<sw_param offset="0xe000b0ac" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_type_id_match3_copy_en">
<name>copy_en</name>
<desc>Enable copying of type ID match 3 matched frames</desc>
<sw_param offset="0xe000b0b0" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_gem0_type_id_match3_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write</desc>
<sw_param offset="0xe000b0b0" start="30" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_type_id_match3_type_id_match3">
<name>type_id_match3</name>
<desc>Type ID match 3. For use in comparisons with received frames type ID/length field.</desc>
<sw_param offset="0xe000b0b0" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_type_id_match4_copy_en">
<name>copy_en</name>
<desc>Enable copying of type ID match 4 matched frames</desc>
<sw_param offset="0xe000b0b4" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_gem0_type_id_match4_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write</desc>
<sw_param offset="0xe000b0b4" start="30" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_type_id_match4_type_id_match4">
<name>type_id_match4</name>
<desc>Type ID match 4. For use in comparisons with received frames type ID/length field.</desc>
<sw_param offset="0xe000b0b4" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_wake_on_lan_reserved">
<name>reserved</name>
<desc>Reserved - read 0, ignored when written</desc>
<sw_param offset="0xe000b0b8" start="31" end="20" />
</parameter>
<parameter uniqueid="ps7_gem0_wake_on_lan_multi_hash_en">
<name>multi_hash_en</name>
<desc>Wake on LAN multicast hash event enable. When set multicast hash events will cause the wol output to be asserted.</desc>
<sw_param offset="0xe000b0b8" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_gem0_wake_on_lan_spec_addr_reg1_en">
<name>spec_addr_reg1_en</name>
<desc>Wake on LAN specific address register 1 event enable. When set specific address 1 events will cause the wol output to be asserted.</desc>
<sw_param offset="0xe000b0b8" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_gem0_wake_on_lan_arp_req_en">
<name>arp_req_en</name>
<desc>Wake on LAN ARP request event enable. When set ARP request events will cause the wol output to be asserted.</desc>
<sw_param offset="0xe000b0b8" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_gem0_wake_on_lan_magic_pkt_en">
<name>magic_pkt_en</name>
<desc>Wake on LAN magic packet event enable. When set magic packet events will cause the wol output to be asserted.</desc>
<sw_param offset="0xe000b0b8" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_wake_on_lan_arp_req_ip_addr">
<name>arp_req_ip_addr</name>
<desc>Wake on LAN ARP request IP address. Written to define the least significant 16 bits of the target IP address that is matched to generate a Wake on LAN event. A value of zero will not generate an event, even if this is matched by the received frame.</desc>
<sw_param offset="0xe000b0b8" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_ipg_stretch_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b0bc" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_ipg_stretch_ipg_stretch">
<name>ipg_stretch</name>
<desc>Bits 7:0 are multiplied with the previously transmitted frame length (including preamble) bits 15:8 +1 divide the frame length. If the resulting number is greater than 96 and bit 28 is set in the network configuration register then the resulting number is used for the transmit inter-packet-gap. 1 is added to bits 15:8 to prevent a divide by zero.</desc>
<sw_param offset="0xe000b0bc" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_stacked_vlan_stacked_vlan_en">
<name>stacked_vlan_en</name>
<desc>Enable Stacked VLAN processing mode</desc>
<sw_param offset="0xe000b0c0" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_gem0_stacked_vlan_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b0c0" start="30" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_stacked_vlan_user_def_vlan_type">
<name>user_def_vlan_type</name>
<desc>User defined VLAN_TYPE field. When Stacked VLAN is enabled, the first VLAN tag in a received frame will only be accepted if the VLAN type field is equal to this user defined VLAN_TYPE OR equal to the standard VLAN type (0x8100). Note that the second VLAN tag of a Stacked VLAN packet will only be matched correctly if its VLAN_TYPE field equals 0x8100.</desc>
<sw_param offset="0xe000b0c0" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_tx_pfc_pause_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b0c4" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_tx_pfc_pause_pauseq_sel">
<name>pauseq_sel</name>
<desc>If bit 17 of the network control register is written with a one then for each entry equal to zero in the Transmit PFC Pause Register[15:8], the PFC pause frame's pause quantum field associated with that entry will be taken from the transmit pause quantum register. For each entry equal to one in the Transmit PFC Pause Register [15:8], the pause quantum associated with that entry will be zero.</desc>
<sw_param offset="0xe000b0c4" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_gem0_tx_pfc_pause_pri_en_vec_val">
<name>pri_en_vec_val</name>
<desc>If bit 17 of the network control register is written with a one then the priority enable vector of the PFC priority based pause frame will be set equal to the value stored in this register [7:0].</desc>
<sw_param offset="0xe000b0c4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_spec_addr1_mask_bot_mask_bits_bot">
<name>mask_bits_bot</name>
<desc>Setting a bit to one masks the corresponding bit in the specific address 1 register</desc>
<sw_param offset="0xe000b0c8" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_spec_addr1_mask_top_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b0cc" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_spec_addr1_mask_top_mask_bits_top">
<name>mask_bits_top</name>
<desc>Setting a bit to one masks the corresponding bit in the specific address 1 register</desc>
<sw_param offset="0xe000b0cc" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_module_id_module_id">
<name>module_id</name>
<desc>Module identification number - for the GEM, this value is fixed at 0x0002.</desc>
<sw_param offset="0xe000b0fc" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_module_id_module_rev">
<name>module_rev</name>
<desc>Module revision - fixed byte value specific to the revision of the design which is incremented after each release of the IP. Corresponds to Pele having GEM p23.</desc>
<sw_param offset="0xe000b0fc" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_octets_tx_bot_octets_tx_bot">
<name>octets_tx_bot</name>
<desc>Transmitted octets in frame without errors [31:0].
The number of octets transmitted in valid frames of any type. This counter is 48-bits, and is read through two registers. This count does not include octets from automatically generated pause frames.</desc>
<sw_param offset="0xe000b100" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_octets_tx_top_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b104" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_octets_tx_top_octets_tx_top">
<name>octets_tx_top</name>
<desc>Transmitted octets in frame without errors [47:32].
The number of octets transmitted in valid frames of
any type. This counter is 48-bits, and is read through
two registers. This count does not include octets
from automatically generated pause frames.</desc>
<sw_param offset="0xe000b104" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_frames_tx_a">
<name>a</name>
<desc>Frames transmitted without error. A 32 bit register
counting the number of frames successfully
transmitted, i.e. no under run and not too many
retries. Excludes pause frames.</desc>
<sw_param offset="0xe000b108" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_broadcast_frames_tx_a">
<name>a</name>
<desc>Broadcast frames transmitted without error. A 32 bit
register counting the number of broadcast frames
successfully transmitted without error, i.e. no under
run and not too many retries. Excludes pause
frames.</desc>
<sw_param offset="0xe000b10c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_multi_frames_tx_a">
<name>a</name>
<desc>Multicast frames transmitted without error. A 32 bit
register counting the number of multicast frames
successfully transmitted without error, i.e. no under
run and not too many retries. Excludes pause
frames.</desc>
<sw_param offset="0xe000b110" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_pause_frames_tx_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b114" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_pause_frames_tx_pause_frames_tx">
<name>pause_frames_tx</name>
<desc>Transmitted pause frames - a 16 bit register
counting the number of pause frames transmitted.
Only pause frames triggered by the register interface
or through the external pause pins are counted as
pause frames. Pause frames received through the
external FIFO interface are counted in the frames
transmitted counter.</desc>
<sw_param offset="0xe000b114" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_frames_64b_tx_a">
<name>a</name>
<desc>64 byte frames transmitted without error. A 32 bit
register counting the number of 64 byte frames
successfully transmitted without error, i.e. no under
run and not too many retries. Excludes pause
frames.</desc>
<sw_param offset="0xe000b118" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_frames_65to127b_tx_a">
<name>a</name>
<desc>65 to127 byte frames transmitted without error. A 32
bit register counting the number of 65 to127 byte
frames successfully transmitted without error, i.e. no
under run and not too many retries.</desc>
<sw_param offset="0xe000b11c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_frames_128to255b_tx_a">
<name>a</name>
<desc>128 to 255 byte frames transmitted without error. A
32 bit register counting the number of 128 to 255
byte frames successfully transmitted without error,
i.e. no under run and not too many retries.</desc>
<sw_param offset="0xe000b120" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_frames_256to511b_tx_a">
<name>a</name>
<desc>256 to 511 byte frames transmitted without error. A
32 bit register counting the number of 256 to 511
byte frames successfully transmitted without error,
i.e. no under run and not too many retries.</desc>
<sw_param offset="0xe000b124" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_frames_512to1023b_tx_a">
<name>a</name>
<desc>512 to 1023 byte frames transmitted without error. A
32 bit register counting the number of 512 to 1023
byte frames successfully transmitted without error,
i.e. no under run and not too many retries.</desc>
<sw_param offset="0xe000b128" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_frames_1024to1518b_tx_a">
<name>a</name>
<desc>1024 to 1518 byte frames transmitted without error.
A 32 bit register counting the number of 1024 to
1518 byte frames successfully transmitted without
error, i.e. no under run and not too many retries.</desc>
<sw_param offset="0xe000b12c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_tx_under_runs_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b134" start="31" end="10" />
</parameter>
<parameter uniqueid="ps7_gem0_tx_under_runs_tx_under_runs">
<name>tx_under_runs</name>
<desc>Transmit under runs - a 10 bit register counting the
number of frames not transmitted due to a transmit
under run. If this register is incremented then no
other statistics register is incremented.</desc>
<sw_param offset="0xe000b134" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_single_collisn_frames_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b138" start="31" end="18" />
</parameter>
<parameter uniqueid="ps7_gem0_single_collisn_frames_single_collisn">
<name>single_collisn</name>
<desc>Single collision frames - an 18 bit register counting
the number of frames experiencing a single collision
before being successfully transmitted, i.e. no under
run.</desc>
<sw_param offset="0xe000b138" start="17" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_multi_collisn_frames_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b13c" start="31" end="18" />
</parameter>
<parameter uniqueid="ps7_gem0_multi_collisn_frames_multi_collisn">
<name>multi_collisn</name>
<desc>Multiple collision frames - an 18 bit register counting
the number of frames experiencing between two and
fifteen collisions prior to being successfully
transmitted, i.e. no under run and not too many
retries.</desc>
<sw_param offset="0xe000b13c" start="17" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_excessive_collisns_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b140" start="31" end="10" />
</parameter>
<parameter uniqueid="ps7_gem0_excessive_collisns_excessive_collisns">
<name>excessive_collisns</name>
<desc>Excessive collisions - a 10 bit register counting the
number of frames that failed to be transmitted
because they experienced 16 collisions.</desc>
<sw_param offset="0xe000b140" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_late_collisns_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b144" start="31" end="10" />
</parameter>
<parameter uniqueid="ps7_gem0_late_collisns_late_collisns">
<name>late_collisns</name>
<desc>Late collisions - a 10 bit register counting the number
of late collision occurring after the slot time (512 bits)
has expired. In 10/100 mode, late collisions are
counted twice i.e. both as a collision and a late
collision. In gigabit mode, a late collision causes the
transmission to be aborted, thus the single and multi
collision registers are not updated.</desc>
<sw_param offset="0xe000b144" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_deferred_tx_frames_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b148" start="31" end="18" />
</parameter>
<parameter uniqueid="ps7_gem0_deferred_tx_frames_deferred_tx">
<name>deferred_tx</name>
<desc>Deferred transmission frames - an 18 bit register
counting the number of frames experiencing deferral
due to carrier sense being active on their first
attempt at transmission. Frames involved in any
collision are not counted nor are frames that
experienced a transmit under run.</desc>
<sw_param offset="0xe000b148" start="17" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_carrier_sense_errs_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b14c" start="31" end="10" />
</parameter>
<parameter uniqueid="ps7_gem0_carrier_sense_errs_carrier_sense_errs">
<name>carrier_sense_errs</name>
<desc>Carrier sense errors - a 10 bit register counting the
number of frames transmitted where carrier sense
was not seen during transmission or where carrier
sense was deasserted after being asserted in a
transmit frame without collision (no under run). Only
incremented in half duplex mode. The only effect of
a carrier sense error is to increment this register.
The behaviour of the other statistics registers is
unaffected by the detection of a carrier sense error.</desc>
<sw_param offset="0xe000b14c" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_octets_rx_bot_octets_rx_bot">
<name>octets_rx_bot</name>
<desc>Received octets in frame without errors [31:0]. The
number of octets received in valid frames of any
type. This counter is 48-bits and is read through two
registers. This count does not include octets from
pause frames, and is only incremented if the frame is
successfully filtered and copied to memory.</desc>
<sw_param offset="0xe000b150" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_octets_rx_top_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b154" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_octets_rx_top_octets_rx_top">
<name>octets_rx_top</name>
<desc>Received octets in frame without errors [47:32]. The
number of octets received in valid frames of any
type. This counter is 48-bits and is read through two
registers. This count does not include octets from
pause frames, and is only incremented if the frame is
successfully filtered and copied to memory.</desc>
<sw_param offset="0xe000b154" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_frames_rx_a">
<name>a</name>
<desc>Frames received without error. A 32 bit register
counting the number of frames successfully
received. Excludes pause frames, and is only
incremented if the frame is successfully filtered and
copied to memory.</desc>
<sw_param offset="0xe000b158" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_bdcast_fames_rx_a">
<name>a</name>
<desc>Broadcast frames received without error. A 32 bit
register counting the number of broadcast frames
successfully received without error. Excludes pause
frames, and is only incremented if the frame is
successfully filtered and copied to memory.</desc>
<sw_param offset="0xe000b15c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_multi_frames_rx_a">
<name>a</name>
<desc>Multicast frames received without error. A 32 bit
register counting the number of multicast frames
successfully received without error. Excludes pause
frames, and is only incremented if the frame is
successfully filtered and copied to memory.</desc>
<sw_param offset="0xe000b160" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_pause_rx_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b164" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_pause_rx_pause_rx">
<name>pause_rx</name>
<desc>Received pause frames - a 16 bit register counting
the number of pause frames received without error.</desc>
<sw_param offset="0xe000b164" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_frames_64b_rx_a">
<name>a</name>
<desc>64 byte frames received without error. A 32 bit
register counting the number of 64 byte frames
successfully received without error. Excludes pause
frames, and is only incremented if the frame is
successfully filtered and copied to memory.</desc>
<sw_param offset="0xe000b168" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_frames_65to127b_rx_a">
<name>a</name>
<desc>65 to 127 byte frames received without error. A 32 bit
register counting the number of 65 to 127 byte
frames successfully received without error. Excludes
pause frames, and is only incremented if the frame is
successfully filtered and copied to memory.</desc>
<sw_param offset="0xe000b16c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_frames_128to255b_rx_a">
<name>a</name>
<desc>128 to 255 byte frames received without error. A 32
bit register counting the number of 128 to 255 byte
frames successfully received without error. Excludes
pause frames, and is only incremented if the frame is
successfully filtered and copied to memory.</desc>
<sw_param offset="0xe000b170" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_frames_256to511b_rx_a">
<name>a</name>
<desc>256 to 511 byte frames received without error. A 32
bit register counting the number of 256 to 511 byte
frames successfully transmitted without error.
Excludes pause frames, and is only incremented if
the frame is successfully filtered and copied to
memory.</desc>
<sw_param offset="0xe000b174" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_frames_512to1023b_rx_a">
<name>a</name>
<desc>512 to 1023 byte frames received without error. A 32
bit register counting the number of 512 to 1023 byte
frames successfully received without error. Excludes
pause frames, and is only incremented if the frame is
successfully filtered and copied to memory.</desc>
<sw_param offset="0xe000b178" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_frames_1024to1518b_rx_a">
<name>a</name>
<desc>1024 to 1518 byte frames received without error. A
32 bit register counting the number of 1024 to 1518
byte frames successfully received without error.
Excludes pause frames, and is only incremented if
the frame is successfully filtered and copied to
memory.</desc>
<sw_param offset="0xe000b17c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_undersz_rx_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b184" start="31" end="10" />
</parameter>
<parameter uniqueid="ps7_gem0_undersz_rx_undersz_rx">
<name>undersz_rx</name>
<desc>Undersize frames received - a 10 bit register
counting the number of frames received less than 64
bytes in length (10/100 mode or gigabit mode, full
duplex) that do not have either a CRC error or an
alignment error. In gigabit mode, half duplex, this
register counts either frames not conforming to the
minimum slot time of 512 bytes or frames not
conforming to the minimum frame size once bursting
is active.</desc>
<sw_param offset="0xe000b184" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_fcs_errors_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b190" start="31" end="10" />
</parameter>
<parameter uniqueid="ps7_gem0_fcs_errors_fcs_errors">
<name>fcs_errors</name>
<desc>Frame check sequence errors - a 10 bit register
counting frames that are an integral number of
bytes, have bad CRC and are between 64 and 1518
bytes in length. This register is
also incremented if a symbol error is detected and
the frame is of valid length and has an integral
number of bytes.
This register is incremented for a frame with bad
FCS, regardless of whether it is copied to memory
due to ignore FCS mode being enabled in bit 26 of
the network configuration register.H524</desc>
<sw_param offset="0xe000b190" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_length_field_errors_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b194" start="31" end="10" />
</parameter>
<parameter uniqueid="ps7_gem0_length_field_errors_length_field_errors">
<name>length_field_errors</name>
<desc>Length field frame errors - this 10-bit register counts
the number of frames received that have a
measured length shorter than that extracted from the
length field (bytes 13 and 14). This condition is only
counted if the value of the length field is less than
0x0600, the frame is not of excessive length and
checking is enabled through bit 16 of the network
configuration register.</desc>
<sw_param offset="0xe000b194" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_rx_symbol_errors_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b198" start="31" end="10" />
</parameter>
<parameter uniqueid="ps7_gem0_rx_symbol_errors_rx_symbol_errors">
<name>rx_symbol_errors</name>
<desc>Receive symbol errors - a 10-bit register counting
the number of frames that had rx_er asserted
during reception. For 10/100 mode symbol errors
are counted regardless of frame length checks. For
gigabit mode the frame must satisfy slot time
requirements in order to count a symbol error.
Additionally, in gigabit half duplex mode, carrier
extension errors are also recorded. Receive symbol
errors will also be counted as an FCS or alignment
error if the frame is between 64 and 1518 bytes. If the frame is larger it will be
recorded as a jabber error.</desc>
<sw_param offset="0xe000b198" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_align_errors_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b19c" start="31" end="10" />
</parameter>
<parameter uniqueid="ps7_gem0_align_errors_align_errors">
<name>align_errors</name>
<desc>Alignment errors - a 10 bit register counting frames
that are not an integral number of bytes long and
have bad CRC when their length is truncated to an
integral number of bytes and are between 64 and
1518 bytes in length. This register is
also incremented if a symbol error is detected and
the frame is of valid length and does not have an
integral number of bytes.</desc>
<sw_param offset="0xe000b19c" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_rx_resource_errors_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b1a0" start="31" end="18" />
</parameter>
<parameter uniqueid="ps7_gem0_rx_resource_errors_rx_resource_errors">
<name>rx_resource_errors</name>
<desc>Receive resource errors - an 18 bit register counting
the number of frames that were successfully
received by the MAC (correct address matched
frame and adequate slot time) but could not be
copied to memory because no receive buffer was
available. This will be either because the AHB bus
was not granted in time or because a hresp not OK
was returned.</desc>
<sw_param offset="0xe000b1a0" start="17" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_rx_overrun_errors_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b1a4" start="31" end="10" />
</parameter>
<parameter uniqueid="ps7_gem0_rx_overrun_errors_rx_overrun_errors">
<name>rx_overrun_errors</name>
<desc>Receive overruns - a 10 bit register counting the
number of frames that are address recognized but
were not copied to memory due to a receive overrun.</desc>
<sw_param offset="0xe000b1a4" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_ip_hdr_csum_errors_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b1a8" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_gem0_ip_hdr_csum_errors_ip_hdr_csum_errors">
<name>ip_hdr_csum_errors</name>
<desc>0 IP header checksum errors - an 8-bit register
counting the number of frames discarded due to an
incorrect IP header checksum, but are between 64
and 1518 bytes and do not
have a CRC error, an alignment error, nor a symbol
error.</desc>
<sw_param offset="0xe000b1a8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_tcp_csum_errors_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b1ac" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_gem0_tcp_csum_errors_tcp_csum_errors">
<name>tcp_csum_errors</name>
<desc>TCP checksum errors - an 8-bit register counting the
number of frames discarded due to an incorrect TCP
checksum, but are between 64 and 1518 bytes and do not have a CRC error,
an alignment error, nor a symbol error.</desc>
<sw_param offset="0xe000b1ac" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_udp_csum_errors_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b1b0" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_gem0_udp_csum_errors_udp_csum_errors">
<name>udp_csum_errors</name>
<desc>UDP checksum errors - an 8-bit register counting the
number of frames discarded due to an incorrect UDP
checksum, but are between 64 and 1518 bytes and do not have a CRC error,
an alignment error, nor a symbol error.</desc>
<sw_param offset="0xe000b1b0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_timer_strobe_s_a">
<name>a</name>
<desc>The value of the Timer Seconds register captured
when gem_tsu_ms and gem_tsu_inc_ctrl are zero</desc>
<sw_param offset="0xe000b1c8" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_timer_strobe_ns_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b1cc" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_gem0_timer_strobe_ns_ns_reg_val">
<name>ns_reg_val</name>
<desc>The value of the Timer Nanoseconds register
captured when gem_tsu_ms and gem_tsu_inc_ctrl
are zero.</desc>
<sw_param offset="0xe000b1cc" start="29" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_timer_s_a">
<name>a</name>
<desc>Timer count in seconds. This register is writeable. It
increments by one when the 1588 nanoseconds
counter counts to one second. It may also be
incremented when the timer adjust register is
written.</desc>
<sw_param offset="0xe000b1d0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_timer_ns_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b1d4" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_gem0_timer_ns_timer_ct_ns">
<name>timer_ct_ns</name>
<desc>Timer count in nanoseconds. This register is
writeable. It can also be adjusted by writes to the
1588 timer adjust register. It increments by the value
of the 1588 timer increment register each clock
cycle.</desc>
<sw_param offset="0xe000b1d4" start="29" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_timer_adjust_add_subn">
<name>add_subn</name>
<desc>Write as one to subtract from the 1588 timer. Write
as zero to add to it.</desc>
<sw_param offset="0xe000b1d8" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_gem0_timer_adjust_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b1d8" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_gem0_timer_adjust_ns_delta">
<name>ns_delta</name>
<desc>The number of nanoseconds to increment or
decrement the 1588 timer nanoseconds register. If
necessary the 1588 seconds register will be
incremented or decremented.</desc>
<sw_param offset="0xe000b1d8" start="29" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_timer_incr_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b1dc" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_gem0_timer_incr_incr_b4_alt">
<name>incr_b4_alt</name>
<desc>The number of increments after which the alternative
increment is used</desc>
<sw_param offset="0xe000b1dc" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_timer_incr_alt_ct_ns_delta">
<name>alt_ct_ns_delta</name>
<desc>Alternative count of nanoseconds by which the 1588
timer nanoseconds register will be incremented
each clock cycle.</desc>
<sw_param offset="0xe000b1dc" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_gem0_timer_incr_ns_delta">
<name>ns_delta</name>
<desc>A count of nanoseconds by which the 1588 timer
nanoseconds register will be incremented each
clock cycle.</desc>
<sw_param offset="0xe000b1dc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_ptp_tx_s_a">
<name>a</name>
<desc>The register is updated with the value that the 1588
timer seconds register held when the SFD of a PTP
transmit primary event crosses the MII interface. The
actual update occurs when the GEM recognizes the
frame as a PTP sync or delay_req frame. An
interrupt is issued when the register is updated.</desc>
<sw_param offset="0xe000b1e0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_ptp_tx_ns_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b1e4" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_gem0_ptp_tx_ns_ns_reg_val">
<name>ns_reg_val</name>
<desc>The register is updated with the value that the 1588
timer nanoseconds register held when the SFD of a
PTP transmit primary event crosses the MII
interface. The actual update occurs when the GEM
recognizes the frame as a PTP sync or delay_req
frame. An interrupt is issued when the register is
updated.</desc>
<sw_param offset="0xe000b1e4" start="29" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_ptp_rx_s_a">
<name>a</name>
<desc>The register is updated with the value that the 1588
timer seconds register held when the SFD of a PTP
receive primary event crosses the MII interface. The
actual update occurs when the GEM recognizes the
frame as a PTP sync or delay_req frame. An
interrupt is issued when the register is updated.</desc>
<sw_param offset="0xe000b1e8" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_ptp_rx_ns_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b1ec" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_gem0_ptp_rx_ns_ns_reg_val">
<name>ns_reg_val</name>
<desc>The register is updated with the value that the 1588
timer nanoseconds register held when the SFD of a
PTP receive primary event crosses the MII interface.
The actual update occurs when the GEM recognizes
the frame as a PTP sync or delay_req frame. An
interrupt is issued when the register is updated.</desc>
<sw_param offset="0xe000b1ec" start="29" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_ptp_peer_tx_s_a">
<name>a</name>
<desc>The register is updated with the value that the 1588
timer seconds register held when the SFD of a PTP
transmit peer event crosses the MII interface. The
actual update occurs when the GEM recognizes the
frame as a PTP pdealy_req or pdelay_resp frame.
An interrupt is issued when the register is updated.</desc>
<sw_param offset="0xe000b1f0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_ptp_peer_tx_ns_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b1f4" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_gem0_ptp_peer_tx_ns_ns_reg_val">
<name>ns_reg_val</name>
<desc>The register is updated with the value that the 1588
timer nanoseconds register held when the SFD of a
PTP transmit peer event crosses the MII interface.
The actual update occurs when the GEM recognizes
the frame as a PTP pdelay_req or pdelay_resp
frame. An interrupt is issued when the register is
updated.</desc>
<sw_param offset="0xe000b1f4" start="29" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_ptp_peer_rx_s_a">
<name>a</name>
<desc>The register is updated with the value that the 1588
timer seconds register held when the SFD of a PTP
receive peer event crosses the MII interface. The
actual update occurs when the GEM recognizes the
frame as a PTP pdelay_req or pdelay_resp frame.
An interrupt is issued when the register is updated.</desc>
<sw_param offset="0xe000b1f8" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_ptp_peer_rx_ns_reserved">
<name>reserved</name>
<desc>Reserved, read as 0, ignored on write.</desc>
<sw_param offset="0xe000b1fc" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_gem0_ptp_peer_rx_ns_ns_reg_val">
<name>ns_reg_val</name>
<desc>The register is updated with the value that the 1588
timer nanoseconds register held when the SFD of a
PTP receive peer event crosses the MII interface.
The actual update occurs when the GEM recognizes
the frame as a PTP pdelay_req or pdelay_resp
frame. An interrupt is issued when the register is
updated.</desc>
<sw_param offset="0xe000b1fc" start="29" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg1_reserved">
<name>reserved</name>
<desc>Reserved. Set to 0</desc>
<sw_param offset="0xe000b280" start="31" end="28" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg1_gem_dma_bus_width">
<name>gem_dma_bus_width</name>
<desc>Takes the value of the `gem_dma_bus_width DEFINE
3'b001 : 32-bit
3'b010 : 64-bit
3'b100 : 128-bit</desc>
<sw_param offset="0xe000b280" start="27" end="25" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg1_extra_spec_add">
<name>extra_spec_add</name>
<desc>Takes the value of the `extra_spec_add DEFINE. Undefined in Pele</desc>
<sw_param offset="0xe000b280" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg1_gem_irq_read_clear">
<name>gem_irq_read_clear</name>
<desc>Takes the value of the `gem_irq_read_clear DEFINE. Undefined in Pele. Keeping undefined means interrupt status registers are write-one-to-clear rather than clearing when read.</desc>
<sw_param offset="0xe000b280" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg1_gem_no_snapshot">
<name>gem_no_snapshot</name>
<desc>Takes the value of the `gem_no_snapshot DEFINE. Defined for Pele. Remove statistics snapshot
(not supported by driver)</desc>
<sw_param offset="0xe000b280" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg1_gem_no_stats">
<name>gem_no_stats</name>
<desc>Takes the value of the `gem_no_stats DEFINE. Undefined for Pele.
Include statistics registers.</desc>
<sw_param offset="0xe000b280" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg1_gem_no_scan_pins">
<name>gem_no_scan_pins</name>
<desc>Takes the value of the `gem_no_scan_pins DEFINE. Defined for Pele. Remove placeholder scan pins from module.</desc>
<sw_param offset="0xe000b280" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg1_gem_user_in_width">
<name>gem_user_in_width</name>
<desc>Takes the value of the `gem_user_in_width DEFINE. Undefined for Pele. No requirement for user I/O.</desc>
<sw_param offset="0xe000b280" start="19" end="15" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg1_gem_user_out_width">
<name>gem_user_out_width</name>
<desc>Takes the value of the `gem_user_out_width DEFINE. Undefined for Pele. No requirement for user I/O.</desc>
<sw_param offset="0xe000b280" start="14" end="10" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg1_gem_user_io">
<name>gem_user_io</name>
<desc>Takes the value of the `gem_user_io DEFINE. Undefined for Pele. No requirement for user I/O.</desc>
<sw_param offset="0xe000b280" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg1_gem_apb_rev2">
<name>gem_apb_rev2</name>
<desc>Takes the value of the `gem_apb_rev2 DEFINE. Defined for Pele. Use AMBA 2.0 APB.</desc>
<sw_param offset="0xe000b280" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg1_gem_apb_rev1">
<name>gem_apb_rev1</name>
<desc>Takes the value of the `gem_apb_rev1 DEFINE. Undefined for Pele. Use AMBA 2.0 APB.</desc>
<sw_param offset="0xe000b280" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg1_gem_ext_fifo_interface">
<name>gem_ext_fifo_interface</name>
<desc>Takes the value of the `gem_ext_fifo_interface. Undefined for Pele. Use AHB DMA; External FIFO interface not implemented.</desc>
<sw_param offset="0xe000b280" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg1_gem_no_int_loopback">
<name>gem_no_int_loopback</name>
<desc>Takes the value of the `gem_no_int_loopback DEFINE. Undefined for Pele. Include loopback test mode</desc>
<sw_param offset="0xe000b280" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg1_gem_int_loopback">
<name>gem_int_loopback</name>
<desc>Takes the value of the `gem_int_loopback DEFINE. Defined for Pele. Include loopback test mode.</desc>
<sw_param offset="0xe000b280" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg1_TDC_50">
<name>TDC_50</name>
<desc>Takes the value of the `TDC_50 DEFINE. Undefined for Pele. Only used with PCS.</desc>
<sw_param offset="0xe000b280" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg1_RDC_50">
<name>RDC_50</name>
<desc>Takes the value of the `RDC_50 DEFINE. Undefined for Pele. Only used with PCS.</desc>
<sw_param offset="0xe000b280" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg1_gem_serdes">
<name>gem_serdes</name>
<desc>Takes the value of the `gem_serdes DEFINE. Undefined for Pele. Only used with PCS.</desc>
<sw_param offset="0xe000b280" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg1_gem_no_pcs">
<name>gem_no_pcs</name>
<desc>Takes the value of the `gem_no_pcs DEFINE. Defined for Pele. Use GEM without 1000-BASE-X PCS sublayer and Ten Bit Interface</desc>
<sw_param offset="0xe000b280" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg2_reserved">
<name>reserved</name>
<desc>Reserved. Set to zero.</desc>
<sw_param offset="0xe000b284" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg2_gem_tx_pbuf_addr">
<name>gem_tx_pbuf_addr</name>
<desc>Takes the value of the `gem_tx_pbuf_addr DEFINE. Max address bits for Tx packet buffer (10-bits for maximum 4 kB buffer)
Buffer size for Tx packet buffer mode will be 4kB.
This will allow one standard packet to be received while another is transferred to system memory by the DMA interface.</desc>
<sw_param offset="0xe000b284" start="29" end="26" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg2_gem_rx_pbuf_addr">
<name>gem_rx_pbuf_addr</name>
<desc>Takes the value of the `gem_rx_pbuf_addr DEFINE. Max address bits for Rx packet buffer (10-bits for maximum 4 kB buffer)
Buffer size for Rx packet buffer mode will be 4kB.
This will allow one standard packet to be received while another is transferred to system memory by the DMA interface.</desc>
<sw_param offset="0xe000b284" start="25" end="22" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg2_gem_tx_pkt_buffer">
<name>gem_tx_pkt_buffer</name>
<desc>Takes the value of the `gem_tx_pkt_buffer DEFINE. Defined for Pele. Includes the transmitter packet buffer</desc>
<sw_param offset="0xe000b284" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg2_gem_rx_pkt_buffer">
<name>gem_rx_pkt_buffer</name>
<desc>Takes the value of the `gem_rx_pkt_buffer DEFINE. Defined for Pele. Includes the receiver packet buffer</desc>
<sw_param offset="0xe000b284" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg2_gem_hprot_value">
<name>gem_hprot_value</name>
<desc>Takes the value of the `gem_hprot_value DEFINE. For Pele set the fixed AHB HPROT value used during transfers</desc>
<sw_param offset="0xe000b284" start="19" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg2_gem_jumbo_max_length">
<name>gem_jumbo_max_length</name>
<desc>Takes the value of the `gem_jumbo_max_length DEFINE. Maximum length of jumbo frames accepted by receiver.
This is set to the size of the smallest of the two packet buffer, minus a margin for packet headers. However, Pele will not support jumbo frames.</desc>
<sw_param offset="0xe000b284" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg3_gem_rx_base2_fifo_size">
<name>gem_rx_base2_fifo_size</name>
<desc>Takes the value of the `gem_rx_base2_fifo_size DEFINE. Base-2 equivalent of `gem_rx_fifo_size</desc>
<sw_param offset="0xe000b288" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg3_gem_rx_fifo_size">
<name>gem_rx_fifo_size</name>
<desc>Takes the value of the `gem_rx_fifo_size DEFINE. Set the size of the small Rx FIFO for grant latency. Extended to 16 deep to allow buffering of 64 byte maximum AHB burst size in Pele.</desc>
<sw_param offset="0xe000b288" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg4_gem_tx_base2_fifo_size">
<name>gem_tx_base2_fifo_size</name>
<desc>Takes the value of the `gem_tx_base2_fifo_size DEFINE. Base-2 equivalent of `gem_tx_fifo_size</desc>
<sw_param offset="0xe000b28c" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg4_gem_tx_fifo_size">
<name>gem_tx_fifo_size</name>
<desc>Takes the value of the `gem_tx_fifo_size DEFINE. Set the size of the small TX FIFO for grant latency</desc>
<sw_param offset="0xe000b28c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg5_reserved">
<name>reserved</name>
<desc>Reserved. Set to zero.</desc>
<sw_param offset="0xe000b290" start="31" end="29" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg5_gem_tsu_clk">
<name>gem_tsu_clk</name>
<desc>Takes the value of the `gem_tsu_clk DEFINE. Undefined in Pele. 1588 Time Stamp Unit clock sourced from pclk rather than independent tsu_clk.</desc>
<sw_param offset="0xe000b290" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg5_gem_rx_buffer_length_def">
<name>gem_rx_buffer_length_def</name>
<desc>Takes the value of the `gem_rx_buffer_length_def DEFINE. Set the default buffer length used by Rx DMA to 128 bytes in Pele</desc>
<sw_param offset="0xe000b290" start="27" end="20" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg5_gem_tx_pbuf_size_def">
<name>gem_tx_pbuf_size_def</name>
<desc>Takes the value of the `gem_tx_pbuf_size_def DEFINE. Full 4 kB Tx packet buffer size - dedicated memory resource in Pele.</desc>
<sw_param offset="0xe000b290" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg5_gem_rx_pbuf_size_def">
<name>gem_rx_pbuf_size_def</name>
<desc>Takes the value of the `gem_rx_pbuf_size_def DEFINE. Full
4 kB Rx packet buffer size - dedicated memory resource in Pele.</desc>
<sw_param offset="0xe000b290" start="18" end="17" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg5_gem_endian_swap_def">
<name>gem_endian_swap_def</name>
<desc>Takes the value of the `gem_endian_swap_def DEFINE. Set to big endian data, little endian management descriptors in Pele.</desc>
<sw_param offset="0xe000b290" start="16" end="15" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg5_gem_mdc_clock_div">
<name>gem_mdc_clock_div</name>
<desc>Takes the value of the `gem_mdc_clock_div DEFINE. Set default MDC clock divisor (can still be programmed) in Pele.</desc>
<sw_param offset="0xe000b290" start="14" end="12" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg5_gem_dma_bus_width">
<name>gem_dma_bus_width</name>
<desc>Takes the value of the `gem_dma_bus_width_def DEFINE. Limit to 32-bit AHB bus in Pele</desc>
<sw_param offset="0xe000b290" start="11" end="10" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg5_gem_phy_ident">
<name>gem_phy_ident</name>
<desc>Takes the value of the `gem_phy_ident DEFINE. Undefined in Pele. Only used in PCS.</desc>
<sw_param offset="0xe000b290" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg5_gem_tsu">
<name>gem_tsu</name>
<desc>Takes the value of the `gem_tsu DEFINE. Defined in Pele. Include support for 1588 Time Stamp Unit</desc>
<sw_param offset="0xe000b290" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg5_gem_tx_fifo_cnt_width">
<name>gem_tx_fifo_cnt_width</name>
<desc>Takes the value of the `gem_tx_fifo_cnt_width DEFINE. Width for `gem_tx_fifo_size</desc>
<sw_param offset="0xe000b290" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg5_gem_rx_fifo_cnt_width">
<name>gem_rx_fifo_cnt_width</name>
<desc>Takes the value of the `gem_rx_fifo_cnt_width DEFINE. Width for `gem_rx_fifo_size.</desc>
<sw_param offset="0xe000b290" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg6_reserved">
<name>reserved</name>
<desc>Reserved. Set to zero.</desc>
<sw_param offset="0xe000b294" start="31" end="12" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg6_gem_tx_pbufq_seg_sz">
<name>gem_tx_pbufq_seg_sz</name>
<desc>Takes the value of the `gem_tx_pbuf_queue_segment_size DEFINE. Uses default GEM value in Pele. Ignored, no priority dma.</desc>
<sw_param offset="0xe000b294" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg6_dma_priority_queue7">
<name>dma_priority_queue7</name>
<desc>Takes the value of the `dma_priority_queue7 DEFINE. Undefined. No priority DMA In Pele.</desc>
<sw_param offset="0xe000b294" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg6_dma_priority_queue6">
<name>dma_priority_queue6</name>
<desc>Takes the value of the `dma_priority_queue6 DEFINE. Undefined. No priority DMA In Pele.</desc>
<sw_param offset="0xe000b294" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg6_dma_priority_queue5">
<name>dma_priority_queue5</name>
<desc>Takes the value of the `dma_priority_queue5 DEFINE. Undefined. No priority DMA In Pele.</desc>
<sw_param offset="0xe000b294" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg6_dma_priority_queue4">
<name>dma_priority_queue4</name>
<desc>Takes the value of the `dma_priority_queue4 DEFINE. Undefined. No priority DMA In Pele.</desc>
<sw_param offset="0xe000b294" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg6_dma_priority_queue3">
<name>dma_priority_queue3</name>
<desc>Takes the value of the `dma_priority_queue3 DEFINE. Undefined. No priority DMA In Pele.</desc>
<sw_param offset="0xe000b294" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg6_dma_priority_queue2">
<name>dma_priority_queue2</name>
<desc>Takes the value of the `dma_priority_queue2 DEFINE. Undefined. No priority DMA In Pele.</desc>
<sw_param offset="0xe000b294" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg6_dma_priority_queue1">
<name>dma_priority_queue1</name>
<desc>Takes the value of the `dma_priority_queue1 DEFINE. Undefined. No priority DMA In Pele.</desc>
<sw_param offset="0xe000b294" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg6_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Set to zero.</desc>
<sw_param offset="0xe000b294" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg7_tx_pbuf_numseg_q7">
<name>tx_pbuf_numseg_q7</name>
<desc>Takes the value of the `gem_tx_pbuf_num_segments_q7 DEFINE. Undefined. No priority DMA In Pele.</desc>
<sw_param offset="0xe000b298" start="31" end="28" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg7_tx_pbuf_numseg_q6">
<name>tx_pbuf_numseg_q6</name>
<desc>Takes the value of the `gem_tx_pbuf_num_segments_q6 DEFINE. Undefined. No priority DMA In Pele.</desc>
<sw_param offset="0xe000b298" start="27" end="24" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg7_tx_pbuf_numseg_q5">
<name>tx_pbuf_numseg_q5</name>
<desc>Takes the value of the `gem_tx_pbuf_num_segments_q5 DEFINE. Undefined. No priority DMA In Pele.</desc>
<sw_param offset="0xe000b298" start="23" end="20" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg7_tx_pbuf_numseg_q4">
<name>tx_pbuf_numseg_q4</name>
<desc>Takes the value of the `gem_tx_pbuf_num_segments_q4 DEFINE. Undefined. No priority DMA In Pele.</desc>
<sw_param offset="0xe000b298" start="19" end="16" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg7_tx_pbuf_numseg_q3">
<name>tx_pbuf_numseg_q3</name>
<desc>Takes the value of the `gem_tx_pbuf_num_segments_q3 DEFINE. Undefined. No priority DMA In Pele.</desc>
<sw_param offset="0xe000b298" start="15" end="12" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg7_tx_pbuf_numseg_q2">
<name>tx_pbuf_numseg_q2</name>
<desc>Takes the value of the `gem_tx_pbuf_num_segments_q2 DEFINE. Undefined. No priority DMA In Pele.</desc>
<sw_param offset="0xe000b298" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg7_tx_pbuf_numseg_q1">
<name>tx_pbuf_numseg_q1</name>
<desc>Takes the value of the `gem_tx_pbuf_num_segments_q1 DEFINE. Undefined. No priority DMA In Pele.</desc>
<sw_param offset="0xe000b298" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_gem0_design_cfg7_tx_pbuf_numseg_q0">
<name>tx_pbuf_numseg_q0</name>
<desc>Takes the value of the `gem_tx_pbuf_num_segments_q0 DEFINE. Undefined. No priority DMA In Pele.</desc>
<sw_param offset="0xe000b298" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_qspi_Config_reg_leg_flsh">
<name>leg_flsh</name>
<desc>Flash memory interface mode control:
0 = legacy SPI mode
1 = Flash memory interface mode
This control is required to enable or disable automatic recognition of instruction bytes in the first byte of a transfer.
If this mode is disabled, the core will operate in standard SPI mode, with no dual- or quad-bit input or output capability; the extended bits will be configured as inputs to prevent any driver contention on these pins.
If enabled, flash memory interface instructions are automatically recognized and the I/O configured accordingly.</desc>
<sw_param offset="0xe000d000" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_qspi_Config_reg_reserved_5">
<name>reserved_4</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe000d000" start="30" end="27" />
</parameter>
<parameter uniqueid="ps7_qspi_Config_reg_endian">
<name>endian</name>
<desc>0 for little endian format when writing to the transmit data register 0x1C or reading from the receive data register 0x20.
1 for big endian format when writing to the transmit data register 0x1C or reading from the receive data register 0x20.</desc>
<sw_param offset="0xe000d000" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_qspi_Config_reg_reserved_4">
<name>reserved_4</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe000d000" start="25" end="20" />
</parameter>
<parameter uniqueid="ps7_qspi_Config_reg_Holdb_dr">
<name>Holdb_dr</name>
<desc>Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required.
Both pins are always driven by the controller in quad mode.</desc>
<sw_param offset="0xe000d000" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_qspi_Config_reg_reserved_3">
<name>reserved_3</name>
<desc>Reserved</desc>
<sw_param offset="0xe000d000" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_qspi_Config_reg_reserved_2">
<name>reserved_2</name>
<desc>Reserved, do not modify</desc>
<sw_param offset="0xe000d000" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_qspi_Config_reg_Man_start_com">
<name>Man_start_com</name>
<desc>Manual Start Command
1 = start transmission of data
0 = don't care</desc>
<sw_param offset="0xe000d000" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_qspi_Config_reg_Man_start_en">
<name>Man_start_en</name>
<desc>Manual Start Enable
1 = enables maual start
0 = auto mode</desc>
<sw_param offset="0xe000d000" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_qspi_Config_reg_Manual_CS">
<name>Manual_CS</name>
<desc>Manual CS
1 = manual CS mode
0 = auto mode</desc>
<sw_param offset="0xe000d000" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_qspi_Config_reg_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe000d000" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_qspi_Config_reg_PCS">
<name>PCS</name>
<desc>Peripheral chip select line, directly drive n_ss_out if Manual_C is set</desc>
<sw_param offset="0xe000d000" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_qspi_Config_reg_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe000d000" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_qspi_Config_reg_REF_CLK">
<name>REF_CLK</name>
<desc>Master reference clock select
1 = use ext_clk
0 = use SPI REFERENCE CLOCK</desc>
<sw_param offset="0xe000d000" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_qspi_Config_reg_FIFO_WIDTH">
<name>FIFO_WIDTH</name>
<desc>FIFO width
00 = 8bits
01 = 16bits
10 = 24bits
11 = 32bits</desc>
<sw_param offset="0xe000d000" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_qspi_Config_reg_BAUD_RATE_DIV">
<name>BAUD_RATE_DIV</name>
<desc>Master mode baud rate divisor
000 = divide by 2
001 = divide by 4
010 = divide by 8
011 = divide by 16
100 = divide by 32
101 = divide by 64
110 = divide by 128
111 = divide by 256</desc>
<sw_param offset="0xe000d000" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_qspi_Config_reg_CLK_PH">
<name>CLK_PH</name>
<desc>Clock phase
1 = the SPI clock is inactive outside the word
0 = the SPI clock is active outside the word</desc>
<sw_param offset="0xe000d000" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_qspi_Config_reg_CLK_POL">
<name>CLK_POL</name>
<desc>Clock polarity outside SPI word
1 = the SPI clock is quiescent high
0 = the SPI clock is quiescent low</desc>
<sw_param offset="0xe000d000" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_qspi_Config_reg_MODE_SEL">
<name>MODE_SEL</name>
<desc>Mode select
1 = the SPI is in master mode
0 = the SPI is in slave mode</desc>
<sw_param offset="0xe000d000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_qspi_Intr_status_REG_reserved_1">
<name>reserved_1</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe000d004" start="31" end="7" />
</parameter>
<parameter uniqueid="ps7_qspi_Intr_status_REG_TX_FIFO_underflow">
<name>TX_FIFO_underflow</name>
<desc>TX FIFO underflow
1 = underflow is detected
0 = no underflow has been detected</desc>
<sw_param offset="0xe000d004" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_qspi_Intr_status_REG_RX_FIFO_full">
<name>RX_FIFO_full</name>
<desc>RX FIFO full
1 = FIFO is full
0 = FIFO is not full</desc>
<sw_param offset="0xe000d004" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_qspi_Intr_status_REG_RX_FIFO_not_empty">
<name>RX_FIFO_not_empty</name>
<desc>RX FIFO not empty
1 = FIFO has more than or equal to THRESHOLD entries
0 = FIFO has less than RX THRESHOLD entries</desc>
<sw_param offset="0xe000d004" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_qspi_Intr_status_REG_TX_FIFO_full">
<name>TX_FIFO_full</name>
<desc>TX FIFO full
1 = FIFO is full
0 = FIFO is not full</desc>
<sw_param offset="0xe000d004" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_qspi_Intr_status_REG_TX_FIFO_not_full">
<name>TX_FIFO_not_full</name>
<desc>TX FIFO not full
1 = FIFO has less than THRESHOLD entries
0 = FIFO has more than or equal toTHRESHOLD entries</desc>
<sw_param offset="0xe000d004" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_qspi_Intr_status_REG_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe000d004" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_qspi_Intr_status_REG_RX_OVERFLOW">
<name>RX_OVERFLOW</name>
<desc>Receive Overflow interrupt
1 = overflow occured
0 = no overflow occurred</desc>
<sw_param offset="0xe000d004" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_qspi_Intrpt_en_REG_reserved_1">
<name>reserved_1</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe000d008" start="31" end="7" />
</parameter>
<parameter uniqueid="ps7_qspi_Intrpt_en_REG_TX_FIFO_underflow">
<name>TX_FIFO_underflow</name>
<desc>TX FIFO underflow
enable
1 = enable the interrupt
0 = no effect</desc>
<sw_param offset="0xe000d008" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_qspi_Intrpt_en_REG_RX_FIFO_full">
<name>RX_FIFO_full</name>
<desc>RX FIFO full
enable
1 = enable the interrupt
0 = no effect</desc>
<sw_param offset="0xe000d008" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_qspi_Intrpt_en_REG_RX_FIFO_not_empty">
<name>RX_FIFO_not_empty</name>
<desc>RX FIFO not empty
enable
1 = enable the interrupt
0 = no effect</desc>
<sw_param offset="0xe000d008" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_qspi_Intrpt_en_REG_TX_FIFO_full">
<name>TX_FIFO_full</name>
<desc>TX FIFO full
enable
1 = enable the interrupt
0 = no effect</desc>
<sw_param offset="0xe000d008" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_qspi_Intrpt_en_REG_TX_FIFO_not_full">
<name>TX_FIFO_not_full</name>
<desc>TX FIFO not full
enable
1 = enable the interrupt
0 = no effect</desc>
<sw_param offset="0xe000d008" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_qspi_Intrpt_en_REG_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe000d008" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_qspi_Intrpt_en_REG_RX_OVERFLOW">
<name>RX_OVERFLOW</name>
<desc>Receive Overflow interrupt enable
1 = enable the interrupt
0 = no effect</desc>
<sw_param offset="0xe000d008" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_qspi_Intrpt_dis_REG_reserved_1">
<name>reserved_1</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe000d00c" start="31" end="7" />
</parameter>
<parameter uniqueid="ps7_qspi_Intrpt_dis_REG_TX_FIFO_underflow">
<name>TX_FIFO_underflow</name>
<desc>TX FIFO underflow
enable
1 = disables the interrupt
0 = no effect</desc>
<sw_param offset="0xe000d00c" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_qspi_Intrpt_dis_REG_RX_FIFO_full">
<name>RX_FIFO_full</name>
<desc>RX FIFO full
enable
1 = disables the interrupt
0 = no effect</desc>
<sw_param offset="0xe000d00c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_qspi_Intrpt_dis_REG_RX_FIFO_not_empty">
<name>RX_FIFO_not_empty</name>
<desc>RX FIFO not empty
enable
1 = disables the interrupt
0 = no effect</desc>
<sw_param offset="0xe000d00c" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_qspi_Intrpt_dis_REG_TX_FIFO_full">
<name>TX_FIFO_full</name>
<desc>TX FIFO full
enable
1 = disables the interrupt
0 = no effect</desc>
<sw_param offset="0xe000d00c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_qspi_Intrpt_dis_REG_TX_FIFO_not_full">
<name>TX_FIFO_not_full</name>
<desc>TX FIFO not full
enable
1 = disables the interrupt
0 = no effect</desc>
<sw_param offset="0xe000d00c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_qspi_Intrpt_dis_REG_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe000d00c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_qspi_Intrpt_dis_REG_RX_OVERFLOW">
<name>RX_OVERFLOW</name>
<desc>Receive Overflow interrupt enable
1 = disables the interrupt
0 = no effect</desc>
<sw_param offset="0xe000d00c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_qspi_Intrpt_mask_REG_reserved_1">
<name>reserved_1</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe000d010" start="31" end="7" />
</parameter>
<parameter uniqueid="ps7_qspi_Intrpt_mask_REG_TX_FIFO_underflow">
<name>TX_FIFO_underflow</name>
<desc>TX FIFO underflow
enable
1 = interrupt is disabled
0 = interrupt is enabled</desc>
<sw_param offset="0xe000d010" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_qspi_Intrpt_mask_REG_RX_FIFO_full">
<name>RX_FIFO_full</name>
<desc>RX FIFO full
enable
1 = interrupt is disabled
0 = interrupt is enabled</desc>
<sw_param offset="0xe000d010" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_qspi_Intrpt_mask_REG_RX_FIFO_not_empty">
<name>RX_FIFO_not_empty</name>
<desc>RX FIFO not empty
enable
1 = interrupt is disabled
0 = interrupt is enabled</desc>
<sw_param offset="0xe000d010" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_qspi_Intrpt_mask_REG_TX_FIFO_full">
<name>TX_FIFO_full</name>
<desc>TX FIFO full
enable
1 = interrupt is disabled
0 = interrupt is enabled</desc>
<sw_param offset="0xe000d010" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_qspi_Intrpt_mask_REG_TX_FIFO_not_full">
<name>TX_FIFO_not_full</name>
<desc>TX FIFO not full
enable
1 = interrupt is disabled
0 = interrupt is enabled</desc>
<sw_param offset="0xe000d010" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_qspi_Intrpt_mask_REG_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe000d010" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_qspi_Intrpt_mask_REG_RX_OVERFLOW">
<name>RX_OVERFLOW</name>
<desc>Receive Overflow interrupt enable
1 = interrupt is disabled
0 = interrupt is enabled</desc>
<sw_param offset="0xe000d010" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_qspi_En_REG_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe000d014" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_qspi_En_REG_SPI_EN">
<name>SPI_EN</name>
<desc>SPI_Enable
1 = enable the SPI
0 = disable the SPI</desc>
<sw_param offset="0xe000d014" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_qspi_Delay_REG_d_nss">
<name>d_nss</name>
<desc>Delay in SPI REFERENCE CLOCK or ext_clk cycles
for the length that the master mode chip select outputs are de-asserted between words when cpha=0.</desc>
<sw_param offset="0xe000d018" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_qspi_Delay_REG_d_btwn">
<name>d_btwn</name>
<desc>Delay in SPI REFERENCE CLOCK or ext_clk cycles
between one chip select being de-activated and the
activation of another</desc>
<sw_param offset="0xe000d018" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_qspi_Delay_REG_d_after">
<name>d_after</name>
<desc>Delay in SPI REFERENCE CLOCK or ext_clk cycles between last bit of current word and the first bit of the next word.</desc>
<sw_param offset="0xe000d018" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_qspi_Delay_REG_d_int">
<name>d_int</name>
<desc>Added delay in SPI REFERENCE CLOCK or ext_clk
cycles between setting n_ss_out low and first bit
transfer.</desc>
<sw_param offset="0xe000d018" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_qspi_TXD0_TXD">
<name>TXD</name>
<desc>Data to TX FIFO, for 4-byte instruction for normal read/write data transfer.</desc>
<sw_param offset="0xe000d01c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_qspi_Rx_data_REG_RX_FIFO_data">
<name>RX_FIFO_data</name>
<desc>Data from TX FIFO</desc>
<sw_param offset="0xe000d020" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_qspi_Slave_Idle_count_REG_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe000d024" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_qspi_Slave_Idle_count_REG_Slave_Idle_coun">
<name>Slave_Idle_coun</name>
<desc>SPI in slave mode detects a start only when the
external SPI master serial clock (sclk_in) is stable
(quiescent state) for SPI REFERENCE CLOCK cycles
specified by slave idle count register or when the SPI
is deselected.</desc>
<sw_param offset="0xe000d024" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_qspi_TX_thres_REG_DEPTH_of_TX_FIFO">
<name>DEPTH_of_TX_FIFO</name>
<desc>Defines the level at which the TX FIFO not full interrupt is generated</desc>
<sw_param offset="0xe000d028" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_qspi_RX_thres_REG_DEPTH_of_RX_FIFO">
<name>DEPTH_of_RX_FIFO</name>
<desc>Defines the level at which the RX FIFO not empty interrupt is generated</desc>
<sw_param offset="0xe000d02c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_qspi_GPIO_reserved">
<name>reserved</name>
<desc>Reserved for future GPIO.</desc>
<sw_param offset="0xe000d030" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_qspi_GPIO_WP_N">
<name>WP_N</name>
<desc>Write Protect.
Write Protect output for flash devices supporting this function.
Active low (may be inverted externally to the core if required for flash devices requiring active high write protect signal.)</desc>
<sw_param offset="0xe000d030" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_qspi_LPBK_DLY_ADJ_reserved">
<name>reserved</name>
<desc>Reserved.</desc>
<sw_param offset="0xe000d038" start="31" end="9" />
</parameter>
<parameter uniqueid="ps7_qspi_LPBK_DLY_ADJ_LPBK_SEL">
<name>LPBK_SEL</name>
<desc>Loopback clock select:
0 - loopback at pad
1 - loopback through external connections</desc>
<sw_param offset="0xe000d038" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_qspi_LPBK_DLY_ADJ_LPBK_PH">
<name>LPBK_PH</name>
<desc>Loopback clock phase selection. 0 - normal, 1 - inverted</desc>
<sw_param offset="0xe000d038" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_qspi_LPBK_DLY_ADJ_reserved_1">
<name>reserved_1</name>
<desc>Reserved, do not modify</desc>
<sw_param offset="0xe000d038" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_qspi_LPBK_DLY_ADJ_USE_LPBK">
<name>USE_LPBK</name>
<desc>Use external loopback master clock for read data capturing when baud rate divisor (reg 0x00) is 2.</desc>
<sw_param offset="0xe000d038" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_qspi_LPBK_DLY_ADJ_DLY1">
<name>DLY1</name>
<desc>Delay adjustment (00, 01, 10, 11) for 0, 0.4, 0.8 or 1.2 ns, this is added to DLY0 to form the overall delay.</desc>
<sw_param offset="0xe000d038" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_qspi_LPBK_DLY_ADJ_DLY0">
<name>DLY0</name>
<desc>Delay adjustment step, 0 to 7, each step is around 0.2 ns.</desc>
<sw_param offset="0xe000d038" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_qspi_TXD1_TXD">
<name>TXD</name>
<desc>Data to TX FIFO, for 1-byte instruction, not for normal data transfer.
In little endian mode (default), only bits 7:0 are valid, bits 31:8 are ignored.
In big endian mode, only the 8 MS bits are valid.</desc>
<sw_param offset="0xe000d080" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_qspi_TXD2_TXD">
<name>TXD</name>
<desc>Data to TX FIFO, for 2-byte instruction, not for normal data transfer.
In little endian mode (default), only bits 15:0 are valid, bits 31:16 are ignored.
In big endian mode, only the 16 MS bits are valid.</desc>
<sw_param offset="0xe000d084" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_qspi_TXD3_TXD">
<name>TXD</name>
<desc>Data to TX FIFO, for 3-byte instruction, not for normal data transfer.
In little endian mode (default), only bits 23:0 are valid, bits 31:24 are ignored.
In big endian mode, only the 24 MS bits are valid.</desc>
<sw_param offset="0xe000d088" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_qspi_LQSPI_CFG_LQ_MODE">
<name>LQ_MODE</name>
<desc>Linear quad SPI mode, if set, else quad SPI mode</desc>
<sw_param offset="0xe000d0a0" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_qspi_LQSPI_CFG_TWO_MEM">
<name>TWO_MEM</name>
<desc>Both upper and lower memories are active, if set</desc>
<sw_param offset="0xe000d0a0" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_qspi_LQSPI_CFG_SEP_BUS">
<name>SEP_BUS</name>
<desc>Separate memory bus, if set.
Only has meaning if bit 30 is set</desc>
<sw_param offset="0xe000d0a0" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_qspi_LQSPI_CFG_U_PAGE">
<name>U_PAGE</name>
<desc>Upper memory page, if set.
Only has meaning if bit 30 is set AND bit 29 is clear AND bit 31 is clear.
In LQSPI mode, address bit 25 will indicate lower (0) or upper (1) page.
In IO mode, this bit is used to select the lower or upper memory for configuration or read/write operations.</desc>
<sw_param offset="0xe000d0a0" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_qspi_LQSPI_CFG_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe000d0a0" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_qspi_LQSPI_CFG_reserved_1">
<name>reserved_1</name>
<desc>Reserved.
Write to this location may lead to unpredictable behavior.</desc>
<sw_param offset="0xe000d0a0" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_qspi_LQSPI_CFG_MODE_EN">
<name>MODE_EN</name>
<desc>Enable MODE_BITS[23:16] to be sent, if set.
This bit MUST BE SET for dual I/O or quad I/O read (specified through [7:0]).
This bit MUST BE CLEAR for all other read modes as they do not have mode bits.
If this bit is 0, bits 24, and [23:16] are ignored.
Here is a summary of how bits 25, 24 and 23:16 are related.
Bit 25
bit 24
bits 23:16
0
x
x
1
0
not 8'bxx10xxxx
1
1
8'bxx10xxxx</desc>
<sw_param offset="0xe000d0a0" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_qspi_LQSPI_CFG_MODE_ON">
<name>MODE_ON</name>
<desc>This bit is only relevant if bit 25 is set, else it is ignored.
If this bit is set, instruction code is only sent for the very first read transfer.
If this bit is clear, instruction code will be sent for all read transfers.
This bit is configured in association with the MODE_BITS.
For Winbond devices, this bit MUST BE SET if the MODE_BITS are 8'bxx10xxxx, else this bit MUST BE CLEAR.</desc>
<sw_param offset="0xe000d0a0" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_qspi_LQSPI_CFG_MODE_BITS">
<name>MODE_BITS</name>
<desc>These bits are only relevant if bit 25 is set, else it is ignored.
If bit 25 is set, this value is required for both dual I/O read and quad I/O read.
See vendor's datasheet for more information.
For Winbond's device, the continuous read mode value is 8'bxx10xxxx to skip the instruction code for the next read transfer, else instruction code is sent for all read transfers.
Bit 24 has to be configured accordingly with this value.</desc>
<sw_param offset="0xe000d0a0" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_qspi_LQSPI_CFG_reserved_2">
<name>reserved_2</name>
<desc>Reserved, value is undefined when read.</desc>
<sw_param offset="0xe000d0a0" start="15" end="11" />
</parameter>
<parameter uniqueid="ps7_qspi_LQSPI_CFG_DUMMY_BYTE">
<name>DUMMY_BYTE</name>
<desc>Number of dummy bytes between address and return read data</desc>
<sw_param offset="0xe000d0a0" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_qspi_LQSPI_CFG_INST_CODE">
<name>INST_CODE</name>
<desc>Read instruction code.
The known read instruction codes are:
8'h03 - Read
8'h0B - Fast read
8'h3B - Fast read dual output
8'h6B - Fast read quad output
8'hBB - Fast read dual I/O
8'hEB - Fast read quad I/O</desc>
<sw_param offset="0xe000d0a0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_qspi_LQSPI_STS_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe000d0a4" start="8" end="3" />
</parameter>
<parameter uniqueid="ps7_qspi_LQSPI_STS_D_FSM_ERR">
<name>D_FSM_ERR</name>
<desc>Data FSM error, if set</desc>
<sw_param offset="0xe000d0a4" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_qspi_LQSPI_STS_WR_RECVD">
<name>WR_RECVD</name>
<desc>AXI write command received, if set</desc>
<sw_param offset="0xe000d0a4" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_qspi_LQSPI_STS_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe000d0a4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_qspi_MOD_ID_a">
<name>a</name>
<desc>Module ID value.</desc>
<sw_param offset="0xe000d0fc" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_SRR_reserved">
<name>reserved</name>
<desc>Reserved.</desc>
<sw_param offset="0xe0009000" start="31" end="2" />
</parameter>
<parameter uniqueid="ps7_can1_SRR_CEN">
<name>CEN</name>
<desc>Can Enable
The Enable bit for the CAN controller.
1 = The CAN controller is in Loop Back, Sleep or Normal mode depending on the LBACK and SLEEP bits in the MSR.
0 = The CAN controller is in the Configuration mode.
If the CEN bit is changed during core operation, it is
recommended to reset the core so that operations start afresh.</desc>
<sw_param offset="0xe0009000" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_can1_SRR_SRST">
<name>SRST</name>
<desc>Reset
The Software reset bit for the CAN controller.
1 = CAN controller is reset.
If a 1 is written to this bit, all the CAN controller configuration registers (including the SRR) are reset. Reads to this bit always return a 0.</desc>
<sw_param offset="0xe0009000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_MSR_reserved">
<name>reserved</name>
<desc>Reserved.</desc>
<sw_param offset="0xe0009004" start="31" end="3" />
</parameter>
<parameter uniqueid="ps7_can1_MSR_SNOOP">
<name>SNOOP</name>
<desc>Snoop Mode Select
The Snoop Mode Select bit.
1 = CAN controller is in Snoop mode.
0 = CAN controller is in Normal, Loop Back, Configuration, or Sleep mode.
This bit can be written to only when CEN bit in SRR is 0.</desc>
<sw_param offset="0xe0009004" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_can1_MSR_LBACK">
<name>LBACK</name>
<desc>Loop Back Mode Select
The Loop Back Mode Select bit.
1 = CAN controller is in Loop Back mode.
0 = CAN controller is in Normal, Snoop, Configuration, or Sleep mode.
This bit can be written to only when CEN bit in SRR is 0.</desc>
<sw_param offset="0xe0009004" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_can1_MSR_SLEEP">
<name>SLEEP</name>
<desc>Sleep Mode Select
The Sleep Mode select bit.
1 = CAN controller is in Sleep mode.
0 = CAN controller is in Normal, Snoop, Configuration or Loop Back mode.
This bit is cleared when the CAN controller wakes up from the Sleep mode.</desc>
<sw_param offset="0xe0009004" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_BRPR_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0009008" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_can1_BRPR_BRP">
<name>BRP</name>
<desc>Baud Rate Prescaler
These bits indicate the prescaler value. The actual
value ranges from 1 to 256.</desc>
<sw_param offset="0xe0009008" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_BTR_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe000900c" start="31" end="9" />
</parameter>
<parameter uniqueid="ps7_can1_BTR_SJW">
<name>SJW</name>
<desc>Synchronization Jump Width
Indicates the Synchronization Jump Width as specified in the CAN 2.0A and CAN 2.0B standard. The actual value is one more than the value written to the register.</desc>
<sw_param offset="0xe000900c" start="8" end="7" />
</parameter>
<parameter uniqueid="ps7_can1_BTR_TS2">
<name>TS2</name>
<desc>Time Segment 2
Indicates Phase Segment 2 as specified in the CAN 2.0A and CAN 2.0B standard. The actual value is one more than the value written to the register.</desc>
<sw_param offset="0xe000900c" start="6" end="4" />
</parameter>
<parameter uniqueid="ps7_can1_BTR_TS1">
<name>TS1</name>
<desc>Time Segment 1
Indicates the Sum of Propagation Segment and Phase
Segment 1 as specified in the CAN 2.0A and CAN 2.0B
standard. The actual value is one more than the value
written to the register.</desc>
<sw_param offset="0xe000900c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_ECR_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0009010" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_can1_ECR_REC">
<name>REC</name>
<desc>Receive Error Counter
Indicates the Value of the Receive Error Counter.</desc>
<sw_param offset="0xe0009010" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_can1_ECR_TEC">
<name>TEC</name>
<desc>Transmit Error Counter
Indicates the Value of the Transmit Error Counter.</desc>
<sw_param offset="0xe0009010" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_ESR_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0009014" start="31" end="5" />
</parameter>
<parameter uniqueid="ps7_can1_ESR_ACKER">
<name>ACKER</name>
<desc>ACK Error
Indicates an acknowledgement error.
1 = Indicates an acknowledgement error has
occurred.
0 = Indicates an acknowledgement error has not
occurred on the bus since the last write to this
register.
If this bit is set, writing a 1 clears it.</desc>
<sw_param offset="0xe0009014" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_can1_ESR_BERR">
<name>BERR</name>
<desc>Bit Error
Indicates the received bit is not the same as the
transmitted bit during bus communication.
1 = Indicates a bit error has occurred.
0 = Indicates a bit error has not occurred on the bus
since the last write to this register.
If this bit is set, writing a 1 clears it.</desc>
<sw_param offset="0xe0009014" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_can1_ESR_STER">
<name>STER</name>
<desc>Stuff Error
Indicates an error if there is a stuffing violation.
1 = Indicates a stuff error has occurred.
0 = Indicates a stuff error has not occurred on the
bus since the last write to this register.
If this bit is set, writing a 1 clears it.</desc>
<sw_param offset="0xe0009014" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_can1_ESR_FMER">
<name>FMER</name>
<desc>Form Error
Indicates an error in one of the fixed form fields in the
message frame.
1 = Indicates a form error has occurred.
0 = Indicates a form error has not occurred on the
bus since the last write to this register.
If this bit is set, writing a 1 clears it.</desc>
<sw_param offset="0xe0009014" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_can1_ESR_CRCER">
<name>CRCER</name>
<desc>CRC Error
Indicates a CRC error has occurred.
1 = Indicates a CRC error has occurred.
0 = Indicates a CRC error has not occurred on the
bus since the last write to this register.
If this bit is set, writing a 1 clears it.
In case of a CRC Error and a CRC delimiter corruption, only the FMER bit is set.</desc>
<sw_param offset="0xe0009014" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_SR_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0009018" start="31" end="13" />
</parameter>
<parameter uniqueid="ps7_can1_SR_SNOOP">
<name>SNOOP</name>
<desc>Snoop Mode
Indicates the CAN controller is in Snoop Mode.
1 = Indicates the CAN controller is in Snoop Mode.
0 = Indicates the CAN controller is not in Snoop mode.</desc>
<sw_param offset="0xe0009018" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_can1_SR_ACFBSY">
<name>ACFBSY</name>
<desc>Acceptance Filter Busy
This bit indicates that the Acceptance Filter Mask
Registers and the Acceptance Filter ID Registers
cannot be written to.
1 = Acceptance Filter Mask Registers and
Acceptance Filter ID Registers cannot be written
to.
0 = Acceptance Filter Mask Registers and the
Acceptance Filter ID Registers can be written to.
This bit exists only when the number of acceptance
filters is not 0
This bit is set when a 0 is written to any of the valid
UAF bits in the Acceptance Filter Register.</desc>
<sw_param offset="0xe0009018" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_can1_SR_TXFLL">
<name>TXFLL</name>
<desc>Transmit FIFO Full
Indicates that the TX FIFO is full.
1 = Indicates the TX FIFO is full.
0 = Indicates the TX FIFO is not full.</desc>
<sw_param offset="0xe0009018" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_can1_SR_TXBFLL">
<name>TXBFLL</name>
<desc>High Priority Transmit Buffer Full
Indicates the High Priority Transmit Buffer is full.
1 = Indicates the High Priority Transmit Buffer is full.
0 = Indicates the High Priority Transmit Buffer is not full.</desc>
<sw_param offset="0xe0009018" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_can1_SR_ESTAT">
<name>ESTAT</name>
<desc>Error Status
Indicates the error status of the CAN controller.
00 = Indicates Configuration Mode (CONFIG = 1).
Error State is undefined.
01 = Indicates Error Active State.
11 = Indicates Error Passive State.
10 = Indicates Bus Off State.</desc>
<sw_param offset="0xe0009018" start="8" end="7" />
</parameter>
<parameter uniqueid="ps7_can1_SR_ERRWRN">
<name>ERRWRN</name>
<desc>Error Warning
Indicates that either the Transmit Error counter or the
Receive Error counter has exceeded a value of 96.
1 = One or more error counters have a value greater
than or equal to 96.
0 = Neither of the error counters has a value greater
than or equal to 96.</desc>
<sw_param offset="0xe0009018" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_can1_SR_BBSY">
<name>BBSY</name>
<desc>Bus Busy
Indicates the CAN bus status.
1 = Indicates that the CAN controller is either
receiving a message or transmitting a message.
0 = Indicates that the CAN controller is either in
Configuration mode or the bus is idle.</desc>
<sw_param offset="0xe0009018" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_can1_SR_BIDLE">
<name>BIDLE</name>
<desc>Bus Idle
Indicates the CAN bus status.
1 = Indicates no bus communication is taking place.
0 = Indicates the CAN controller is either in
Configuration mode or the bus is busy.</desc>
<sw_param offset="0xe0009018" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_can1_SR_NORMAL">
<name>NORMAL</name>
<desc>Normal Mode
Indicates the CAN controller is in Normal Mode.
1 = Indicates the CAN controller is in Normal Mode.
0 = Indicates the CAN controller is not in Normal
mode.</desc>
<sw_param offset="0xe0009018" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_can1_SR_SLEEP">
<name>SLEEP</name>
<desc>Sleep Mode
Indicates the CAN controller is in Sleep mode.
1 = Indicates the CAN controller is in Sleep mode.
0 = Indicates the CAN controller is not in Sleep mode.</desc>
<sw_param offset="0xe0009018" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_can1_SR_LBACK">
<name>LBACK</name>
<desc>Loop Back Mode
Indicates the CAN controller is in Loop Back mode.
1 = Indicates the CAN controller is in Loop Back
mode.
0 = Indicates the CAN controller is not in Loop Back
mode.</desc>
<sw_param offset="0xe0009018" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_can1_SR_CONFIG">
<name>CONFIG</name>
<desc>Configuration Mode Indicator
Indicates the CAN controller is in Configuration mode.
1 = Indicates the CAN controller is in Configuration
mode.
0 = Indicates the CAN controller is not in
Configuration mode.</desc>
<sw_param offset="0xe0009018" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_ISR_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xe000901c" start="31" end="15" />
</parameter>
<parameter uniqueid="ps7_can1_ISR_TXFEMP">
<name>TXFEMP</name>
<desc>Transmit FIFO EmptyInterrupt
A 1 indicates that the Transmit FIFO is empty.
The interrupt continues to assert as long as the TX
FIFO is empty.
This bit can be cleared only by writing to the ICR.</desc>
<sw_param offset="0xe000901c" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_can1_ISR_TXFWMEMP">
<name>TXFWMEMP</name>
<desc>Transmit FIFO Watermark Empty Interrupt
A 1 indicates that the TX FIFO is empty based on
watermark programming.
The interrupt continues to assert as long as the number
of empty spaces in the TX FIFO is greater than TX FIFO
empty watermark.
This bit can be cleared only by writing to the Interrupt
Clear Register.</desc>
<sw_param offset="0xe000901c" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_can1_ISR_RXFWMFLL">
<name>RXFWMFLL</name>
<desc>Receive FIFO Watermark Full Interrupt
A 1 indicates that the RX FIFO is full based on
watermark programming.
The interrupt continues to assert as long as the RX
FIFO count is above RX FIFO Full watermark.
This bit can be cleared only by writing to the Interrupt
Clear Register.</desc>
<sw_param offset="0xe000901c" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_can1_ISR_WKUP">
<name>WKUP</name>
<desc>Wake up Interrupt
A 1 indicates that the CAN controller entered Normal
mode from Sleep Mode.
This bit can be cleared by writing to the ICR.
This bit is also cleared when a 0 is written to the CEN
bit in the SRR.</desc>
<sw_param offset="0xe000901c" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_can1_ISR_SLP">
<name>SLP</name>
<desc>Sleep Interrupt
A 1 indicates that the CAN controller entered Sleep mode.
This bit can be cleared by writing to the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.</desc>
<sw_param offset="0xe000901c" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_can1_ISR_BSOFF">
<name>BSOFF</name>
<desc>Bus Off Interrupt
A 1 indicates that the CAN controller entered the Bus Off state.
This bit can be cleared by writing to the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.</desc>
<sw_param offset="0xe000901c" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_can1_ISR_ERROR">
<name>ERROR</name>
<desc>Error Interrupt
A 1 indicates that an error occurred during message transmission or reception.
This bit can be cleared by writing to the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.</desc>
<sw_param offset="0xe000901c" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_can1_ISR_RXNEMP">
<name>RXNEMP</name>
<desc>Receive FIFO Not Empty Interrupt
A 1 indicates that the Receive FIFO is not empty.
This bit can be cleared only by writing to the ICR.</desc>
<sw_param offset="0xe000901c" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_can1_ISR_RXOFLW">
<name>RXOFLW</name>
<desc>RX FIFO Overflow Interrupt
A 1 indicates that a message has been lost. This condition occurs when a new message is being received and the Receive FIFO is Full.
This bit can be cleared by writing to the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.</desc>
<sw_param offset="0xe000901c" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_can1_ISR_RXUFLW">
<name>RXUFLW</name>
<desc>RX FIFO Underflow Interrupt
A 1 indicates that a read operation was attempted on an empty RX FIFO.
This bit can be cleared only by writing to the ICR.</desc>
<sw_param offset="0xe000901c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_can1_ISR_RXOK">
<name>RXOK</name>
<desc>New Message Received Interrupt
A 1 indicates that a message was received successfully and stored into the RX FIFO.
This bit can be cleared by writing to the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.</desc>
<sw_param offset="0xe000901c" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_can1_ISR_TXBFLL">
<name>TXBFLL</name>
<desc>High Priority Transmit Buffer Full Interrupt
A 1 indicates that the High Priority Transmit Buffer is full.
The status of the bit is unaffected if write transactions occur on the High Priority Transmit Buffer when it is already full.
This bit can be cleared only by writing to the ICR.</desc>
<sw_param offset="0xe000901c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_can1_ISR_TXFLL">
<name>TXFLL</name>
<desc>Transmit FIFO Full Interrupt
A 1 indicates that the TX FIFO is full.
The status of the bit is unaffected if write transactions occur on the Transmit FIFO when it is already full.
This bit can be cleared only by writing to the Interrupt Clear Register.</desc>
<sw_param offset="0xe000901c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_can1_ISR_TXOK">
<name>TXOK</name>
<desc>Transmission Successful Interrupt
A 1 indicates that a message was transmitted successfully.
This bit can be cleared by writing to the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.
In Loop Back mode, both TXOK and RXOK bits are set. The RXOK bit is set before the TXOK bit.</desc>
<sw_param offset="0xe000901c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_can1_ISR_ARBLST">
<name>ARBLST</name>
<desc>Arbitration Lost Interrupt
A 1 indicates that arbitration was lost during message transmission.
This bit can be cleared by writing to the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.</desc>
<sw_param offset="0xe000901c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_IER_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0009020" start="31" end="15" />
</parameter>
<parameter uniqueid="ps7_can1_IER_ETXFEMP">
<name>ETXFEMP</name>
<desc>Enable TXFIFO Empty Interrupt
Writes to this bit enable or disable interrupts when the
TXFEMP bit in the ISR is set.
1 = Enable interrupt generation if TXFEMP bit in ISR is set.
0 = Disable interrupt generation if TXFEMP bit in ISR is set.</desc>
<sw_param offset="0xe0009020" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_can1_IER_ETXFWMEMP">
<name>ETXFWMEMP</name>
<desc>Enable TXFIFO watermark Empty Interrupt
Writes to this bit enable or disable interrupts when the
TXFWMEMP bit in the ISR is set.
1 = Enable interrupt generation if TXFWMEMP bit in ISR is set.
0 = Disable interrupt generation if TXFWMEMP bit in ISR is set.</desc>
<sw_param offset="0xe0009020" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_can1_IER_ERXFWMFLL">
<name>ERXFWMFLL</name>
<desc>Enable RXFIFO watermark Full Interrupt
Writes to this bit enable or disable interrupts when the RXFLL bit in the ISR is set.
1 = Enable interrupt generation if RXFWMFLL bit in ISR is set.
0 = Disable interrupt generation if RXFWMFLL bit in ISR is set.</desc>
<sw_param offset="0xe0009020" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_can1_IER_EWKUP">
<name>EWKUP</name>
<desc>Enable Wake up Interrupt
Writes to this bit enable or disable interrupts when the
WKUP bit in the ISR is set.
1 = Enable interrupt generation if WKUP bit in ISR is set.
0 = Disable interrupt generation if WKUP bit in ISR is set.</desc>
<sw_param offset="0xe0009020" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_can1_IER_ESLP">
<name>ESLP</name>
<desc>Enable Sleep Interrupt
Writes to this bit enable or disable interrupts when the
SLP bit in the ISR is set.
1 = Enable interrupt generation if SLP bit in ISR is set.
0 = Disable interrupt generation if SLP bit in ISR is set.</desc>
<sw_param offset="0xe0009020" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_can1_IER_EBSOFF">
<name>EBSOFF</name>
<desc>Enable Bus OFF Interrupt
Writes to this bit enable or disable interrupts when the
BSOFF bit in the ISR is set.
1 = Enable interrupt generation if BSOFF bit in ISR is set.
0 = Disable interrupt generation if BSOFF bit in ISR is set.</desc>
<sw_param offset="0xe0009020" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_can1_IER_EERROR">
<name>EERROR</name>
<desc>Enable Error Interrupt
Writes to this bit enable or disable interrupts when the
ERROR bit in the ISR is set.
1 = Enable interrupt generation if ERROR bit in ISR is
set.
0 = Disable interrupt generation if ERROR bit in ISR is
set.</desc>
<sw_param offset="0xe0009020" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_can1_IER_ERXNEMP">
<name>ERXNEMP</name>
<desc>Enable Receive FIFO Not Empty Interrupt
Writes to this bit enable or disable interrupts when the
RXNEMP bit in the ISR is set.
1 = Enable interrupt generation if RXNEMP bit in ISR is
set.
0 = Disable interrupt generation if RXNEMP bit in ISR
is set.</desc>
<sw_param offset="0xe0009020" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_can1_IER_ERXOFLW">
<name>ERXOFLW</name>
<desc>Enable RX FIFO Overflow Interrupt
Writes to this bit enable or disable interrupts when the
RXOFLW bit in the ISR is set.
1 = Enable interrupt generation if RXOFLW bit in ISR is
set.
0 = Disable interrupt generation if RXOFLW bit in ISR
is set.</desc>
<sw_param offset="0xe0009020" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_can1_IER_ERXUFLW">
<name>ERXUFLW</name>
<desc>Enable RX FIFO Underflow Interrupt
Writes to this bit enable or disable interrupts when the
RXUFLW bit in the ISR is set.
1 = Enable interrupt generation if RXUFLW bit in ISR is
set.
0 = Disable interrupt generation if RXUFLW bit in ISR is
set.</desc>
<sw_param offset="0xe0009020" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_can1_IER_ERXOK">
<name>ERXOK</name>
<desc>Enable New Message Received Interrupt
Writes to this bit enable or disable interrupts when the
RXOK bit in the ISR is set.
1 = Enable interrupt generation if RXOK bit in ISR is
set.
0 = Disable interrupt generation if RXOK bit in ISR is
set.</desc>
<sw_param offset="0xe0009020" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_can1_IER_ETXBFLL">
<name>ETXBFLL</name>
<desc>Enable High Priority Transmit Buffer Full Interrupt
Writes to this bit enable or disable interrupts when the
TXBFLL bit in the ISR is set.
1 = Enable interrupt generation if TXBFLL bit in ISR is
set.
0 = Disable interrupt generation if TXBFLL bit in ISR is
set.</desc>
<sw_param offset="0xe0009020" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_can1_IER_ETXFLL">
<name>ETXFLL</name>
<desc>Enable Transmit FIFO Full Interrupt
Writes to this bit enable or disable interrupts when
TXFLL bit in the ISR is set.
1 = Enable interrupt generation if TXFLL bit in ISR is
set.
0 = Disable interrupt generation if TXFLL bit in ISR is
set.</desc>
<sw_param offset="0xe0009020" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_can1_IER_ETXOK">
<name>ETXOK</name>
<desc>Enable Transmission Successful Interrupt
Writes to this bit enable or disable interrupts when the
TXOK bit in the ISR is set.
1 = Enable interrupt generation if TXOK bit in ISR is set.
0 = Disable interrupt generation if TXOK bit in ISR is
set.</desc>
<sw_param offset="0xe0009020" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_can1_IER_EARBLST">
<name>EARBLST</name>
<desc>Enable Arbitration Lost Interrupt
Writes to this bit enable or disable interrupts when the
ARBLST bit in the ISR is set.
1 = Enable interrupt generation if ARBLST bit in ISR is
set.
0 = Disable interrupt generation if ARBLST bit in ISR is
set.</desc>
<sw_param offset="0xe0009020" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_ICR_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0009024" start="31" end="15" />
</parameter>
<parameter uniqueid="ps7_can1_ICR_CTXFEMP">
<name>CTXFEMP</name>
<desc>Clear TXFIFO Empty Interrupt
Writing a 1 to this bit clears the TXFEMP bit in the
ISR.</desc>
<sw_param offset="0xe0009024" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_can1_ICR_CTXFWMEMP">
<name>CTXFWMEMP</name>
<desc>Clear TXFIFO Watermark Empty Interrupt
Writing a 1 to this bit clears the TXFWMEMP bit in
the ISR.</desc>
<sw_param offset="0xe0009024" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_can1_ICR_CRXFWMFLL">
<name>CRXFWMFLL</name>
<desc>Clear RXFIFO Watermark Full Interrupt
Writing a 1 to this bit clears the RXFWMFLL bit in
the ISR.</desc>
<sw_param offset="0xe0009024" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_can1_ICR_CWKUP">
<name>CWKUP</name>
<desc>Clear Wake up Interrupt
Writing a 1 to this bit clears the WKUP bit in the ISR.</desc>
<sw_param offset="0xe0009024" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_can1_ICR_CSLP">
<name>CSLP</name>
<desc>Clear Sleep Interrupt
Writing a 1 to this bit clears the SLP bit in the ISR.</desc>
<sw_param offset="0xe0009024" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_can1_ICR_CBSOFF">
<name>CBSOFF</name>
<desc>Clear Bus Off Interrupt
Writing a 1 to this bit clears the BSOFF bit in the
ISR.</desc>
<sw_param offset="0xe0009024" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_can1_ICR_CERROR">
<name>CERROR</name>
<desc>Clear Error Interrupt
Writing a 1 to this bit clears the ERROR bit in the
ISR.</desc>
<sw_param offset="0xe0009024" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_can1_ICR_CRXNEMP">
<name>CRXNEMP</name>
<desc>Clear Receive FIFO Not Empty Interrupt
Writing a 1 to this bit clears the RXNEMP bit in the
ISR.</desc>
<sw_param offset="0xe0009024" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_can1_ICR_CRXOFLW">
<name>CRXOFLW</name>
<desc>Clear RX FIFO Overflow Interrupt
Writing a 1 to this bit clears the RXOFLW bit in the
ISR.</desc>
<sw_param offset="0xe0009024" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_can1_ICR_CRXUFLW">
<name>CRXUFLW</name>
<desc>Clear RX FIFO Underflow Interrupt
Writing a 1 to this bit clears the RXUFLW bit in the
ISR.</desc>
<sw_param offset="0xe0009024" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_can1_ICR_CRXOK">
<name>CRXOK</name>
<desc>Clear New Message Received Interrupt
Writing a 1 to this bit clears the RXOK bit in the ISR.</desc>
<sw_param offset="0xe0009024" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_can1_ICR_CTXBFLL">
<name>CTXBFLL</name>
<desc>Clear High Priority Transmit Buffer Full Interrupt
Writing a 1 to this bit clears the TXBFLL bit in the
ISR.</desc>
<sw_param offset="0xe0009024" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_can1_ICR_CTXFLL">
<name>CTXFLL</name>
<desc>Clear Transmit FIFO Full Interrupt
Writing a 1 to this bit clears the TXFLL bit in the
ISR.</desc>
<sw_param offset="0xe0009024" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_can1_ICR_CTXOK">
<name>CTXOK</name>
<desc>Clear Arbitration Lost Interrupt
Writing a 1 to this bit clears the ARBLST bit in the
ISR.</desc>
<sw_param offset="0xe0009024" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_can1_ICR_CARBLST">
<name>CARBLST</name>
<desc>Clear Arbitration Lost Interrupt
Writing a 1 to this bit clears the ARBLST bit in the
ISR.</desc>
<sw_param offset="0xe0009024" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_TCR_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xe0009028" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_can1_TCR_CTS">
<name>CTS</name>
<desc>Clear Timestamp
Internal free running counter is cleared to 0 when
CTS=1. This bit only needs to be written once with a 1
to clear the counter. The bit will automatically return to
0.</desc>
<sw_param offset="0xe0009028" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_WIR_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xe000902c" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_can1_WIR_EW">
<name>EW</name>
<desc>TXFIFO Empty watermark
TXFIFO generates an EMPTY interrupt based on the
value programmed in this field. The valid range is
(1-63). Only bits 18-23 are writable. No protection is
given for illegal programming in this field.
This field can be written to only when CEN bit in SRR is
0.</desc>
<sw_param offset="0xe000902c" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_can1_WIR_FW">
<name>FW</name>
<desc>RXFIFO Full watermark
RXFIFO generates FULL interrupt based on the value
programmed in this field. The valid range is (1-63). Only
bits 26-31 are writable. No protection is given for illegal
programming in this field. This field can be written to
only when CEN bit in SRR is 0.</desc>
<sw_param offset="0xe000902c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_TXFIFO_ID_IDH">
<name>IDH</name>
<desc>Standard Message ID
The Identifier portion for a Standard Frame is 11 bits.
These bits indicate the Standard Frame ID.
This field is valid for both Standard and Extended
Frames.</desc>
<sw_param offset="0xe0009030" start="31" end="21" />
</parameter>
<parameter uniqueid="ps7_can1_TXFIFO_ID_SRRRTR">
<name>SRRRTR</name>
<desc>Substitute Remote Transmission Request
This bit differentiates between data frames and
remote frames. Valid only for Standard Frames. For
Extended frames this bit is 1.
1 = Indicates that the message frame is a Remote
Frame.
0 = Indicates that the message frame is a Data
Frame.</desc>
<sw_param offset="0xe0009030" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_can1_TXFIFO_ID_IDE">
<name>IDE</name>
<desc>Identifier Extension
This bit differentiates between frames using the
Standard Identifier and those using the Extended
Identifier. Valid for both Standard and Extended
Frames.
1 = Indicates the use of an Extended Message
Identifier.
0= Indicates the use of a Standard Message
Identifier.</desc>
<sw_param offset="0xe0009030" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_can1_TXFIFO_ID_IDL">
<name>IDL</name>
<desc>Extended Message ID
This field indicates the Extended Identifier.
Valid only for Extended Frames.
For Standard Frames, reads from this field return 0s
For Standard Frames, writes to this field should be 0s</desc>
<sw_param offset="0xe0009030" start="18" end="1" />
</parameter>
<parameter uniqueid="ps7_can1_TXFIFO_ID_RTR">
<name>RTR</name>
<desc>Remote Transmission Request
This bit differentiates between data frames and
remote frames.
Valid only for Extended Frames.
1 = Indicates the message object is a Remote Frame
0 = Indicates the message object is a Data Frame
For Standard Frames, reads from this bit returns 0
For Standard Frames, writes to this bit should be 0</desc>
<sw_param offset="0xe0009030" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_TXFIFO_DLC_DLC">
<name>DLC</name>
<desc>Data Length Code
This is the data length portion of the control field of
the CAN frame. This indicates the number valid data
bytes in Data Word 1 and Data Word 2 registers.</desc>
<sw_param offset="0xe0009034" start="31" end="28" />
</parameter>
<parameter uniqueid="ps7_can1_TXFIFO_DLC_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xe0009034" start="27" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_TXFIFO_DATA1_DB0">
<name>DB0</name>
<desc>Data Byte 0
Reads from this field return invalid data if the
message has no data.</desc>
<sw_param offset="0xe0009038" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_can1_TXFIFO_DATA1_DB1">
<name>DB1</name>
<desc>Data Byte 1
Reads from this field return invalid data if the
message has only 1 byte of data or fewer</desc>
<sw_param offset="0xe0009038" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_can1_TXFIFO_DATA1_DB2">
<name>DB2</name>
<desc>Data Byte 2
Reads from this field return invalid data if the
message has only 2 byte of data or fewer</desc>
<sw_param offset="0xe0009038" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_can1_TXFIFO_DATA1_DB3">
<name>DB3</name>
<desc>Data Byte 3
Reads from this field return invalid data if the
message has only 3 byte of data or fewer</desc>
<sw_param offset="0xe0009038" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_TXFIFO_DATA2_DB0">
<name>DB0</name>
<desc>Data Byte 4
Reads from this field return invalid data if the
message has only 4 byte of data or fewer</desc>
<sw_param offset="0xe000903c" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_can1_TXFIFO_DATA2_DB1">
<name>DB1</name>
<desc>Data Byte 5
Reads from this field return invalid data if the
message has only 5 byte of data or fewer</desc>
<sw_param offset="0xe000903c" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_can1_TXFIFO_DATA2_DB2">
<name>DB2</name>
<desc>Data Byte 6
Reads from this field return invalid data if the
message has only 6 byte of data or fewer</desc>
<sw_param offset="0xe000903c" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_can1_TXFIFO_DATA2_DB3">
<name>DB3</name>
<desc>Data Byte 7
Reads from this field return invalid data if the
message has 7 byte of data or fewer</desc>
<sw_param offset="0xe000903c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_TXHPB_ID_IDH">
<name>IDH</name>
<desc>Standard Message ID
The Identifier portion for a Standard Frame is 11 bits.
These bits indicate the Standard Frame ID.
This field is valid for both Standard and Extended
Frames.</desc>
<sw_param offset="0xe0009040" start="31" end="21" />
</parameter>
<parameter uniqueid="ps7_can1_TXHPB_ID_SRRRTR">
<name>SRRRTR</name>
<desc>Substitute Remote Transmission Request
This bit differentiates between data frames and
remote frames. Valid only for Standard Frames. For
Extended frames this bit is 1.
1 = Indicates that the message frame is a Remote
Frame.
0 = Indicates that the message frame is a Data
Frame.</desc>
<sw_param offset="0xe0009040" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_can1_TXHPB_ID_IDE">
<name>IDE</name>
<desc>Identifier Extension
This bit differentiates between frames using the
Standard Identifier and those using the Extended
Identifier. Valid for both Standard and Extended
Frames.
1 = Indicates the use of an Extended Message
Identifier.
0= Indicates the use of a Standard Message
Identifier.</desc>
<sw_param offset="0xe0009040" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_can1_TXHPB_ID_IDL">
<name>IDL</name>
<desc>Extended Message ID
This field indicates the Extended Identifier.
Valid only for Extended Frames.
For Standard Frames, reads from this field return 0s
For Standard Frames, writes to this field should be 0s</desc>
<sw_param offset="0xe0009040" start="18" end="1" />
</parameter>
<parameter uniqueid="ps7_can1_TXHPB_ID_RTR">
<name>RTR</name>
<desc>Remote Transmission Request
This bit differentiates between data frames and
remote frames.
Valid only for Extended Frames.
1 = Indicates the message object is a Remote Frame
0 = Indicates the message object is a Data Frame
For Standard Frames, reads from this bit returns 0
For Standard Frames, writes to this bit should be 0</desc>
<sw_param offset="0xe0009040" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_TXHPB_DLC_DLC">
<name>DLC</name>
<desc>Data Length Code
This is the data length portion of the control field of
the CAN frame. This indicates the number valid data
bytes in Data Word 1 and Data Word 2 registers.</desc>
<sw_param offset="0xe0009044" start="31" end="28" />
</parameter>
<parameter uniqueid="ps7_can1_TXHPB_DLC_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xe0009044" start="27" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_TXHPB_DATA1_DB0">
<name>DB0</name>
<desc>Data Byte 0
Reads from this field return invalid data if the
message has no data.</desc>
<sw_param offset="0xe0009048" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_can1_TXHPB_DATA1_DB1">
<name>DB1</name>
<desc>Data Byte 1
Reads from this field return invalid data if the
message has only 1 byte of data or fewer</desc>
<sw_param offset="0xe0009048" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_can1_TXHPB_DATA1_DB2">
<name>DB2</name>
<desc>Data Byte 2
Reads from this field return invalid data if the
message has only 2 byte of data or fewer</desc>
<sw_param offset="0xe0009048" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_can1_TXHPB_DATA1_DB3">
<name>DB3</name>
<desc>Data Byte 3
Reads from this field return invalid data if the
message has only 3 byte of data or fewer</desc>
<sw_param offset="0xe0009048" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_TXHPB_DATA2_DB0">
<name>DB0</name>
<desc>Data Byte 4
Reads from this field return invalid data if the
message has only 4 byte of data or fewer</desc>
<sw_param offset="0xe000904c" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_can1_TXHPB_DATA2_DB1">
<name>DB1</name>
<desc>Data Byte 5
Reads from this field return invalid data if the
message has only 5 byte of data or fewer</desc>
<sw_param offset="0xe000904c" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_can1_TXHPB_DATA2_DB2">
<name>DB2</name>
<desc>Data Byte 6
Reads from this field return invalid data if the
message has only 6 byte of data or fewer</desc>
<sw_param offset="0xe000904c" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_can1_TXHPB_DATA2_DB3">
<name>DB3</name>
<desc>Data Byte 7
Reads from this field return invalid data if the
message has 7 byte of data or fewer</desc>
<sw_param offset="0xe000904c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_RXFIFO_ID_IDH">
<name>IDH</name>
<desc>Standard Message ID
The Identifier portion for a Standard Frame is 11 bits.
These bits indicate the Standard Frame ID.
This field is valid for both Standard and Extended
Frames.</desc>
<sw_param offset="0xe0009050" start="31" end="21" />
</parameter>
<parameter uniqueid="ps7_can1_RXFIFO_ID_SRRRTR">
<name>SRRRTR</name>
<desc>Substitute Remote Transmission Request
This bit differentiates between data frames and
remote frames. Valid only for Standard Frames. For
Extended frames this bit is 1.
1 = Indicates that the message frame is a Remote
Frame.
0 = Indicates that the message frame is a Data
Frame.</desc>
<sw_param offset="0xe0009050" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_can1_RXFIFO_ID_IDE">
<name>IDE</name>
<desc>Identifier Extension
This bit differentiates between frames using the
Standard Identifier and those using the Extended
Identifier. Valid for both Standard and Extended
Frames.
1 = Indicates the use of an Extended Message
Identifier.
0= Indicates the use of a Standard Message
Identifier.</desc>
<sw_param offset="0xe0009050" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_can1_RXFIFO_ID_IDL">
<name>IDL</name>
<desc>Extended Message ID
This field indicates the Extended Identifier.
Valid only for Extended Frames.
For Standard Frames, reads from this field return 0s
For Standard Frames, writes to this field should be 0s</desc>
<sw_param offset="0xe0009050" start="18" end="1" />
</parameter>
<parameter uniqueid="ps7_can1_RXFIFO_ID_RTR">
<name>RTR</name>
<desc>Remote Transmission Request
This bit differentiates between data frames and
remote frames.
Valid only for Extended Frames.
1 = Indicates the message object is a Remote Frame
0 = Indicates the message object is a Data Frame
For Standard Frames, reads from this bit returns 0
For Standard Frames, writes to this bit should be 0</desc>
<sw_param offset="0xe0009050" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_RXFIFO_DLC_DLC">
<name>DLC</name>
<desc>Data Length Code
This is the data length portion of the control field of
the CAN frame. This indicates the number valid data
bytes in Data Word 1 and Data Word 2 registers.</desc>
<sw_param offset="0xe0009054" start="31" end="28" />
</parameter>
<parameter uniqueid="ps7_can1_RXFIFO_DLC_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xe0009054" start="27" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_RXFIFO_DATA1_DB0">
<name>DB0</name>
<desc>Data Byte 0
Reads from this field return invalid data if the
message has no data.</desc>
<sw_param offset="0xe0009058" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_can1_RXFIFO_DATA1_DB1">
<name>DB1</name>
<desc>Data Byte 1
Reads from this field return invalid data if the
message has only 1 byte of data or fewer</desc>
<sw_param offset="0xe0009058" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_can1_RXFIFO_DATA1_DB2">
<name>DB2</name>
<desc>Data Byte 2
Reads from this field return invalid data if the
message has only 2 byte of data or fewer</desc>
<sw_param offset="0xe0009058" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_can1_RXFIFO_DATA1_DB3">
<name>DB3</name>
<desc>Data Byte 3
Reads from this field return invalid data if the
message has only 3 byte of data or fewer</desc>
<sw_param offset="0xe0009058" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_RXFIFO_DATA2_DB0">
<name>DB0</name>
<desc>Data Byte 4
Reads from this field return invalid data if the
message has only 4 byte of data or fewer</desc>
<sw_param offset="0xe000905c" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_can1_RXFIFO_DATA2_DB1">
<name>DB1</name>
<desc>Data Byte 5
Reads from this field return invalid data if the
message has only 5 byte of data or fewer</desc>
<sw_param offset="0xe000905c" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_can1_RXFIFO_DATA2_DB2">
<name>DB2</name>
<desc>Data Byte 6
Reads from this field return invalid data if the
message has only 6 byte of data or fewer</desc>
<sw_param offset="0xe000905c" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_can1_RXFIFO_DATA2_DB3">
<name>DB3</name>
<desc>Data Byte 7
Reads from this field return invalid data if the
message has 7 byte of data or fewer</desc>
<sw_param offset="0xe000905c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_AFR_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xe0009060" start="31" end="4" />
</parameter>
<parameter uniqueid="ps7_can1_AFR_UAF4">
<name>UAF4</name>
<desc>Use Acceptance Filter Number 4
Enables the use of acceptance filter pair 4.
1 = Indicates Acceptance Filter Mask Register 4 and
Acceptance Filter ID Register 4 are used for
acceptance filtering.
0 = Indicates Acceptance Filter Mask Register 4 and
Acceptance Filter ID Register 4 are not used for
acceptance filtering.</desc>
<sw_param offset="0xe0009060" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_can1_AFR_UAF3">
<name>UAF3</name>
<desc>Use Acceptance Filter Number 3
Enables the use of acceptance filter pair 3.
1 = Indicates Acceptance Filter Mask Register 3 and
Acceptance Filter ID Register 3 are used for
acceptance filtering.
0 = Indicates Acceptance Filter Mask Register 3 and
Acceptance Filter ID Register 3 are not used for
acceptance filtering.</desc>
<sw_param offset="0xe0009060" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_can1_AFR_UAF2">
<name>UAF2</name>
<desc>Use Acceptance Filter Number 2
Enables the use of acceptance filter pair 2.
1 = Indicates Acceptance Filter Mask Register 2 and
Acceptance Filter ID Register 2 are used for
acceptance filtering.
0 = Indicates Acceptance Filter Mask Register 2 and
Acceptance Filter ID Register 2 are not used for
acceptance filtering.</desc>
<sw_param offset="0xe0009060" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_can1_AFR_UAF1">
<name>UAF1</name>
<desc>Use Acceptance Filter Number 1.
Enables the use of acceptance filter pair 1.
1 = Indicates Acceptance Filter Mask Register 1 and
Acceptance Filter ID Register 1 are used for
acceptance filtering.
0 = Indicates Acceptance Filter Mask Register 1 and
Acceptance Filter ID Register 1 are not used for
acceptance filtering.</desc>
<sw_param offset="0xe0009060" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_AFMR1_AMIDH">
<name>AMIDH</name>
<desc>Standard Message ID Mask
These bits are used for masking the Identifier in a
Standard Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe0009064" start="31" end="21" />
</parameter>
<parameter uniqueid="ps7_can1_AFMR1_AMSRR">
<name>AMSRR</name>
<desc>Substitute Remote Transmission Request Mask
This bit is used for masking the RTR bit in a Standard
Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe0009064" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_can1_AFMR1_AMIDE">
<name>AMIDE</name>
<desc>Identifier Extension Mask
Used for masking the IDE bit in CAN frames.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.
If AMIDE = 1 and the AIIDE bit in the corresponding
Acceptance ID register is 0, this mask is applicable to
only Standard frames.
If AMIDE = 1 and the AIIDE bit in the corresponding
Acceptance ID register is 1, this mask is applicable to
only extended frames.
If AMIDE = 0 this mask is applicable to Standard
frame.</desc>
<sw_param offset="0xe0009064" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_can1_AFMR1_AMIDL">
<name>AMIDL</name>
<desc>Extended Message ID Mask
These bits are used for masking the Identifier in an
Extended Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe0009064" start="18" end="1" />
</parameter>
<parameter uniqueid="ps7_can1_AFMR1_AMRTR">
<name>AMRTR</name>
<desc>Remote Transmission Request Mask.
This bit is used for masking the RTR bit in an Extended
Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe0009064" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_AFIR1_AIIDH">
<name>AIIDH</name>
<desc>Standard Message ID
Standard Identifier</desc>
<sw_param offset="0xe0009068" start="31" end="21" />
</parameter>
<parameter uniqueid="ps7_can1_AFIR1_AISRR">
<name>AISRR</name>
<desc>Substitute Remote Transmission Request
Indicates the Remote Transmission Request bit for
Standard frames</desc>
<sw_param offset="0xe0009068" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_can1_AFIR1_AIIDE">
<name>AIIDE</name>
<desc>Identifier Extension
Differentiates between Standard and Extended
frames</desc>
<sw_param offset="0xe0009068" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_can1_AFIR1_AIIDL">
<name>AIIDL</name>
<desc>Extended Message ID Mask
Extended Identifier</desc>
<sw_param offset="0xe0009068" start="18" end="1" />
</parameter>
<parameter uniqueid="ps7_can1_AFIR1_AIRTR">
<name>AIRTR</name>
<desc>Remote Transmission Request Mask
RTR bit for Extended frames.</desc>
<sw_param offset="0xe0009068" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_AFMR2_AMIDH">
<name>AMIDH</name>
<desc>Standard Message ID Mask
These bits are used for masking the Identifier in a
Standard Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe000906c" start="31" end="21" />
</parameter>
<parameter uniqueid="ps7_can1_AFMR2_AMSRR">
<name>AMSRR</name>
<desc>Substitute Remote Transmission Request Mask
This bit is used for masking the RTR bit in a Standard
Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe000906c" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_can1_AFMR2_AMIDE">
<name>AMIDE</name>
<desc>Identifier Extension Mask
Used for masking the IDE bit in CAN frames.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.
If AMIDE = 1 and the AIIDE bit in the corresponding
Acceptance ID register is 0, this mask is applicable to
only Standard frames.
If AMIDE = 1 and the AIIDE bit in the corresponding
Acceptance ID register is 1, this mask is applicable to
only extended frames.
If AMIDE = 0 this mask is applicable to Standard
frame.</desc>
<sw_param offset="0xe000906c" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_can1_AFMR2_AMIDL">
<name>AMIDL</name>
<desc>Extended Message ID Mask
These bits are used for masking the Identifier in an
Extended Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe000906c" start="18" end="1" />
</parameter>
<parameter uniqueid="ps7_can1_AFMR2_AMRTR">
<name>AMRTR</name>
<desc>Remote Transmission Request Mask.
This bit is used for masking the RTR bit in an Extended
Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe000906c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_AFIR2_AIIDH">
<name>AIIDH</name>
<desc>Standard Message ID
Standard Identifier</desc>
<sw_param offset="0xe0009070" start="31" end="21" />
</parameter>
<parameter uniqueid="ps7_can1_AFIR2_AISRR">
<name>AISRR</name>
<desc>Substitute Remote Transmission Request
Indicates the Remote Transmission Request bit for
Standard frames</desc>
<sw_param offset="0xe0009070" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_can1_AFIR2_AIIDE">
<name>AIIDE</name>
<desc>Identifier Extension
Differentiates between Standard and Extended
frames</desc>
<sw_param offset="0xe0009070" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_can1_AFIR2_AIIDL">
<name>AIIDL</name>
<desc>Extended Message ID Mask
Extended Identifier</desc>
<sw_param offset="0xe0009070" start="18" end="1" />
</parameter>
<parameter uniqueid="ps7_can1_AFIR2_AIRTR">
<name>AIRTR</name>
<desc>Remote Transmission Request Mask
RTR bit for Extended frames.</desc>
<sw_param offset="0xe0009070" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_AFMR3_AMIDH">
<name>AMIDH</name>
<desc>Standard Message ID Mask
These bits are used for masking the Identifier in a
Standard Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe0009074" start="31" end="21" />
</parameter>
<parameter uniqueid="ps7_can1_AFMR3_AMSRR">
<name>AMSRR</name>
<desc>Substitute Remote Transmission Request Mask
This bit is used for masking the RTR bit in a Standard
Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe0009074" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_can1_AFMR3_AMIDE">
<name>AMIDE</name>
<desc>Identifier Extension Mask
Used for masking the IDE bit in CAN frames.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.
If AMIDE = 1 and the AIIDE bit in the corresponding
Acceptance ID register is 0, this mask is applicable to
only Standard frames.
If AMIDE = 1 and the AIIDE bit in the corresponding
Acceptance ID register is 1, this mask is applicable to
only extended frames.
If AMIDE = 0 this mask is applicable to Standard
frame.</desc>
<sw_param offset="0xe0009074" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_can1_AFMR3_AMIDL">
<name>AMIDL</name>
<desc>Extended Message ID Mask
These bits are used for masking the Identifier in an
Extended Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe0009074" start="18" end="1" />
</parameter>
<parameter uniqueid="ps7_can1_AFMR3_AMRTR">
<name>AMRTR</name>
<desc>Remote Transmission Request Mask.
This bit is used for masking the RTR bit in an Extended
Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe0009074" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_AFIR3_AIIDH">
<name>AIIDH</name>
<desc>Standard Message ID
Standard Identifier</desc>
<sw_param offset="0xe0009078" start="31" end="21" />
</parameter>
<parameter uniqueid="ps7_can1_AFIR3_AISRR">
<name>AISRR</name>
<desc>Substitute Remote Transmission Request
Indicates the Remote Transmission Request bit for
Standard frames</desc>
<sw_param offset="0xe0009078" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_can1_AFIR3_AIIDE">
<name>AIIDE</name>
<desc>Identifier Extension
Differentiates between Standard and Extended
frames</desc>
<sw_param offset="0xe0009078" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_can1_AFIR3_AIIDL">
<name>AIIDL</name>
<desc>Extended Message ID Mask
Extended Identifier</desc>
<sw_param offset="0xe0009078" start="18" end="1" />
</parameter>
<parameter uniqueid="ps7_can1_AFIR3_AIRTR">
<name>AIRTR</name>
<desc>Remote Transmission Request Mask
RTR bit for Extended frames.</desc>
<sw_param offset="0xe0009078" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_AFMR4_AMIDH">
<name>AMIDH</name>
<desc>Standard Message ID Mask
These bits are used for masking the Identifier in a
Standard Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe000907c" start="31" end="21" />
</parameter>
<parameter uniqueid="ps7_can1_AFMR4_AMSRR">
<name>AMSRR</name>
<desc>Substitute Remote Transmission Request Mask
This bit is used for masking the RTR bit in a Standard
Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe000907c" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_can1_AFMR4_AMIDE">
<name>AMIDE</name>
<desc>Identifier Extension Mask
Used for masking the IDE bit in CAN frames.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.
If AMIDE = 1 and the AIIDE bit in the corresponding
Acceptance ID register is 0, this mask is applicable to
only Standard frames.
If AMIDE = 1 and the AIIDE bit in the corresponding
Acceptance ID register is 1, this mask is applicable to
only extended frames.
If AMIDE = 0 this mask is applicable to Standard
frame.</desc>
<sw_param offset="0xe000907c" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_can1_AFMR4_AMIDL">
<name>AMIDL</name>
<desc>Extended Message ID Mask
These bits are used for masking the Identifier in an
Extended Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe000907c" start="18" end="1" />
</parameter>
<parameter uniqueid="ps7_can1_AFMR4_AMRTR">
<name>AMRTR</name>
<desc>Remote Transmission Request Mask.
This bit is used for masking the RTR bit in an Extended
Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe000907c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can1_AFIR4_AIIDH">
<name>AIIDH</name>
<desc>Standard Message ID
Standard Identifier</desc>
<sw_param offset="0xe0009080" start="31" end="21" />
</parameter>
<parameter uniqueid="ps7_can1_AFIR4_AISRR">
<name>AISRR</name>
<desc>Substitute Remote Transmission Request
Indicates the Remote Transmission Request bit for
Standard frames</desc>
<sw_param offset="0xe0009080" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_can1_AFIR4_AIIDE">
<name>AIIDE</name>
<desc>Identifier Extension
Differentiates between Standard and Extended
frames</desc>
<sw_param offset="0xe0009080" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_can1_AFIR4_AIIDL">
<name>AIIDL</name>
<desc>Extended Message ID Mask
Extended Identifier</desc>
<sw_param offset="0xe0009080" start="18" end="1" />
</parameter>
<parameter uniqueid="ps7_can1_AFIR4_AIRTR">
<name>AIRTR</name>
<desc>Remote Transmission Request Mask
RTR bit for Extended frames.</desc>
<sw_param offset="0xe0009080" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_SRR_reserved">
<name>reserved</name>
<desc>Reserved.</desc>
<sw_param offset="0xe0008000" start="31" end="2" />
</parameter>
<parameter uniqueid="ps7_can0_SRR_CEN">
<name>CEN</name>
<desc>Can Enable
The Enable bit for the CAN controller.
1 = The CAN controller is in Loop Back, Sleep or Normal mode depending on the LBACK and SLEEP bits in the MSR.
0 = The CAN controller is in the Configuration mode.
If the CEN bit is changed during core operation, it is
recommended to reset the core so that operations start afresh.</desc>
<sw_param offset="0xe0008000" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_can0_SRR_SRST">
<name>SRST</name>
<desc>Reset
The Software reset bit for the CAN controller.
1 = CAN controller is reset.
If a 1 is written to this bit, all the CAN controller configuration registers (including the SRR) are reset. Reads to this bit always return a 0.</desc>
<sw_param offset="0xe0008000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_MSR_reserved">
<name>reserved</name>
<desc>Reserved.</desc>
<sw_param offset="0xe0008004" start="31" end="3" />
</parameter>
<parameter uniqueid="ps7_can0_MSR_SNOOP">
<name>SNOOP</name>
<desc>Snoop Mode Select
The Snoop Mode Select bit.
1 = CAN controller is in Snoop mode.
0 = CAN controller is in Normal, Loop Back, Configuration, or Sleep mode.
This bit can be written to only when CEN bit in SRR is 0.</desc>
<sw_param offset="0xe0008004" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_can0_MSR_LBACK">
<name>LBACK</name>
<desc>Loop Back Mode Select
The Loop Back Mode Select bit.
1 = CAN controller is in Loop Back mode.
0 = CAN controller is in Normal, Snoop, Configuration, or Sleep mode.
This bit can be written to only when CEN bit in SRR is 0.</desc>
<sw_param offset="0xe0008004" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_can0_MSR_SLEEP">
<name>SLEEP</name>
<desc>Sleep Mode Select
The Sleep Mode select bit.
1 = CAN controller is in Sleep mode.
0 = CAN controller is in Normal, Snoop, Configuration or Loop Back mode.
This bit is cleared when the CAN controller wakes up from the Sleep mode.</desc>
<sw_param offset="0xe0008004" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_BRPR_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0008008" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_can0_BRPR_BRP">
<name>BRP</name>
<desc>Baud Rate Prescaler
These bits indicate the prescaler value. The actual
value ranges from 1 to 256.</desc>
<sw_param offset="0xe0008008" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_BTR_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe000800c" start="31" end="9" />
</parameter>
<parameter uniqueid="ps7_can0_BTR_SJW">
<name>SJW</name>
<desc>Synchronization Jump Width
Indicates the Synchronization Jump Width as specified in the CAN 2.0A and CAN 2.0B standard. The actual value is one more than the value written to the register.</desc>
<sw_param offset="0xe000800c" start="8" end="7" />
</parameter>
<parameter uniqueid="ps7_can0_BTR_TS2">
<name>TS2</name>
<desc>Time Segment 2
Indicates Phase Segment 2 as specified in the CAN 2.0A and CAN 2.0B standard. The actual value is one more than the value written to the register.</desc>
<sw_param offset="0xe000800c" start="6" end="4" />
</parameter>
<parameter uniqueid="ps7_can0_BTR_TS1">
<name>TS1</name>
<desc>Time Segment 1
Indicates the Sum of Propagation Segment and Phase
Segment 1 as specified in the CAN 2.0A and CAN 2.0B
standard. The actual value is one more than the value
written to the register.</desc>
<sw_param offset="0xe000800c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_ECR_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0008010" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_can0_ECR_REC">
<name>REC</name>
<desc>Receive Error Counter
Indicates the Value of the Receive Error Counter.</desc>
<sw_param offset="0xe0008010" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_can0_ECR_TEC">
<name>TEC</name>
<desc>Transmit Error Counter
Indicates the Value of the Transmit Error Counter.</desc>
<sw_param offset="0xe0008010" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_ESR_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0008014" start="31" end="5" />
</parameter>
<parameter uniqueid="ps7_can0_ESR_ACKER">
<name>ACKER</name>
<desc>ACK Error
Indicates an acknowledgement error.
1 = Indicates an acknowledgement error has
occurred.
0 = Indicates an acknowledgement error has not
occurred on the bus since the last write to this
register.
If this bit is set, writing a 1 clears it.</desc>
<sw_param offset="0xe0008014" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_can0_ESR_BERR">
<name>BERR</name>
<desc>Bit Error
Indicates the received bit is not the same as the
transmitted bit during bus communication.
1 = Indicates a bit error has occurred.
0 = Indicates a bit error has not occurred on the bus
since the last write to this register.
If this bit is set, writing a 1 clears it.</desc>
<sw_param offset="0xe0008014" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_can0_ESR_STER">
<name>STER</name>
<desc>Stuff Error
Indicates an error if there is a stuffing violation.
1 = Indicates a stuff error has occurred.
0 = Indicates a stuff error has not occurred on the
bus since the last write to this register.
If this bit is set, writing a 1 clears it.</desc>
<sw_param offset="0xe0008014" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_can0_ESR_FMER">
<name>FMER</name>
<desc>Form Error
Indicates an error in one of the fixed form fields in the
message frame.
1 = Indicates a form error has occurred.
0 = Indicates a form error has not occurred on the
bus since the last write to this register.
If this bit is set, writing a 1 clears it.</desc>
<sw_param offset="0xe0008014" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_can0_ESR_CRCER">
<name>CRCER</name>
<desc>CRC Error
Indicates a CRC error has occurred.
1 = Indicates a CRC error has occurred.
0 = Indicates a CRC error has not occurred on the
bus since the last write to this register.
If this bit is set, writing a 1 clears it.
In case of a CRC Error and a CRC delimiter corruption, only the FMER bit is set.</desc>
<sw_param offset="0xe0008014" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_SR_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0008018" start="31" end="13" />
</parameter>
<parameter uniqueid="ps7_can0_SR_SNOOP">
<name>SNOOP</name>
<desc>Snoop Mode
Indicates the CAN controller is in Snoop Mode.
1 = Indicates the CAN controller is in Snoop Mode.
0 = Indicates the CAN controller is not in Snoop mode.</desc>
<sw_param offset="0xe0008018" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_can0_SR_ACFBSY">
<name>ACFBSY</name>
<desc>Acceptance Filter Busy
This bit indicates that the Acceptance Filter Mask
Registers and the Acceptance Filter ID Registers
cannot be written to.
1 = Acceptance Filter Mask Registers and
Acceptance Filter ID Registers cannot be written
to.
0 = Acceptance Filter Mask Registers and the
Acceptance Filter ID Registers can be written to.
This bit exists only when the number of acceptance
filters is not 0
This bit is set when a 0 is written to any of the valid
UAF bits in the Acceptance Filter Register.</desc>
<sw_param offset="0xe0008018" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_can0_SR_TXFLL">
<name>TXFLL</name>
<desc>Transmit FIFO Full
Indicates that the TX FIFO is full.
1 = Indicates the TX FIFO is full.
0 = Indicates the TX FIFO is not full.</desc>
<sw_param offset="0xe0008018" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_can0_SR_TXBFLL">
<name>TXBFLL</name>
<desc>High Priority Transmit Buffer Full
Indicates the High Priority Transmit Buffer is full.
1 = Indicates the High Priority Transmit Buffer is full.
0 = Indicates the High Priority Transmit Buffer is not full.</desc>
<sw_param offset="0xe0008018" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_can0_SR_ESTAT">
<name>ESTAT</name>
<desc>Error Status
Indicates the error status of the CAN controller.
00 = Indicates Configuration Mode (CONFIG = 1).
Error State is undefined.
01 = Indicates Error Active State.
11 = Indicates Error Passive State.
10 = Indicates Bus Off State.</desc>
<sw_param offset="0xe0008018" start="8" end="7" />
</parameter>
<parameter uniqueid="ps7_can0_SR_ERRWRN">
<name>ERRWRN</name>
<desc>Error Warning
Indicates that either the Transmit Error counter or the
Receive Error counter has exceeded a value of 96.
1 = One or more error counters have a value greater
than or equal to 96.
0 = Neither of the error counters has a value greater
than or equal to 96.</desc>
<sw_param offset="0xe0008018" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_can0_SR_BBSY">
<name>BBSY</name>
<desc>Bus Busy
Indicates the CAN bus status.
1 = Indicates that the CAN controller is either
receiving a message or transmitting a message.
0 = Indicates that the CAN controller is either in
Configuration mode or the bus is idle.</desc>
<sw_param offset="0xe0008018" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_can0_SR_BIDLE">
<name>BIDLE</name>
<desc>Bus Idle
Indicates the CAN bus status.
1 = Indicates no bus communication is taking place.
0 = Indicates the CAN controller is either in
Configuration mode or the bus is busy.</desc>
<sw_param offset="0xe0008018" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_can0_SR_NORMAL">
<name>NORMAL</name>
<desc>Normal Mode
Indicates the CAN controller is in Normal Mode.
1 = Indicates the CAN controller is in Normal Mode.
0 = Indicates the CAN controller is not in Normal
mode.</desc>
<sw_param offset="0xe0008018" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_can0_SR_SLEEP">
<name>SLEEP</name>
<desc>Sleep Mode
Indicates the CAN controller is in Sleep mode.
1 = Indicates the CAN controller is in Sleep mode.
0 = Indicates the CAN controller is not in Sleep mode.</desc>
<sw_param offset="0xe0008018" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_can0_SR_LBACK">
<name>LBACK</name>
<desc>Loop Back Mode
Indicates the CAN controller is in Loop Back mode.
1 = Indicates the CAN controller is in Loop Back
mode.
0 = Indicates the CAN controller is not in Loop Back
mode.</desc>
<sw_param offset="0xe0008018" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_can0_SR_CONFIG">
<name>CONFIG</name>
<desc>Configuration Mode Indicator
Indicates the CAN controller is in Configuration mode.
1 = Indicates the CAN controller is in Configuration
mode.
0 = Indicates the CAN controller is not in
Configuration mode.</desc>
<sw_param offset="0xe0008018" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_ISR_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xe000801c" start="31" end="15" />
</parameter>
<parameter uniqueid="ps7_can0_ISR_TXFEMP">
<name>TXFEMP</name>
<desc>Transmit FIFO EmptyInterrupt
A 1 indicates that the Transmit FIFO is empty.
The interrupt continues to assert as long as the TX
FIFO is empty.
This bit can be cleared only by writing to the ICR.</desc>
<sw_param offset="0xe000801c" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_can0_ISR_TXFWMEMP">
<name>TXFWMEMP</name>
<desc>Transmit FIFO Watermark Empty Interrupt
A 1 indicates that the TX FIFO is empty based on
watermark programming.
The interrupt continues to assert as long as the number
of empty spaces in the TX FIFO is greater than TX FIFO
empty watermark.
This bit can be cleared only by writing to the Interrupt
Clear Register.</desc>
<sw_param offset="0xe000801c" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_can0_ISR_RXFWMFLL">
<name>RXFWMFLL</name>
<desc>Receive FIFO Watermark Full Interrupt
A 1 indicates that the RX FIFO is full based on
watermark programming.
The interrupt continues to assert as long as the RX
FIFO count is above RX FIFO Full watermark.
This bit can be cleared only by writing to the Interrupt
Clear Register.</desc>
<sw_param offset="0xe000801c" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_can0_ISR_WKUP">
<name>WKUP</name>
<desc>Wake up Interrupt
A 1 indicates that the CAN controller entered Normal
mode from Sleep Mode.
This bit can be cleared by writing to the ICR.
This bit is also cleared when a 0 is written to the CEN
bit in the SRR.</desc>
<sw_param offset="0xe000801c" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_can0_ISR_SLP">
<name>SLP</name>
<desc>Sleep Interrupt
A 1 indicates that the CAN controller entered Sleep mode.
This bit can be cleared by writing to the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.</desc>
<sw_param offset="0xe000801c" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_can0_ISR_BSOFF">
<name>BSOFF</name>
<desc>Bus Off Interrupt
A 1 indicates that the CAN controller entered the Bus Off state.
This bit can be cleared by writing to the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.</desc>
<sw_param offset="0xe000801c" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_can0_ISR_ERROR">
<name>ERROR</name>
<desc>Error Interrupt
A 1 indicates that an error occurred during message transmission or reception.
This bit can be cleared by writing to the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.</desc>
<sw_param offset="0xe000801c" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_can0_ISR_RXNEMP">
<name>RXNEMP</name>
<desc>Receive FIFO Not Empty Interrupt
A 1 indicates that the Receive FIFO is not empty.
This bit can be cleared only by writing to the ICR.</desc>
<sw_param offset="0xe000801c" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_can0_ISR_RXOFLW">
<name>RXOFLW</name>
<desc>RX FIFO Overflow Interrupt
A 1 indicates that a message has been lost. This condition occurs when a new message is being received and the Receive FIFO is Full.
This bit can be cleared by writing to the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.</desc>
<sw_param offset="0xe000801c" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_can0_ISR_RXUFLW">
<name>RXUFLW</name>
<desc>RX FIFO Underflow Interrupt
A 1 indicates that a read operation was attempted on an empty RX FIFO.
This bit can be cleared only by writing to the ICR.</desc>
<sw_param offset="0xe000801c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_can0_ISR_RXOK">
<name>RXOK</name>
<desc>New Message Received Interrupt
A 1 indicates that a message was received successfully and stored into the RX FIFO.
This bit can be cleared by writing to the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.</desc>
<sw_param offset="0xe000801c" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_can0_ISR_TXBFLL">
<name>TXBFLL</name>
<desc>High Priority Transmit Buffer Full Interrupt
A 1 indicates that the High Priority Transmit Buffer is full.
The status of the bit is unaffected if write transactions occur on the High Priority Transmit Buffer when it is already full.
This bit can be cleared only by writing to the ICR.</desc>
<sw_param offset="0xe000801c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_can0_ISR_TXFLL">
<name>TXFLL</name>
<desc>Transmit FIFO Full Interrupt
A 1 indicates that the TX FIFO is full.
The status of the bit is unaffected if write transactions occur on the Transmit FIFO when it is already full.
This bit can be cleared only by writing to the Interrupt Clear Register.</desc>
<sw_param offset="0xe000801c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_can0_ISR_TXOK">
<name>TXOK</name>
<desc>Transmission Successful Interrupt
A 1 indicates that a message was transmitted successfully.
This bit can be cleared by writing to the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.
In Loop Back mode, both TXOK and RXOK bits are set. The RXOK bit is set before the TXOK bit.</desc>
<sw_param offset="0xe000801c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_can0_ISR_ARBLST">
<name>ARBLST</name>
<desc>Arbitration Lost Interrupt
A 1 indicates that arbitration was lost during message transmission.
This bit can be cleared by writing to the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.</desc>
<sw_param offset="0xe000801c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_IER_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0008020" start="31" end="15" />
</parameter>
<parameter uniqueid="ps7_can0_IER_ETXFEMP">
<name>ETXFEMP</name>
<desc>Enable TXFIFO Empty Interrupt
Writes to this bit enable or disable interrupts when the
TXFEMP bit in the ISR is set.
1 = Enable interrupt generation if TXFEMP bit in ISR is set.
0 = Disable interrupt generation if TXFEMP bit in ISR is set.</desc>
<sw_param offset="0xe0008020" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_can0_IER_ETXFWMEMP">
<name>ETXFWMEMP</name>
<desc>Enable TXFIFO watermark Empty Interrupt
Writes to this bit enable or disable interrupts when the
TXFWMEMP bit in the ISR is set.
1 = Enable interrupt generation if TXFWMEMP bit in ISR is set.
0 = Disable interrupt generation if TXFWMEMP bit in ISR is set.</desc>
<sw_param offset="0xe0008020" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_can0_IER_ERXFWMFLL">
<name>ERXFWMFLL</name>
<desc>Enable RXFIFO watermark Full Interrupt
Writes to this bit enable or disable interrupts when the RXFLL bit in the ISR is set.
1 = Enable interrupt generation if RXFWMFLL bit in ISR is set.
0 = Disable interrupt generation if RXFWMFLL bit in ISR is set.</desc>
<sw_param offset="0xe0008020" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_can0_IER_EWKUP">
<name>EWKUP</name>
<desc>Enable Wake up Interrupt
Writes to this bit enable or disable interrupts when the
WKUP bit in the ISR is set.
1 = Enable interrupt generation if WKUP bit in ISR is set.
0 = Disable interrupt generation if WKUP bit in ISR is set.</desc>
<sw_param offset="0xe0008020" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_can0_IER_ESLP">
<name>ESLP</name>
<desc>Enable Sleep Interrupt
Writes to this bit enable or disable interrupts when the
SLP bit in the ISR is set.
1 = Enable interrupt generation if SLP bit in ISR is set.
0 = Disable interrupt generation if SLP bit in ISR is set.</desc>
<sw_param offset="0xe0008020" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_can0_IER_EBSOFF">
<name>EBSOFF</name>
<desc>Enable Bus OFF Interrupt
Writes to this bit enable or disable interrupts when the
BSOFF bit in the ISR is set.
1 = Enable interrupt generation if BSOFF bit in ISR is set.
0 = Disable interrupt generation if BSOFF bit in ISR is set.</desc>
<sw_param offset="0xe0008020" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_can0_IER_EERROR">
<name>EERROR</name>
<desc>Enable Error Interrupt
Writes to this bit enable or disable interrupts when the
ERROR bit in the ISR is set.
1 = Enable interrupt generation if ERROR bit in ISR is
set.
0 = Disable interrupt generation if ERROR bit in ISR is
set.</desc>
<sw_param offset="0xe0008020" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_can0_IER_ERXNEMP">
<name>ERXNEMP</name>
<desc>Enable Receive FIFO Not Empty Interrupt
Writes to this bit enable or disable interrupts when the
RXNEMP bit in the ISR is set.
1 = Enable interrupt generation if RXNEMP bit in ISR is
set.
0 = Disable interrupt generation if RXNEMP bit in ISR
is set.</desc>
<sw_param offset="0xe0008020" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_can0_IER_ERXOFLW">
<name>ERXOFLW</name>
<desc>Enable RX FIFO Overflow Interrupt
Writes to this bit enable or disable interrupts when the
RXOFLW bit in the ISR is set.
1 = Enable interrupt generation if RXOFLW bit in ISR is
set.
0 = Disable interrupt generation if RXOFLW bit in ISR
is set.</desc>
<sw_param offset="0xe0008020" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_can0_IER_ERXUFLW">
<name>ERXUFLW</name>
<desc>Enable RX FIFO Underflow Interrupt
Writes to this bit enable or disable interrupts when the
RXUFLW bit in the ISR is set.
1 = Enable interrupt generation if RXUFLW bit in ISR is
set.
0 = Disable interrupt generation if RXUFLW bit in ISR is
set.</desc>
<sw_param offset="0xe0008020" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_can0_IER_ERXOK">
<name>ERXOK</name>
<desc>Enable New Message Received Interrupt
Writes to this bit enable or disable interrupts when the
RXOK bit in the ISR is set.
1 = Enable interrupt generation if RXOK bit in ISR is
set.
0 = Disable interrupt generation if RXOK bit in ISR is
set.</desc>
<sw_param offset="0xe0008020" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_can0_IER_ETXBFLL">
<name>ETXBFLL</name>
<desc>Enable High Priority Transmit Buffer Full Interrupt
Writes to this bit enable or disable interrupts when the
TXBFLL bit in the ISR is set.
1 = Enable interrupt generation if TXBFLL bit in ISR is
set.
0 = Disable interrupt generation if TXBFLL bit in ISR is
set.</desc>
<sw_param offset="0xe0008020" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_can0_IER_ETXFLL">
<name>ETXFLL</name>
<desc>Enable Transmit FIFO Full Interrupt
Writes to this bit enable or disable interrupts when
TXFLL bit in the ISR is set.
1 = Enable interrupt generation if TXFLL bit in ISR is
set.
0 = Disable interrupt generation if TXFLL bit in ISR is
set.</desc>
<sw_param offset="0xe0008020" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_can0_IER_ETXOK">
<name>ETXOK</name>
<desc>Enable Transmission Successful Interrupt
Writes to this bit enable or disable interrupts when the
TXOK bit in the ISR is set.
1 = Enable interrupt generation if TXOK bit in ISR is set.
0 = Disable interrupt generation if TXOK bit in ISR is
set.</desc>
<sw_param offset="0xe0008020" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_can0_IER_EARBLST">
<name>EARBLST</name>
<desc>Enable Arbitration Lost Interrupt
Writes to this bit enable or disable interrupts when the
ARBLST bit in the ISR is set.
1 = Enable interrupt generation if ARBLST bit in ISR is
set.
0 = Disable interrupt generation if ARBLST bit in ISR is
set.</desc>
<sw_param offset="0xe0008020" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_ICR_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe0008024" start="31" end="15" />
</parameter>
<parameter uniqueid="ps7_can0_ICR_CTXFEMP">
<name>CTXFEMP</name>
<desc>Clear TXFIFO Empty Interrupt
Writing a 1 to this bit clears the TXFEMP bit in the
ISR.</desc>
<sw_param offset="0xe0008024" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_can0_ICR_CTXFWMEMP">
<name>CTXFWMEMP</name>
<desc>Clear TXFIFO Watermark Empty Interrupt
Writing a 1 to this bit clears the TXFWMEMP bit in
the ISR.</desc>
<sw_param offset="0xe0008024" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_can0_ICR_CRXFWMFLL">
<name>CRXFWMFLL</name>
<desc>Clear RXFIFO Watermark Full Interrupt
Writing a 1 to this bit clears the RXFWMFLL bit in
the ISR.</desc>
<sw_param offset="0xe0008024" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_can0_ICR_CWKUP">
<name>CWKUP</name>
<desc>Clear Wake up Interrupt
Writing a 1 to this bit clears the WKUP bit in the ISR.</desc>
<sw_param offset="0xe0008024" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_can0_ICR_CSLP">
<name>CSLP</name>
<desc>Clear Sleep Interrupt
Writing a 1 to this bit clears the SLP bit in the ISR.</desc>
<sw_param offset="0xe0008024" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_can0_ICR_CBSOFF">
<name>CBSOFF</name>
<desc>Clear Bus Off Interrupt
Writing a 1 to this bit clears the BSOFF bit in the
ISR.</desc>
<sw_param offset="0xe0008024" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_can0_ICR_CERROR">
<name>CERROR</name>
<desc>Clear Error Interrupt
Writing a 1 to this bit clears the ERROR bit in the
ISR.</desc>
<sw_param offset="0xe0008024" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_can0_ICR_CRXNEMP">
<name>CRXNEMP</name>
<desc>Clear Receive FIFO Not Empty Interrupt
Writing a 1 to this bit clears the RXNEMP bit in the
ISR.</desc>
<sw_param offset="0xe0008024" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_can0_ICR_CRXOFLW">
<name>CRXOFLW</name>
<desc>Clear RX FIFO Overflow Interrupt
Writing a 1 to this bit clears the RXOFLW bit in the
ISR.</desc>
<sw_param offset="0xe0008024" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_can0_ICR_CRXUFLW">
<name>CRXUFLW</name>
<desc>Clear RX FIFO Underflow Interrupt
Writing a 1 to this bit clears the RXUFLW bit in the
ISR.</desc>
<sw_param offset="0xe0008024" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_can0_ICR_CRXOK">
<name>CRXOK</name>
<desc>Clear New Message Received Interrupt
Writing a 1 to this bit clears the RXOK bit in the ISR.</desc>
<sw_param offset="0xe0008024" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_can0_ICR_CTXBFLL">
<name>CTXBFLL</name>
<desc>Clear High Priority Transmit Buffer Full Interrupt
Writing a 1 to this bit clears the TXBFLL bit in the
ISR.</desc>
<sw_param offset="0xe0008024" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_can0_ICR_CTXFLL">
<name>CTXFLL</name>
<desc>Clear Transmit FIFO Full Interrupt
Writing a 1 to this bit clears the TXFLL bit in the
ISR.</desc>
<sw_param offset="0xe0008024" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_can0_ICR_CTXOK">
<name>CTXOK</name>
<desc>Clear Arbitration Lost Interrupt
Writing a 1 to this bit clears the ARBLST bit in the
ISR.</desc>
<sw_param offset="0xe0008024" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_can0_ICR_CARBLST">
<name>CARBLST</name>
<desc>Clear Arbitration Lost Interrupt
Writing a 1 to this bit clears the ARBLST bit in the
ISR.</desc>
<sw_param offset="0xe0008024" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_TCR_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xe0008028" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_can0_TCR_CTS">
<name>CTS</name>
<desc>Clear Timestamp
Internal free running counter is cleared to 0 when
CTS=1. This bit only needs to be written once with a 1
to clear the counter. The bit will automatically return to
0.</desc>
<sw_param offset="0xe0008028" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_WIR_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xe000802c" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_can0_WIR_EW">
<name>EW</name>
<desc>TXFIFO Empty watermark
TXFIFO generates an EMPTY interrupt based on the
value programmed in this field. The valid range is
(1-63). Only bits 18-23 are writable. No protection is
given for illegal programming in this field.
This field can be written to only when CEN bit in SRR is
0.</desc>
<sw_param offset="0xe000802c" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_can0_WIR_FW">
<name>FW</name>
<desc>RXFIFO Full watermark
RXFIFO generates FULL interrupt based on the value
programmed in this field. The valid range is (1-63). Only
bits 26-31 are writable. No protection is given for illegal
programming in this field. This field can be written to
only when CEN bit in SRR is 0.</desc>
<sw_param offset="0xe000802c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_TXFIFO_ID_IDH">
<name>IDH</name>
<desc>Standard Message ID
The Identifier portion for a Standard Frame is 11 bits.
These bits indicate the Standard Frame ID.
This field is valid for both Standard and Extended
Frames.</desc>
<sw_param offset="0xe0008030" start="31" end="21" />
</parameter>
<parameter uniqueid="ps7_can0_TXFIFO_ID_SRRRTR">
<name>SRRRTR</name>
<desc>Substitute Remote Transmission Request
This bit differentiates between data frames and
remote frames. Valid only for Standard Frames. For
Extended frames this bit is 1.
1 = Indicates that the message frame is a Remote
Frame.
0 = Indicates that the message frame is a Data
Frame.</desc>
<sw_param offset="0xe0008030" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_can0_TXFIFO_ID_IDE">
<name>IDE</name>
<desc>Identifier Extension
This bit differentiates between frames using the
Standard Identifier and those using the Extended
Identifier. Valid for both Standard and Extended
Frames.
1 = Indicates the use of an Extended Message
Identifier.
0= Indicates the use of a Standard Message
Identifier.</desc>
<sw_param offset="0xe0008030" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_can0_TXFIFO_ID_IDL">
<name>IDL</name>
<desc>Extended Message ID
This field indicates the Extended Identifier.
Valid only for Extended Frames.
For Standard Frames, reads from this field return 0s
For Standard Frames, writes to this field should be 0s</desc>
<sw_param offset="0xe0008030" start="18" end="1" />
</parameter>
<parameter uniqueid="ps7_can0_TXFIFO_ID_RTR">
<name>RTR</name>
<desc>Remote Transmission Request
This bit differentiates between data frames and
remote frames.
Valid only for Extended Frames.
1 = Indicates the message object is a Remote Frame
0 = Indicates the message object is a Data Frame
For Standard Frames, reads from this bit returns 0
For Standard Frames, writes to this bit should be 0</desc>
<sw_param offset="0xe0008030" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_TXFIFO_DLC_DLC">
<name>DLC</name>
<desc>Data Length Code
This is the data length portion of the control field of
the CAN frame. This indicates the number valid data
bytes in Data Word 1 and Data Word 2 registers.</desc>
<sw_param offset="0xe0008034" start="31" end="28" />
</parameter>
<parameter uniqueid="ps7_can0_TXFIFO_DLC_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xe0008034" start="27" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_TXFIFO_DATA1_DB0">
<name>DB0</name>
<desc>Data Byte 0
Reads from this field return invalid data if the
message has no data.</desc>
<sw_param offset="0xe0008038" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_can0_TXFIFO_DATA1_DB1">
<name>DB1</name>
<desc>Data Byte 1
Reads from this field return invalid data if the
message has only 1 byte of data or fewer</desc>
<sw_param offset="0xe0008038" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_can0_TXFIFO_DATA1_DB2">
<name>DB2</name>
<desc>Data Byte 2
Reads from this field return invalid data if the
message has only 2 byte of data or fewer</desc>
<sw_param offset="0xe0008038" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_can0_TXFIFO_DATA1_DB3">
<name>DB3</name>
<desc>Data Byte 3
Reads from this field return invalid data if the
message has only 3 byte of data or fewer</desc>
<sw_param offset="0xe0008038" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_TXFIFO_DATA2_DB0">
<name>DB0</name>
<desc>Data Byte 4
Reads from this field return invalid data if the
message has only 4 byte of data or fewer</desc>
<sw_param offset="0xe000803c" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_can0_TXFIFO_DATA2_DB1">
<name>DB1</name>
<desc>Data Byte 5
Reads from this field return invalid data if the
message has only 5 byte of data or fewer</desc>
<sw_param offset="0xe000803c" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_can0_TXFIFO_DATA2_DB2">
<name>DB2</name>
<desc>Data Byte 6
Reads from this field return invalid data if the
message has only 6 byte of data or fewer</desc>
<sw_param offset="0xe000803c" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_can0_TXFIFO_DATA2_DB3">
<name>DB3</name>
<desc>Data Byte 7
Reads from this field return invalid data if the
message has 7 byte of data or fewer</desc>
<sw_param offset="0xe000803c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_TXHPB_ID_IDH">
<name>IDH</name>
<desc>Standard Message ID
The Identifier portion for a Standard Frame is 11 bits.
These bits indicate the Standard Frame ID.
This field is valid for both Standard and Extended
Frames.</desc>
<sw_param offset="0xe0008040" start="31" end="21" />
</parameter>
<parameter uniqueid="ps7_can0_TXHPB_ID_SRRRTR">
<name>SRRRTR</name>
<desc>Substitute Remote Transmission Request
This bit differentiates between data frames and
remote frames. Valid only for Standard Frames. For
Extended frames this bit is 1.
1 = Indicates that the message frame is a Remote
Frame.
0 = Indicates that the message frame is a Data
Frame.</desc>
<sw_param offset="0xe0008040" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_can0_TXHPB_ID_IDE">
<name>IDE</name>
<desc>Identifier Extension
This bit differentiates between frames using the
Standard Identifier and those using the Extended
Identifier. Valid for both Standard and Extended
Frames.
1 = Indicates the use of an Extended Message
Identifier.
0= Indicates the use of a Standard Message
Identifier.</desc>
<sw_param offset="0xe0008040" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_can0_TXHPB_ID_IDL">
<name>IDL</name>
<desc>Extended Message ID
This field indicates the Extended Identifier.
Valid only for Extended Frames.
For Standard Frames, reads from this field return 0s
For Standard Frames, writes to this field should be 0s</desc>
<sw_param offset="0xe0008040" start="18" end="1" />
</parameter>
<parameter uniqueid="ps7_can0_TXHPB_ID_RTR">
<name>RTR</name>
<desc>Remote Transmission Request
This bit differentiates between data frames and
remote frames.
Valid only for Extended Frames.
1 = Indicates the message object is a Remote Frame
0 = Indicates the message object is a Data Frame
For Standard Frames, reads from this bit returns 0
For Standard Frames, writes to this bit should be 0</desc>
<sw_param offset="0xe0008040" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_TXHPB_DLC_DLC">
<name>DLC</name>
<desc>Data Length Code
This is the data length portion of the control field of
the CAN frame. This indicates the number valid data
bytes in Data Word 1 and Data Word 2 registers.</desc>
<sw_param offset="0xe0008044" start="31" end="28" />
</parameter>
<parameter uniqueid="ps7_can0_TXHPB_DLC_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xe0008044" start="27" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_TXHPB_DATA1_DB0">
<name>DB0</name>
<desc>Data Byte 0
Reads from this field return invalid data if the
message has no data.</desc>
<sw_param offset="0xe0008048" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_can0_TXHPB_DATA1_DB1">
<name>DB1</name>
<desc>Data Byte 1
Reads from this field return invalid data if the
message has only 1 byte of data or fewer</desc>
<sw_param offset="0xe0008048" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_can0_TXHPB_DATA1_DB2">
<name>DB2</name>
<desc>Data Byte 2
Reads from this field return invalid data if the
message has only 2 byte of data or fewer</desc>
<sw_param offset="0xe0008048" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_can0_TXHPB_DATA1_DB3">
<name>DB3</name>
<desc>Data Byte 3
Reads from this field return invalid data if the
message has only 3 byte of data or fewer</desc>
<sw_param offset="0xe0008048" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_TXHPB_DATA2_DB0">
<name>DB0</name>
<desc>Data Byte 4
Reads from this field return invalid data if the
message has only 4 byte of data or fewer</desc>
<sw_param offset="0xe000804c" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_can0_TXHPB_DATA2_DB1">
<name>DB1</name>
<desc>Data Byte 5
Reads from this field return invalid data if the
message has only 5 byte of data or fewer</desc>
<sw_param offset="0xe000804c" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_can0_TXHPB_DATA2_DB2">
<name>DB2</name>
<desc>Data Byte 6
Reads from this field return invalid data if the
message has only 6 byte of data or fewer</desc>
<sw_param offset="0xe000804c" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_can0_TXHPB_DATA2_DB3">
<name>DB3</name>
<desc>Data Byte 7
Reads from this field return invalid data if the
message has 7 byte of data or fewer</desc>
<sw_param offset="0xe000804c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_RXFIFO_ID_IDH">
<name>IDH</name>
<desc>Standard Message ID
The Identifier portion for a Standard Frame is 11 bits.
These bits indicate the Standard Frame ID.
This field is valid for both Standard and Extended
Frames.</desc>
<sw_param offset="0xe0008050" start="31" end="21" />
</parameter>
<parameter uniqueid="ps7_can0_RXFIFO_ID_SRRRTR">
<name>SRRRTR</name>
<desc>Substitute Remote Transmission Request
This bit differentiates between data frames and
remote frames. Valid only for Standard Frames. For
Extended frames this bit is 1.
1 = Indicates that the message frame is a Remote
Frame.
0 = Indicates that the message frame is a Data
Frame.</desc>
<sw_param offset="0xe0008050" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_can0_RXFIFO_ID_IDE">
<name>IDE</name>
<desc>Identifier Extension
This bit differentiates between frames using the
Standard Identifier and those using the Extended
Identifier. Valid for both Standard and Extended
Frames.
1 = Indicates the use of an Extended Message
Identifier.
0= Indicates the use of a Standard Message
Identifier.</desc>
<sw_param offset="0xe0008050" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_can0_RXFIFO_ID_IDL">
<name>IDL</name>
<desc>Extended Message ID
This field indicates the Extended Identifier.
Valid only for Extended Frames.
For Standard Frames, reads from this field return 0s
For Standard Frames, writes to this field should be 0s</desc>
<sw_param offset="0xe0008050" start="18" end="1" />
</parameter>
<parameter uniqueid="ps7_can0_RXFIFO_ID_RTR">
<name>RTR</name>
<desc>Remote Transmission Request
This bit differentiates between data frames and
remote frames.
Valid only for Extended Frames.
1 = Indicates the message object is a Remote Frame
0 = Indicates the message object is a Data Frame
For Standard Frames, reads from this bit returns 0
For Standard Frames, writes to this bit should be 0</desc>
<sw_param offset="0xe0008050" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_RXFIFO_DLC_DLC">
<name>DLC</name>
<desc>Data Length Code
This is the data length portion of the control field of
the CAN frame. This indicates the number valid data
bytes in Data Word 1 and Data Word 2 registers.</desc>
<sw_param offset="0xe0008054" start="31" end="28" />
</parameter>
<parameter uniqueid="ps7_can0_RXFIFO_DLC_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xe0008054" start="27" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_RXFIFO_DATA1_DB0">
<name>DB0</name>
<desc>Data Byte 0
Reads from this field return invalid data if the
message has no data.</desc>
<sw_param offset="0xe0008058" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_can0_RXFIFO_DATA1_DB1">
<name>DB1</name>
<desc>Data Byte 1
Reads from this field return invalid data if the
message has only 1 byte of data or fewer</desc>
<sw_param offset="0xe0008058" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_can0_RXFIFO_DATA1_DB2">
<name>DB2</name>
<desc>Data Byte 2
Reads from this field return invalid data if the
message has only 2 byte of data or fewer</desc>
<sw_param offset="0xe0008058" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_can0_RXFIFO_DATA1_DB3">
<name>DB3</name>
<desc>Data Byte 3
Reads from this field return invalid data if the
message has only 3 byte of data or fewer</desc>
<sw_param offset="0xe0008058" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_RXFIFO_DATA2_DB0">
<name>DB0</name>
<desc>Data Byte 4
Reads from this field return invalid data if the
message has only 4 byte of data or fewer</desc>
<sw_param offset="0xe000805c" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_can0_RXFIFO_DATA2_DB1">
<name>DB1</name>
<desc>Data Byte 5
Reads from this field return invalid data if the
message has only 5 byte of data or fewer</desc>
<sw_param offset="0xe000805c" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_can0_RXFIFO_DATA2_DB2">
<name>DB2</name>
<desc>Data Byte 6
Reads from this field return invalid data if the
message has only 6 byte of data or fewer</desc>
<sw_param offset="0xe000805c" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_can0_RXFIFO_DATA2_DB3">
<name>DB3</name>
<desc>Data Byte 7
Reads from this field return invalid data if the
message has 7 byte of data or fewer</desc>
<sw_param offset="0xe000805c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_AFR_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xe0008060" start="31" end="4" />
</parameter>
<parameter uniqueid="ps7_can0_AFR_UAF4">
<name>UAF4</name>
<desc>Use Acceptance Filter Number 4
Enables the use of acceptance filter pair 4.
1 = Indicates Acceptance Filter Mask Register 4 and
Acceptance Filter ID Register 4 are used for
acceptance filtering.
0 = Indicates Acceptance Filter Mask Register 4 and
Acceptance Filter ID Register 4 are not used for
acceptance filtering.</desc>
<sw_param offset="0xe0008060" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_can0_AFR_UAF3">
<name>UAF3</name>
<desc>Use Acceptance Filter Number 3
Enables the use of acceptance filter pair 3.
1 = Indicates Acceptance Filter Mask Register 3 and
Acceptance Filter ID Register 3 are used for
acceptance filtering.
0 = Indicates Acceptance Filter Mask Register 3 and
Acceptance Filter ID Register 3 are not used for
acceptance filtering.</desc>
<sw_param offset="0xe0008060" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_can0_AFR_UAF2">
<name>UAF2</name>
<desc>Use Acceptance Filter Number 2
Enables the use of acceptance filter pair 2.
1 = Indicates Acceptance Filter Mask Register 2 and
Acceptance Filter ID Register 2 are used for
acceptance filtering.
0 = Indicates Acceptance Filter Mask Register 2 and
Acceptance Filter ID Register 2 are not used for
acceptance filtering.</desc>
<sw_param offset="0xe0008060" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_can0_AFR_UAF1">
<name>UAF1</name>
<desc>Use Acceptance Filter Number 1.
Enables the use of acceptance filter pair 1.
1 = Indicates Acceptance Filter Mask Register 1 and
Acceptance Filter ID Register 1 are used for
acceptance filtering.
0 = Indicates Acceptance Filter Mask Register 1 and
Acceptance Filter ID Register 1 are not used for
acceptance filtering.</desc>
<sw_param offset="0xe0008060" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_AFMR1_AMIDH">
<name>AMIDH</name>
<desc>Standard Message ID Mask
These bits are used for masking the Identifier in a
Standard Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe0008064" start="31" end="21" />
</parameter>
<parameter uniqueid="ps7_can0_AFMR1_AMSRR">
<name>AMSRR</name>
<desc>Substitute Remote Transmission Request Mask
This bit is used for masking the RTR bit in a Standard
Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe0008064" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_can0_AFMR1_AMIDE">
<name>AMIDE</name>
<desc>Identifier Extension Mask
Used for masking the IDE bit in CAN frames.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.
If AMIDE = 1 and the AIIDE bit in the corresponding
Acceptance ID register is 0, this mask is applicable to
only Standard frames.
If AMIDE = 1 and the AIIDE bit in the corresponding
Acceptance ID register is 1, this mask is applicable to
only extended frames.
If AMIDE = 0 this mask is applicable to Standard
frame.</desc>
<sw_param offset="0xe0008064" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_can0_AFMR1_AMIDL">
<name>AMIDL</name>
<desc>Extended Message ID Mask
These bits are used for masking the Identifier in an
Extended Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe0008064" start="18" end="1" />
</parameter>
<parameter uniqueid="ps7_can0_AFMR1_AMRTR">
<name>AMRTR</name>
<desc>Remote Transmission Request Mask.
This bit is used for masking the RTR bit in an Extended
Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe0008064" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_AFIR1_AIIDH">
<name>AIIDH</name>
<desc>Standard Message ID
Standard Identifier</desc>
<sw_param offset="0xe0008068" start="31" end="21" />
</parameter>
<parameter uniqueid="ps7_can0_AFIR1_AISRR">
<name>AISRR</name>
<desc>Substitute Remote Transmission Request
Indicates the Remote Transmission Request bit for
Standard frames</desc>
<sw_param offset="0xe0008068" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_can0_AFIR1_AIIDE">
<name>AIIDE</name>
<desc>Identifier Extension
Differentiates between Standard and Extended
frames</desc>
<sw_param offset="0xe0008068" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_can0_AFIR1_AIIDL">
<name>AIIDL</name>
<desc>Extended Message ID Mask
Extended Identifier</desc>
<sw_param offset="0xe0008068" start="18" end="1" />
</parameter>
<parameter uniqueid="ps7_can0_AFIR1_AIRTR">
<name>AIRTR</name>
<desc>Remote Transmission Request Mask
RTR bit for Extended frames.</desc>
<sw_param offset="0xe0008068" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_AFMR2_AMIDH">
<name>AMIDH</name>
<desc>Standard Message ID Mask
These bits are used for masking the Identifier in a
Standard Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe000806c" start="31" end="21" />
</parameter>
<parameter uniqueid="ps7_can0_AFMR2_AMSRR">
<name>AMSRR</name>
<desc>Substitute Remote Transmission Request Mask
This bit is used for masking the RTR bit in a Standard
Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe000806c" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_can0_AFMR2_AMIDE">
<name>AMIDE</name>
<desc>Identifier Extension Mask
Used for masking the IDE bit in CAN frames.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.
If AMIDE = 1 and the AIIDE bit in the corresponding
Acceptance ID register is 0, this mask is applicable to
only Standard frames.
If AMIDE = 1 and the AIIDE bit in the corresponding
Acceptance ID register is 1, this mask is applicable to
only extended frames.
If AMIDE = 0 this mask is applicable to Standard
frame.</desc>
<sw_param offset="0xe000806c" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_can0_AFMR2_AMIDL">
<name>AMIDL</name>
<desc>Extended Message ID Mask
These bits are used for masking the Identifier in an
Extended Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe000806c" start="18" end="1" />
</parameter>
<parameter uniqueid="ps7_can0_AFMR2_AMRTR">
<name>AMRTR</name>
<desc>Remote Transmission Request Mask.
This bit is used for masking the RTR bit in an Extended
Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe000806c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_AFIR2_AIIDH">
<name>AIIDH</name>
<desc>Standard Message ID
Standard Identifier</desc>
<sw_param offset="0xe0008070" start="31" end="21" />
</parameter>
<parameter uniqueid="ps7_can0_AFIR2_AISRR">
<name>AISRR</name>
<desc>Substitute Remote Transmission Request
Indicates the Remote Transmission Request bit for
Standard frames</desc>
<sw_param offset="0xe0008070" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_can0_AFIR2_AIIDE">
<name>AIIDE</name>
<desc>Identifier Extension
Differentiates between Standard and Extended
frames</desc>
<sw_param offset="0xe0008070" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_can0_AFIR2_AIIDL">
<name>AIIDL</name>
<desc>Extended Message ID Mask
Extended Identifier</desc>
<sw_param offset="0xe0008070" start="18" end="1" />
</parameter>
<parameter uniqueid="ps7_can0_AFIR2_AIRTR">
<name>AIRTR</name>
<desc>Remote Transmission Request Mask
RTR bit for Extended frames.</desc>
<sw_param offset="0xe0008070" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_AFMR3_AMIDH">
<name>AMIDH</name>
<desc>Standard Message ID Mask
These bits are used for masking the Identifier in a
Standard Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe0008074" start="31" end="21" />
</parameter>
<parameter uniqueid="ps7_can0_AFMR3_AMSRR">
<name>AMSRR</name>
<desc>Substitute Remote Transmission Request Mask
This bit is used for masking the RTR bit in a Standard
Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe0008074" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_can0_AFMR3_AMIDE">
<name>AMIDE</name>
<desc>Identifier Extension Mask
Used for masking the IDE bit in CAN frames.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.
If AMIDE = 1 and the AIIDE bit in the corresponding
Acceptance ID register is 0, this mask is applicable to
only Standard frames.
If AMIDE = 1 and the AIIDE bit in the corresponding
Acceptance ID register is 1, this mask is applicable to
only extended frames.
If AMIDE = 0 this mask is applicable to Standard
frame.</desc>
<sw_param offset="0xe0008074" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_can0_AFMR3_AMIDL">
<name>AMIDL</name>
<desc>Extended Message ID Mask
These bits are used for masking the Identifier in an
Extended Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe0008074" start="18" end="1" />
</parameter>
<parameter uniqueid="ps7_can0_AFMR3_AMRTR">
<name>AMRTR</name>
<desc>Remote Transmission Request Mask.
This bit is used for masking the RTR bit in an Extended
Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe0008074" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_AFIR3_AIIDH">
<name>AIIDH</name>
<desc>Standard Message ID
Standard Identifier</desc>
<sw_param offset="0xe0008078" start="31" end="21" />
</parameter>
<parameter uniqueid="ps7_can0_AFIR3_AISRR">
<name>AISRR</name>
<desc>Substitute Remote Transmission Request
Indicates the Remote Transmission Request bit for
Standard frames</desc>
<sw_param offset="0xe0008078" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_can0_AFIR3_AIIDE">
<name>AIIDE</name>
<desc>Identifier Extension
Differentiates between Standard and Extended
frames</desc>
<sw_param offset="0xe0008078" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_can0_AFIR3_AIIDL">
<name>AIIDL</name>
<desc>Extended Message ID Mask
Extended Identifier</desc>
<sw_param offset="0xe0008078" start="18" end="1" />
</parameter>
<parameter uniqueid="ps7_can0_AFIR3_AIRTR">
<name>AIRTR</name>
<desc>Remote Transmission Request Mask
RTR bit for Extended frames.</desc>
<sw_param offset="0xe0008078" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_AFMR4_AMIDH">
<name>AMIDH</name>
<desc>Standard Message ID Mask
These bits are used for masking the Identifier in a
Standard Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe000807c" start="31" end="21" />
</parameter>
<parameter uniqueid="ps7_can0_AFMR4_AMSRR">
<name>AMSRR</name>
<desc>Substitute Remote Transmission Request Mask
This bit is used for masking the RTR bit in a Standard
Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe000807c" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_can0_AFMR4_AMIDE">
<name>AMIDE</name>
<desc>Identifier Extension Mask
Used for masking the IDE bit in CAN frames.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.
If AMIDE = 1 and the AIIDE bit in the corresponding
Acceptance ID register is 0, this mask is applicable to
only Standard frames.
If AMIDE = 1 and the AIIDE bit in the corresponding
Acceptance ID register is 1, this mask is applicable to
only extended frames.
If AMIDE = 0 this mask is applicable to Standard
frame.</desc>
<sw_param offset="0xe000807c" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_can0_AFMR4_AMIDL">
<name>AMIDL</name>
<desc>Extended Message ID Mask
These bits are used for masking the Identifier in an
Extended Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe000807c" start="18" end="1" />
</parameter>
<parameter uniqueid="ps7_can0_AFMR4_AMRTR">
<name>AMRTR</name>
<desc>Remote Transmission Request Mask.
This bit is used for masking the RTR bit in an Extended
Frame.
1= Indicates the corresponding bit in Acceptance
Mask ID Register is used when comparing the
incoming message identifier.
0 = Indicates the corresponding bit in Acceptance
Mask ID Register is not used when comparing the
incoming message identifier.</desc>
<sw_param offset="0xe000807c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_can0_AFIR4_AIIDH">
<name>AIIDH</name>
<desc>Standard Message ID
Standard Identifier</desc>
<sw_param offset="0xe0008080" start="31" end="21" />
</parameter>
<parameter uniqueid="ps7_can0_AFIR4_AISRR">
<name>AISRR</name>
<desc>Substitute Remote Transmission Request
Indicates the Remote Transmission Request bit for
Standard frames</desc>
<sw_param offset="0xe0008080" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_can0_AFIR4_AIIDE">
<name>AIIDE</name>
<desc>Identifier Extension
Differentiates between Standard and Extended
frames</desc>
<sw_param offset="0xe0008080" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_can0_AFIR4_AIIDL">
<name>AIIDL</name>
<desc>Extended Message ID Mask
Extended Identifier</desc>
<sw_param offset="0xe0008080" start="18" end="1" />
</parameter>
<parameter uniqueid="ps7_can0_AFIR4_AIRTR">
<name>AIRTR</name>
<desc>Remote Transmission Request Mask
RTR bit for Extended frames.</desc>
<sw_param offset="0xe0008080" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_cpu_qos_cntl_en_awar_ot">
<name>en_awar_ot</name>
<desc>Enable combined regulation of outstanding transactions.</desc>
<sw_param offset="0xf894610c" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_cpu_qos_cntl_en_ar_ot">
<name>en_ar_ot</name>
<desc>Enable regulation of outstanding read transactions.</desc>
<sw_param offset="0xf894610c" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_cpu_qos_cntl_en_aw_ot">
<name>en_aw_ot</name>
<desc>Enable regulation of outstanding write transactions.</desc>
<sw_param offset="0xf894610c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_cpu_qos_cntl_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf894610c" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_cpu_qos_cntl_en_awar_rate">
<name>en_awar_rate</name>
<desc>Enable combined AW/AR rate regulation.</desc>
<sw_param offset="0xf894610c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_cpu_qos_cntl_en_ar_rate">
<name>en_ar_rate</name>
<desc>Enable AR rate regulation.</desc>
<sw_param offset="0xf894610c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_cpu_qos_cntl_en_aw_rate">
<name>en_aw_rate</name>
<desc>Enable AW rate regulation.</desc>
<sw_param offset="0xf894610c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_cpu_max_ot_ar_max_oti">
<name>ar_max_oti</name>
<desc>Integer part of max outstanding AR addresses.</desc>
<sw_param offset="0xf8946110" start="29" end="24" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_cpu_max_ot_ar_max_otf">
<name>ar_max_otf</name>
<desc>Fraction part of max outstanding AR addresses.</desc>
<sw_param offset="0xf8946110" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_cpu_max_ot_aw_max_oti">
<name>aw_max_oti</name>
<desc>Integer part of max outstanding AW addresses.</desc>
<sw_param offset="0xf8946110" start="13" end="8" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_cpu_max_ot_aw_max_otf">
<name>aw_max_otf</name>
<desc>Fraction part of max outstanding AW addresses.</desc>
<sw_param offset="0xf8946110" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_cpu_max_comb_ot_awar_max_oti">
<name>awar_max_oti</name>
<desc>Integer part of max combined outstanding AW/AR addresses.</desc>
<sw_param offset="0xf8946114" start="14" end="8" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_cpu_max_comb_ot_awar_max_otf">
<name>awar_max_otf</name>
<desc>Fraction part of max combined outstanding AW/AR addresses.</desc>
<sw_param offset="0xf8946114" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_cpu_aw_p_a">
<name>a</name>
<desc>channel peak rate. 8-bit fraction of the number of transfers per cycle. A value of 0x80 (decimal 0.5) sets a rate of one transaction every 2 cycles. A value of 0x40 sets a rate of one transaction every 4 cycles, etc.</desc>
<sw_param offset="0xf8946118" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_cpu_aw_b_a">
<name>a</name>
<desc>channel burstiness (integer number of transfers)</desc>
<sw_param offset="0xf894611c" start="39" end="24" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_cpu_aw_r_a">
<name>a</name>
<desc>channel average rate. 12-bit fraction of the number of transfers per cycle. A value of 0x800 (decimal 0.5) sets a rate of one transaction every 2 cycles. A value of 0x400 sets a rate of one transaction every 4 cycles, etc.</desc>
<sw_param offset="0xf8946120" start="11" end="0" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_cpu_ar_p_a">
<name>a</name>
<desc>channel peak rate. 8-bit fraction of the number of transfers per cycle. A value of 0x80 (decimal 0.5) sets a rate of one transaction every 2 cycles. A value of 0x40 sets a rate of one transaction every 4 cycles, etc.</desc>
<sw_param offset="0xf8946124" start="27" end="20" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_cpu_ar_b_a">
<name>a</name>
<desc>channel burstiness (integer number of transfers)</desc>
<sw_param offset="0xf8946128" start="39" end="24" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_cpu_ar_r_a">
<name>a</name>
<desc>channel average rate. 12-bit fraction of the number of transfers per cycle. A value of 0x800 (decimal 0.5) sets a rate of one transaction every 2 cycles. A value of 0x400 sets a rate of one transaction every 4 cycles, etc.</desc>
<sw_param offset="0xf894612c" start="11" end="0" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_iou_qos_cntl_en_awar_ot">
<name>en_awar_ot</name>
<desc>Enable combined regulation of outstanding transactions.</desc>
<sw_param offset="0xf894810c" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_iou_qos_cntl_en_ar_ot">
<name>en_ar_ot</name>
<desc>Enable regulation of outstanding read transactions.</desc>
<sw_param offset="0xf894810c" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_iou_qos_cntl_en_aw_ot">
<name>en_aw_ot</name>
<desc>Enable regulation of outstanding write transactions.</desc>
<sw_param offset="0xf894810c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_iou_qos_cntl_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf894810c" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_iou_qos_cntl_en_awar_rate">
<name>en_awar_rate</name>
<desc>Enable combined AW/AR rate regulation.</desc>
<sw_param offset="0xf894810c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_iou_qos_cntl_en_ar_rate">
<name>en_ar_rate</name>
<desc>Enable AR rate regulation.</desc>
<sw_param offset="0xf894810c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_iou_qos_cntl_en_aw_rate">
<name>en_aw_rate</name>
<desc>Enable AW rate regulation.</desc>
<sw_param offset="0xf894810c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_iou_max_ot_ar_max_oti">
<name>ar_max_oti</name>
<desc>Integer part of max outstanding AR addresses.</desc>
<sw_param offset="0xf8948110" start="29" end="24" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_iou_max_ot_ar_max_otf">
<name>ar_max_otf</name>
<desc>Fraction part of max outstanding AR addresses.</desc>
<sw_param offset="0xf8948110" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_iou_max_ot_aw_max_oti">
<name>aw_max_oti</name>
<desc>Integer part of max outstanding AW addresses.</desc>
<sw_param offset="0xf8948110" start="13" end="8" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_iou_max_ot_aw_max_otf">
<name>aw_max_otf</name>
<desc>Fraction part of max outstanding AW addresses.</desc>
<sw_param offset="0xf8948110" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_iou_max_comb_ot_awar_max_oti">
<name>awar_max_oti</name>
<desc>Integer part of max combined outstanding AW/AR addresses.</desc>
<sw_param offset="0xf8948114" start="14" end="8" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_iou_max_comb_ot_awar_max_otf">
<name>awar_max_otf</name>
<desc>Fraction part of max combined outstanding AW/AR addresses.</desc>
<sw_param offset="0xf8948114" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_iou_aw_p_a">
<name>a</name>
<desc>channel peak rate. 8-bit fraction of the number of transfers per cycle. A value of 0x80 (decimal 0.5) sets a rate of one transaction every 2 cycles. A value of 0x40 sets a rate of one transaction every 4 cycles, etc.</desc>
<sw_param offset="0xf8948118" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_iou_aw_b_a">
<name>a</name>
<desc>channel burstiness (integer number of transfers)</desc>
<sw_param offset="0xf894811c" start="39" end="24" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_iou_aw_r_a">
<name>a</name>
<desc>channel average rate. 12-bit fraction of the number of transfers per cycle. A value of 0x800 (decimal 0.5) sets a rate of one transaction every 2 cycles. A value of 0x400 sets a rate of one transaction every 4 cycles, etc.</desc>
<sw_param offset="0xf8948120" start="11" end="0" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_iou_ar_p_a">
<name>a</name>
<desc>channel peak rate. 8-bit fraction of the number of transfers per cycle. A value of 0x80 (decimal 0.5) sets a rate of one transaction every 2 cycles. A value of 0x40 sets a rate of one transaction every 4 cycles, etc.</desc>
<sw_param offset="0xf8948124" start="27" end="20" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_iou_ar_b_a">
<name>a</name>
<desc>channel burstiness (integer number of transfers)</desc>
<sw_param offset="0xf8948128" start="39" end="24" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_iou_ar_r_a">
<name>a</name>
<desc>channel average rate. 12-bit fraction of the number of transfers per cycle. A value of 0x800 (decimal 0.5) sets a rate of one transaction every 2 cycles. A value of 0x400 sets a rate of one transaction every 4 cycles, etc.</desc>
<sw_param offset="0xf894812c" start="11" end="0" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_dmac_qos_cntl_en_awar_ot">
<name>en_awar_ot</name>
<desc>Enable combined regulation of outstanding transactions.</desc>
<sw_param offset="0xf894710c" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_dmac_qos_cntl_en_ar_ot">
<name>en_ar_ot</name>
<desc>Enable regulation of outstanding read transactions.</desc>
<sw_param offset="0xf894710c" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_dmac_qos_cntl_en_aw_ot">
<name>en_aw_ot</name>
<desc>Enable regulation of outstanding write transactions.</desc>
<sw_param offset="0xf894710c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_dmac_qos_cntl_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf894710c" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_dmac_qos_cntl_en_awar_rate">
<name>en_awar_rate</name>
<desc>Enable combined AW/AR rate regulation.</desc>
<sw_param offset="0xf894710c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_dmac_qos_cntl_en_ar_rate">
<name>en_ar_rate</name>
<desc>Enable AR rate regulation.</desc>
<sw_param offset="0xf894710c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_dmac_qos_cntl_en_aw_rate">
<name>en_aw_rate</name>
<desc>Enable AW rate regulation.</desc>
<sw_param offset="0xf894710c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_dmac_max_ot_ar_max_oti">
<name>ar_max_oti</name>
<desc>Integer part of max outstanding AR addresses.</desc>
<sw_param offset="0xf8947110" start="29" end="24" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_dmac_max_ot_ar_max_otf">
<name>ar_max_otf</name>
<desc>Fraction part of max outstanding AR addresses.</desc>
<sw_param offset="0xf8947110" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_dmac_max_ot_aw_max_oti">
<name>aw_max_oti</name>
<desc>Integer part of max outstanding AW addresses.</desc>
<sw_param offset="0xf8947110" start="13" end="8" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_dmac_max_ot_aw_max_otf">
<name>aw_max_otf</name>
<desc>Fraction part of max outstanding AW addresses.</desc>
<sw_param offset="0xf8947110" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_dmac_max_comb_ot_awar_max_oti">
<name>awar_max_oti</name>
<desc>Integer part of max combined outstanding AW/AR addresses.</desc>
<sw_param offset="0xf8947114" start="14" end="8" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_dmac_max_comb_ot_awar_max_otf">
<name>awar_max_otf</name>
<desc>Fraction part of max combined outstanding AW/AR addresses.</desc>
<sw_param offset="0xf8947114" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_dmac_aw_p_a">
<name>a</name>
<desc>channel peak rate. 8-bit fraction of the number of transfers per cycle. A value of 0x80 (decimal 0.5) sets a rate of one transaction every 2 cycles. A value of 0x40 sets a rate of one transaction every 4 cycles, etc.</desc>
<sw_param offset="0xf8947118" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_dmac_aw_b_a">
<name>a</name>
<desc>channel burstiness (integer number of transfers)</desc>
<sw_param offset="0xf894711c" start="39" end="24" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_dmac_aw_r_a">
<name>a</name>
<desc>channel average rate. 12-bit fraction of the number of transfers per cycle. A value of 0x800 (decimal 0.5) sets a rate of one transaction every 2 cycles. A value of 0x400 sets a rate of one transaction every 4 cycles, etc.</desc>
<sw_param offset="0xf8947120" start="11" end="0" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_dmac_ar_p_a">
<name>a</name>
<desc>channel peak rate. 8-bit fraction of the number of transfers per cycle. A value of 0x80 (decimal 0.5) sets a rate of one transaction every 2 cycles. A value of 0x40 sets a rate of one transaction every 4 cycles, etc.</desc>
<sw_param offset="0xf8947124" start="27" end="20" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_dmac_ar_b_a">
<name>a</name>
<desc>channel burstiness (integer number of transfers)</desc>
<sw_param offset="0xf8947128" start="39" end="24" />
</parameter>
<parameter uniqueid="ps7_gpv_qos301_dmac_ar_r_a">
<name>a</name>
<desc>channel average rate. 12-bit fraction of the number of transfers per cycle. A value of 0x800 (decimal 0.5) sets a rate of one transaction every 2 cycles. A value of 0x400 sets a rate of one transaction every 4 cycles, etc.</desc>
<sw_param offset="0xf894712c" start="11" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_Control_MinHoldTime">
<name>MinHoldTime</name>
<desc>The formatting scheme can easily become inefficient if fast switching occurs, so, where possible, this must be minimized. If a source has nothing to transmit, then
another source is selected irrespective of the minimum number of cycles. Reset is 0x3. The CSTF holds for the minimum hold time and one additional cycle.
The mFunnelum value that can be entered is 0xE and this equates to 15 cycles.
0xF is reserved.</desc>
<sw_param offset="0xf8804000" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_Control_EnableSlave7">
<name>EnableSlave7</name>
<desc>Setting this bit enables this slave port. If the bit is not set then this has the effect of excluding the port from the priority selection scheme.</desc>
<sw_param offset="0xf8804000" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_Control_EnableSlave6">
<name>EnableSlave6</name>
<desc>Setting this bit enables this slave port. If the bit is not set then this has the effect of excluding the port from the priority selection scheme.</desc>
<sw_param offset="0xf8804000" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_Control_EnableSlave5">
<name>EnableSlave5</name>
<desc>Setting this bit enables this slave port. If the bit is not set then this has the effect of excluding the port from the priority selection scheme.</desc>
<sw_param offset="0xf8804000" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_Control_EnableSlave4">
<name>EnableSlave4</name>
<desc>Setting this bit enables this slave port. If the bit is not set then this has the effect of excluding the port from the priority selection scheme.</desc>
<sw_param offset="0xf8804000" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_Control_EnableSlave3">
<name>EnableSlave3</name>
<desc>Setting this bit enables this slave port. If the bit is not set then this has the effect of excluding the port from the priority selection scheme.</desc>
<sw_param offset="0xf8804000" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_Control_EnableSlave2">
<name>EnableSlave2</name>
<desc>Setting this bit enables this slave port. If the bit is not set then this has the effect of excluding the port from the priority selection scheme.</desc>
<sw_param offset="0xf8804000" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_Control_EnableSlave1">
<name>EnableSlave1</name>
<desc>Setting this bit enables this slave port. If the bit is not set then this has the effect of excluding the port from the priority selection scheme.</desc>
<sw_param offset="0xf8804000" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_Control_EnableSlave0">
<name>EnableSlave0</name>
<desc>Setting this bit enables this slave port. If the bit is not set then this has the effect of excluding the port from the priority selection scheme.</desc>
<sw_param offset="0xf8804000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_PriControl_PriPort7">
<name>PriPort7</name>
<desc>8th port priority value.</desc>
<sw_param offset="0xf8804004" start="23" end="21" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_PriControl_PriPort6">
<name>PriPort6</name>
<desc>7th port priority value.</desc>
<sw_param offset="0xf8804004" start="20" end="18" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_PriControl_PriPort5">
<name>PriPort5</name>
<desc>6th port priority value.</desc>
<sw_param offset="0xf8804004" start="17" end="15" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_PriControl_PriPort4">
<name>PriPort4</name>
<desc>5th port priority value.</desc>
<sw_param offset="0xf8804004" start="14" end="12" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_PriControl_PriPort3">
<name>PriPort3</name>
<desc>4th port priority value.</desc>
<sw_param offset="0xf8804004" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_PriControl_PriPort2">
<name>PriPort2</name>
<desc>3rd port priority value.</desc>
<sw_param offset="0xf8804004" start="8" end="6" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_PriControl_PriPort1">
<name>PriPort1</name>
<desc>2nd port priority value.</desc>
<sw_param offset="0xf8804004" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_PriControl_PriPort0">
<name>PriPort0</name>
<desc>1st port priority value.</desc>
<sw_param offset="0xf8804004" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_ITATBDATA0_ATDATA31">
<name>ATDATA31</name>
<desc>Read the value of ATDATAS[31], set the value of ATDATAM[31]</desc>
<sw_param offset="0xf8804eec" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_ITATBDATA0_ATDATA23">
<name>ATDATA23</name>
<desc>Read the value of ATDATAS[23], set the value of ATDATAM[23]</desc>
<sw_param offset="0xf8804eec" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_ITATBDATA0_ATDATA15">
<name>ATDATA15</name>
<desc>Read the value of ATDATAS[15], set the value of ATDATAM[15]</desc>
<sw_param offset="0xf8804eec" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_ITATBDATA0_ATDATA7">
<name>ATDATA7</name>
<desc>Read the value of ATDATAS[7], set the value of ATDATAM[7]</desc>
<sw_param offset="0xf8804eec" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_ITATBDATA0_ATDATA0">
<name>ATDATA0</name>
<desc>Read the value of ATDATAS[0], set the value of ATDATAM[0]</desc>
<sw_param offset="0xf8804eec" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_ITATBCTR2_AFREADY">
<name>AFREADY</name>
<desc>Read the value of AFVALIDM. Set the value of AFVALIDS&lt;n&gt;, where &lt;n&gt; is defined by the status of the CSTF Control Register.</desc>
<sw_param offset="0xf8804ef0" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_ITATBCTR2_a">
<name>a</name>
<desc>Read the value of ATREADYM. Set the value of ATREADYS&lt;n&gt;, where &lt;n&gt; is defined by the status of the CSTF Control Register.</desc>
<sw_param offset="0xf8804ef0" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_ITATBCTR1_ATID">
<name>ATID</name>
<desc>Read the value of ATIDS. Set the value of ATIDM.</desc>
<sw_param offset="0xf8804ef4" start="6" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_ITATBCTR0_ATBYTES">
<name>ATBYTES</name>
<desc>Read the value of ATBYTESS&lt;n&gt;. Set the value of ATBYTESM.</desc>
<sw_param offset="0xf8804ef8" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_ITATBCTR0_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8804ef8" start="7" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_ITATBCTR0_AFREADY">
<name>AFREADY</name>
<desc>Read the value of AFREADYS&lt;n&gt;. Set the value of AFREADYM.</desc>
<sw_param offset="0xf8804ef8" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_ITATBCTR0_ATVALID">
<name>ATVALID</name>
<desc>Read the value of ATVALIDS&lt;n&gt;. Set the value of ATVALIDM.</desc>
<sw_param offset="0xf8804ef8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_IMCR_a">
<name>a</name>
<desc>Enable Integration Test registers.</desc>
<sw_param offset="0xf8804f00" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_CTSR_a">
<name>a</name>
<desc>The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed.
Read:
1= Claim tag is implemented, 0 = Claim tag is not implemented
Write:
1= Set claim tag bit, 0= No effect</desc>
<sw_param offset="0xf8804fa0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_CTCR_a">
<name>a</name>
<desc>The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed.
Read: Current value of claim tag.
Write: 1= Clear claim tag bit, 0= No effect</desc>
<sw_param offset="0xf8804fa4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_LAR_a">
<name>a</name>
<desc>Write Access Code.
Write behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
After reset (via PRESETDBGn), Funnel is locked, i.e., writes to all other registers using lower 2GB addresses are ignored.
To unlock, 0xC5ACCE55 must be written this register.
After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register.
- PADDRDBG31=1 (upper 2GB):
Funnel is unlocked when upper 2GB addresses are used to write to all the registers.
However, write to this register is ignored using a upper 2GB address!
Note: read from this register always returns 0, regardless of PADDRDBG31.</desc>
<sw_param offset="0xf8804fb0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_LSR_n8BIT">
<name>n8BIT</name>
<desc>Set to 0 since Funnel implements a 32-bit lock access register</desc>
<sw_param offset="0xf8804fb4" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_LSR_STATUS">
<name>STATUS</name>
<desc>Read behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
When a lower 2GB address is used to read this register, this bit indicates whether Funnel is in locked state
(1= locked, 0= unlocked).
- PADDRDBG31=1 (upper 2GB):
always returns 0.</desc>
<sw_param offset="0xf8804fb4" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_LSR_IMP">
<name>IMP</name>
<desc>Read behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
always returns 1, meaning lock mechanism are implemented.
- PADDRDBG31=1 (upper 2GB):
always returns 0, meaning lock mechanism is NOT implemented.</desc>
<sw_param offset="0xf8804fb4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_ASR_a">
<name>a</name>
<desc>Indicates functionality not implemented</desc>
<sw_param offset="0xf8804fb8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_DEVID_StaticPrio">
<name>StaticPrio</name>
<desc>CSTF implemts a static priority scheme</desc>
<sw_param offset="0xf8804fc8" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_DEVID_NumInPorts">
<name>NumInPorts</name>
<desc>Number of input ports</desc>
<sw_param offset="0xf8804fc8" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_DTIR_a">
<name>a</name>
<desc>a trace link and specifically a funnel/router</desc>
<sw_param offset="0xf8804fcc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_PERIPHID4_n4KB_count">
<name>n4KB_count</name>
<desc>4KB Count, set to 0</desc>
<sw_param offset="0xf8804fd0" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_PERIPHID4_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 continuation code</desc>
<sw_param offset="0xf8804fd0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_PERIPHID5_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf8804fd4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_PERIPHID6_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf8804fd8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_PERIPHID7_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf8804fdc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_PERIPHID0_a">
<name>a</name>
<desc>PartNumber0</desc>
<sw_param offset="0xf8804fe0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_PERIPHID1_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 Identity Code [3:0]</desc>
<sw_param offset="0xf8804fe4" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_PERIPHID1_PartNumber1">
<name>PartNumber1</name>
<desc>PartNumber1</desc>
<sw_param offset="0xf8804fe4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_PERIPHID2_RevNum">
<name>RevNum</name>
<desc>Revision number of Peripheral</desc>
<sw_param offset="0xf8804fe8" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_PERIPHID2_JEDEC">
<name>JEDEC</name>
<desc>Indicates that a JEDEC assigned value is used</desc>
<sw_param offset="0xf8804fe8" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_PERIPHID2_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 Identity Code [6:4]</desc>
<sw_param offset="0xf8804fe8" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_PERIPHID3_RevAnd">
<name>RevAnd</name>
<desc>RevAnd, at top level</desc>
<sw_param offset="0xf8804fec" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_PERIPHID3_CustMod">
<name>CustMod</name>
<desc>Customer Modified</desc>
<sw_param offset="0xf8804fec" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_COMPID0_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8804ff0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_COMPID1_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8804ff4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_COMPID2_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8804ff8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_funnel_COMPID3_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8804ffc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_i2c1_Control_reg0_divisor_a">
<name>divisor_a</name>
<desc>Divisor for stage A clock divider.
0 - 3: Divides the input pclk frequency by divisor_a + 1.</desc>
<sw_param offset="0xe0005000" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_i2c1_Control_reg0_divisor_b">
<name>divisor_b</name>
<desc>Divisor for stage B clock divider.
0 -31 : Divides the output frequency from divisor_a by divisor_b + 1.</desc>
<sw_param offset="0xe0005000" start="13" end="8" />
</parameter>
<parameter uniqueid="ps7_i2c1_Control_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0005000" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_i2c1_Control_reg0_CLR_FIFO">
<name>CLR_FIFO</name>
<desc>clear_fifo:This bit is implemented only if FIFO is implemented.
1 - initializes the FIFO to all zeros and clears the transfer size register. Automatically gets cleared on the next APB clock after
being set.</desc>
<sw_param offset="0xe0005000" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_i2c1_Control_reg0_SLVMON">
<name>SLVMON</name>
<desc>Slave monitor mode
1 - monitor mode.
0 - normal operation.</desc>
<sw_param offset="0xe0005000" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_i2c1_Control_reg0_HOLD">
<name>HOLD</name>
<desc>hold_bus
1 - when no more data is available for transmit or no more data can be received, hold the sclk line low until serviced by the host.
0 - allow the transfer to terminate as soon as all the data has been transmitted or received.</desc>
<sw_param offset="0xe0005000" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_i2c1_Control_reg0_ACKEN">
<name>ACKEN</name>
<desc>ackn_enabled: This bit must always be set if FIFO is implemented.
1 - acknowledge enabled, ACK transmitted
0 - acknowledge disabled, NACK transmitted.</desc>
<sw_param offset="0xe0005000" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_i2c1_Control_reg0_NEA">
<name>NEA</name>
<desc>Addressing mode: This bit is used in master
mode only.
1 - normal (7-bit) address
0 - reserved</desc>
<sw_param offset="0xe0005000" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_i2c1_Control_reg0_MS">
<name>MS</name>
<desc>Overall interface mode:
1 - master
0 - slave</desc>
<sw_param offset="0xe0005000" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_i2c1_Control_reg0_RW">
<name>RW</name>
<desc>Direction of transfer:
This bit is used in master mode only.
1 - master receiver
0 - master transmitter.</desc>
<sw_param offset="0xe0005000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_i2c1_Status_reg0_reserved_2">
<name>reserved_2</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0005004" start="15" end="9" />
</parameter>
<parameter uniqueid="ps7_i2c1_Status_reg0_BA">
<name>BA</name>
<desc>Bus Active
1 - ongoing transfer on the I2C bus.</desc>
<sw_param offset="0xe0005004" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_i2c1_Status_reg0_RXOVF">
<name>RXOVF</name>
<desc>Receiver Overflow
1 - when the receiver receives a byte of data before the previous byte has been read by the host.</desc>
<sw_param offset="0xe0005004" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_i2c1_Status_reg0_TXDV">
<name>TXDV</name>
<desc>Transmit Data Valid - SW should not use this to determine data completion, it is the RAW value on the interface.
Please use COMP in the ISR.
1 - still a byte of data to be transmitted by the interface.</desc>
<sw_param offset="0xe0005004" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_i2c1_Status_reg0_RXDV">
<name>RXDV</name>
<desc>Receiver Data Valid
1 -valid, new data to be read from the interface.</desc>
<sw_param offset="0xe0005004" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_i2c1_Status_reg0_reserved_1">
<name>reserved_1</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0005004" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_i2c1_Status_reg0_RXRW">
<name>RXRW</name>
<desc>RX read_write
1 - mode of the transmission received from a master.</desc>
<sw_param offset="0xe0005004" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_i2c1_Status_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0005004" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_i2c1_I2C_address_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0005008" start="15" end="10" />
</parameter>
<parameter uniqueid="ps7_i2c1_I2C_address_reg0_ADD">
<name>ADD</name>
<desc>Address
0 - 1024: Normal addressing mode uses add[6:0]. Extended addressing mode uses add[9:0].</desc>
<sw_param offset="0xe0005008" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_i2c1_I2C_data_reg0_reserved">
<name>reserved</name>
<desc>reads the last received byte of data.</desc>
<sw_param offset="0xe000500c" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_i2c1_I2C_data_reg0_DATA">
<name>DATA</name>
<desc>data
0 -255: When written to, the data register sets data to transmit. When read from, the data register</desc>
<sw_param offset="0xe000500c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_i2c1_Interrupt_status_reg0_reserved_1">
<name>reserved_1</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0005010" start="15" end="10" />
</parameter>
<parameter uniqueid="ps7_i2c1_Interrupt_status_reg0_ARB_LOST">
<name>ARB_LOST</name>
<desc>arbitration lost
1 = master loses bus ownership during a transfer due to ongoing arbitration</desc>
<sw_param offset="0xe0005010" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_i2c1_Interrupt_status_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0005010" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_i2c1_Interrupt_status_reg0_RX_UNF">
<name>RX_UNF</name>
<desc>FIFO receive underflow
1 = host attempts to read from the I2C data register more times than the value of the transfer size register plus one</desc>
<sw_param offset="0xe0005010" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_i2c1_Interrupt_status_reg0_TX_OVF">
<name>TX_OVF</name>
<desc>FIFO transmit overflow
1 = host attempts to write to the I2C data register more times than the FIFO depth</desc>
<sw_param offset="0xe0005010" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_i2c1_Interrupt_status_reg0_RX_OVF">
<name>RX_OVF</name>
<desc>Receive overflow
1 =
transfer is complete</desc>
<sw_param offset="0xe0005010" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_i2c1_Interrupt_status_reg0_SLV_RDY">
<name>SLV_RDY</name>
<desc>Monitored slave ready
1 =
addressed slave returns ACK.</desc>
<sw_param offset="0xe0005010" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_i2c1_Interrupt_status_reg0_TO">
<name>TO</name>
<desc>Transfer time out
1 =
I2C sclk line is kept low for longer time</desc>
<sw_param offset="0xe0005010" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_i2c1_Interrupt_status_reg0_NACK">
<name>NACK</name>
<desc>Transfer not acknowledged
1 = slave responds with a NACK or master terminates the transfer before all data is supplied</desc>
<sw_param offset="0xe0005010" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_i2c1_Interrupt_status_reg0_DATA">
<name>DATA</name>
<desc>More data
1 =
Data being sent or received</desc>
<sw_param offset="0xe0005010" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_i2c1_Interrupt_status_reg0_COMP">
<name>COMP</name>
<desc>Transfer complete
1 =
transfer is complete</desc>
<sw_param offset="0xe0005010" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_i2c1_Transfer_size_reg0_Transfer_Size">
<name>Transfer_Size</name>
<desc>Transfer Size
0-255: Master transmitter mode, Master receiver mode,
Slave transmitter mode, Slave receiver mode.</desc>
<sw_param offset="0xe0005014" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_i2c1_Slave_mon_pause_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0005018" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_i2c1_Slave_mon_pause_reg0_Pause">
<name>Pause</name>
<desc>pause interval
0 - 7: pause interval</desc>
<sw_param offset="0xe0005018" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_i2c1_Time_out_reg0_TO">
<name>TO</name>
<desc>Time Out
127 - 32 : value of time out register</desc>
<sw_param offset="0xe000501c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_mask_reg0_reserved_1">
<name>reserved_1</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0005020" start="15" end="10" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_mask_reg0_ARB_LOST">
<name>ARB_LOST</name>
<desc>arbitration lost
1 = Mask this interrupt
0 = unmask this interrupt</desc>
<sw_param offset="0xe0005020" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_mask_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0005020" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_mask_reg0_RX_UNF">
<name>RX_UNF</name>
<desc>FIFO receive underflow
1 = Mask this interrupt
0 = unmask this interrupt</desc>
<sw_param offset="0xe0005020" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_mask_reg0_TX_OVF">
<name>TX_OVF</name>
<desc>FIFO transmit overflow
1 = Mask this interrupt
0 = unmask this interrupt</desc>
<sw_param offset="0xe0005020" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_mask_reg0_RX_OVF">
<name>RX_OVF</name>
<desc>Receive overflow
1 = Mask this interrupt
0 = unmask this interrupt</desc>
<sw_param offset="0xe0005020" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_mask_reg0_SLV_RDY">
<name>SLV_RDY</name>
<desc>Monitored slave ready
1 = Mask this interrupt
0 = unmask this interrupt</desc>
<sw_param offset="0xe0005020" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_mask_reg0_TO">
<name>TO</name>
<desc>Transfer time out
1 = Mask this interrupt
0 = unmask this interrupt</desc>
<sw_param offset="0xe0005020" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_mask_reg0_NACK">
<name>NACK</name>
<desc>Transfer not acknowledged
1 = Mask this interrupt
0 = unmask this interrupt</desc>
<sw_param offset="0xe0005020" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_mask_reg0_DATA">
<name>DATA</name>
<desc>More data
1 = Mask this interrupt
0 = unmask this interrupt</desc>
<sw_param offset="0xe0005020" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_mask_reg0_COMP">
<name>COMP</name>
<desc>Transfer complete
1 = Mask this interrupt
0 = unmask this interrupt</desc>
<sw_param offset="0xe0005020" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_enable_reg0_reserved_1">
<name>reserved_1</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0005024" start="15" end="10" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_enable_reg0_ARB_LOST">
<name>ARB_LOST</name>
<desc>arbitration lost
1 = enable this interrupt</desc>
<sw_param offset="0xe0005024" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_enable_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0005024" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_enable_reg0_RX_UNF">
<name>RX_UNF</name>
<desc>FIFO receive underflow
1 = enable this interrupt</desc>
<sw_param offset="0xe0005024" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_enable_reg0_TX_OVF">
<name>TX_OVF</name>
<desc>FIFO transmit overflow
1 = enable this interrupt</desc>
<sw_param offset="0xe0005024" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_enable_reg0_RX_OVF">
<name>RX_OVF</name>
<desc>Receive overflow
1 = enable this interrupt</desc>
<sw_param offset="0xe0005024" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_enable_reg0_SLV_RDY">
<name>SLV_RDY</name>
<desc>Monitored slave ready
1 = enable this interrupt</desc>
<sw_param offset="0xe0005024" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_enable_reg0_TO">
<name>TO</name>
<desc>Transfer time out
1 = enable this interrupt</desc>
<sw_param offset="0xe0005024" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_enable_reg0_NACK">
<name>NACK</name>
<desc>Transfer not acknowledged
1 = enable this interrupt</desc>
<sw_param offset="0xe0005024" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_enable_reg0_DATA">
<name>DATA</name>
<desc>More data
1 = enable this interrupt</desc>
<sw_param offset="0xe0005024" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_enable_reg0_COMP">
<name>COMP</name>
<desc>Transfer complete
Will be set when transfer is complete
1 = enable this interrupt</desc>
<sw_param offset="0xe0005024" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_disable_reg0_reserved_1">
<name>reserved_1</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0005028" start="15" end="10" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_disable_reg0_ARB_LOST">
<name>ARB_LOST</name>
<desc>arbitration lost
1 = disable this interrupt</desc>
<sw_param offset="0xe0005028" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_disable_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0005028" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_disable_reg0_RX_UNF">
<name>RX_UNF</name>
<desc>FIFO receive underflow
1 = disable this interrupt</desc>
<sw_param offset="0xe0005028" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_disable_reg0_TX_OVF">
<name>TX_OVF</name>
<desc>FIFO transmit overflow
1 = disable this interrupt</desc>
<sw_param offset="0xe0005028" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_disable_reg0_RX_OVF">
<name>RX_OVF</name>
<desc>Receive overflow
1 = disable this interrupt</desc>
<sw_param offset="0xe0005028" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_disable_reg0_SLV_RDY">
<name>SLV_RDY</name>
<desc>Monitored slave ready
1 = disable this interrupt</desc>
<sw_param offset="0xe0005028" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_disable_reg0_TO">
<name>TO</name>
<desc>Transfer time out
1 = disable this interrupt</desc>
<sw_param offset="0xe0005028" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_disable_reg0_NACK">
<name>NACK</name>
<desc>Transfer not acknowledged
1 = disable this interrupt</desc>
<sw_param offset="0xe0005028" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_disable_reg0_DATA">
<name>DATA</name>
<desc>Master Write or Slave Transmitter
Master Read or Slave Receiver
1 = disable this interrupt</desc>
<sw_param offset="0xe0005028" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_i2c1_Intrpt_disable_reg0_COMP">
<name>COMP</name>
<desc>Transfer complete
Will be set when transfer is complete
1 = disable this interrupt</desc>
<sw_param offset="0xe0005028" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_i2c0_Control_reg0_divisor_a">
<name>divisor_a</name>
<desc>Divisor for stage A clock divider.
0 - 3: Divides the input pclk frequency by divisor_a + 1.</desc>
<sw_param offset="0xe0004000" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_i2c0_Control_reg0_divisor_b">
<name>divisor_b</name>
<desc>Divisor for stage B clock divider.
0 -31 : Divides the output frequency from divisor_a by divisor_b + 1.</desc>
<sw_param offset="0xe0004000" start="13" end="8" />
</parameter>
<parameter uniqueid="ps7_i2c0_Control_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0004000" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_i2c0_Control_reg0_CLR_FIFO">
<name>CLR_FIFO</name>
<desc>clear_fifo:This bit is implemented only if FIFO is implemented.
1 - initializes the FIFO to all zeros and clears the transfer size register. Automatically gets cleared on the next APB clock after
being set.</desc>
<sw_param offset="0xe0004000" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_i2c0_Control_reg0_SLVMON">
<name>SLVMON</name>
<desc>Slave monitor mode
1 - monitor mode.
0 - normal operation.</desc>
<sw_param offset="0xe0004000" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_i2c0_Control_reg0_HOLD">
<name>HOLD</name>
<desc>hold_bus
1 - when no more data is available for transmit or no more data can be received, hold the sclk line low until serviced by the host.
0 - allow the transfer to terminate as soon as all the data has been transmitted or received.</desc>
<sw_param offset="0xe0004000" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_i2c0_Control_reg0_ACKEN">
<name>ACKEN</name>
<desc>ackn_enabled: This bit must always be set if FIFO is implemented.
1 - acknowledge enabled, ACK transmitted
0 - acknowledge disabled, NACK transmitted.</desc>
<sw_param offset="0xe0004000" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_i2c0_Control_reg0_NEA">
<name>NEA</name>
<desc>Addressing mode: This bit is used in master
mode only.
1 - normal (7-bit) address
0 - reserved</desc>
<sw_param offset="0xe0004000" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_i2c0_Control_reg0_MS">
<name>MS</name>
<desc>Overall interface mode:
1 - master
0 - slave</desc>
<sw_param offset="0xe0004000" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_i2c0_Control_reg0_RW">
<name>RW</name>
<desc>Direction of transfer:
This bit is used in master mode only.
1 - master receiver
0 - master transmitter.</desc>
<sw_param offset="0xe0004000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_i2c0_Status_reg0_reserved_2">
<name>reserved_2</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0004004" start="15" end="9" />
</parameter>
<parameter uniqueid="ps7_i2c0_Status_reg0_BA">
<name>BA</name>
<desc>Bus Active
1 - ongoing transfer on the I2C bus.</desc>
<sw_param offset="0xe0004004" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_i2c0_Status_reg0_RXOVF">
<name>RXOVF</name>
<desc>Receiver Overflow
1 - when the receiver receives a byte of data before the previous byte has been read by the host.</desc>
<sw_param offset="0xe0004004" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_i2c0_Status_reg0_TXDV">
<name>TXDV</name>
<desc>Transmit Data Valid - SW should not use this to determine data completion, it is the RAW value on the interface.
Please use COMP in the ISR.
1 - still a byte of data to be transmitted by the interface.</desc>
<sw_param offset="0xe0004004" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_i2c0_Status_reg0_RXDV">
<name>RXDV</name>
<desc>Receiver Data Valid
1 -valid, new data to be read from the interface.</desc>
<sw_param offset="0xe0004004" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_i2c0_Status_reg0_reserved_1">
<name>reserved_1</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0004004" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_i2c0_Status_reg0_RXRW">
<name>RXRW</name>
<desc>RX read_write
1 - mode of the transmission received from a master.</desc>
<sw_param offset="0xe0004004" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_i2c0_Status_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0004004" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_i2c0_I2C_address_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0004008" start="15" end="10" />
</parameter>
<parameter uniqueid="ps7_i2c0_I2C_address_reg0_ADD">
<name>ADD</name>
<desc>Address
0 - 1024: Normal addressing mode uses add[6:0]. Extended addressing mode uses add[9:0].</desc>
<sw_param offset="0xe0004008" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_i2c0_I2C_data_reg0_reserved">
<name>reserved</name>
<desc>reads the last received byte of data.</desc>
<sw_param offset="0xe000400c" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_i2c0_I2C_data_reg0_DATA">
<name>DATA</name>
<desc>data
0 -255: When written to, the data register sets data to transmit. When read from, the data register</desc>
<sw_param offset="0xe000400c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_i2c0_Interrupt_status_reg0_reserved_1">
<name>reserved_1</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0004010" start="15" end="10" />
</parameter>
<parameter uniqueid="ps7_i2c0_Interrupt_status_reg0_ARB_LOST">
<name>ARB_LOST</name>
<desc>arbitration lost
1 = master loses bus ownership during a transfer due to ongoing arbitration</desc>
<sw_param offset="0xe0004010" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_i2c0_Interrupt_status_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0004010" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_i2c0_Interrupt_status_reg0_RX_UNF">
<name>RX_UNF</name>
<desc>FIFO receive underflow
1 = host attempts to read from the I2C data register more times than the value of the transfer size register plus one</desc>
<sw_param offset="0xe0004010" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_i2c0_Interrupt_status_reg0_TX_OVF">
<name>TX_OVF</name>
<desc>FIFO transmit overflow
1 = host attempts to write to the I2C data register more times than the FIFO depth</desc>
<sw_param offset="0xe0004010" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_i2c0_Interrupt_status_reg0_RX_OVF">
<name>RX_OVF</name>
<desc>Receive overflow
1 =
transfer is complete</desc>
<sw_param offset="0xe0004010" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_i2c0_Interrupt_status_reg0_SLV_RDY">
<name>SLV_RDY</name>
<desc>Monitored slave ready
1 =
addressed slave returns ACK.</desc>
<sw_param offset="0xe0004010" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_i2c0_Interrupt_status_reg0_TO">
<name>TO</name>
<desc>Transfer time out
1 =
I2C sclk line is kept low for longer time</desc>
<sw_param offset="0xe0004010" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_i2c0_Interrupt_status_reg0_NACK">
<name>NACK</name>
<desc>Transfer not acknowledged
1 = slave responds with a NACK or master terminates the transfer before all data is supplied</desc>
<sw_param offset="0xe0004010" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_i2c0_Interrupt_status_reg0_DATA">
<name>DATA</name>
<desc>More data
1 =
Data being sent or received</desc>
<sw_param offset="0xe0004010" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_i2c0_Interrupt_status_reg0_COMP">
<name>COMP</name>
<desc>Transfer complete
1 =
transfer is complete</desc>
<sw_param offset="0xe0004010" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_i2c0_Transfer_size_reg0_Transfer_Size">
<name>Transfer_Size</name>
<desc>Transfer Size
0-255: Master transmitter mode, Master receiver mode,
Slave transmitter mode, Slave receiver mode.</desc>
<sw_param offset="0xe0004014" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_i2c0_Slave_mon_pause_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0004018" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_i2c0_Slave_mon_pause_reg0_Pause">
<name>Pause</name>
<desc>pause interval
0 - 7: pause interval</desc>
<sw_param offset="0xe0004018" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_i2c0_Time_out_reg0_TO">
<name>TO</name>
<desc>Time Out
127 - 32 : value of time out register</desc>
<sw_param offset="0xe000401c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_mask_reg0_reserved_1">
<name>reserved_1</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0004020" start="15" end="10" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_mask_reg0_ARB_LOST">
<name>ARB_LOST</name>
<desc>arbitration lost
1 = Mask this interrupt
0 = unmask this interrupt</desc>
<sw_param offset="0xe0004020" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_mask_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0004020" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_mask_reg0_RX_UNF">
<name>RX_UNF</name>
<desc>FIFO receive underflow
1 = Mask this interrupt
0 = unmask this interrupt</desc>
<sw_param offset="0xe0004020" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_mask_reg0_TX_OVF">
<name>TX_OVF</name>
<desc>FIFO transmit overflow
1 = Mask this interrupt
0 = unmask this interrupt</desc>
<sw_param offset="0xe0004020" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_mask_reg0_RX_OVF">
<name>RX_OVF</name>
<desc>Receive overflow
1 = Mask this interrupt
0 = unmask this interrupt</desc>
<sw_param offset="0xe0004020" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_mask_reg0_SLV_RDY">
<name>SLV_RDY</name>
<desc>Monitored slave ready
1 = Mask this interrupt
0 = unmask this interrupt</desc>
<sw_param offset="0xe0004020" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_mask_reg0_TO">
<name>TO</name>
<desc>Transfer time out
1 = Mask this interrupt
0 = unmask this interrupt</desc>
<sw_param offset="0xe0004020" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_mask_reg0_NACK">
<name>NACK</name>
<desc>Transfer not acknowledged
1 = Mask this interrupt
0 = unmask this interrupt</desc>
<sw_param offset="0xe0004020" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_mask_reg0_DATA">
<name>DATA</name>
<desc>More data
1 = Mask this interrupt
0 = unmask this interrupt</desc>
<sw_param offset="0xe0004020" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_mask_reg0_COMP">
<name>COMP</name>
<desc>Transfer complete
1 = Mask this interrupt
0 = unmask this interrupt</desc>
<sw_param offset="0xe0004020" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_enable_reg0_reserved_1">
<name>reserved_1</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0004024" start="15" end="10" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_enable_reg0_ARB_LOST">
<name>ARB_LOST</name>
<desc>arbitration lost
1 = enable this interrupt</desc>
<sw_param offset="0xe0004024" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_enable_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0004024" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_enable_reg0_RX_UNF">
<name>RX_UNF</name>
<desc>FIFO receive underflow
1 = enable this interrupt</desc>
<sw_param offset="0xe0004024" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_enable_reg0_TX_OVF">
<name>TX_OVF</name>
<desc>FIFO transmit overflow
1 = enable this interrupt</desc>
<sw_param offset="0xe0004024" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_enable_reg0_RX_OVF">
<name>RX_OVF</name>
<desc>Receive overflow
1 = enable this interrupt</desc>
<sw_param offset="0xe0004024" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_enable_reg0_SLV_RDY">
<name>SLV_RDY</name>
<desc>Monitored slave ready
1 = enable this interrupt</desc>
<sw_param offset="0xe0004024" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_enable_reg0_TO">
<name>TO</name>
<desc>Transfer time out
1 = enable this interrupt</desc>
<sw_param offset="0xe0004024" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_enable_reg0_NACK">
<name>NACK</name>
<desc>Transfer not acknowledged
1 = enable this interrupt</desc>
<sw_param offset="0xe0004024" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_enable_reg0_DATA">
<name>DATA</name>
<desc>More data
1 = enable this interrupt</desc>
<sw_param offset="0xe0004024" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_enable_reg0_COMP">
<name>COMP</name>
<desc>Transfer complete
Will be set when transfer is complete
1 = enable this interrupt</desc>
<sw_param offset="0xe0004024" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_disable_reg0_reserved_1">
<name>reserved_1</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0004028" start="15" end="10" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_disable_reg0_ARB_LOST">
<name>ARB_LOST</name>
<desc>arbitration lost
1 = disable this interrupt</desc>
<sw_param offset="0xe0004028" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_disable_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0004028" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_disable_reg0_RX_UNF">
<name>RX_UNF</name>
<desc>FIFO receive underflow
1 = disable this interrupt</desc>
<sw_param offset="0xe0004028" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_disable_reg0_TX_OVF">
<name>TX_OVF</name>
<desc>FIFO transmit overflow
1 = disable this interrupt</desc>
<sw_param offset="0xe0004028" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_disable_reg0_RX_OVF">
<name>RX_OVF</name>
<desc>Receive overflow
1 = disable this interrupt</desc>
<sw_param offset="0xe0004028" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_disable_reg0_SLV_RDY">
<name>SLV_RDY</name>
<desc>Monitored slave ready
1 = disable this interrupt</desc>
<sw_param offset="0xe0004028" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_disable_reg0_TO">
<name>TO</name>
<desc>Transfer time out
1 = disable this interrupt</desc>
<sw_param offset="0xe0004028" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_disable_reg0_NACK">
<name>NACK</name>
<desc>Transfer not acknowledged
1 = disable this interrupt</desc>
<sw_param offset="0xe0004028" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_disable_reg0_DATA">
<name>DATA</name>
<desc>Master Write or Slave Transmitter
Master Read or Slave Receiver
1 = disable this interrupt</desc>
<sw_param offset="0xe0004028" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_i2c0_Intrpt_disable_reg0_COMP">
<name>COMP</name>
<desc>Transfer complete
Will be set when transfer is complete
1 = disable this interrupt</desc>
<sw_param offset="0xe0004028" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg0_cache_id_implementer">
<name>implementer</name>
<desc>0x41, ARM</desc>
<sw_param offset="0xf8f02000" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg0_cache_id_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f02000" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg0_cache_id_cache_id">
<name>cache_id</name>
<desc>cache id</desc>
<sw_param offset="0xf8f02000" start="15" end="10" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg0_cache_id_part_num">
<name>part_num</name>
<desc>part number</desc>
<sw_param offset="0xf8f02000" start="9" end="6" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg0_cache_id_rtl_release">
<name>rtl_release</name>
<desc>RTL release R3p2</desc>
<sw_param offset="0xf8f02000" start="5" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg0_cache_type_data_banking">
<name>data_banking</name>
<desc>0 = Data banking not implemented.
1 = Data banking implemented.</desc>
<sw_param offset="0xf8f02004" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg0_cache_type_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f02004" start="30" end="29" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg0_cache_type_ctype">
<name>ctype</name>
<desc>11xy, where:
x=1 if pl310_LOCKDOWN_BY_MASTER is defined, otherwise 0
y=1 if pl310_LOCKDOWN_BY_LINE is defined, otherwise 0.</desc>
<sw_param offset="0xf8f02004" start="28" end="25" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg0_cache_type_H">
<name>H</name>
<desc>unified</desc>
<sw_param offset="0xf8f02004" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg0_cache_type_Dsize_23">
<name>Dsize_23</name>
<desc>fixed to 0</desc>
<sw_param offset="0xf8f02004" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg0_cache_type_Dsize_mid">
<name>Dsize_mid</name>
<desc>L2 cache way size Read from Auxiliary Control Register19 through 17</desc>
<sw_param offset="0xf8f02004" start="22" end="20" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg0_cache_type_Dsize_19">
<name>Dsize_19</name>
<desc>fixed to 0</desc>
<sw_param offset="0xf8f02004" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg0_cache_type_L2_assoc_D">
<name>L2_assoc_D</name>
<desc>Read from Auxiliary Control Register bit 16</desc>
<sw_param offset="0xf8f02004" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg0_cache_type_reserved_1">
<name>reserved_1</name>
<desc>reserved</desc>
<sw_param offset="0xf8f02004" start="17" end="14" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg0_cache_type_l2cache_line_len_D">
<name>l2cache_line_len_D</name>
<desc>L2 cache line length - 00-32 bytes</desc>
<sw_param offset="0xf8f02004" start="13" end="12" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg0_cache_type_Isize_11">
<name>Isize_11</name>
<desc>fixed to 0</desc>
<sw_param offset="0xf8f02004" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg0_cache_type_Isize_mid">
<name>Isize_mid</name>
<desc>L2 cache way size Read from Auxiliary Control Register[19:17]</desc>
<sw_param offset="0xf8f02004" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg0_cache_type_Isize_7">
<name>Isize_7</name>
<desc>fixed to 0</desc>
<sw_param offset="0xf8f02004" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg0_cache_type_L2_assoc_I">
<name>L2_assoc_I</name>
<desc>Read from Auxiliary Control Register bit 16</desc>
<sw_param offset="0xf8f02004" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg0_cache_type_reserved_2">
<name>reserved_2</name>
<desc>reserved</desc>
<sw_param offset="0xf8f02004" start="5" end="2" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg0_cache_type_l2cache_line_len_I">
<name>l2cache_line_len_I</name>
<desc>L2 cache line length - 00-32 bytes</desc>
<sw_param offset="0xf8f02004" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_control_reserved">
<name>reserved</name>
<desc>reserved, reserved</desc>
<sw_param offset="0xf8f02100" start="30" end="1" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_control_l2_enable">
<name>l2_enable</name>
<desc>0 = L2 Cache is disabled. This is the default value.
1 = L2 Cache is enabled.</desc>
<sw_param offset="0xf8f02100" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_aux_control_reserved">
<name>reserved</name>
<desc>reserved, reserved</desc>
<sw_param offset="0xf8f02104" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_aux_control_early_bresp_en">
<name>early_bresp_en</name>
<desc>Early BRESP enable
0 = Early BRESP disabled. This is the default.
1 = Early BRESP enabled.</desc>
<sw_param offset="0xf8f02104" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_aux_control_instr_prefetch_en">
<name>instr_prefetch_en</name>
<desc>Instruction prefetch enable
0 = Instruction prefetching disabled. This is the default.
1 = Instruction prefetching enabled.</desc>
<sw_param offset="0xf8f02104" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_aux_control_data_prefetch_en">
<name>data_prefetch_en</name>
<desc>Data prefetch enable
0 = Data prefetching disabled. This is the default.
1 = Data prefetching enabled.</desc>
<sw_param offset="0xf8f02104" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_aux_control_nonsec_inte_access_ctrl">
<name>nonsec_inte_access_ctrl</name>
<desc>Non-secure interrupt access control 0 = Interrupt Clear, 0x220, and Interrupt Mask, 0x214, can only be modified or read
with secure accesses. This is the default.
1 = Interrupt Clear, 0x220, and Interrupt Mask, 0x214, can be modified or read with
secure or non-secure accesses.</desc>
<sw_param offset="0xf8f02104" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_aux_control_nonsec_lockdown_en">
<name>nonsec_lockdown_en</name>
<desc>Non-secure lockdown enable
0 = Lockdown registers cannot be modified using non-secure accesses. This is the
default.
1 = Non-secure accesses can write to the lockdown registers.</desc>
<sw_param offset="0xf8f02104" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_aux_control_cache_replace_policy">
<name>cache_replace_policy</name>
<desc>Cache replacement policy
0 = pseudo-random replacement using lfsr.
1 = round-robin replacement. This is the default.</desc>
<sw_param offset="0xf8f02104" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_aux_control_force_write_alloc">
<name>force_write_alloc</name>
<desc>Force write allocate
b00 = Use AWCACHE attributes for WA. This is the default.
b01 = Force no allocate, set WA bit always 0.
b10 = Override AWCACHE attributes, set WA bit always 1, all cacheable write
misses become write allocated.
b11 = Internally mapped to 00. See Cache operation on page 2-11 for more
information.</desc>
<sw_param offset="0xf8f02104" start="24" end="23" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_aux_control_shared_attr_override_en">
<name>shared_attr_override_en</name>
<desc>Shared attribute override enable
0 = Treats shared accesses as specified in Shareable attribute on page 2-15. This
is the default.
1 = Shared attribute internally ignored.</desc>
<sw_param offset="0xf8f02104" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_aux_control_parity_en">
<name>parity_en</name>
<desc>Parity enable
0 = Disabled. This is the default.
1 = Enabled</desc>
<sw_param offset="0xf8f02104" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_aux_control_event_mon_bus_en">
<name>event_mon_bus_en</name>
<desc>Event monitor bus enable
0 = Disabled. This is the default.
1 = Enabled</desc>
<sw_param offset="0xf8f02104" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_aux_control_way_size">
<name>way_size</name>
<desc>Way-size
b000 = Reserved, internally mapped to 16KB.
b001 = 16KB.
b010 = 32KB.
b011 = 64KB.
b100 = 128KB.
b101 = 256KB.
b110 = 512KB.
b111 = Reserved, internally mapped to 512 KB.</desc>
<sw_param offset="0xf8f02104" start="19" end="17" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_aux_control_associativity">
<name>associativity</name>
<desc>Associativity
0 = 8-way.
1 = 16-way.</desc>
<sw_param offset="0xf8f02104" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_aux_control_reserved_1">
<name>reserved_1</name>
<desc>reserved, reserved</desc>
<sw_param offset="0xf8f02104" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_aux_control_shared_attr_inva_en">
<name>shared_attr_inva_en</name>
<desc>Shared Attribute Invalidate
Enable 0 = Shared invalidate behavior disabled. This is the default.
1 = Shared invalidate behavior enabled, if Shared Attribute Override Enable bit
not set. See Shareable attribute on page 2-15.</desc>
<sw_param offset="0xf8f02104" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_aux_control_ex_cache_config">
<name>ex_cache_config</name>
<desc>Exclusive cache configuration
0 = Disabled. This is the default.
1 = Enabled,</desc>
<sw_param offset="0xf8f02104" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_aux_control_store_buff_dev_lim_en">
<name>store_buff_dev_lim_en</name>
<desc>Store buffer device limitation Enable
0 = Store buffer device limitation disabled. Device writes can take all slots in store
buffer. This is the default.
1= Store buffer device limitation enabled. Device writes cannot take all slots in
store buffer when connected to the Cortex-A9 MPCore processor. There is always
one available slot to service Normal Memory</desc>
<sw_param offset="0xf8f02104" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_aux_control_high_pr_so_dev_rd_en">
<name>high_pr_so_dev_rd_en</name>
<desc>High Priority for SO and Dev Reads Enable
0 = Strongly Ordered and Device reads have lower priority than cacheable
accesses when arbitrated in the L2CC (L2C-310) master ports. This is the default.
1 = Strongly Ordered and Device reads get the highest priority when arbitrated in
the L2CC (L2C-310) master ports.</desc>
<sw_param offset="0xf8f02104" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_aux_control_reserved_2">
<name>reserved_2</name>
<desc>reserved, reserved</desc>
<sw_param offset="0xf8f02104" start="9" end="1" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_aux_control_full_line_zero_enable">
<name>full_line_zero_enable</name>
<desc>Full Line of Zero Enable
0 = Full line of write zero behavior disabled. This is the default.
1 = Full line of write zero behavior Enabled.</desc>
<sw_param offset="0xf8f02104" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_tag_ram_control_reserved">
<name>reserved</name>
<desc>reserved, reserved</desc>
<sw_param offset="0xf8f02108" start="31" end="11" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_tag_ram_control_ram_wr_access_lat">
<name>ram_wr_access_lat</name>
<desc>RAM write access latency Default value depends on the value of pl310_TAG_WRITE_LAT
b000 = 1 cycle of latency, there is no additional latency.
b001 = 2 cycles of latency.
b010 = 3 cycles of latency.
b011 = 4 cycles of latency.
b100 = 5 cycles of latency.
b101 = 6 cycles of latency.
b110 = 7 cycles of latency.
b111 = 8 cycles of latency</desc>
<sw_param offset="0xf8f02108" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_tag_ram_control_reserved_1">
<name>reserved_1</name>
<desc>reserved, reserved</desc>
<sw_param offset="0xf8f02108" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_tag_ram_control_ram_rd_access_lat">
<name>ram_rd_access_lat</name>
<desc>RAM read access latency Default value depends on the value of pl310_TAG_READ_LAT
b000 = 1 cycle of latency, there is no additional latency.
b001 = 2 cycles of latency.
b010 = 3 cycles of latency.
b011 = 4 cycles of latency.
b100 = 5 cycles of latency.
b101 = 6 cycles of latency.
b110 = 7 cycles of latency.
b111 = 8 cycles of latency.</desc>
<sw_param offset="0xf8f02108" start="6" end="4" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_tag_ram_control_reserved_2">
<name>reserved_2</name>
<desc>reserved, reserved</desc>
<sw_param offset="0xf8f02108" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_tag_ram_control_ram_setup_lat">
<name>ram_setup_lat</name>
<desc>RAM setup latency Default value depends on the value of pl310_TAG_SETUP_LAT
b000 = 1 cycle of latency, there is no additional latency.
b001 = 2 cycles of latency.
b010 = 3 cycles of latency.
b011 = 4 cycles of latency.
b100 = 5 cycles of latency.
b101 = 6 cycles of latency.
b110 = 7 cycles of latency.
b111 = 8 cycles of latency.</desc>
<sw_param offset="0xf8f02108" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_data_ram_control_reserved">
<name>reserved</name>
<desc>reserved, reserved</desc>
<sw_param offset="0xf8f0210c" start="31" end="11" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_data_ram_control_ram_wr_access_lat">
<name>ram_wr_access_lat</name>
<desc>RAM write access latency Default value depends on the value of pl310_DATA_WRITE_LAT
b000 = 1 cycle of latency, there is no additional latency.
b001 = 2 cycles of latency.
b010 = 3 cycles of latency.
b011 = 4 cycles of latency.
b100 = 5 cycles of latency.
b101 = 6 cycles of latency.
b110 = 7 cycles of latency.
b111 = 8 cycles of latency</desc>
<sw_param offset="0xf8f0210c" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_data_ram_control_reserved_1">
<name>reserved_1</name>
<desc>reserved, reserved</desc>
<sw_param offset="0xf8f0210c" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_data_ram_control_ram_rd_access_lat">
<name>ram_rd_access_lat</name>
<desc>RAM read access latency Default value depends on the value of pl310_DATA_READ_LAT
b000 = 1 cycle of latency, there is no additional latency.
b001 = 2 cycles of latency.
b010 = 3 cycles of latency.
b011 = 4 cycles of latency.
b100 = 5 cycles of latency.
b101 = 6 cycles of latency.
b110 = 7 cycles of latency.
b111 = 8 cycles of latency.</desc>
<sw_param offset="0xf8f0210c" start="6" end="4" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_data_ram_control_reserved_2">
<name>reserved_2</name>
<desc>reserved, reserved</desc>
<sw_param offset="0xf8f0210c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg1_data_ram_control_ran_setup_lat">
<name>ran_setup_lat</name>
<desc>RAM setup latency Default value depends on the value of pl310_DATA_SETUP_LAT
b000 = 1 cycle of latency, there is no additional latency.
b001 = 2 cycles of latency.
b010 = 3 cycles of latency.
b011 = 4 cycles of latency.
b100 = 5 cycles of latency.
b101 = 6 cycles of latency.
b110 = 7 cycles of latency.
b111 = 8 cycles of latency.</desc>
<sw_param offset="0xf8f0210c" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_ev_counter_ctrl_reserved">
<name>reserved</name>
<desc>reserved, reserved</desc>
<sw_param offset="0xf8f02200" start="31" end="3" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_ev_counter_ctrl_counter_reset">
<name>counter_reset</name>
<desc>Always Read as zero. The following counters are reset when a 1 is written to the following bits:
bit[2] = Event Counter1 reset
bit[1] = Event Counter0 reset.</desc>
<sw_param offset="0xf8f02200" start="2" end="1" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_ev_counter_ctrl_ev_ctr_en">
<name>ev_ctr_en</name>
<desc>Event counter enable 0 = Event Counting Disable. This is the default.
1 = Event Counting Enable.</desc>
<sw_param offset="0xf8f02200" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_ev_counter1_cfg_reserved">
<name>reserved</name>
<desc>reserved, reserved</desc>
<sw_param offset="0xf8f02204" start="31" end="6" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_ev_counter1_cfg_ctr_ev_src">
<name>ctr_ev_src</name>
<desc>Counter event source Event Encoding
Counter Disabled b0000
CO b0001
DRHIT b0010
DRREQ b0011
DWHIT b0100
DWREQ b0101
DWTREQ b0110
IRHIT b0111
IRREQ b1000
WA b1001
IPFALLOC b1010
EPFHIT b1011
EPFALLOC b1100
SRRCVD b1101
SRCONF b1110
EPFRCVD b1111</desc>
<sw_param offset="0xf8f02204" start="5" end="2" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_ev_counter1_cfg_ev_ctr_intr_gen">
<name>ev_ctr_intr_gen</name>
<desc>Event counter interrupt generation b00 = Disabled. This is the default.
b01 = Enabled: Increment condition.
b10 = Enabled: Overflow condition.
b11 = Interrupt generation is disabled.</desc>
<sw_param offset="0xf8f02204" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_ev_counter0_cfg_reserved">
<name>reserved</name>
<desc>reserved, reserved</desc>
<sw_param offset="0xf8f02208" start="31" end="6" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_ev_counter0_cfg_ctr_ev_src">
<name>ctr_ev_src</name>
<desc>Counter event source Event Encoding
Counter Disabled b0000
CO b0001
DRHIT b0010
DRREQ b0011
DWHIT b0100
DWREQ b0101
DWTREQ b0110
IRHIT b0111
IRREQ b1000
WA b1001
IPFALLOC b1010
EPFHIT b1011
EPFALLOC b1100
SRRCVD b1101
SRCONF b1110
EPFRCVD b1111</desc>
<sw_param offset="0xf8f02208" start="5" end="2" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_ev_counter0_cfg_ev_ctr_intr_gen">
<name>ev_ctr_intr_gen</name>
<desc>Event counter interrupt generation b00 = Disabled. This is the default.
b01 = Enabled: Increment condition.
b10 = Enabled: Overflow condition.
b11 = Interrupt generation is disabled.</desc>
<sw_param offset="0xf8f02208" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_ev_counter1_counter_val">
<name>counter_val</name>
<desc>Total of the event selected.
If a counter reaches its maximum value, it saturates at that value until it is reset.</desc>
<sw_param offset="0xf8f0220c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_ev_counter0_counter_val">
<name>counter_val</name>
<desc>Total of the event selected.
If a counter reaches its maximum value, it saturates at that value until it is reset.</desc>
<sw_param offset="0xf8f02210" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_mask_reserved">
<name>reserved</name>
<desc>reserved, reserved</desc>
<sw_param offset="0xf8f02214" start="31" end="9" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_mask_DECERR">
<name>DECERR</name>
<desc>DECERR: DECERR from L3</desc>
<sw_param offset="0xf8f02214" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_mask_SLVERR">
<name>SLVERR</name>
<desc>SLVERR: SLVERR from L3</desc>
<sw_param offset="0xf8f02214" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_mask_ERRRD">
<name>ERRRD</name>
<desc>ERRRD: Error on L2 data RAM, Read</desc>
<sw_param offset="0xf8f02214" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_mask_ERRRT">
<name>ERRRT</name>
<desc>ERRRT: Error on L2 tag RAM, Read</desc>
<sw_param offset="0xf8f02214" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_mask_ERRWD">
<name>ERRWD</name>
<desc>ERRWD: Error on L2 data RAM, Write</desc>
<sw_param offset="0xf8f02214" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_mask_ERRWT">
<name>ERRWT</name>
<desc>ERRWT: Error on L2 tag RAM, Write</desc>
<sw_param offset="0xf8f02214" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_mask_PARRD">
<name>PARRD</name>
<desc>PARRD: Parity Error on L2 data RAM, Read</desc>
<sw_param offset="0xf8f02214" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_mask_PARRT">
<name>PARRT</name>
<desc>PARRT: Parity Error on L2 tag RAM, Read</desc>
<sw_param offset="0xf8f02214" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_mask_ECNTR">
<name>ECNTR</name>
<desc>ECNTR: Event Counter1/0 Overflow Increment</desc>
<sw_param offset="0xf8f02214" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_mask_status_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f02218" start="31" end="9" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_mask_status_DECERR">
<name>DECERR</name>
<desc>DECERR: DECERR from L3</desc>
<sw_param offset="0xf8f02218" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_mask_status_SLVERR">
<name>SLVERR</name>
<desc>SLVERR: SLVERR from L3</desc>
<sw_param offset="0xf8f02218" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_mask_status_ERRRD">
<name>ERRRD</name>
<desc>ERRRD: Error on L2 data RAM, Read</desc>
<sw_param offset="0xf8f02218" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_mask_status_ERRRT">
<name>ERRRT</name>
<desc>ERRRT: Error on L2 tag RAM, Read</desc>
<sw_param offset="0xf8f02218" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_mask_status_ERRWD">
<name>ERRWD</name>
<desc>ERRWD: Error on L2 data RAM, Write</desc>
<sw_param offset="0xf8f02218" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_mask_status_ERRWT">
<name>ERRWT</name>
<desc>ERRWT: Error on L2 tag RAM, Write</desc>
<sw_param offset="0xf8f02218" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_mask_status_PARRD">
<name>PARRD</name>
<desc>PARRD: Parity Error on L2 data RAM, Read</desc>
<sw_param offset="0xf8f02218" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_mask_status_PARRT">
<name>PARRT</name>
<desc>PARRT: Parity Error on L2 tag RAM, Read</desc>
<sw_param offset="0xf8f02218" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_mask_status_ECNTR">
<name>ECNTR</name>
<desc>ECNTR: Event Counter1/0 Overflow Increment</desc>
<sw_param offset="0xf8f02218" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_raw_status_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f0221c" start="31" end="9" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_raw_status_DECERR">
<name>DECERR</name>
<desc>DECERR: DECERR from L3</desc>
<sw_param offset="0xf8f0221c" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_raw_status_SLVERR">
<name>SLVERR</name>
<desc>SLVERR: SLVERR from L3</desc>
<sw_param offset="0xf8f0221c" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_raw_status_ERRRD">
<name>ERRRD</name>
<desc>ERRRD: Error on L2 data RAM, Read</desc>
<sw_param offset="0xf8f0221c" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_raw_status_ERRRT">
<name>ERRRT</name>
<desc>ERRRT: Error on L2 tag RAM, Read</desc>
<sw_param offset="0xf8f0221c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_raw_status_ERRWD">
<name>ERRWD</name>
<desc>ERRWD: Error on L2 data RAM, Write</desc>
<sw_param offset="0xf8f0221c" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_raw_status_ERRWT">
<name>ERRWT</name>
<desc>ERRWT: Error on L2 tag RAM, Write</desc>
<sw_param offset="0xf8f0221c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_raw_status_PARRD">
<name>PARRD</name>
<desc>PARRD: Parity Error on L2 data RAM, Read</desc>
<sw_param offset="0xf8f0221c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_raw_status_PARRT">
<name>PARRT</name>
<desc>PARRT: Parity Error on L2 tag RAM, Read</desc>
<sw_param offset="0xf8f0221c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_raw_status_ECNTR">
<name>ECNTR</name>
<desc>ECNTR: Event Counter1/0 Overflow Increment</desc>
<sw_param offset="0xf8f0221c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_clear_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f02220" start="31" end="9" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_clear_DECERR">
<name>DECERR</name>
<desc>DECERR: DECERR from L3</desc>
<sw_param offset="0xf8f02220" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_clear_SLVERR">
<name>SLVERR</name>
<desc>SLVERR: SLVERR from L3</desc>
<sw_param offset="0xf8f02220" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_clear_ERRRD">
<name>ERRRD</name>
<desc>ERRRD: Error on L2 data RAM, Read</desc>
<sw_param offset="0xf8f02220" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_clear_ERRRT">
<name>ERRRT</name>
<desc>ERRRT: Error on L2 tag RAM, Read</desc>
<sw_param offset="0xf8f02220" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_clear_ERRWD">
<name>ERRWD</name>
<desc>ERRWD: Error on L2 data RAM, Write</desc>
<sw_param offset="0xf8f02220" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_clear_ERRWT">
<name>ERRWT</name>
<desc>ERRWT: Error on L2 tag RAM, Write</desc>
<sw_param offset="0xf8f02220" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_clear_PARRD">
<name>PARRD</name>
<desc>PARRD: Parity Error on L2 data RAM, Read</desc>
<sw_param offset="0xf8f02220" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_clear_PARRT">
<name>PARRT</name>
<desc>PARRT: Parity Error on L2 tag RAM, Read</desc>
<sw_param offset="0xf8f02220" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg2_int_clear_ECNTR">
<name>ECNTR</name>
<desc>ECNTR: Event Counter1/0 Overflow Increment</desc>
<sw_param offset="0xf8f02220" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_cache_sync_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f02730" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_cache_sync_c">
<name>c</name>
<desc>Cache Sync: Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and EB, are empty.</desc>
<sw_param offset="0xf8f02730" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_inv_pa_tag">
<name>tag</name>
<desc>tag</desc>
<sw_param offset="0xf8f02770" start="31" end="12" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_inv_pa_index">
<name>index</name>
<desc>index</desc>
<sw_param offset="0xf8f02770" start="11" end="5" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_inv_pa_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f02770" start="4" end="1" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_inv_pa_c">
<name>c</name>
<desc>C Flag
When written must be 0.
When read, indicates that a background operation is in progress</desc>
<sw_param offset="0xf8f02770" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_inv_way_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f0277c" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_inv_way_way_bits">
<name>way_bits</name>
<desc>way bits: You can select multiple ways at the same time, by setting the Way bits to 1</desc>
<sw_param offset="0xf8f0277c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_clean_pa_tag">
<name>tag</name>
<desc>tag</desc>
<sw_param offset="0xf8f027b0" start="31" end="12" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_clean_pa_index">
<name>index</name>
<desc>index</desc>
<sw_param offset="0xf8f027b0" start="11" end="5" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_clean_pa_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f027b0" start="4" end="1" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_clean_pa_c">
<name>c</name>
<desc>C Flag
When written must be 0.
When read, indicates that a background operation is in progress</desc>
<sw_param offset="0xf8f027b0" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_clean_index_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f027b8" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_clean_index_way">
<name>way</name>
<desc>way</desc>
<sw_param offset="0xf8f027b8" start="30" end="28" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_clean_index_reserved_1">
<name>reserved_1</name>
<desc>reserved</desc>
<sw_param offset="0xf8f027b8" start="27" end="12" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_clean_index_index">
<name>index</name>
<desc>index</desc>
<sw_param offset="0xf8f027b8" start="11" end="5" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_clean_index_reserved_2">
<name>reserved_2</name>
<desc>reserved</desc>
<sw_param offset="0xf8f027b8" start="4" end="1" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_clean_index_c">
<name>c</name>
<desc>c</desc>
<sw_param offset="0xf8f027b8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_clean_way_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f027bc" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_clean_way_way_bits">
<name>way_bits</name>
<desc>way bits: You can select multiple ways at the same time, by setting the Way bits to 1</desc>
<sw_param offset="0xf8f027bc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_clean_inv_pa_tag">
<name>tag</name>
<desc>tag</desc>
<sw_param offset="0xf8f027f0" start="31" end="12" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_clean_inv_pa_index">
<name>index</name>
<desc>index</desc>
<sw_param offset="0xf8f027f0" start="11" end="5" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_clean_inv_pa_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f027f0" start="4" end="1" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_clean_inv_pa_c">
<name>c</name>
<desc>C Flag
When written must be 0.
When read, indicates that a background operation is in progress</desc>
<sw_param offset="0xf8f027f0" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_clean_inv_index_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f027f8" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_clean_inv_index_way">
<name>way</name>
<desc>way</desc>
<sw_param offset="0xf8f027f8" start="30" end="28" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_clean_inv_index_reserved_1">
<name>reserved_1</name>
<desc>reserved</desc>
<sw_param offset="0xf8f027f8" start="27" end="12" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_clean_inv_index_index">
<name>index</name>
<desc>index</desc>
<sw_param offset="0xf8f027f8" start="11" end="5" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_clean_inv_index_reserved_2">
<name>reserved_2</name>
<desc>reserved</desc>
<sw_param offset="0xf8f027f8" start="4" end="1" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_clean_inv_index_c">
<name>c</name>
<desc>c</desc>
<sw_param offset="0xf8f027f8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_clean_inv_way_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f027fc" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg7_clean_inv_way_way_bits">
<name>way_bits</name>
<desc>way bits: You can select multiple ways at the same time, by setting the Way bits to 1</desc>
<sw_param offset="0xf8f027fc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_d_lockdown0_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f02900" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_d_lockdown0_DATALOCK000">
<name>DATALOCK000</name>
<desc>Use when AR/WUSERSx[7:5] = 000</desc>
<sw_param offset="0xf8f02900" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_i_lockdown0_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f02904" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_i_lockdown0_INSTRLOCK000">
<name>INSTRLOCK000</name>
<desc>Use when AR/WUSERSx[7:5] = 000</desc>
<sw_param offset="0xf8f02904" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_d_lockdown1_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f02908" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_d_lockdown1_DATALOCK001">
<name>DATALOCK001</name>
<desc>Use when AR/WUSERSx[7:5] = 001</desc>
<sw_param offset="0xf8f02908" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_i_lockdown1_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f0290c" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_i_lockdown1_INSTRLOCK001">
<name>INSTRLOCK001</name>
<desc>Use when AR/WUSERSx[7:5] = 001</desc>
<sw_param offset="0xf8f0290c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_d_lockdown2_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f02910" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_d_lockdown2_DATALOCK010">
<name>DATALOCK010</name>
<desc>Use when AR/WUSERSx[7:5] = 010</desc>
<sw_param offset="0xf8f02910" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_i_lockdown2_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f02914" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_i_lockdown2_INSTRLOCK010">
<name>INSTRLOCK010</name>
<desc>Use when AR/WUSERSx[7:5] = 010</desc>
<sw_param offset="0xf8f02914" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_d_lockdown3_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f02918" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_d_lockdown3_DATALOCK011">
<name>DATALOCK011</name>
<desc>Use when AR/WUSERSx[7:5] = 011</desc>
<sw_param offset="0xf8f02918" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_i_lockdown3_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f0291c" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_i_lockdown3_INSTRLOCK011">
<name>INSTRLOCK011</name>
<desc>Use when AR/WUSERSx[7:5] = 011</desc>
<sw_param offset="0xf8f0291c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_d_lockdown4_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f02920" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_d_lockdown4_DATALOCK100">
<name>DATALOCK100</name>
<desc>Use when AR/WUSERSx[7:5] = 100</desc>
<sw_param offset="0xf8f02920" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_i_lockdown4_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f02924" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_i_lockdown4_INSTRLOCK100">
<name>INSTRLOCK100</name>
<desc>Use when AR/WUSERSx[7:5] = 100</desc>
<sw_param offset="0xf8f02924" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_d_lockdown5_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f02928" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_d_lockdown5_DATALOCK101">
<name>DATALOCK101</name>
<desc>Use when AR/WUSERSx[7:5] = 101</desc>
<sw_param offset="0xf8f02928" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_i_lockdown5_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f0292c" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_i_lockdown5_INSTRLOCK101">
<name>INSTRLOCK101</name>
<desc>Use when AR/WUSERSx[7:5] = 101</desc>
<sw_param offset="0xf8f0292c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_d_lockdown6_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f02930" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_d_lockdown6_DATALOCK110">
<name>DATALOCK110</name>
<desc>Use when AR/WUSERSx[7:5] = 110</desc>
<sw_param offset="0xf8f02930" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_i_lockdown6_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f02934" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_i_lockdown6_INSTRLOCK110">
<name>INSTRLOCK110</name>
<desc>Use when AR/WUSERSx[7:5] = 110</desc>
<sw_param offset="0xf8f02934" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_d_lockdown7_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f02938" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_d_lockdown7_DATALOCK111">
<name>DATALOCK111</name>
<desc>Use when AR/WUSERSx[7:5] = 111</desc>
<sw_param offset="0xf8f02938" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_i_lockdown7_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f0293c" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_i_lockdown7_INSTRLOCK111">
<name>INSTRLOCK111</name>
<desc>Use when AR/WUSERSx[7:5] = 111</desc>
<sw_param offset="0xf8f0293c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_lock_line_en_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f02950" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_lock_line_en_lock_down_by_line_enable">
<name>lock_down_by_line_enable</name>
<desc>0 = Lockdown by line disabled. This is the default.
1 = Lockdown by line enabled.</desc>
<sw_param offset="0xf8f02950" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_unlock_way_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f02954" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg9_unlock_way_unlock_all_lines_by_way_operation">
<name>unlock_all_lines_by_way_operation</name>
<desc>For all bits:
0 = Unlock all lines disabled. This is the default.
1 = Unlock all lines operation in progress for the corresponding way.</desc>
<sw_param offset="0xf8f02954" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg12_addr_filtering_start_addr_filtering_start">
<name>addr_filtering_start</name>
<desc>Address filtering start address.</desc>
<sw_param offset="0xf8f02c00" start="31" end="20" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg12_addr_filtering_start_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f02c00" start="19" end="1" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg12_addr_filtering_start_addr_filtering_enable">
<name>addr_filtering_enable</name>
<desc>0 = Address filtering disabled.
1 = Address filtering enabled</desc>
<sw_param offset="0xf8f02c00" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg12_addr_filtering_end_addr_filtering_end">
<name>addr_filtering_end</name>
<desc>Address filtering end address.</desc>
<sw_param offset="0xf8f02c04" start="31" end="20" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg12_addr_filtering_end_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f02c04" start="19" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg15_debug_ctrl_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f02f40" start="31" end="3" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg15_debug_ctrl_SPNIDEN">
<name>SPNIDEN</name>
<desc>Reads value of SPNIDEN input.</desc>
<sw_param offset="0xf8f02f40" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg15_debug_ctrl_DWB">
<name>DWB</name>
<desc>DWB: Disable write-back, force WT 0 = Enable write-back behavior. This is the default.
1 = Force write-through behavior</desc>
<sw_param offset="0xf8f02f40" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg15_debug_ctrl_DCL">
<name>DCL</name>
<desc>DCL: Disable cache linefill 0 = Enable cache linefills. This is the default.
1 = Disable cache linefills.</desc>
<sw_param offset="0xf8f02f40" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg15_prefetch_ctrl_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f02f60" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg15_prefetch_ctrl_double_linefill_en">
<name>double_linefill_en</name>
<desc>Double linefill enable: You can set the following options for this register bit:
0 The L2CC always issues 4x64-bit read bursts to L3 on reads
that miss in the L2 cache. This is the default.
1 The L2CC issues 8x64-bit read bursts to L3 on reads that
miss in the L2 cache.</desc>
<sw_param offset="0xf8f02f60" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg15_prefetch_ctrl_inst_pref_en">
<name>inst_pref_en</name>
<desc>Instruction prefetch enable: You can set the following options for this register bit:
0 Instruction prefetching disabled. This is the default.
1 Instruction prefetching enabled</desc>
<sw_param offset="0xf8f02f60" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg15_prefetch_ctrl_data_pref_en">
<name>data_pref_en</name>
<desc>Data prefetch enable: You can set the following options for this register bit:
0 Data prefetching disabled. This is the default.
1 Data prefetching enabled.</desc>
<sw_param offset="0xf8f02f60" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg15_prefetch_ctrl_double_linefill_on_wrapread_en">
<name>double_linefill_on_wrapread_en</name>
<desc>Double linefill on WRAP read disable: You can set the following options for this register bit:
0 Double linefill on WRAP read enabled. This is the default.
1 Double linefill on WRAP read disabled</desc>
<sw_param offset="0xf8f02f60" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg15_prefetch_ctrl_reserved_1">
<name>reserved_1</name>
<desc>reserved</desc>
<sw_param offset="0xf8f02f60" start="26" end="25" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg15_prefetch_ctrl_pref_drop_en">
<name>pref_drop_en</name>
<desc>Prefetch drop enable: You can set the following options for this register bit:
0 The L2CC does not discard prefetch reads issued to L3. This
is the default.
1 The L2CC discards prefetch reads issued to L3 when there is
a resource conflict with explicit reads.</desc>
<sw_param offset="0xf8f02f60" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg15_prefetch_ctrl_incr_double_linefill_en">
<name>incr_double_linefill_en</name>
<desc>Incr double Linefill enable: You can set the following options for this register bit:
0 The L2CC does not issue INCR 8x64-bit read bursts to L3 on
reads that miss in the L2 cache. This is the default.
1 The L2CC can issue INCR 8x64-bit read bursts to L3 on
reads that miss in the L2 cache.</desc>
<sw_param offset="0xf8f02f60" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg15_prefetch_ctrl_reserved_2">
<name>reserved_2</name>
<desc>reserved</desc>
<sw_param offset="0xf8f02f60" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg15_prefetch_ctrl_not_same_id_on_excl_seq_en">
<name>not_same_id_on_excl_seq_en</name>
<desc>Not same ID on exclusive sequence enable: You can set the following options for this register bit:
0 Read and write portions of a non-cacheable exclusive
sequence have the same AXI ID when issued to L3. This is
the default.
1 Read and write portions of a non-cacheable exclusive
sequence do not have the same AXI ID when issued to L3.</desc>
<sw_param offset="0xf8f02f60" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg15_prefetch_ctrl_reserved_3">
<name>reserved_3</name>
<desc>reserved</desc>
<sw_param offset="0xf8f02f60" start="20" end="5" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg15_prefetch_ctrl_prefetch_offset">
<name>prefetch_offset</name>
<desc>Default = b00000.</desc>
<sw_param offset="0xf8f02f60" start="4" end="0" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg15_power_ctrl_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f02f80" start="31" end="2" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg15_power_ctrl_dynamic_clk_gating_en">
<name>dynamic_clk_gating_en</name>
<desc>Dynamic clock gating enable.
1 = Enabled.
0 = Masked. This is the default.</desc>
<sw_param offset="0xf8f02f80" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_l2cache_reg15_power_ctrl_standby_mode_en">
<name>standby_mode_en</name>
<desc>Standby mode enable.
1 = Enabled.
0 = Masked. This is the default</desc>
<sw_param offset="0xf8f02f80" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ocm_OCM_PARITY_CTRL_reserved">
<name>reserved</name>
<desc>Returns 0 when read</desc>
<sw_param offset="0xf800c000" start="31" end="21" />
</parameter>
<parameter uniqueid="ps7_ocm_OCM_PARITY_CTRL_OddParityEn">
<name>OddParityEn</name>
<desc>Enable RAM Odd Parity Generation. One control bit per data byte (OddParity[0] controls Data[7:0] e.t.c)
0 - Even Parity generated
1 - Odd
Parity generated</desc>
<sw_param offset="0xf800c000" start="20" end="5" />
</parameter>
<parameter uniqueid="ps7_ocm_OCM_PARITY_CTRL_LockFailErrIrqEn">
<name>LockFailErrIrqEn</name>
<desc>Enable interrupt when
an AXI LOCK ("locked access") command is detected.</desc>
<sw_param offset="0xf800c000" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_ocm_OCM_PARITY_CTRL_MultipleParityErrIrqEn">
<name>MultipleParityErrIrqEn</name>
<desc>Same as SingleParityErrIrqEn, but enables IRQ on multiple parity errors detected.
0 - IRQ is not generated when parity error detected and ParityCheckDis=0
1 - IRQ is generated when parity error detected and ParityCheckDis=0.</desc>
<sw_param offset="0xf800c000" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_ocm_OCM_PARITY_CTRL_SingleParityErrIrqEn">
<name>SingleParityErrIrqEn</name>
<desc>Enable interrupt when a single parity error is detected. Note that even if this field is 0, the OCM_IRQ_STS register will still log the error if ParityCheckDis=0. This allows software the option of polling if an error occurred.
0 - IRQ is not generated when parity error detected and ParityCheckDis=0
1 - IRQ is generated when parity error detected and ParityCheckDis=0.</desc>
<sw_param offset="0xf800c000" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_ocm_OCM_PARITY_CTRL_RdRespParityErrEn">
<name>RdRespParityErrEn</name>
<desc>Enable AXI read 'SLVERR' response for parity error detection.
0 - Error will not be sent on AXI read channel when parity error detected
1 - Error will be sent on AXI read channel when parity error detected and ParityCheckDis=0</desc>
<sw_param offset="0xf800c000" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ocm_OCM_PARITY_CTRL_ParityCheckDis">
<name>ParityCheckDis</name>
<desc>Disable RAM Parity Checking. No checking or logging of status will occur when 1.
0 - RAM Parity checking is enabled
1 - RAM Parity checking is disabled</desc>
<sw_param offset="0xf800c000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ocm_OCM_PARITY_ERRADDRESS_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800c004" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_ocm_OCM_PARITY_ERRADDRESS_ParityErrAddress">
<name>ParityErrAddress</name>
<desc>When a parity Error occurs, the access address associated with the error is logged here. The first error address will be held if multiple parity errors occur. Need an explicit write of all '1's' to reset/clear this field.</desc>
<sw_param offset="0xf800c004" start="13" end="0" />
</parameter>
<parameter uniqueid="ps7_ocm_OCM_IRQ_STS_reserved">
<name>reserved</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800c008" start="31" end="3" />
</parameter>
<parameter uniqueid="ps7_ocm_OCM_IRQ_STS_LockFailErr">
<name>LockFailErr</name>
<desc>When set (1), indicates that an AXI LOCK has been attempted (not supported by OCM). This is a sticky bit. Once set it can only be cleared by explicitly writing a 1 to this field. This field drives the interrupt pin. (Associated irq enable bit must be set)</desc>
<sw_param offset="0xf800c008" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_ocm_OCM_IRQ_STS_MultipleParityErr">
<name>MultipleParityErr</name>
<desc>Status of OCM multiple parity error. This is a sticky bit. Once set it can only be cleared by explicitly writing a 1 to this field. This field drives the interrupt pin. (Associated irq enable bit must be set)
0 - Multiple OCM parity Errors have not occurred
1 - Multiple OCM parity Errors have occurred</desc>
<sw_param offset="0xf800c008" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ocm_OCM_IRQ_STS_SingleParityErr">
<name>SingleParityErr</name>
<desc>Status of OCM single parity error. This is a sticky bit. Once set it can only be cleared by explicitly writing a 1 to this field. This field drives the interrupt pin (Associated irq enable bit must be set)
0 - Single OCM parity Error has not occurred
1 - Single OCM parity Error has occurred</desc>
<sw_param offset="0xf800c008" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ocm_OCM_CONTROL_reserved_1">
<name>reserved_1</name>
<desc>Return 0 when read</desc>
<sw_param offset="0xf800c00c" start="31" end="3" />
</parameter>
<parameter uniqueid="ps7_ocm_OCM_CONTROL_reserved">
<name>reserved</name>
<desc>Read/Write reserved register</desc>
<sw_param offset="0xf800c00c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_ocm_OCM_CONTROL_DisableRom">
<name>DisableRom</name>
<desc>When set (1), disables the ROM CEN signal. This is useful when the 2:1 clock ratio is used and the ROM clk exceeds its specifications</desc>
<sw_param offset="0xf800c00c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ocm_OCM_CONTROL_ScuWrPriorityLo">
<name>ScuWrPriorityLo</name>
<desc>When set (1), changes the priority of the SCU write port to LOW from Medium</desc>
<sw_param offset="0xf800c00c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu0_PMXEVCNTR0_PMXEVCNTR0">
<name>PMXEVCNTR0</name>
<desc>PMU event counter 0</desc>
<sw_param offset="0xf8891000" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu0_PMXEVCNTR1_PMXEVCNTR1">
<name>PMXEVCNTR1</name>
<desc>PMU event counter 1</desc>
<sw_param offset="0xf8891004" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu0_PMXEVCNTR2_PMXEVCNTR2">
<name>PMXEVCNTR2</name>
<desc>PMU event counter 2</desc>
<sw_param offset="0xf8891008" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu0_PMXEVCNTR3_PMXEVCNTR3">
<name>PMXEVCNTR3</name>
<desc>PMU event counter 3</desc>
<sw_param offset="0xf889100c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu0_PMXEVCNTR4_PMXEVCNTR4">
<name>PMXEVCNTR4</name>
<desc>PMU event counter 4</desc>
<sw_param offset="0xf8891010" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu0_PMXEVCNTR5_PMXEVCNTR5">
<name>PMXEVCNTR5</name>
<desc>PMU event counter 5</desc>
<sw_param offset="0xf8891014" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu0_PMCCNTR_PMCCNTR">
<name>PMCCNTR</name>
<desc>pmccntr</desc>
<sw_param offset="0xf889107c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu0_PMXEVTYPER0_PMXEVTYPER0">
<name>PMXEVTYPER0</name>
<desc>pmevtyper0</desc>
<sw_param offset="0xf8891400" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu0_PMXEVTYPER1_PMXEVTYPER1">
<name>PMXEVTYPER1</name>
<desc>pmevtyper1</desc>
<sw_param offset="0xf8891404" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu0_PMXEVTYPER2_PMXEVTYPER2">
<name>PMXEVTYPER2</name>
<desc>pmevtyper2</desc>
<sw_param offset="0xf8891408" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu0_PMXEVTYPER3_PMXEVTYPER3">
<name>PMXEVTYPER3</name>
<desc>pmevtyper3</desc>
<sw_param offset="0xf889140c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu0_PMXEVTYPER4_PMXEVTYPER4">
<name>PMXEVTYPER4</name>
<desc>pmevtyper4</desc>
<sw_param offset="0xf8891410" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu0_PMXEVTYPER5_PMXEVTYPER5">
<name>PMXEVTYPER5</name>
<desc>pmevtyper5</desc>
<sw_param offset="0xf8891414" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu0_PMCNTENSET_PMCNTENSET">
<name>PMCNTENSET</name>
<desc>pmcntenset</desc>
<sw_param offset="0xf8891c00" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu0_PMCNTENCLR_PMCNTENCLR">
<name>PMCNTENCLR</name>
<desc>pmcntenclr</desc>
<sw_param offset="0xf8891c20" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu0_PMINTENSET_PMINTENSET">
<name>PMINTENSET</name>
<desc>pmintenset</desc>
<sw_param offset="0xf8891c40" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu0_PMINTENCLR_PMINTENCLR">
<name>PMINTENCLR</name>
<desc>pmintenclr</desc>
<sw_param offset="0xf8891c60" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu0_PMOVSR_PMOVSR">
<name>PMOVSR</name>
<desc>pmovsr</desc>
<sw_param offset="0xf8891c80" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu0_PMSWINC_PMSWINC">
<name>PMSWINC</name>
<desc>pmswinc</desc>
<sw_param offset="0xf8891ca0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu0_PMCR_PMCR">
<name>PMCR</name>
<desc>pmcr</desc>
<sw_param offset="0xf8891e04" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu0_PMUSERENR_PMUSERENR">
<name>PMUSERENR</name>
<desc>pmuserenr
This register is read-only in user mode.</desc>
<sw_param offset="0xf8891e08" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu1_PMXEVCNTR0_PMXEVCNTR0">
<name>PMXEVCNTR0</name>
<desc>PMU event counter 0</desc>
<sw_param offset="0xf8893000" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu1_PMXEVCNTR1_PMXEVCNTR1">
<name>PMXEVCNTR1</name>
<desc>PMU event counter 1</desc>
<sw_param offset="0xf8893004" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu1_PMXEVCNTR2_PMXEVCNTR2">
<name>PMXEVCNTR2</name>
<desc>PMU event counter 2</desc>
<sw_param offset="0xf8893008" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu1_PMXEVCNTR3_PMXEVCNTR3">
<name>PMXEVCNTR3</name>
<desc>PMU event counter 3</desc>
<sw_param offset="0xf889300c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu1_PMXEVCNTR4_PMXEVCNTR4">
<name>PMXEVCNTR4</name>
<desc>PMU event counter 4</desc>
<sw_param offset="0xf8893010" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu1_PMXEVCNTR5_PMXEVCNTR5">
<name>PMXEVCNTR5</name>
<desc>PMU event counter 5</desc>
<sw_param offset="0xf8893014" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu1_PMCCNTR_PMCCNTR">
<name>PMCCNTR</name>
<desc>pmccntr</desc>
<sw_param offset="0xf889307c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu1_PMXEVTYPER0_PMXEVTYPER0">
<name>PMXEVTYPER0</name>
<desc>pmevtyper0</desc>
<sw_param offset="0xf8893400" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu1_PMXEVTYPER1_PMXEVTYPER1">
<name>PMXEVTYPER1</name>
<desc>pmevtyper1</desc>
<sw_param offset="0xf8893404" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu1_PMXEVTYPER2_PMXEVTYPER2">
<name>PMXEVTYPER2</name>
<desc>pmevtyper2</desc>
<sw_param offset="0xf8893408" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu1_PMXEVTYPER3_PMXEVTYPER3">
<name>PMXEVTYPER3</name>
<desc>pmevtyper3</desc>
<sw_param offset="0xf889340c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu1_PMXEVTYPER4_PMXEVTYPER4">
<name>PMXEVTYPER4</name>
<desc>pmevtyper4</desc>
<sw_param offset="0xf8893410" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu1_PMXEVTYPER5_PMXEVTYPER5">
<name>PMXEVTYPER5</name>
<desc>pmevtyper5</desc>
<sw_param offset="0xf8893414" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu1_PMCNTENSET_PMCNTENSET">
<name>PMCNTENSET</name>
<desc>pmcntenset</desc>
<sw_param offset="0xf8893c00" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu1_PMCNTENCLR_PMCNTENCLR">
<name>PMCNTENCLR</name>
<desc>pmcntenclr</desc>
<sw_param offset="0xf8893c20" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu1_PMINTENSET_PMINTENSET">
<name>PMINTENSET</name>
<desc>pmintenset</desc>
<sw_param offset="0xf8893c40" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu1_PMINTENCLR_PMINTENCLR">
<name>PMINTENCLR</name>
<desc>pmintenclr</desc>
<sw_param offset="0xf8893c60" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu1_PMOVSR_PMOVSR">
<name>PMOVSR</name>
<desc>pmovsr</desc>
<sw_param offset="0xf8893c80" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu1_PMSWINC_PMSWINC">
<name>PMSWINC</name>
<desc>pmswinc</desc>
<sw_param offset="0xf8893ca0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu1_PMCR_PMCR">
<name>PMCR</name>
<desc>pmcr</desc>
<sw_param offset="0xf8893e04" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_cpu_pmu1_PMUSERENR_PMUSERENR">
<name>PMUSERENR</name>
<desc>pmuserenr
This register is read-only in user mode.</desc>
<sw_param offset="0xf8893e08" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_SCL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000000" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_SCL_LOCK">
<name>LOCK</name>
<desc>Secure configuration lock: 0 = unlocked, Secure writes to Secure configuration registers are enabled
1 = locked, all writes to Secure configuration registers are disabled and cannot be enabled until power-on reset is asserted.</desc>
<sw_param offset="0xf8000000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_SLCR_LOCK_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000004" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_SLCR_LOCK_LOCK_KEY">
<name>LOCK_KEY</name>
<desc>When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.</desc>
<sw_param offset="0xf8000004" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_SLCR_UNLOCK_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000008" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_SLCR_UNLOCK_UNLOCK_KEY">
<name>UNLOCK_KEY</name>
<desc>When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.</desc>
<sw_param offset="0xf8000008" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_SLCR_LOCKSTA_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800000c" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_SLCR_LOCKSTA_LOCK_STATUS">
<name>LOCK_STATUS</name>
<desc>Current state of write protection mode of SLCR:
0 - Registers are writeable;
1 - Registers are not writeable. Any attempted writes are ignored, but reads will complete as normal.</desc>
<sw_param offset="0xf800000c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_ARM_PLL_CTRL_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000100" start="31" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_ARM_PLL_CTRL_PLL_FDIV">
<name>PLL_FDIV</name>
<desc>Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state.</desc>
<sw_param offset="0xf8000100" start="18" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_ARM_PLL_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000100" start="11" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_ARM_PLL_CTRL_PLL_BYPASS_FORCE">
<name>PLL_BYPASS_FORCE</name>
<desc>Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed.</desc>
<sw_param offset="0xf8000100" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_ARM_PLL_CTRL_PLL_BYPASS_QUAL">
<name>PLL_BYPASS_QUAL</name>
<desc>Qualifies the PLL bootstrap signal sampled from boot_mode[3] in the MIO. By default the bootstrap will directly control all three PLL bypass muxes within the clock controller. 0 - PLL bypass mux in clock controller is only controlled by PLL_BYPASS_FORCE bit. 1 - PLL bypass mux in clock controller
is controlled by sampled boot_mode[3] provided PLL_BYPASS_FORCE is not set.</desc>
<sw_param offset="0xf8000100" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_ARM_PLL_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000100" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_ARM_PLL_CTRL_PLL_PWRDWN">
<name>PLL_PWRDWN</name>
<desc>Drives the PWRDWN input of the PLL: 0 - PLL powered up; 1 - PLL powered down.</desc>
<sw_param offset="0xf8000100" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_ARM_PLL_CTRL_PLL_RESET">
<name>PLL_RESET</name>
<desc>Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.</desc>
<sw_param offset="0xf8000100" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_PLL_CTRL_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000104" start="31" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_PLL_CTRL_PLL_FDIV">
<name>PLL_FDIV</name>
<desc>Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state.</desc>
<sw_param offset="0xf8000104" start="18" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_PLL_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000104" start="11" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_PLL_CTRL_PLL_BYPASS_FORCE">
<name>PLL_BYPASS_FORCE</name>
<desc>Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed</desc>
<sw_param offset="0xf8000104" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_PLL_CTRL_PLL_BYPASS_QUAL">
<name>PLL_BYPASS_QUAL</name>
<desc>Qualifies the PLL bootstrap signal sampled from boot_mode[3] in the MIO. By default the bootstrap will directly control all three PLL bypass muxes within the clock controller. 0 - PLL bypass mux in clock controller is only controlled by PLL_BYPASS_FORCE bit. 1 - PLL bypass mux in clock controller
is controlled by sampled boot_mode[3] provided PLL_BYPASS_FORCE is not set.</desc>
<sw_param offset="0xf8000104" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_PLL_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000104" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_PLL_CTRL_PLL_PWRDWN">
<name>PLL_PWRDWN</name>
<desc>Drives the PWRDWN input of the PLL. 0 - PLL powered up.1 - PLL powered down</desc>
<sw_param offset="0xf8000104" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_PLL_CTRL_PLL_RESET">
<name>PLL_RESET</name>
<desc>Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.</desc>
<sw_param offset="0xf8000104" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_IO_PLL_CTRL_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000108" start="31" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_IO_PLL_CTRL_PLL_FDIV">
<name>PLL_FDIV</name>
<desc>Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state.</desc>
<sw_param offset="0xf8000108" start="18" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_IO_PLL_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000108" start="11" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_IO_PLL_CTRL_PLL_BYPASS_FORCE">
<name>PLL_BYPASS_FORCE</name>
<desc>Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin).
1 - PLL forced to be bypassed</desc>
<sw_param offset="0xf8000108" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_IO_PLL_CTRL_PLL_BYPASS_QUAL">
<name>PLL_BYPASS_QUAL</name>
<desc>Qualifies the PLL bootstrap signal sampled from boot_mode[3] in the MIO. By default the bootstrap will directly control all three PLL bypass muxes within the clock controller. 0 - PLL bypass mux in clock controller is only controlled by PLL_BYPASS_FORCE bit. 1 - PLL bypass mux in clock controller
is controlled by sampled boot_mode[3] provided PLL_BYPASS_FORCE is not set.</desc>
<sw_param offset="0xf8000108" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_IO_PLL_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000108" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_IO_PLL_CTRL_PLL_PWRDWN">
<name>PLL_PWRDWN</name>
<desc>Drives the PWRDWN input of the PLL. 0 - PLL powered up. 1 - PLL powered down</desc>
<sw_param offset="0xf8000108" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_IO_PLL_CTRL_PLL_RESET">
<name>PLL_RESET</name>
<desc>Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.</desc>
<sw_param offset="0xf8000108" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_PLL_STATUS_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800010c" start="31" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_PLL_STATUS_IO_PLL_STABLE">
<name>IO_PLL_STABLE</name>
<desc>IO PLL clock stable status. 0 - IO PLL out of lock and not bypassed. 1 - IO PLL in lock or bypassed. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read.</desc>
<sw_param offset="0xf800010c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_PLL_STATUS_DDR_PLL_STABLE">
<name>DDR_PLL_STABLE</name>
<desc>DDR PLL clock stable status. 0 - DDR PLL out of lock and not bypassed. 1 - DDR PLL in lock or bypassed. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read.</desc>
<sw_param offset="0xf800010c" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_PLL_STATUS_ARM_PLL_STABLE">
<name>ARM_PLL_STABLE</name>
<desc>ARM PLL clock stable status. 0 - ARM PLL out of lock and not in bypass. 1 - ARM PLL in lock or bypassed. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read.</desc>
<sw_param offset="0xf800010c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_PLL_STATUS_IO_PLL_LOCK">
<name>IO_PLL_LOCK</name>
<desc>IO PLL lock status. 0 - IO PLL out of lock. 1 - IO PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used.</desc>
<sw_param offset="0xf800010c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_PLL_STATUS_DDR_PLL_LOCK">
<name>DDR_PLL_LOCK</name>
<desc>DDR PLL lock status. 0 - DDR PLL out of lock. 1 - DDR PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used.</desc>
<sw_param offset="0xf800010c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_PLL_STATUS_ARM_PLL_LOCK">
<name>ARM_PLL_LOCK</name>
<desc>ARM PLL lock status. 0 - ARM PLL out of lock. 1 - ARM PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used.</desc>
<sw_param offset="0xf800010c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_ARM_PLL_CFG_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000110" start="31" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_ARM_PLL_CFG_LOCK_CNT">
<name>LOCK_CNT</name>
<desc>Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked.</desc>
<sw_param offset="0xf8000110" start="21" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_ARM_PLL_CFG_PLL_CP">
<name>PLL_CP</name>
<desc>Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control</desc>
<sw_param offset="0xf8000110" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_ARM_PLL_CFG_PLL_RES">
<name>PLL_RES</name>
<desc>Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control</desc>
<sw_param offset="0xf8000110" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_ARM_PLL_CFG_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000110" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_PLL_CFG_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000114" start="31" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_PLL_CFG_LOCK_CNT">
<name>LOCK_CNT</name>
<desc>Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked.</desc>
<sw_param offset="0xf8000114" start="21" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_PLL_CFG_PLL_CP">
<name>PLL_CP</name>
<desc>Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control</desc>
<sw_param offset="0xf8000114" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_PLL_CFG_PLL_RES">
<name>PLL_RES</name>
<desc>Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control</desc>
<sw_param offset="0xf8000114" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_PLL_CFG_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000114" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_IO_PLL_CFG_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000118" start="31" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_IO_PLL_CFG_LOCK_CNT">
<name>LOCK_CNT</name>
<desc>Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked.</desc>
<sw_param offset="0xf8000118" start="21" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_IO_PLL_CFG_PLL_CP">
<name>PLL_CP</name>
<desc>Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control</desc>
<sw_param offset="0xf8000118" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_IO_PLL_CFG_PLL_RES">
<name>PLL_RES</name>
<desc>Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control</desc>
<sw_param offset="0xf8000118" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_IO_PLL_CFG_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000118" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_PLL_BG_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800011c" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_PLL_BG_CTRL_BG_PWRDWN">
<name>BG_PWRDWN</name>
<desc>Drives the PWRDWN input of the PLL BandGap
0 - PLL BandGap powered up
1 - PLL BandGap powered down
These signal should not be changed by the end user. This Bandgap is shared by IOB, so IOB may go X if changed.</desc>
<sw_param offset="0xf800011c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_ARM_CLK_CTRL_reserved_3">
<name>reserved_3</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000120" start="31" end="29" />
</parameter>
<parameter uniqueid="ps7_slcr_ARM_CLK_CTRL_CPU_PERI_CLKACT">
<name>CPU_PERI_CLKACT</name>
<desc>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf8000120" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_slcr_ARM_CLK_CTRL_CPU_1XCLKACT">
<name>CPU_1XCLKACT</name>
<desc>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf8000120" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_slcr_ARM_CLK_CTRL_CPU_2XCLKACT">
<name>CPU_2XCLKACT</name>
<desc>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf8000120" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_slcr_ARM_CLK_CTRL_CPU_3OR2XCLKACT">
<name>CPU_3OR2XCLKACT</name>
<desc>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf8000120" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_slcr_ARM_CLK_CTRL_CPU_6OR4XCLKACT">
<name>CPU_6OR4XCLKACT</name>
<desc>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf8000120" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_slcr_ARM_CLK_CTRL_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000120" start="23" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_ARM_CLK_CTRL_DIVISOR">
<name>DIVISOR</name>
<desc>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</desc>
<sw_param offset="0xf8000120" start="13" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_ARM_CLK_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000120" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_ARM_CLK_CTRL_SRCSEL">
<name>SRCSEL</name>
<desc>Selects the source used to generate the clock. 0x - Source for generated clock is CPU PLL. 10 - Source for generated clock is DDR divided clock. 11 - Source for generated clock is IO PLL</desc>
<sw_param offset="0xf8000120" start="5" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_ARM_CLK_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000120" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_CLK_CTRL_DDR_2XCLK_DIVISOR">
<name>DDR_2XCLK_DIVISOR</name>
<desc>Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk)</desc>
<sw_param offset="0xf8000124" start="31" end="26" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_CLK_CTRL_DDR_3XCLK_DIVISOR">
<name>DDR_3XCLK_DIVISOR</name>
<desc>Divisor value for the ddr_3xclk</desc>
<sw_param offset="0xf8000124" start="25" end="20" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_CLK_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000124" start="19" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_CLK_CTRL_DDR_2XCLKACT">
<name>DDR_2XCLKACT</name>
<desc>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf8000124" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_CLK_CTRL_DDR_3XCLKACT">
<name>DDR_3XCLKACT</name>
<desc>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf8000124" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_DCI_CLK_CTRL_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000128" start="31" end="26" />
</parameter>
<parameter uniqueid="ps7_slcr_DCI_CLK_CTRL_DIVISOR1">
<name>DIVISOR1</name>
<desc>Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider</desc>
<sw_param offset="0xf8000128" start="25" end="20" />
</parameter>
<parameter uniqueid="ps7_slcr_DCI_CLK_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000128" start="19" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_DCI_CLK_CTRL_DIVISOR0">
<name>DIVISOR0</name>
<desc>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</desc>
<sw_param offset="0xf8000128" start="13" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_DCI_CLK_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000128" start="7" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_DCI_CLK_CTRL_CLKACT">
<name>CLKACT</name>
<desc>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf8000128" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_APER_CLK_CTRL_reserved_7">
<name>reserved_7</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800012c" start="31" end="25" />
</parameter>
<parameter uniqueid="ps7_slcr_APER_CLK_CTRL_SMC_CPU_1XCLKACT">
<name>SMC_CPU_1XCLKACT</name>
<desc>SMC AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf800012c" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_slcr_APER_CLK_CTRL_LQSPI_CPU_1XCLKACT">
<name>LQSPI_CPU_1XCLKACT</name>
<desc>LQSPI AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf800012c" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_slcr_APER_CLK_CTRL_GPIO_CPU_1XCLKACT">
<name>GPIO_CPU_1XCLKACT</name>
<desc>GPIO AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf800012c" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_APER_CLK_CTRL_UART1_CPU_1XCLKACT">
<name>UART1_CPU_1XCLKACT</name>
<desc>UART 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf800012c" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_slcr_APER_CLK_CTRL_UART0_CPU_1XCLKACT">
<name>UART0_CPU_1XCLKACT</name>
<desc>UART 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf800012c" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_slcr_APER_CLK_CTRL_I2C1_CPU_1XCLKACT">
<name>I2C1_CPU_1XCLKACT</name>
<desc>I2C 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf800012c" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_APER_CLK_CTRL_I2C0_CPU_1XCLKACT">
<name>I2C0_CPU_1XCLKACT</name>
<desc>I2C 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf800012c" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_slcr_APER_CLK_CTRL_CAN1_CPU_1XCLKACT">
<name>CAN1_CPU_1XCLKACT</name>
<desc>CAN 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf800012c" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_slcr_APER_CLK_CTRL_CAN0_CPU_1XCLKACT">
<name>CAN0_CPU_1XCLKACT</name>
<desc>CAN 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf800012c" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_APER_CLK_CTRL_SPI1_CPU_1XCLKACT">
<name>SPI1_CPU_1XCLKACT</name>
<desc>SPI 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf800012c" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_slcr_APER_CLK_CTRL_SPI0_CPU_1XCLKACT">
<name>SPI0_CPU_1XCLKACT</name>
<desc>SPI 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf800012c" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_APER_CLK_CTRL_reserved_6">
<name>reserved_6</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800012c" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_APER_CLK_CTRL_reserved_5">
<name>reserved_5</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800012c" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_APER_CLK_CTRL_SDI1_CPU_1XCLKACT">
<name>SDI1_CPU_1XCLKACT</name>
<desc>SDIO 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf800012c" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_APER_CLK_CTRL_SDI0_CPU_1XCLKACT">
<name>SDI0_CPU_1XCLKACT</name>
<desc>SDIO0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf800012c" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_slcr_APER_CLK_CTRL_reserved_4">
<name>reserved_4</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800012c" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_APER_CLK_CTRL_reserved_3">
<name>reserved_3</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800012c" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_APER_CLK_CTRL_GEM1_CPU_1XCLKACT">
<name>GEM1_CPU_1XCLKACT</name>
<desc>Gigabit Ethernet MAC 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf800012c" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_slcr_APER_CLK_CTRL_GEM0_CPU_1XCLKACT">
<name>GEM0_CPU_1XCLKACT</name>
<desc>Gigabit Ethernet MAC 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf800012c" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_APER_CLK_CTRL_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800012c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_APER_CLK_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800012c" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_APER_CLK_CTRL_USB1_CPU_1XCLKACT">
<name>USB1_CPU_1XCLKACT</name>
<desc>USB 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf800012c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_APER_CLK_CTRL_USB0_CPU_1XCLKACT">
<name>USB0_CPU_1XCLKACT</name>
<desc>USB 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf800012c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_APER_CLK_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800012c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_APER_CLK_CTRL_DMA_CPU_2XCLKACT">
<name>DMA_CPU_2XCLKACT</name>
<desc>DMA 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf800012c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_USB0_CLK_CTRL_reserved_3">
<name>reserved_3</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000130" start="31" end="26" />
</parameter>
<parameter uniqueid="ps7_slcr_USB0_CLK_CTRL_DIVISOR1">
<name>DIVISOR1</name>
<desc>Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider</desc>
<sw_param offset="0xf8000130" start="25" end="20" />
</parameter>
<parameter uniqueid="ps7_slcr_USB0_CLK_CTRL_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000130" start="19" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_USB0_CLK_CTRL_DIVISOR0">
<name>DIVISOR0</name>
<desc>Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider</desc>
<sw_param offset="0xf8000130" start="13" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_USB0_CLK_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000130" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_slcr_USB0_CLK_CTRL_SRCSEL">
<name>SRCSEL</name>
<desc>Selects the source used to generate the clock.
1xx - Source for generated clock is USB0 MIO ULPI clock (top level USB0 MIO ULPI clock is an input).
00x - Source for generated clock is IO PLL (top level USB0 MIO ULPI clock is an output).
010 - Source for generated clock is ARM PLL (top level USB0 MIO ULPI clock is an output).
011 - Source for generated clock is DDR PLL (top level USB0 MIO ULPI clock is an output)</desc>
<sw_param offset="0xf8000130" start="6" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_USB0_CLK_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000130" start="3" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_USB0_CLK_CTRL_CLKACT">
<name>CLKACT</name>
<desc>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf8000130" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_USB1_CLK_CTRL_reserved_3">
<name>reserved_3</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000134" start="31" end="26" />
</parameter>
<parameter uniqueid="ps7_slcr_USB1_CLK_CTRL_DIVISOR1">
<name>DIVISOR1</name>
<desc>Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider</desc>
<sw_param offset="0xf8000134" start="25" end="20" />
</parameter>
<parameter uniqueid="ps7_slcr_USB1_CLK_CTRL_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000134" start="19" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_USB1_CLK_CTRL_DIVISOR0">
<name>DIVISOR0</name>
<desc>Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider</desc>
<sw_param offset="0xf8000134" start="13" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_USB1_CLK_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000134" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_slcr_USB1_CLK_CTRL_SRCSEL">
<name>SRCSEL</name>
<desc>Selects the source used to generate the clock.
1xx - Source for generated clock is USB0 MIO ULPI clock (top level USB0 MIO ULPI clock is an input).
00x - Source for generated clock is IO PLL (top level USB0 MIO ULPI clock is an output).
010 - Source for generated clock is ARM PLL (top level USB0 MIO ULPI clock is an output).
011 - Source for generated clock is DDR PLL (top level USB0 MIO ULPI clock is an output)</desc>
<sw_param offset="0xf8000134" start="6" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_USB1_CLK_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000134" start="3" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_USB1_CLK_CTRL_CLKACT">
<name>CLKACT</name>
<desc>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf8000134" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM0_RCLK_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000138" start="31" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM0_RCLK_CTRL_SRCSEL">
<name>SRCSEL</name>
<desc>Selects the source used to generate the clock.
0 - Source for generated clock is GEM 0 MIO RX clock.
1 - Source for generated clock is GEM 0 FMIO RX clock.</desc>
<sw_param offset="0xf8000138" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM0_RCLK_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000138" start="3" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM0_RCLK_CTRL_CLKACT">
<name>CLKACT</name>
<desc>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf8000138" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM1_RCLK_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800013c" start="31" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM1_RCLK_CTRL_SRCSEL">
<name>SRCSEL</name>
<desc>Selects the source used to generate the clock.
0 - Source for generated clock is GEM 0 MIO RX clock.
1 - Source for generated clock is GEM 0 FMIO RX clock.</desc>
<sw_param offset="0xf800013c" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM1_RCLK_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800013c" start="3" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM1_RCLK_CTRL_CLKACT">
<name>CLKACT</name>
<desc>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf800013c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM0_CLK_CTRL_reserved_3">
<name>reserved_3</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000140" start="31" end="26" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM0_CLK_CTRL_DIVISOR1">
<name>DIVISOR1</name>
<desc>Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider</desc>
<sw_param offset="0xf8000140" start="25" end="20" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM0_CLK_CTRL_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000140" start="19" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM0_CLK_CTRL_DIVISOR">
<name>DIVISOR</name>
<desc>Provides the divisor used to divide the source clock to generate the required generated clock frequency.
First cascade divider</desc>
<sw_param offset="0xf8000140" start="13" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM0_CLK_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000140" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM0_CLK_CTRL_SRCSEL">
<name>SRCSEL</name>
<desc>Selects the source used to generate the clock. 1xx - Source for generated clock is Ethernet 0 FMIO clock. 00x - Source for generated clock is IO PLL. 010 - Source for generated clock is ARM PLL. 011 - Source for generated clock is DDR PLL</desc>
<sw_param offset="0xf8000140" start="6" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM0_CLK_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000140" start="3" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM0_CLK_CTRL_CLKACT">
<name>CLKACT</name>
<desc>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf8000140" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM1_CLK_CTRL_reserved_3">
<name>reserved_3</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000144" start="31" end="26" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM1_CLK_CTRL_DIVISOR1">
<name>DIVISOR1</name>
<desc>Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider</desc>
<sw_param offset="0xf8000144" start="25" end="20" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM1_CLK_CTRL_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000144" start="19" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM1_CLK_CTRL_DIVISOR">
<name>DIVISOR</name>
<desc>Provides the divisor used to divide the source clock to generate the required generated clock frequency.
First cascade divider</desc>
<sw_param offset="0xf8000144" start="13" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM1_CLK_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000144" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM1_CLK_CTRL_SRCSEL">
<name>SRCSEL</name>
<desc>Selects the source used to generate the clock. 1xx - Source for generated clock is Ethernet 0 FMIO clock. 00x - Source for generated clock is IO PLL. 010 - Source for generated clock is ARM PLL. 011 - Source for generated clock is DDR PLL</desc>
<sw_param offset="0xf8000144" start="6" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM1_CLK_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000144" start="3" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM1_CLK_CTRL_CLKACT">
<name>CLKACT</name>
<desc>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf8000144" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_SMC_CLK_CTRL_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000148" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_SMC_CLK_CTRL_DIVISOR">
<name>DIVISOR</name>
<desc>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</desc>
<sw_param offset="0xf8000148" start="13" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_SMC_CLK_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000148" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_SMC_CLK_CTRL_SRCSEL">
<name>SRCSEL</name>
<desc>Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.</desc>
<sw_param offset="0xf8000148" start="5" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_SMC_CLK_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000148" start="3" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_SMC_CLK_CTRL_CLKACT">
<name>CLKACT</name>
<desc>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf8000148" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_LQSPI_CLK_CTRL_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800014c" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_LQSPI_CLK_CTRL_DIVISOR">
<name>DIVISOR</name>
<desc>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</desc>
<sw_param offset="0xf800014c" start="13" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_LQSPI_CLK_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800014c" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_LQSPI_CLK_CTRL_SRCSEL">
<name>SRCSEL</name>
<desc>Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.</desc>
<sw_param offset="0xf800014c" start="5" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_LQSPI_CLK_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800014c" start="3" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_LQSPI_CLK_CTRL_CLKACT">
<name>CLKACT</name>
<desc>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf800014c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_SDIO_CLK_CTRL_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000150" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_SDIO_CLK_CTRL_DIVISOR">
<name>DIVISOR</name>
<desc>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</desc>
<sw_param offset="0xf8000150" start="13" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_SDIO_CLK_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000150" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_SDIO_CLK_CTRL_SRCSEL">
<name>SRCSEL</name>
<desc>Selects the source used to generate the clock.
0x - Source for generated clock is IO PLL.
10 - Source for generated clock is ARM PLL.
11 - Source for generated clock is DDR PLL.</desc>
<sw_param offset="0xf8000150" start="5" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_SDIO_CLK_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000150" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_SDIO_CLK_CTRL_CLKACT1">
<name>CLKACT1</name>
<desc>SDIO 1 Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf8000150" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_SDIO_CLK_CTRL_CLKACT0">
<name>CLKACT0</name>
<desc>SDIO 0 Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf8000150" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_UART_CLK_CTRL_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000154" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_UART_CLK_CTRL_DIVISOR">
<name>DIVISOR</name>
<desc>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</desc>
<sw_param offset="0xf8000154" start="13" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_UART_CLK_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000154" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_UART_CLK_CTRL_SRCSEL">
<name>SRCSEL</name>
<desc>Selects the source used to generate the clock.
0x - Source for generated clock is IO PLL.
10 - Source for generated clock is ARM PLL.
11 - Source for generated clock is DDR PLL.</desc>
<sw_param offset="0xf8000154" start="5" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_UART_CLK_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000154" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_UART_CLK_CTRL_CLKACT1">
<name>CLKACT1</name>
<desc>UART 1 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf8000154" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_UART_CLK_CTRL_CLKACT0">
<name>CLKACT0</name>
<desc>UART 0 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf8000154" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_SPI_CLK_CTRL_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000158" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_SPI_CLK_CTRL_DIVISOR">
<name>DIVISOR</name>
<desc>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</desc>
<sw_param offset="0xf8000158" start="13" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_SPI_CLK_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000158" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_SPI_CLK_CTRL_SRCSEL">
<name>SRCSEL</name>
<desc>Selects the source used to generate the clock.
0x - Source for generated clock is IO PLL.
10 - Source for generated clock is ARM PLL.
11 - Source for generated clock is DDR PLL.</desc>
<sw_param offset="0xf8000158" start="5" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_SPI_CLK_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000158" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_SPI_CLK_CTRL_CLKACT1">
<name>CLKACT1</name>
<desc>SPI 1 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf8000158" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_SPI_CLK_CTRL_CLKACT0">
<name>CLKACT0</name>
<desc>SPI 0 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf8000158" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_CAN_CLK_CTRL_reserved_3">
<name>reserved_3</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800015c" start="31" end="26" />
</parameter>
<parameter uniqueid="ps7_slcr_CAN_CLK_CTRL_DIVISOR1">
<name>DIVISOR1</name>
<desc>Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider</desc>
<sw_param offset="0xf800015c" start="25" end="20" />
</parameter>
<parameter uniqueid="ps7_slcr_CAN_CLK_CTRL_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800015c" start="19" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_CAN_CLK_CTRL_DIVISOR0">
<name>DIVISOR0</name>
<desc>Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider</desc>
<sw_param offset="0xf800015c" start="13" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_CAN_CLK_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800015c" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_CAN_CLK_CTRL_SRCSEL">
<name>SRCSEL</name>
<desc>Selects the source used to generate the clock.
0x - Source for generated clock is IO PLL.
10 - Source for generated clock is ARM PLL.
11 - Source for generated clock is DDR PLL.</desc>
<sw_param offset="0xf800015c" start="5" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_CAN_CLK_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800015c" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_CAN_CLK_CTRL_CLKACT1">
<name>CLKACT1</name>
<desc>CAN 1 Reference Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf800015c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_CAN_CLK_CTRL_CLKACT0">
<name>CLKACT0</name>
<desc>CAN 0 Reference Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</desc>
<sw_param offset="0xf800015c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_CAN_MIOCLK_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000160" start="31" end="23" />
</parameter>
<parameter uniqueid="ps7_slcr_CAN_MIOCLK_CTRL_CAN1_REF_SEL">
<name>CAN1_REF_SEL</name>
<desc>CAN1 Reference Clock selection. 0 - From internal PLL. 1 - From MIO based on the next field</desc>
<sw_param offset="0xf8000160" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_CAN_MIOCLK_CTRL_CAN1_MUX">
<name>CAN1_MUX</name>
<desc>CAN1 mux selection for MIO.
Setting this to zero will select MIO[0] as the clock source.
Only values 0-53 are valid.</desc>
<sw_param offset="0xf8000160" start="21" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_CAN_MIOCLK_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000160" start="15" end="7" />
</parameter>
<parameter uniqueid="ps7_slcr_CAN_MIOCLK_CTRL_CAN0_REF_SEL">
<name>CAN0_REF_SEL</name>
<desc>CAN 0 Reference Clock selection. 0 - From internal PLL. 1 - From MIO based on the next field</desc>
<sw_param offset="0xf8000160" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_CAN_MIOCLK_CTRL_CAN0_MUX">
<name>CAN0_MUX</name>
<desc>CAN0 mux selection for MIO.
Setting this to zero will select MIO[0] as the clock source.
Only values 0-53 are valid.</desc>
<sw_param offset="0xf8000160" start="5" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_DBG_CLK_CTRL_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000164" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_DBG_CLK_CTRL_DIVISOR">
<name>DIVISOR</name>
<desc>Provides the divisor used to divide the source clock to generate the required generated debug trace clock frequency.</desc>
<sw_param offset="0xf8000164" start="13" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_DBG_CLK_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000164" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_slcr_DBG_CLK_CTRL_SRCSEL">
<name>SRCSEL</name>
<desc>Selects the source used to generate the clock. 1xx - Source for generated clock FMIO trace clock. 00x - Source for generated clock is IO PLL. 010 - Source for generated clock is ARM PLL. 011 - Source for generated clock is DDR PLL</desc>
<sw_param offset="0xf8000164" start="6" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_DBG_CLK_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000164" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_DBG_CLK_CTRL_CPU_1XCLKACT">
<name>CPU_1XCLKACT</name>
<desc>Debug
CPU 1x Clock active. 0 - Clocks are disabled. 1 - Clocks are enabled</desc>
<sw_param offset="0xf8000164" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_DBG_CLK_CTRL_CLKACT_TRC">
<name>CLKACT_TRC</name>
<desc>Debug Trace Clock active. 0 - Clock is disabled. 1 - Clock is enabled</desc>
<sw_param offset="0xf8000164" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_PCAP_CLK_CTRL_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000168" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_PCAP_CLK_CTRL_DIVISOR">
<name>DIVISOR</name>
<desc>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</desc>
<sw_param offset="0xf8000168" start="13" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_PCAP_CLK_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000168" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_PCAP_CLK_CTRL_SRCSEL">
<name>SRCSEL</name>
<desc>Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL</desc>
<sw_param offset="0xf8000168" start="5" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_PCAP_CLK_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000168" start="3" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_PCAP_CLK_CTRL_CLKACT">
<name>CLKACT</name>
<desc>Clock active 0 - Clock is disabled 1 - Clock is enabled</desc>
<sw_param offset="0xf8000168" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_TOPSW_CLK_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800016c" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_TOPSW_CLK_CTRL_CLK_DIS">
<name>CLK_DIS</name>
<desc>Clock disable control. 0 - Clock is not disabled. 1 - Clock can be disabled</desc>
<sw_param offset="0xf800016c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA0_CLK_CTRL_reserved_3">
<name>reserved_3</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000170" start="31" end="26" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA0_CLK_CTRL_DIVISOR1">
<name>DIVISOR1</name>
<desc>Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider</desc>
<sw_param offset="0xf8000170" start="25" end="20" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA0_CLK_CTRL_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000170" start="19" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA0_CLK_CTRL_DIVISOR0">
<name>DIVISOR0</name>
<desc>Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider</desc>
<sw_param offset="0xf8000170" start="13" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA0_CLK_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000170" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA0_CLK_CTRL_SRCSEL">
<name>SRCSEL</name>
<desc>Selects the source used to generate the clock.
0x - Source for generated clock is IO PLL.
10 - Source for generated clock is ARM PLL.
11 - Source for generated clock is DDR PLL.</desc>
<sw_param offset="0xf8000170" start="5" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA0_CLK_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000170" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA0_THR_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000174" start="31" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA0_THR_CTRL_SYNC">
<name>SYNC</name>
<desc>Indicates whether fpga_stop input from the fabric should be considered synchronous or asynchronous to generated FPGA clock output.
0 - fpga_stop is asynchronous to FPGA clock.
1 - fpga_stop is synchronous to FPGA clock.</desc>
<sw_param offset="0xf8000174" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA0_THR_CTRL_EDGE">
<name>EDGE</name>
<desc>Selects between edge stop or level stop modes of operation for the clock throttle logic.
0 - debug level stop mode.
1 - debug edge stop mode.</desc>
<sw_param offset="0xf8000174" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA0_THR_CTRL_CNT_RST">
<name>CNT_RST</name>
<desc>Resets clock throttle counter when in halt state.
0 - No effect.
1 - Causes counter to be reset once HALT state is entered.</desc>
<sw_param offset="0xf8000174" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA0_THR_CTRL_CPU_START">
<name>CPU_START</name>
<desc>Start or restart count on detection of 0 to 1 transition in the value of this bit. A read will always return the written value.
0 - No effect.
1 - Start count or restart count if previous value was 0.</desc>
<sw_param offset="0xf8000174" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA0_THR_CNT_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000178" start="31" end="20" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA0_THR_CNT_DLY_CNT">
<name>DLY_CNT</name>
<desc>Delay count value. Specifies the minimum number of output clock pulses before entering HALT state due to fpga_stop assertion.</desc>
<sw_param offset="0xf8000178" start="19" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA0_THR_CNT_LAST_CNT">
<name>LAST_CNT</name>
<desc>Last count value. Specifies the total number of clocks output in debug mode by the clock throttle logic.</desc>
<sw_param offset="0xf8000178" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA0_THR_STA_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800017c" start="31" end="17" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA0_THR_STA_RUNNING">
<name>RUNNING</name>
<desc>Current running status of FPGA clock output.
0 - Clock is stopped or in normal mode (OK to change config).
1 - Clock is runnnig in debug mode (Keep config static).</desc>
<sw_param offset="0xf800017c" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA0_THR_STA_CURR_VAL">
<name>CURR_VAL</name>
<desc>Current clock throttle counter value, which indicates the number of clock pulses output so far (only accurate when halted).</desc>
<sw_param offset="0xf800017c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA1_CLK_CTRL_reserved_3">
<name>reserved_3</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000180" start="31" end="26" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA1_CLK_CTRL_DIVISOR1">
<name>DIVISOR1</name>
<desc>Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider</desc>
<sw_param offset="0xf8000180" start="25" end="20" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA1_CLK_CTRL_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000180" start="19" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA1_CLK_CTRL_DIVISOR0">
<name>DIVISOR0</name>
<desc>Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider</desc>
<sw_param offset="0xf8000180" start="13" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA1_CLK_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000180" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA1_CLK_CTRL_SRCSEL">
<name>SRCSEL</name>
<desc>Selects the source used to generate the clock.
0x - Source for generated clock is IO PLL.
10 - Source for generated clock is ARM PLL.
11 - Source for generated clock is DDR PLL.</desc>
<sw_param offset="0xf8000180" start="5" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA1_CLK_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000180" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA1_THR_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000184" start="31" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA1_THR_CTRL_SYNC">
<name>SYNC</name>
<desc>Indicates whether fpga_stop input from the fabric should be considered synchronous or asynchronous to generated FPGA clock output.
0 - fpga_stop is asynchronous to FPGA clock.
1 - fpga_stop is synchronous to FPGA clock.</desc>
<sw_param offset="0xf8000184" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA1_THR_CTRL_EDGE">
<name>EDGE</name>
<desc>Selects between edge stop or level stop modes of operation for the clock throttle logic.
0 - debug level stop mode.
1 - debug edge stop mode.</desc>
<sw_param offset="0xf8000184" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA1_THR_CTRL_CNT_RST">
<name>CNT_RST</name>
<desc>Resets clock throttle counter when in halt state.
0 - No effect.
1 - Causes counter to be reset once HALT state is entered.</desc>
<sw_param offset="0xf8000184" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA1_THR_CTRL_CPU_START">
<name>CPU_START</name>
<desc>Start or restart count on detection of 0 to 1 transition in the value of this bit. A read will always return the written value.
0 - No effect.
1 - Start count or restart count if previous value was 0.</desc>
<sw_param offset="0xf8000184" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA1_THR_CNT_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000188" start="31" end="20" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA1_THR_CNT_DLY_CNT">
<name>DLY_CNT</name>
<desc>Delay count value. Specifies the minimum number of output clock pulses before entering HALT state due to fpga_stop assertion.</desc>
<sw_param offset="0xf8000188" start="19" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA1_THR_CNT_LAST_CNT">
<name>LAST_CNT</name>
<desc>Last count value. Specifies the total number of clocks output in debug mode by the clock throttle logic.</desc>
<sw_param offset="0xf8000188" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA1_THR_STA_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800018c" start="31" end="17" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA1_THR_STA_RUNNING">
<name>RUNNING</name>
<desc>Current running status of FPGA clock output.
0 - Clock is stopped or in normal mode (OK to change config).
1 - Clock is runnnig in debug mode (Keep config static).</desc>
<sw_param offset="0xf800018c" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA1_THR_STA_CURR_VAL">
<name>CURR_VAL</name>
<desc>Current clock throttle counter value, which indicates the number of clock pulses output so far (only accurate when halted).</desc>
<sw_param offset="0xf800018c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA2_CLK_CTRL_reserved_3">
<name>reserved_3</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000190" start="31" end="26" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA2_CLK_CTRL_DIVISOR1">
<name>DIVISOR1</name>
<desc>Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider</desc>
<sw_param offset="0xf8000190" start="25" end="20" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA2_CLK_CTRL_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000190" start="19" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA2_CLK_CTRL_DIVISOR0">
<name>DIVISOR0</name>
<desc>Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider</desc>
<sw_param offset="0xf8000190" start="13" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA2_CLK_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000190" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA2_CLK_CTRL_SRCSEL">
<name>SRCSEL</name>
<desc>Selects the source used to generate the clock.
0x - Source for generated clock is IO PLL.
10 - Source for generated clock is ARM PLL.
11 - Source for generated clock is DDR PLL.</desc>
<sw_param offset="0xf8000190" start="5" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA2_CLK_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000190" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA2_THR_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000194" start="31" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA2_THR_CTRL_SYNC">
<name>SYNC</name>
<desc>Indicates whether fpga_stop input from the fabric should be considered synchronous or asynchronous to generated FPGA clock output.
0 - fpga_stop is asynchronous to FPGA clock.
1 - fpga_stop is synchronous to FPGA clock.</desc>
<sw_param offset="0xf8000194" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA2_THR_CTRL_EDGE">
<name>EDGE</name>
<desc>Selects between edge stop or level stop modes of operation for the clock throttle logic.
0 - debug level stop mode.
1 - debug edge stop mode.</desc>
<sw_param offset="0xf8000194" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA2_THR_CTRL_CNT_RST">
<name>CNT_RST</name>
<desc>Resets clock throttle counter when in halt state.
0 - No effect.
1 - Causes counter to be reset once HALT state is entered.</desc>
<sw_param offset="0xf8000194" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA2_THR_CTRL_CPU_START">
<name>CPU_START</name>
<desc>Start or restart count on detection of 0 to 1 transition in the value of this bit. A read will always return the written value.
0 - No effect.
1 - Start count or restart count if previous value was 0.</desc>
<sw_param offset="0xf8000194" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA2_THR_CNT_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000198" start="31" end="20" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA2_THR_CNT_DLY_CNT">
<name>DLY_CNT</name>
<desc>Delay count value. Specifies the minimum number of output clock pulses before entering HALT state due to fpga_stop assertion.</desc>
<sw_param offset="0xf8000198" start="19" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA2_THR_CNT_LAST_CNT">
<name>LAST_CNT</name>
<desc>Last count value. Specifies the total number of clocks output in debug mode by the clock throttle logic.</desc>
<sw_param offset="0xf8000198" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA2_THR_STA_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800019c" start="31" end="17" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA2_THR_STA_RUNNING">
<name>RUNNING</name>
<desc>Current running status of FPGA clock output.
0 - Clock is stopped or in normal mode (OK to change config).
1 - Clock is runnnig in debug mode (Keep config static).</desc>
<sw_param offset="0xf800019c" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA2_THR_STA_CURR_VAL">
<name>CURR_VAL</name>
<desc>Current clock throttle counter value, which indicates the number of clock pulses output so far (only accurate when halted).</desc>
<sw_param offset="0xf800019c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA3_CLK_CTRL_reserved_3">
<name>reserved_3</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf80001a0" start="31" end="26" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA3_CLK_CTRL_DIVISOR1">
<name>DIVISOR1</name>
<desc>Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider</desc>
<sw_param offset="0xf80001a0" start="25" end="20" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA3_CLK_CTRL_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf80001a0" start="19" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA3_CLK_CTRL_DIVISOR0">
<name>DIVISOR0</name>
<desc>Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider</desc>
<sw_param offset="0xf80001a0" start="13" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA3_CLK_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf80001a0" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA3_CLK_CTRL_SRCSEL">
<name>SRCSEL</name>
<desc>Selects the source used to generate the clock.
0x - Source for generated clock is IO PLL.
10 - Source for generated clock is ARM PLL.
11 - Source for generated clock is DDR PLL.</desc>
<sw_param offset="0xf80001a0" start="5" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA3_CLK_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf80001a0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA3_THR_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf80001a4" start="31" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA3_THR_CTRL_SYNC">
<name>SYNC</name>
<desc>Indicates whether fpga_stop input from the fabric should be considered synchronous or asynchronous to generated FPGA clock output.
0 - fpga_stop is asynchronous to FPGA clock.
1 - fpga_stop is synchronous to FPGA clock.</desc>
<sw_param offset="0xf80001a4" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA3_THR_CTRL_EDGE">
<name>EDGE</name>
<desc>Selects between edge stop or level stop modes of operation for the clock throttle logic.
0 - debug level stop mode.
1 - debug edge stop mode.</desc>
<sw_param offset="0xf80001a4" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA3_THR_CTRL_CNT_RST">
<name>CNT_RST</name>
<desc>Resets clock throttle counter when in halt state.
0 - No effect.
1 - Causes counter to be reset once HALT state is entered.</desc>
<sw_param offset="0xf80001a4" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA3_THR_CTRL_CPU_START">
<name>CPU_START</name>
<desc>Start or restart count on detection of 0 to 1 transition in the value of this bit. A read will always return the written value.
0 - No effect.
1 - Start count or restart count if previous value was 0.</desc>
<sw_param offset="0xf80001a4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA3_THR_CNT_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf80001a8" start="31" end="20" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA3_THR_CNT_DLY_CNT">
<name>DLY_CNT</name>
<desc>Delay count value. Specifies the minimum number of output clock pulses before entering HALT state due to fpga_stop assertion.</desc>
<sw_param offset="0xf80001a8" start="19" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA3_THR_CNT_LAST_CNT">
<name>LAST_CNT</name>
<desc>Last count value. Specifies the total number of clocks output in debug mode by the clock throttle logic.</desc>
<sw_param offset="0xf80001a8" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA3_THR_STA_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf80001ac" start="31" end="17" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA3_THR_STA_RUNNING">
<name>RUNNING</name>
<desc>Current running status of FPGA clock output.
0 - Clock is stopped or in normal mode (OK to change config).
1 - Clock is runnnig in debug mode (Keep config static).</desc>
<sw_param offset="0xf80001ac" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA3_THR_STA_CURR_VAL">
<name>CURR_VAL</name>
<desc>Current clock throttle counter value, which indicates the number of clock pulses output so far (only accurate when halted).</desc>
<sw_param offset="0xf80001ac" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_SYNC_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf80001b0" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_SYNC_CTRL_APU_DDR_1TO1">
<name>APU_DDR_1TO1</name>
<desc>Synchronous mode control for the CPU - DDR path
0 - asynchronous mode
1 - CPU and DDR at 1 to 1 clock ratio</desc>
<sw_param offset="0xf80001b0" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_BANDGAP_TRIM_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf80001b8" start="31" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_BANDGAP_TRIM_TRIM_EN">
<name>TRIM_EN</name>
<desc>Use the trim value in this register, if set</desc>
<sw_param offset="0xf80001b8" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_BANDGAP_TRIM_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf80001b8" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_BANDGAP_TRIM_TRIM_VAL">
<name>TRIM_VAL</name>
<desc>Bandgap trim value</desc>
<sw_param offset="0xf80001b8" start="5" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_CC_TEST_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf80001bc" start="31" end="7" />
</parameter>
<parameter uniqueid="ps7_slcr_CC_TEST_FB">
<name>FB</name>
<desc>PLL test</desc>
<sw_param offset="0xf80001bc" start="6" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_CC_TEST_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf80001bc" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_PLL_PREDIVISOR_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf80001c0" start="31" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_PLL_PREDIVISOR_PRE_DIVISOR">
<name>PRE_DIVISOR</name>
<desc>Divisor value.
The input frequency of Zync is between 30-60MHz and the input to the
PLL is between 30-60MHz, there is no reason to change this number from the default
value of one during normal operation.</desc>
<sw_param offset="0xf80001c0" start="5" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_CLK_621_TRUE_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf80001c4" start="31" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_CLK_621_TRUE_CLK_621_TRUE">
<name>CLK_621_TRUE</name>
<desc>Enable the 6:2:1 mode.
1 for 6:3:2:1.
0 for 4:2:2:1.</desc>
<sw_param offset="0xf80001c4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_PICTURE_DBG_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf80001d0" start="31" end="7" />
</parameter>
<parameter uniqueid="ps7_slcr_PICTURE_DBG_CLOCK_SEL">
<name>CLOCK_SEL</name>
<desc>Clock Select.
00=APU PLL clock (default).
01=DDR PLL clock.
10= IO PLL clock.
11= reserved</desc>
<sw_param offset="0xf80001d0" start="6" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_PICTURE_DBG_TRIGGER_EN">
<name>TRIGGER_EN</name>
<desc>This enables all the triggers.</desc>
<sw_param offset="0xf80001d0" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_PICTURE_DBG_CNT_LOAD">
<name>CNT_LOAD</name>
<desc>Load the count value into the counter.</desc>
<sw_param offset="0xf80001d0" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_PICTURE_DBG_TRIGGER_SEL">
<name>TRIGGER_SEL</name>
<desc>Trigger Select.
00 SLCR (default).
01 Fabric (Not implemented).
10 Address match (AXIM) (not implemented)</desc>
<sw_param offset="0xf80001d0" start="2" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_PICTURE_DBG_START">
<name>START</name>
<desc>Picture debug start, if set.</desc>
<sw_param offset="0xf80001d0" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_PICTURE_DBG_UCNT_COUNT_UPPER">
<name>COUNT_UPPER</name>
<desc>Upper 32-bit count value.</desc>
<sw_param offset="0xf80001d4" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_PICTURE_DBG_LCNT_COUNT_LOWER">
<name>COUNT_LOWER</name>
<desc>Lower 32-bit count value.</desc>
<sw_param offset="0xf80001d8" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_PSS_RST_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000200" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_PSS_RST_CTRL_SOFT_RST">
<name>SOFT_RST</name>
<desc>PSS software reset. On assertion of this reset, the entire design will be reset except for the clock generator. This bit is self clearing in that the reset generated will result in the SLCR being reset.
0 - No reset.
1 - PSS software reset initiated.</desc>
<sw_param offset="0xf8000200" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_RST_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000204" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_RST_CTRL_DDR_RST">
<name>DDR_RST</name>
<desc>DDR software reset. On assertion of this reset, the DDR subsystem will be reset.
0 - No reset.
1 - DDR subsystem held in reset.</desc>
<sw_param offset="0xf8000204" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_DMAC_RST_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800020c" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_DMAC_RST_CTRL_DMAC_RST">
<name>DMAC_RST</name>
<desc>DMAC software reset. On assertion of this reset DMAC will be reset.
0 - DMAC not in reset. DMAC TrustZone register is read only.
1 - DMAC held in reset. DMAC TrustZone register is now programmable.</desc>
<sw_param offset="0xf800020c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_USB_RST_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000210" start="31" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_USB_RST_CTRL_USB1_ULPI_RST">
<name>USB1_ULPI_RST</name>
<desc>USB 1 ULPI software reset. On assertion of this reset, the ULPI clock portion of the USB 1 subsystem will be reset.
0 - No reset.
1 - ULPI clock portion of USB 1 subsytem held in reset.</desc>
<sw_param offset="0xf8000210" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_USB_RST_CTRL_USB0_ULPI_RST">
<name>USB0_ULPI_RST</name>
<desc>USB 0 ULPI software reset. On assertion of this reset, the ULPI clock portion of the USB 0 subsystem will be reset.
0 - No reset.
1 - ULPI clock portion of USB 0 subsytem held in reset.</desc>
<sw_param offset="0xf8000210" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_USB_RST_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000210" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_USB_RST_CTRL_USB1_CPU1X_RST">
<name>USB1_CPU1X_RST</name>
<desc>USB 1 master and slave AMBA software reset. On assertion of this reset, the master and slave AMBA clock portion of the USB 1 subsystem will be reset.
0 - No reset.
1 - master and slave AMBA clock portion of USB 1 subsytem held in reset.</desc>
<sw_param offset="0xf8000210" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_USB_RST_CTRL_USB0_CPU1X_RST">
<name>USB0_CPU1X_RST</name>
<desc>USB 0 master and slave AMBA software reset. On assertion of this reset, the master and slave AMBA clock portion of the USB 0 subsystem will be reset.
0 - No reset.
1 - master and slave AMBA clock portion of USB 0 subsytem held in reset.</desc>
<sw_param offset="0xf8000210" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM_RST_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000214" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM_RST_CTRL_GEM1_REF_RST">
<name>GEM1_REF_RST</name>
<desc>Gigabit Ethernet 1 Reference software reset. On assertion of this reset, the Reference clock portion of the GEM 1 subsystem will be reset.
0 - No reset.
1 - Reference clock portion of GEM 1 subsytem held in reset.</desc>
<sw_param offset="0xf8000214" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM_RST_CTRL_GEM0_REF_RST">
<name>GEM0_REF_RST</name>
<desc>Gigabit Ethernet 0 Reference software reset. On assertion of this reset, the Reference clock portion of the GEM 0 subsystem will be reset.
0 - No reset.
1 - Reference clock portion of GEM 0 subsytem held in reset.</desc>
<sw_param offset="0xf8000214" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM_RST_CTRL_GEM1_RX_RST">
<name>GEM1_RX_RST</name>
<desc>Gigabit Ethernet MAC 1 RX software reset. On assertion of this reset, the RX clock portion of the GEM 1 subsystem will be reset.
0 - No reset.
1 - RX clock portion of GEM 1 subsytem held in reset.</desc>
<sw_param offset="0xf8000214" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM_RST_CTRL_GEM0_RX_RST">
<name>GEM0_RX_RST</name>
<desc>Gigabit Ethernet MAC 0 RX software reset. On assertion of this reset, the RX clock portion of the GEM 0 subsystem will be reset.
0 - No reset.
1 - RX clock portion of GEM 0 subsytem held in reset.</desc>
<sw_param offset="0xf8000214" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM_RST_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000214" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM_RST_CTRL_GEM1_CPU1X_RST">
<name>GEM1_CPU1X_RST</name>
<desc>Giagbit Ethernet MAC 1 software reset. On assertion of this reset, the Gigabit Ethernet MAC 1 subsystem will be reset.
0 - No reset.
1 - Gigabit Ethernet MAC 1 subsytem held in reset.</desc>
<sw_param offset="0xf8000214" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_GEM_RST_CTRL_GEM0_CPU1X_RST">
<name>GEM0_CPU1X_RST</name>
<desc>Gigabit Ethernet MAC 0 software reset. On assertion of this reset, the Gigabit Ethernet 0 subsystem will be reset.
0 - No reset.
1 - Gigabit Ethernet MAC 0 subsytem held in reset.</desc>
<sw_param offset="0xf8000214" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_SDIO_RST_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000218" start="31" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_SDIO_RST_CTRL_SDIO1_REF_RST">
<name>SDIO1_REF_RST</name>
<desc>SDIO 1 Reference software reset. On assertion of this reset, the Reference clock portion of the SDIO 1 subsystem will be reset. 0 - No reset. 1 - Reference clock portion of SDIO 1 subsytem held in reset.</desc>
<sw_param offset="0xf8000218" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_SDIO_RST_CTRL_SDIO0_REF_RST">
<name>SDIO0_REF_RST</name>
<desc>SDIO 0 Reference software reset. On assertion of this reset, the Reference clock portion of the SDIO 0 subsystem will be reset. 0 - No reset. 1 - Reference clock portion of SDIO 0 subsytem held in reset.</desc>
<sw_param offset="0xf8000218" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_SDIO_RST_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000218" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_SDIO_RST_CTRL_SDIO1_CPU1X_RST">
<name>SDIO1_CPU1X_RST</name>
<desc>SDIO 1 master and slave AMBA software reset. On assertion of this reset, the master and slave AMBA clock portion of the SDIO 1 subsystem will be reset.
0 - No reset.
1 - master and slave AMBA clock portion of SDIO 1 subsytem held in reset.</desc>
<sw_param offset="0xf8000218" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_SDIO_RST_CTRL_SDIO0_CPU1X_RST">
<name>SDIO0_CPU1X_RST</name>
<desc>SDIO 0 master and slave AMBA software reset. On assertion of this reset, the master and slave AMBA clock portion of the SDIO 0 subsystem will be reset.
0 - No reset.
1 - master and slave AMBA clock portion of SDIO 0 subsytem held in reset.</desc>
<sw_param offset="0xf8000218" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_SPI_RST_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800021c" start="31" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_SPI_RST_CTRL_SPI1_REF_RST">
<name>SPI1_REF_RST</name>
<desc>SPI 1 Reference software reset. On assertion of this reset, the Reference clock portion of the SPI 1 subsystem will be reset. 0 - No reset. 1 - Reference clock portion of SPI 1 subsytem held in reset.</desc>
<sw_param offset="0xf800021c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_SPI_RST_CTRL_SPI0_REF_RST">
<name>SPI0_REF_RST</name>
<desc>SPI 0 Reference software reset. On assertion of this reset, the Reference clock portion of the SPI 0 subsystem will be reset. 0 - No reset. 1 - Reference clock portion of SPI 0 subsytem held in reset.</desc>
<sw_param offset="0xf800021c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_SPI_RST_CTRL_SPI1_CPU1X_RST">
<name>SPI1_CPU1X_RST</name>
<desc>SPI 1 AMBA software reset. On assertion of this reset, the AMBA clock portion of the SPI 1 subsystem will be reset. 0 - No reset. 1 - AMBA clock portion of SPI 1 subsytem held in reset.</desc>
<sw_param offset="0xf800021c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_SPI_RST_CTRL_SPI0_CPU1X_RST">
<name>SPI0_CPU1X_RST</name>
<desc>SPI 0 AMBA software reset. On assertion of this reset, the AMBA clock portion of the SPI 0 subsystem will be reset. 0 - No reset. 1 - AMBA clock portion of SPI 0 subsytem held in reset.</desc>
<sw_param offset="0xf800021c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_CAN_RST_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000220" start="31" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_CAN_RST_CTRL_CAN1_REF_RST">
<name>CAN1_REF_RST</name>
<desc>CAN 1 Reference software reset. On assertion of this reset, the Reference clock portion of the CAN 1 subsystem will be reset. 0 - No reset. 1 - Reference clock portion of CAN 1 subsytem held in reset.</desc>
<sw_param offset="0xf8000220" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_CAN_RST_CTRL_CAN0_REF_RST">
<name>CAN0_REF_RST</name>
<desc>CAN 0 Reference software reset. On assertion of this reset, the Reference clock portion of the CAN 0 subsystem will be reset. 0 - No reset. 1 - Reference clock portion of CAN 0 subsytem held in reset.</desc>
<sw_param offset="0xf8000220" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_CAN_RST_CTRL_CAN1_CPU1X_RST">
<name>CAN1_CPU1X_RST</name>
<desc>CAN 1 AMBA software reset. On assertion of this reset, the AMBA clock portion of the CAN 1 subsystem will be reset. 0 - No reset. 1 - AMBA clock portion of CAN 1 subsytem held in reset.</desc>
<sw_param offset="0xf8000220" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_CAN_RST_CTRL_CAN0_CPU1X_RST">
<name>CAN0_CPU1X_RST</name>
<desc>CAN 0 AMBA software reset. On assertion of this reset, the AMBA clock portion of the CAN 0 subsystem will be reset. 0 - No reset. 1 - AMBA clock portion of CAN 0 subsytem held in reset.</desc>
<sw_param offset="0xf8000220" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_I2C_RST_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000224" start="31" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_I2C_RST_CTRL_I2C1_CPU1X_RST">
<name>I2C1_CPU1X_RST</name>
<desc>I2C 1 AMBA software reset. On assertion of this reset, the AMBA clock portion of the I2C 1 subsystem will be reset. 0 - No reset. 1 - AMBA clock portion of I2C 1 subsytem held in reset.</desc>
<sw_param offset="0xf8000224" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_I2C_RST_CTRL_I2C0_CPU1X_RST">
<name>I2C0_CPU1X_RST</name>
<desc>I2C 0 AMBA software reset. On assertion of this reset, the AMBA clock portion of the I2C 0 subsystem will be reset. 0 - No reset. 1 - AMBA clock portion of I2C 0 subsytem held in reset.</desc>
<sw_param offset="0xf8000224" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_UART_RST_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000228" start="31" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_UART_RST_CTRL_UART1_REF_RST">
<name>UART1_REF_RST</name>
<desc>UART1 Reference software reset. 0 - deassert soft reset. 1 - assert soft reset.</desc>
<sw_param offset="0xf8000228" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_UART_RST_CTRL_UART0_REF_RST">
<name>UART0_REF_RST</name>
<desc>UART0 Reference software reset. 0 - deassert soft reset. 1 - assert soft reset.</desc>
<sw_param offset="0xf8000228" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_UART_RST_CTRL_UART1_CPU1X_RST">
<name>UART1_CPU1X_RST</name>
<desc>UART 1 AMBA software reset. On assertion of this reset, the AMBA clock portion of the UART 1 subsystem will be reset. 0 - No reset. 1 - AMBA clock portion of UART 1 subsytem held in reset.</desc>
<sw_param offset="0xf8000228" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_UART_RST_CTRL_UART0_CPU1X_RST">
<name>UART0_CPU1X_RST</name>
<desc>UART 0 AMBA software reset. On assertion of this reset, the AMBA clock portion of the UART 0 subsystem will be reset. 0 - No reset. 1 - AMBA clock portion of UART 0 subsytem held in reset.</desc>
<sw_param offset="0xf8000228" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIO_RST_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800022c" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIO_RST_CTRL_GPIO_CPU1X_RST">
<name>GPIO_CPU1X_RST</name>
<desc>GPIO AMBA software reset. On assertion of this reset, the AMBA clock portion of the GPIO subsystem will be reset. 0 - No reset. 1 - AMBA clock portion of GPIO subsytem held in reset.</desc>
<sw_param offset="0xf800022c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_LQSPI_RST_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000230" start="31" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_LQSPI_RST_CTRL_QSPI_REF_RST">
<name>QSPI_REF_RST</name>
<desc>QSPI Reference software reset. On assertion of this reset, the Reference clock portion of the QSPI subsystem will be reset. 0 - No reset. 1 - Reference clock portion of QSPI subsytem held in reset.</desc>
<sw_param offset="0xf8000230" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_LQSPI_RST_CTRL_LQSPI_CPU1X_RST">
<name>LQSPI_CPU1X_RST</name>
<desc>Linear QSPI AMBA software reset. On assertion of this reset, the AMBA clock portion of the LQSPI subsystem will be reset. 0 - No reset. 1 - AMBA clock portion of QSPI subsytem held in reset.</desc>
<sw_param offset="0xf8000230" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_SMC_RST_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000234" start="31" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_SMC_RST_CTRL_SMC_REF_RST">
<name>SMC_REF_RST</name>
<desc>SMC Reference software reset. On assertion of this reset, the Reference clock portion of the SMC subsystem will be reset. 0 - No reset. 1 - Reference clock portion of SMC subsytem held in reset.</desc>
<sw_param offset="0xf8000234" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_SMC_RST_CTRL_SMC_CPU1X_RST">
<name>SMC_CPU1X_RST</name>
<desc>SMC AMBA software reset. On assertion of this reset, the AMBA clock portion of the SMC subsystem will be reset. 0 - No reset. 1 - AMBA clock portion of SMC subsytem held in reset.</desc>
<sw_param offset="0xf8000234" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_RST_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000238" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_RST_CTRL_OCM_RST">
<name>OCM_RST</name>
<desc>OCM software reset. On assertion of this reset, the OCM subsystem will be reset. 0 - No reset. 1 - OCM subsytem held in reset.</desc>
<sw_param offset="0xf8000238" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_DEVCI_RST_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800023c" start="31" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_DEVCI_RST_CTRL_DEVCI_CPU1X_RST">
<name>DEVCI_CPU1X_RST</name>
<desc>Device Configuration AMBA software reset. On assertion of this reset, the AMBA clock portion of the Device Config subsystem will be reset. 0 - No reset. 1 - AMBA clock portion of Device Configuration subsytem held in reset.</desc>
<sw_param offset="0xf800023c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_DEVCI_RST_CTRL_PCAP2X_RST">
<name>PCAP2X_RST</name>
<desc>Device Configuration PCAP2X software reset. On assertion of this reset, the PCAP2X clock portion of the Device Config subsystem will be reset. 0 - No reset. 1 - PCAP2X clock portion of Device Configuration subsytem held in reset.</desc>
<sw_param offset="0xf800023c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA_RST_CTRL_reserved_3">
<name>reserved_3</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000240" start="31" end="25" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA_RST_CTRL_FPGA_ACP_RST">
<name>FPGA_ACP_RST</name>
<desc>FPGA ACP port soft reset.
0 - No reset. 1 - ACP AXI interface reset output asserted.</desc>
<sw_param offset="0xf8000240" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA_RST_CTRL_FPGA_AXDS3_RST">
<name>FPGA_AXDS3_RST</name>
<desc>AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS3AXI interface reset output asserted.</desc>
<sw_param offset="0xf8000240" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA_RST_CTRL_FPGA_AXDS2_RST">
<name>FPGA_AXDS2_RST</name>
<desc>AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS2 AXI interface reset output asserted.</desc>
<sw_param offset="0xf8000240" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA_RST_CTRL_FPGA_AXDS1_RST">
<name>FPGA_AXDS1_RST</name>
<desc>AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS1 AXI interface reset output asserted.</desc>
<sw_param offset="0xf8000240" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA_RST_CTRL_FPGA_AXDS0_RST">
<name>FPGA_AXDS0_RST</name>
<desc>AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS0 AXI interface reset output asserted.</desc>
<sw_param offset="0xf8000240" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA_RST_CTRL_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000240" start="19" end="18" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA_RST_CTRL_FSSW1_FPGA_RST">
<name>FSSW1_FPGA_RST</name>
<desc>General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 1 reset is asserted.</desc>
<sw_param offset="0xf8000240" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA_RST_CTRL_FSSW0_FPGA_RST">
<name>FSSW0_FPGA_RST</name>
<desc>General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 0 reset is asserted.</desc>
<sw_param offset="0xf8000240" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA_RST_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000240" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA_RST_CTRL_FPGA_FMSW1_RST">
<name>FPGA_FMSW1_RST</name>
<desc>General purpose FPGA master interface 1 soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0 - No reset. 1 - FPGA master interface 1 reset is asserted.</desc>
<sw_param offset="0xf8000240" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA_RST_CTRL_FPGA_FMSW0_RST">
<name>FPGA_FMSW0_RST</name>
<desc>General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0 - No reset. 1 - FPGA master interface 0 reset is asserted.</desc>
<sw_param offset="0xf8000240" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA_RST_CTRL_FPGA_DMA3_RST">
<name>FPGA_DMA3_RST</name>
<desc>FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 3 peripheral request reset output asserted.</desc>
<sw_param offset="0xf8000240" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA_RST_CTRL_FPGA_DMA2_RST">
<name>FPGA_DMA2_RST</name>
<desc>FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 2 peripheral request reset output asserted.</desc>
<sw_param offset="0xf8000240" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA_RST_CTRL_FPGA_DMA1_RST">
<name>FPGA_DMA1_RST</name>
<desc>FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 1 peripheral request reset output asserted.</desc>
<sw_param offset="0xf8000240" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA_RST_CTRL_FPGA_DMA0_RST">
<name>FPGA_DMA0_RST</name>
<desc>FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 0 peripheral request reset output asserted.</desc>
<sw_param offset="0xf8000240" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA_RST_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000240" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA_RST_CTRL_FPGA3_OUT_RST">
<name>FPGA3_OUT_RST</name>
<desc>FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0 - No reset. 1 - FPGA 3 top level reset output asserted.</desc>
<sw_param offset="0xf8000240" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA_RST_CTRL_FPGA2_OUT_RST">
<name>FPGA2_OUT_RST</name>
<desc>FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0 - No reset. 1 - FPGA 2 top level reset output asserted.</desc>
<sw_param offset="0xf8000240" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA_RST_CTRL_FPGA1_OUT_RST">
<name>FPGA1_OUT_RST</name>
<desc>FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0 - No reset. 1 - FPGA 1 top level reset output asserted.</desc>
<sw_param offset="0xf8000240" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_FPGA_RST_CTRL_FPGA0_OUT_RST">
<name>FPGA0_OUT_RST</name>
<desc>FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0 - No reset. 1 - FPGA 0 top level reset output asserted.</desc>
<sw_param offset="0xf8000240" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_A9_CPU_RST_CTRL_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000244" start="31" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_A9_CPU_RST_CTRL_PERI_RST">
<name>PERI_RST</name>
<desc>CPU peripheral soft reset.</desc>
<sw_param offset="0xf8000244" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_A9_CPU_RST_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000244" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_A9_CPU_RST_CTRL_A9_CLKSTOP1">
<name>A9_CLKSTOP1</name>
<desc>Clock stop if 1 for core 1</desc>
<sw_param offset="0xf8000244" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_A9_CPU_RST_CTRL_A9_CLKSTOP0">
<name>A9_CLKSTOP0</name>
<desc>Clock stop if 1 for core 0</desc>
<sw_param offset="0xf8000244" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_A9_CPU_RST_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000244" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_A9_CPU_RST_CTRL_A9_RST1">
<name>A9_RST1</name>
<desc>0 - No reset.
1 - reset A9 core 1.</desc>
<sw_param offset="0xf8000244" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_A9_CPU_RST_CTRL_A9_RST0">
<name>A9_RST0</name>
<desc>0 - No reset.
1 - reset A9 core 0.</desc>
<sw_param offset="0xf8000244" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_RS_AWDT_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800024c" start="31" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_RS_AWDT_CTRL_CTRL1">
<name>CTRL1</name>
<desc>When the APU watchdog timer 1 goes off, the SLCR can control whether the whole system is reboot or just the ARM core who's WDT went off will be reset. 0 - reset Pele; 1 - reset ARM core</desc>
<sw_param offset="0xf800024c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_RS_AWDT_CTRL_CTRL0">
<name>CTRL0</name>
<desc>When the APU watchdog timer 0 goes off, the SLCR can control whether the whole system is reboot or just the ARM core who's WDT went off will be reset.
0 - reset Pele;
1 - reset ARM core</desc>
<sw_param offset="0xf800024c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_RST_REASON_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000250" start="31" end="7" />
</parameter>
<parameter uniqueid="ps7_slcr_RST_REASON_POR">
<name>POR</name>
<desc>Last reset was due to POR (power on reset), if set.</desc>
<sw_param offset="0xf8000250" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_RST_REASON_SRST_B">
<name>SRST_B</name>
<desc>Last reset was due to SRST_B (soft reset), if set.</desc>
<sw_param offset="0xf8000250" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_RST_REASON_DBG_RST">
<name>DBG_RST</name>
<desc>Last reset was due to debug system
reset, if set.</desc>
<sw_param offset="0xf8000250" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_RST_REASON_SLC_RST">
<name>SLC_RST</name>
<desc>Last reset was due to SLC soft reset, if set.</desc>
<sw_param offset="0xf8000250" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_RST_REASON_AWDT1_RST">
<name>AWDT1_RST</name>
<desc>Last reset was due to APU watchdog timer 1, if set.</desc>
<sw_param offset="0xf8000250" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_RST_REASON_AWDT0_RST">
<name>AWDT0_RST</name>
<desc>Last reset was due to APU watchdog timer 0, if set.</desc>
<sw_param offset="0xf8000250" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_RST_REASON_SWDT_RST">
<name>SWDT_RST</name>
<desc>Last reset was due to system watchdog timeout, if set (see watchdog status for more details).</desc>
<sw_param offset="0xf8000250" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_RST_REASON_CLR_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000254" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_RST_REASON_CLR_CLEAR">
<name>CLEAR</name>
<desc>Clears reset reason source within the reset controller. 0 - No effect. 1 - Clears reset reason source. A read of this register always returns zero.</desc>
<sw_param offset="0xf8000254" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_REBOOT_STATUS_REBOOT_STATE">
<name>REBOOT_STATE</name>
<desc>General 32-bit R/W field to allow software to store information that persists through all resets except power-on reset.</desc>
<sw_param offset="0xf8000258" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_BOOT_MODE_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800025c" start="31" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_BOOT_MODE_PLL_BYPASS">
<name>PLL_BYPASS</name>
<desc>Sampled bootstrap to indicate whether PLLs should be bypassed by default after deglicthed power on reset has completed.
0 - All PLL outputs are by default routed to clock distribution.
1 - All PLL outputs are bypassed and reference clock input will feed clock distribution</desc>
<sw_param offset="0xf800025c" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_BOOT_MODE_BOOT_MODE">
<name>BOOT_MODE</name>
<desc>Sampled bootstrap to indicate current boot mode. Interpreted by software:
x000 - PSS boots from QSPI
x001 - PSS boots from NAND
x010 - PSS boots from NOR
x011 - PSS boots from FPGA, Xilinx internal mode
0100 - PSS boots from JTAG on FPGA side
0111 - DFT mode, special mode to enable FPGA immediately with security shut down.
The reset value depends on what the mode pins are tied to at immediately after reset.</desc>
<sw_param offset="0xf800025c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_APU_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000300" start="31" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_APU_CTRL_CFGSDISABLE">
<name>CFGSDISABLE</name>
<desc>Disables write access to some system control processor registers, and some GIC registers.
Set only.</desc>
<sw_param offset="0xf8000300" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_APU_CTRL_CP15SDISABLE">
<name>CP15SDISABLE</name>
<desc>Disable write access to some system control processor (CP15) registers, in each processor. Set only.
Once set, individual core reset cannot reset this value.</desc>
<sw_param offset="0xf8000300" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_WDT_CLK_SEL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000304" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_WDT_CLK_SEL_SEL">
<name>SEL</name>
<desc>Watchdog timer clock source selection.
0 - cpu_1xclk.
1 - wdt_clk_in from FPGA.</desc>
<sw_param offset="0xf8000304" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ31">
<name>TZ31</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000400" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ30">
<name>TZ30</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000400" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ29">
<name>TZ29</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000400" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ28">
<name>TZ28</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000400" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ27">
<name>TZ27</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000400" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ26">
<name>TZ26</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000400" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ25">
<name>TZ25</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000400" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ24">
<name>TZ24</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000400" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ23">
<name>TZ23</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000400" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ22">
<name>TZ22</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000400" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ21">
<name>TZ21</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000400" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ20">
<name>TZ20</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000400" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ19">
<name>TZ19</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000400" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ18">
<name>TZ18</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000400" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ17">
<name>TZ17</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000400" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ16">
<name>TZ16</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000400" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ15">
<name>TZ15</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000400" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ14">
<name>TZ14</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000400" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ13">
<name>TZ13</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000400" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ12">
<name>TZ12</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000400" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ11">
<name>TZ11</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000400" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ10">
<name>TZ10</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000400" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ9">
<name>TZ9</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000400" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ8">
<name>TZ8</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000400" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ7">
<name>TZ7</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000400" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ6">
<name>TZ6</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000400" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ5">
<name>TZ5</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000400" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ4">
<name>TZ4</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000400" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ3">
<name>TZ3</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000400" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ2">
<name>TZ2</name>
<desc>TrustZone status for 4KB page 2 at 8KB</desc>
<sw_param offset="0xf8000400" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ1">
<name>TZ1</name>
<desc>TrustZone status for 4KB page 1 at 4KB</desc>
<sw_param offset="0xf8000400" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM0_TZ0">
<name>TZ0</name>
<desc>TrustZone status for 4KB page 0 at 0KB</desc>
<sw_param offset="0xf8000400" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ63">
<name>TZ63</name>
<desc>TrustZone status for 4KB page (32+n) at (32+n)*4KB</desc>
<sw_param offset="0xf8000404" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ62">
<name>TZ62</name>
<desc>TrustZone status for 4KB page (32+n) at (32+n)*4KB</desc>
<sw_param offset="0xf8000404" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ61">
<name>TZ61</name>
<desc>TrustZone status for 4KB page (32+n) at (32+n)*4KB</desc>
<sw_param offset="0xf8000404" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ60">
<name>TZ60</name>
<desc>TrustZone status for 4KB page (32+n) at (32+n)*4KB</desc>
<sw_param offset="0xf8000404" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ59">
<name>TZ59</name>
<desc>TrustZone status for 4KB page (32+n) at (32+n)*4KB</desc>
<sw_param offset="0xf8000404" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ58">
<name>TZ58</name>
<desc>TrustZone status for 4KB page (32+n) at (32+n)*4KB</desc>
<sw_param offset="0xf8000404" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ57">
<name>TZ57</name>
<desc>TrustZone status for 4KB page (32+n) at (32+n)*4KB</desc>
<sw_param offset="0xf8000404" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ56">
<name>TZ56</name>
<desc>TrustZone status for 4KB page (32+n) at (32+n)*4KB</desc>
<sw_param offset="0xf8000404" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ55">
<name>TZ55</name>
<desc>TrustZone status for 4KB page (32+n) at (32+n)*4KB</desc>
<sw_param offset="0xf8000404" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ54">
<name>TZ54</name>
<desc>TrustZone status for 4KB page (32+n) at (32+n)*4KB</desc>
<sw_param offset="0xf8000404" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ53">
<name>TZ53</name>
<desc>TrustZone status for 4KB page (32+n) at (32+n)*4KB</desc>
<sw_param offset="0xf8000404" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ52">
<name>TZ52</name>
<desc>TrustZone status for 4KB page (32+n) at (32+n)*4KB</desc>
<sw_param offset="0xf8000404" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ51">
<name>TZ51</name>
<desc>TrustZone status for 4KB page (32+n) at (32+n)*4KB</desc>
<sw_param offset="0xf8000404" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ50">
<name>TZ50</name>
<desc>TrustZone status for 4KB page (32+n) at (32+n)*4KB</desc>
<sw_param offset="0xf8000404" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ49">
<name>TZ49</name>
<desc>TrustZone status for 4KB page (32+n) at (32+n)*4KB</desc>
<sw_param offset="0xf8000404" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ48">
<name>TZ48</name>
<desc>TrustZone status for 4KB page (32+n) at (32+n)*4KB</desc>
<sw_param offset="0xf8000404" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ47">
<name>TZ47</name>
<desc>TrustZone status for 4KB page (32+n) at (32+n)*4KB</desc>
<sw_param offset="0xf8000404" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ46">
<name>TZ46</name>
<desc>TrustZone status for 4KB page (32+n) at (32+n)*4KB</desc>
<sw_param offset="0xf8000404" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ45">
<name>TZ45</name>
<desc>TrustZone status for 4KB page (32+n) at (32+n)*4KB</desc>
<sw_param offset="0xf8000404" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ44">
<name>TZ44</name>
<desc>TrustZone status for 4KB page (32+n) at (32+n)*4KB</desc>
<sw_param offset="0xf8000404" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ43">
<name>TZ43</name>
<desc>TrustZone status for 4KB page (32+n) at (32+n)*4KB</desc>
<sw_param offset="0xf8000404" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ42">
<name>TZ42</name>
<desc>TrustZone status for 4KB page (32+n) at (32+n)*4KB</desc>
<sw_param offset="0xf8000404" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ41">
<name>TZ41</name>
<desc>TrustZone status for 4KB page (32+n) at (32+n)*4KB</desc>
<sw_param offset="0xf8000404" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ40">
<name>TZ40</name>
<desc>TrustZone status for 4KB page (32+n) at (32+n)*4KB</desc>
<sw_param offset="0xf8000404" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ39">
<name>TZ39</name>
<desc>TrustZone status for 4KB page (32+n) at (32+n)*4KB</desc>
<sw_param offset="0xf8000404" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ38">
<name>TZ38</name>
<desc>TrustZone status for 4KB page (32+n) at (32+n)*4KB</desc>
<sw_param offset="0xf8000404" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ37">
<name>TZ37</name>
<desc>TrustZone status for 4KB page (32+n) at (32+n)*4KB</desc>
<sw_param offset="0xf8000404" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ36">
<name>TZ36</name>
<desc>TrustZone status for 4KB page (32+n) at (32+n)*4KB</desc>
<sw_param offset="0xf8000404" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ35">
<name>TZ35</name>
<desc>TrustZone status for 4KB page (32+n) at (32+n)*4KB</desc>
<sw_param offset="0xf8000404" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ34">
<name>TZ34</name>
<desc>TrustZone status for 4KB page 34 at 136KB</desc>
<sw_param offset="0xf8000404" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ33">
<name>TZ33</name>
<desc>TrustZone status for 4KB page 33 at 132KB</desc>
<sw_param offset="0xf8000404" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_RAM1_TZ32">
<name>TZ32</name>
<desc>TrustZone status for 4KB page 32 at 128KB</desc>
<sw_param offset="0xf8000404" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ95">
<name>TZ95</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ94">
<name>TZ94</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ93">
<name>TZ93</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ92">
<name>TZ92</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ91">
<name>TZ91</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ90">
<name>TZ90</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ89">
<name>TZ89</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ88">
<name>TZ88</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ87">
<name>TZ87</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ86">
<name>TZ86</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ85">
<name>TZ85</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ84">
<name>TZ84</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ83">
<name>TZ83</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ82">
<name>TZ82</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ81">
<name>TZ81</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ80">
<name>TZ80</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ79">
<name>TZ79</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ78">
<name>TZ78</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ77">
<name>TZ77</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ76">
<name>TZ76</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ75">
<name>TZ75</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ74">
<name>TZ74</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ73">
<name>TZ73</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ72">
<name>TZ72</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ71">
<name>TZ71</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ70">
<name>TZ70</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ69">
<name>TZ69</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ68">
<name>TZ68</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ67">
<name>TZ67</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ66">
<name>TZ66</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ65">
<name>TZ65</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_OCM_ROM_TZ64">
<name>TZ64</name>
<desc>TrustZone status for 4KB page n at n*4KB</desc>
<sw_param offset="0xf8000408" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ31">
<name>TZ31</name>
<desc>TrustZone status for 64MB section n at n*64MB.
0 = Secure, reset value.
1 = Non-secure.</desc>
<sw_param offset="0xf8000430" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ30">
<name>TZ30</name>
<desc>same</desc>
<sw_param offset="0xf8000430" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ29">
<name>TZ29</name>
<desc>same</desc>
<sw_param offset="0xf8000430" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ28">
<name>TZ28</name>
<desc>same</desc>
<sw_param offset="0xf8000430" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ27">
<name>TZ27</name>
<desc>same</desc>
<sw_param offset="0xf8000430" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ26">
<name>TZ26</name>
<desc>same</desc>
<sw_param offset="0xf8000430" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ25">
<name>TZ25</name>
<desc>same</desc>
<sw_param offset="0xf8000430" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ24">
<name>TZ24</name>
<desc>same</desc>
<sw_param offset="0xf8000430" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ23">
<name>TZ23</name>
<desc>same</desc>
<sw_param offset="0xf8000430" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ22">
<name>TZ22</name>
<desc>same</desc>
<sw_param offset="0xf8000430" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ21">
<name>TZ21</name>
<desc>same</desc>
<sw_param offset="0xf8000430" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ20">
<name>TZ20</name>
<desc>same</desc>
<sw_param offset="0xf8000430" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ19">
<name>TZ19</name>
<desc>same</desc>
<sw_param offset="0xf8000430" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ18">
<name>TZ18</name>
<desc>same</desc>
<sw_param offset="0xf8000430" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ17">
<name>TZ17</name>
<desc>same</desc>
<sw_param offset="0xf8000430" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ16">
<name>TZ16</name>
<desc>same</desc>
<sw_param offset="0xf8000430" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ15">
<name>TZ15</name>
<desc>same</desc>
<sw_param offset="0xf8000430" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ14">
<name>TZ14</name>
<desc>same</desc>
<sw_param offset="0xf8000430" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ13">
<name>TZ13</name>
<desc>same</desc>
<sw_param offset="0xf8000430" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ12">
<name>TZ12</name>
<desc>same</desc>
<sw_param offset="0xf8000430" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ11">
<name>TZ11</name>
<desc>same</desc>
<sw_param offset="0xf8000430" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ10">
<name>TZ10</name>
<desc>same</desc>
<sw_param offset="0xf8000430" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ9">
<name>TZ9</name>
<desc>same</desc>
<sw_param offset="0xf8000430" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ8">
<name>TZ8</name>
<desc>same</desc>
<sw_param offset="0xf8000430" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ7">
<name>TZ7</name>
<desc>same</desc>
<sw_param offset="0xf8000430" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ6">
<name>TZ6</name>
<desc>same</desc>
<sw_param offset="0xf8000430" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ5">
<name>TZ5</name>
<desc>same</desc>
<sw_param offset="0xf8000430" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ4">
<name>TZ4</name>
<desc>same</desc>
<sw_param offset="0xf8000430" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ3">
<name>TZ3</name>
<desc>same</desc>
<sw_param offset="0xf8000430" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ2">
<name>TZ2</name>
<desc>TrustZone status for 64MB section n at n*64MB.
0 = Secure, reset value.
1 = Non-secure.</desc>
<sw_param offset="0xf8000430" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ1">
<name>TZ1</name>
<desc>TrustZone status for 64MB section 1 at 64MB.
0 = Secure, reset value.
1 = Non-secure.</desc>
<sw_param offset="0xf8000430" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DDR_RAM_TZ0">
<name>TZ0</name>
<desc>TrustZone status for 64MB section 0 at 0MB.
0 = Secure, reset value.
1 = Non-secure.</desc>
<sw_param offset="0xf8000430" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DMA_NS_reserved">
<name>reserved</name>
<desc>Should Be Zero</desc>
<sw_param offset="0xf8000440" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DMA_NS_DMAC_NS">
<name>DMAC_NS</name>
<desc>TZ security.
0 = secure, DMAC operates in the secure state.
1 = non-secure, DMAC operates in the non-secure state.</desc>
<sw_param offset="0xf8000440" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DMA_IRQ_NS_reserved">
<name>reserved</name>
<desc>Should Be Zero</desc>
<sw_param offset="0xf8000444" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DMA_IRQ_NS_DMA_IRQ_NS">
<name>DMA_IRQ_NS</name>
<desc>TZ security.
0 = secure, DMAC operates in the secure state.
1 = non-secure, DMAC interrupt/event bit is in the non-secure state.</desc>
<sw_param offset="0xf8000444" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DMA_PERIPH_NS_reserved">
<name>reserved</name>
<desc>Should Be Zero</desc>
<sw_param offset="0xf8000448" start="31" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_DMA_PERIPH_NS_DMAC_PERIPH_NS">
<name>DMAC_PERIPH_NS</name>
<desc>TZ security.
0 = secure, DMAC operates in the secure state.
1 = non-secure, reset value: DMAC peripheral i/f is in the non-secure state.</desc>
<sw_param offset="0xf8000448" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_GEM_reserved">
<name>reserved</name>
<desc>Should Be Zero</desc>
<sw_param offset="0xf8000450" start="31" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_GEM_E1">
<name>E1</name>
<desc>TrustZone status for Gigabit Ethernet MAC 1. 0 = Secure, reset value. 1 = Non-secure.</desc>
<sw_param offset="0xf8000450" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_GEM_E0">
<name>E0</name>
<desc>TrustZone status for Gigabit Ethernet MAC 0. 0 = Secure, reset value. 1 = Non-secure.</desc>
<sw_param offset="0xf8000450" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_SDIO_reserved">
<name>reserved</name>
<desc>Should Be Zero</desc>
<sw_param offset="0xf8000454" start="31" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_SDIO_S1">
<name>S1</name>
<desc>TrustZone status for SDIO controller 1. 0 = Secure, reset value. 1 = Non-secure.</desc>
<sw_param offset="0xf8000454" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_SDIO_S0">
<name>S0</name>
<desc>TrustZone status for SDIO controller 0. 0 = Secure, reset value. 1 = Non-secure.</desc>
<sw_param offset="0xf8000454" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_USB_reserved">
<name>reserved</name>
<desc>Should Be Zero</desc>
<sw_param offset="0xf8000458" start="31" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_USB_U1">
<name>U1</name>
<desc>TrustZone status for USB controller 1. 0 = Secure, reset value. 1 = Non-secure.</desc>
<sw_param offset="0xf8000458" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_USB_U0">
<name>U0</name>
<desc>TrustZone status for USB controller 0. 0 = Secure, reset value. 1 = Non-secure.</desc>
<sw_param offset="0xf8000458" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_FPGA_M_reserved">
<name>reserved</name>
<desc>Should Be Zero</desc>
<sw_param offset="0xf8000484" start="31" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_FPGA_M_M1">
<name>M1</name>
<desc>Secure disable for FPGA AXI master port 1. 0 = master port can make Secure and Non-secure accesses, reset value. 1 = master port can only make Non-secure accesses.</desc>
<sw_param offset="0xf8000484" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_FPGA_M_M0">
<name>M0</name>
<desc>Secure disable for FPGA AXI master port 0. 0 = master port can make Secure and Non-secure accesses, reset value. 1 = master port can only make Non-secure accesses.</desc>
<sw_param offset="0xf8000484" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_FPGA_AFI_reserved">
<name>reserved</name>
<desc>Should Be Zero</desc>
<sw_param offset="0xf8000488" start="31" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_FPGA_AFI_P3">
<name>P3</name>
<desc>Secure disable for FPGA AFI AXI port 3. 0 = port can make Secure and Non-secure accesses, reset value. 1 = port can only make Non-secure accesses.</desc>
<sw_param offset="0xf8000488" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_FPGA_AFI_P2">
<name>P2</name>
<desc>Secure disable for FPGA AFI AXI port 2. 0 = port can make Secure and Non-secure accesses, reset value. 1 = port can only make Non-secure accesses.</desc>
<sw_param offset="0xf8000488" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_FPGA_AFI_P1">
<name>P1</name>
<desc>Secure disable for FPGA AFI AXI port 1. 0 = port can make Secure and Non-secure accesses, reset value. 1 = port can only make Non-secure accesses.</desc>
<sw_param offset="0xf8000488" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_TZ_FPGA_AFI_P0">
<name>P0</name>
<desc>Secure disable for FPGA AFI AXI port 0. 0 = port can make Secure and Non-secure accesses, reset value. 1 = port can only make Non-secure accesses.</desc>
<sw_param offset="0xf8000488" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_DBG_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000500" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_DBG_CTRL_SRST_B_TRI_B">
<name>SRST_B_TRI_B</name>
<desc>Controls direction of top level SRST_B
pad.. When an output, the SRST_B pin is fed by the UART0 TX for firmware debug messages.
0 - SRST_B pad is an input for soft reset signal.
1 - SRST_B pad is an output dirven by UART0 TX.</desc>
<sw_param offset="0xf8000500" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_PSS_IDCODE_IDCODE">
<name>IDCODE</name>
<desc>PSS IDCODE value, defined as follows:
IDCODE[0] - Reserved = 1.
IDCODE[11:1] - Manufacturer ID = 000 0100 1001.
IDCODE[16:12] - Device from FPGA gasket = idcode_devtype[4:0].
IDCODE[20:17] - Subfamily from FPGA gasket = 1001.
IDCODE[27:21] - Family = 001 1011.
IDCODE[31:28] - Revision from FPGA gasket = idcode_version[3:0]</desc>
<sw_param offset="0xf8000530" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_URGENT_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8000600" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_URGENT_S3_ARURGENT">
<name>S3_ARURGENT</name>
<desc>Identifies DDR's AXI port S3 read prioritisation. Same as below.</desc>
<sw_param offset="0xf8000600" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_URGENT_S2_ARURGENT">
<name>S2_ARURGENT</name>
<desc>Identifies DDR's AXI port S2 read prioritisation. Same as below.</desc>
<sw_param offset="0xf8000600" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_URGENT_S1_ARURGENT">
<name>S1_ARURGENT</name>
<desc>Identifies DDR's AXI port S1 read prioritisation. Same as below.</desc>
<sw_param offset="0xf8000600" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_URGENT_S0_ARURGENT">
<name>S0_ARURGENT</name>
<desc>Identifies DDR's AXI port S0 read prioritisation:
0 - DDR's AXI port S0 read not requesting urgent prioritization.
1 - DDR's AXI port S0 read is requesting urgent prioritization.</desc>
<sw_param offset="0xf8000600" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_URGENT_S3_AWURGENT">
<name>S3_AWURGENT</name>
<desc>Identifies DDR's AXI port S3write prioritisation. Same as below.</desc>
<sw_param offset="0xf8000600" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_URGENT_S2_AWURGENT">
<name>S2_AWURGENT</name>
<desc>Identifies DDR's AXI port S2 write prioritisation. Same as below.</desc>
<sw_param offset="0xf8000600" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_URGENT_S1_AWURGENT">
<name>S1_AWURGENT</name>
<desc>Identifies DDR's AXI port S1 write prioritisation. Same as below.</desc>
<sw_param offset="0xf8000600" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_URGENT_S0_AWURGENT">
<name>S0_AWURGENT</name>
<desc>Identifies DDR's AXI port S0 write prioritisation:
0 - DDR's AXI port S0 write not requesting urgent prioritization.
1 - DDR's AXI port S0 write is requesting urgent prioritization.</desc>
<sw_param offset="0xf8000600" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_CAL_START_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800060c" start="31" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_CAL_START_START_CAL_DLL">
<name>START_CAL_DLL</name>
<desc>This register creates a pulse which is first synchronised into the ddr_clk domain and then directly drives the co_gs_dll_calib input into the DDR controller. This signal is a command that indicates to the controller to issue a dll_calib to the DRAM. This signal should pulse for 1 ddrc_core_clk clock cycle to request a dll_calib to be issued. This is only required if the DDR controller register reg_ddrc_dis_dll_calib is 1. If reg_ddrc_dis_dll_calib is 0, the controller will automatically issue DLL Calibs.
0 - Do nothing.
1 - Start DLL calibration command.
A read of this register always returns zero.</desc>
<sw_param offset="0xf800060c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_CAL_START_START_CAL_SHORT">
<name>START_CAL_SHORT</name>
<desc>This register creates a pulse which is first synchronised into the ddr_clk domain and then directly drives the co_gs_zq_calib_short input into the DDR controller. This is required to pulse for 1 clock to issue ZQ Calibration Short Command to the DDR. There should be a minimum of 512 clks gap between 2 ZQ Calib Short commands from the core. If DDR controller register reg_ddrc_dis_auto_zq=0, asserting co_gs_zq_calib_short is not required, as this will be done automatically. If reg_ddrc_dis_auto_zq=1, then the core logic is required to assert co_gs_zq_calib_short periodically to update DDR3 ZQ calibration.
0 - Do nothing.
1 - Start ZQ calibration short command.
A read of this register always returns zero.</desc>
<sw_param offset="0xf800060c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_REF_START_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000614" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_REF_START_START_REF">
<name>START_REF</name>
<desc>This register creates a pulse which is first synchronised into the ddr_clk domain and then directly drives the co_gs_rank_refresh input into the DDR controller. This register must be used with the Virage DRAM controller register bit reg_ddrc_dis_auto_refresh.
This signal is a command that indicates to the controller to issue a refresh to the DRAM. One bit per rank. This signal should pulse for 1 ddrc_core_clk clock cycle to request a refresh to be issued.
0 - Do nothing.
1 - Start refresh.
A read of this register always returns zero.</desc>
<sw_param offset="0xf8000614" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_CMD_STA_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000618" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_CMD_STA_CMD_Q_NEMPTY">
<name>CMD_Q_NEMPTY</name>
<desc>DDR controller command store fill status.
0 - indicates DDRC command store is empty.
1 - indicates there are commands pending in DDRC command store.
This register is a continuous monitor of the ddrc_co_q_not_empty output from the DDR controller, which is first synchronised from ddr_clk into amba1x_clk.</desc>
<sw_param offset="0xf8000618" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_URGENT_SEL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf800061c" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_URGENT_SEL_S3_ARQOS_MODE">
<name>S3_ARQOS_MODE</name>
<desc>Selects between the AXI port s3_arqos[3], fabric signal or static register  to drive the DDRC urgent bit as follows: 2'b00 - The DDRC s3_arurgent bit is driven from the 'S3_ARURGENT' field of the DDR_URGENT_VAL register. 2'b01 - The DDRC s3_arurgent bit is driven from the s3_arqos bit. 2'b10 - The DDRC s3_arurgent bit is driven from the fabric ddr_arb[3] input. 2'b11 - Undefined</desc>
<sw_param offset="0xf800061c" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_URGENT_SEL_S2_ARQOS_MODE">
<name>S2_ARQOS_MODE</name>
<desc>Selects between the AXI port s2_arqos[3], fabric signal or static register  to drive the DDRC urgent bit as follows: 2'b00 - The DDRC s2_arurgent bit is driven from the 'S2_ARURGENT' field of the DDR_URGENT_VAL register. 2'b01 - The DDRC s2_arurgent bit is driven from the s2_arqos bit. 2'b10 - The DDRC s2_arurgent bit is driven from the fabric ddr_arb[2] input. 2'b11 - Undefined.</desc>
<sw_param offset="0xf800061c" start="13" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_URGENT_SEL_S1_ARQOS_MODE">
<name>S1_ARQOS_MODE</name>
<desc>Selects between the AXI port s1_arqos[3], fabric signal or static register  to drive the DDRC urgent bit as follows: 2'b00 - The DDRC s1_arurgent bit is driven from the 'S1_ARURGENT' field of the DDR_URGENT_VAL register. 2'b01 - The DDRC s1_arurgent bit is driven from the s1_arqos bit. 2'b10 - The DDRC s1_arurgent bit is driven from the fabric ddr_arb[1] input. 2'b11 - Undefined.</desc>
<sw_param offset="0xf800061c" start="11" end="10" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_URGENT_SEL_S0_ARQOS_MODE">
<name>S0_ARQOS_MODE</name>
<desc>Selects between the fabric signal or static register  to drive the DDRC urgent bit as follows: 2'b00 - The DDRC s0_arurgent bit is driven from the 'S0_ARURGENT' field of the DDR_URGENT_VAL register. 2'b01 -Undefined. 2'b10 - The DDRC s0_arurgent bit is driven from the fabric ddr_arb[0] input. 2'b11 - Undefined</desc>
<sw_param offset="0xf800061c" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_URGENT_SEL_S3_AWQOS_MODE">
<name>S3_AWQOS_MODE</name>
<desc>Selects between the AXI port s3_awqos[3], fabric signal or static register  to drive the DDRC urgent bit as follows: 2'b00 - The DDRC s3_awurgent bit is driven from the 'S3_AWURGENT' field of the DDR_URGENT_VAL register. 2'b01 - The DDRC s3_awurgent bit is driven from the s3_awqos bit. 2'b10 - The DDRC s3_awurgent bit is driven from the fabric ddr_arb[3] input. 2'b11 - Undefined</desc>
<sw_param offset="0xf800061c" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_URGENT_SEL_S2_AWQOS_MODE">
<name>S2_AWQOS_MODE</name>
<desc>Selects between the AXI port s2_awqos[3], fabric signal or static register  to drive the DDRC urgent bit as follows: 2'b00 - The DDRC s2_awurgent bit is driven from the 'S2_AWURGENT' field of the DDR_URGENT_VAL register. 2'b01 - The DDRC s2_awurgent bit is driven from the s2_awqos bit. 2'b10 - The DDRC s2_awurgent bit is driven from the fabric ddr_arb[2] input. 2'b11 - Undefined</desc>
<sw_param offset="0xf800061c" start="5" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_URGENT_SEL_S1_AWQOS_MODE">
<name>S1_AWQOS_MODE</name>
<desc>Selects between the AXI port s1_awqos[3], fabric signal or static register  to drive the DDRC urgent bit as follows: 2'b00 - The DDRC s1_awurgent bit is driven from the 'S1_AWURGENT' field of the DDR_URGENT_VAL register. 2'b01 - The DDRC s1_awurgent bit is driven from the s1_awqos bit. 2'b10 - The DDRC s1_awurgent bit is driven from the fabric ddr_arb[1] input. 2'b11 - Undefined</desc>
<sw_param offset="0xf800061c" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_URGENT_SEL_S0_AWQOS_MODE">
<name>S0_AWQOS_MODE</name>
<desc>Selects between the fabric signal or static register  to drive the DDRC urgent bit as follows: 2'b00 - The DDRC s0_awurgent bit is driven from the 'S0_AWURGENT' field of the DDR_URGENT_VAL register. 2'b01 -Undefined. 2'b10 - The DDRC s0_awurgent bit is driven from the fabric ddr_arb[0] input. 2'b11 - Undefined.</desc>
<sw_param offset="0xf800061c" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_DFI_STATUS_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000620" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_DDR_DFI_STATUS_DFI_CAL_ST">
<name>DFI_CAL_ST</name>
<desc>This signal is intended to allow a calibration of the IOB's at a time when the DDR controller is in its calibration mode, i.e. during an idle period.</desc>
<sw_param offset="0xf8000620" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_00_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf8000700" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_00_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf8000700" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_00_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf8000700" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_00_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf8000700" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_00_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf8000700" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_00_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0)
0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0)
1= Not Used
2= Not Used
3= Not Used
4= Not Used
5= Not Used
6= Not Used
7= Not Used</desc>
<sw_param offset="0xf8000700" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_00_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= smc_cs0, Output, smc_sram_cs_n[0]- (SRAM CS0)
2= nand_cs, Output, smc_nand_cs_n- (NAND chip select)
3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf8000700" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_00_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= Not Used</desc>
<sw_param offset="0xf8000700" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_00_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= qspi_sel, Output, qspi_n_ss_out_upper- (QSPI Upper select)</desc>
<sw_param offset="0xf8000700" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_00_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf8000700" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_01_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf8000704" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_01_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf8000704" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_01_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf8000704" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_01_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf8000704" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_01_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf8000704" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_01_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0)
0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0)
1= Not Used
2= Not Used
3= Not Used
4= Not Used
5= Not Used
6= Not Used
7= Not Used</desc>
<sw_param offset="0xf8000704" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_01_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= smc_a25, Output, smc_sram_add[25]- (SRAM Address)
2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1)
3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf8000704" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_01_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= Not Used</desc>
<sw_param offset="0xf8000704" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_01_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select)</desc>
<sw_param offset="0xf8000704" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_01_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf8000704" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_02_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf8000708" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_02_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf8000708" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_02_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled
Pull-up disabled by default as this pin is used for mode[0]</desc>
<sw_param offset="0xf8000708" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_02_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf8000708" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_02_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf8000708" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_02_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0)
0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0)
1= Not Used
2= Not Used
3= Not Used
4= Not Used
5= Not Used
6= Not Used
7= Not Used</desc>
<sw_param offset="0xf8000708" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_02_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Output, smc_sram_clk- (SRAM Clock)
2= nand, Output, smc_nand_ale- (NAND Address Latch Enable)
3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf8000708" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_02_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= trace_data, Output, tracedq[8]- (Trace Port Databus)</desc>
<sw_param offset="0xf8000708" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_02_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= qspi, Output, qspi_mo_mo0- (QSPI Databus)
1= qspi, Input, qspi_si_mi0- (QSPI Databus)</desc>
<sw_param offset="0xf8000708" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_02_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf8000708" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_03_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf800070c" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_03_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf800070c" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_03_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled
Pull-up disabled by default as this pin is used for mode[1]</desc>
<sw_param offset="0xf800070c" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_03_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf800070c" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_03_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf800070c" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_03_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0)
0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0)
1= Not Used
2= Not Used
3= Not Used
4= Not Used
5= Not Used
6= Not Used
7= Not Used</desc>
<sw_param offset="0xf800070c" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_03_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data)
= sram_nor, Output, smc_sram_data_out[0]- (SRAM Data)
2= nand, Output, smc_nand_we_b- (NAND Write Enable)
3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf800070c" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_03_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= trace_data, Output, tracedq[9]- (Trace Port Databus)</desc>
<sw_param offset="0xf800070c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_03_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= qspi, Input, qspi_mi_mi1- (QSPI Databus)
1= qspi, Output, qspi_so_mo1- (QSPI Databus)</desc>
<sw_param offset="0xf800070c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_03_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf800070c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_04_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf8000710" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_04_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf8000710" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_04_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled
Pull-up disabled by default as this pin is used for mode[2]</desc>
<sw_param offset="0xf8000710" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_04_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf8000710" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_04_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf8000710" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_04_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0)
0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0)
1= Not Used
2= Not Used
3= Not Used
4= Not Used
5= Not Used
6= Not Used
7= Not Used</desc>
<sw_param offset="0xf8000710" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_04_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data)
= sram_nor, Output, smc_sram_data_out[1]- (SRAM Data)
2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus)
= nand, Output, smc_nand_data_out[2]- (NAND Data Bus)
3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf8000710" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_04_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= trace_data, Output, tracedq[10]- (Trace Port Databus)</desc>
<sw_param offset="0xf8000710" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_04_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= qspi, Input, qspi_mi2- (QSPI Databus)
1= qspi, Output, qspi_mo2- (QSPI Databus)</desc>
<sw_param offset="0xf8000710" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_04_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf8000710" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_05_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf8000714" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_05_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf8000714" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_05_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled
Pull-up disabled by default as this pin is used for mode[3]</desc>
<sw_param offset="0xf8000714" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_05_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf8000714" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_05_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf8000714" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_05_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0)
0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0)
1= Not Used
2= Not Used
3= Not Used
4= Not Used
5= Not Used
6= Not Used
7= Not Used</desc>
<sw_param offset="0xf8000714" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_05_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data)
= sram_nor, Output, smc_sram_data_out[2]- (SRAM Data)
2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus)
= nand, Output, smc_nand_data_out[0]- (NAND Data Bus)
3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf8000714" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_05_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= trace_data, Output, tracedq[11]- (Trace Port Databus)</desc>
<sw_param offset="0xf8000714" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_05_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= qspi, Input, qspi_mi3- (QSPI Databus)
1= qspi, Output, qspi_mo3- (QSPI Databus)</desc>
<sw_param offset="0xf8000714" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_05_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf8000714" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_06_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf8000718" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_06_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf8000718" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_06_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled
Pull-up disabled by default as this pin is used for mode[4]</desc>
<sw_param offset="0xf8000718" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_06_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf8000718" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_06_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf8000718" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_06_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0)
0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0)
1= Not Used
2= Not Used
3= Not Used
4= Not Used
5= Not Used
6= Not Used
7= Not Used</desc>
<sw_param offset="0xf8000718" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_06_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data)
= sram_nor, Output, smc_sram_data_out[3]- (SRAM Data)
2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus)
= nand, Output, smc_nand_data_out[1]- (NAND Data Bus)
3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf8000718" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_06_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= trace_data, Output, tracedq[12]- (Trace Port Databus)</desc>
<sw_param offset="0xf8000718" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_06_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= qspi, Output, qspi_sclk_out- (QSPI Clock)</desc>
<sw_param offset="0xf8000718" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_06_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf8000718" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_07_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf800071c" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_07_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf800071c" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_07_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled
Pull-up disabled by default as this pin is used for vcfg[0]</desc>
<sw_param offset="0xf800071c" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_07_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf800071c" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_07_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf800071c" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_07_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0)
1= Not Used
2= Not Used
3= Not Used
4= Not Used
5= Not Used
6= Not Used
7= Not Used</desc>
<sw_param offset="0xf800071c" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_07_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Output, smc_sram_oe_b- (SRAM Output enable)
2= nand, Output, smc_nand_cle- (NAND Command Latch Enable)
3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf800071c" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_07_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= trace_data, Output, tracedq[13]- (Trace Port Databus)</desc>
<sw_param offset="0xf800071c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_07_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= Not Used</desc>
<sw_param offset="0xf800071c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_07_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf800071c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_08_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf8000720" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_08_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf8000720" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_08_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled
Pull-up disabled by default as this pin is used for vcfg[1]</desc>
<sw_param offset="0xf8000720" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_08_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf8000720" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_08_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf8000720" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_08_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0)
1= can1, Output, can1_phy_tx- (Can TX signal)
2= Not Used
3= Not Used
4= Not Used
5= Not Used
6= Not Used
7= ua1, Output, ua1_txd- (UART transmitter serial output)</desc>
<sw_param offset="0xf8000720" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_08_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable)
2= nand, Output, smc_nand_re_b- (NAND Read Enable)
3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf8000720" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_08_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= trace_data, Output, tracedq[14]- (Trace Port Databus)</desc>
<sw_param offset="0xf8000720" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_08_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)</desc>
<sw_param offset="0xf8000720" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_08_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf8000720" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_09_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf8000724" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_09_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf8000724" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_09_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf8000724" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_09_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf8000724" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_09_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf8000724" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_09_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0)
0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0)
1= can1, Input, can1_phy_rx- (Can RX signal)
2= Not Used
3= Not Used
4= Not Used
5= Not Used
6= Not Used
7= ua1, Input, ua1_rxd- (UART receiver serial input)</desc>
<sw_param offset="0xf8000724" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_09_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Input, smc_sram_data_in[6]- (SRAM Data)
= sram_nor, Output, smc_sram_data_out[6]- (SRAM Data)
2= nand, Input, smc_nand_data_in[4]- (NAND Data Bus)
= nand, Output, smc_nand_data_out[4]- (NAND Data Bus)
3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf8000724" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_09_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= trace_data, Output, tracedq[15]- (Trace Port Databus)</desc>
<sw_param offset="0xf8000724" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_09_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)</desc>
<sw_param offset="0xf8000724" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_09_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf8000724" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_10_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf8000728" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_10_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf8000728" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_10_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf8000728" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_10_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf8000728" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_10_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf8000728" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_10_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0)
0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0)
1= can0, Input, can0_phy_rx- (Can RX signal)
2= i2c0, Input, i2c0_scl_input- (SCL signal)
2= i2c0, Output, i2c0_scl_out- (SCL signal)
3= Not Used
4= sd1, Input, sd1_data_in[0]- (4-bit Data bus)
4= sd1, Output, sd1_data_out[0]- (4-bit Data bus)
5= spi1, Output, spi1_mo- (MOSI signal)
5= spi1, Input, spi1_si- (MOSI signal)
6= Not Used
7= ua0, Input, ua0_rxd- (UART receiver serial input)</desc>
<sw_param offset="0xf8000728" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_10_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data)
= sram_nor, Output, smc_sram_data_out[7]- (SRAM Data)
2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus)
= nand, Output, smc_nand_data_out[5]- (NAND Data Bus)
3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf8000728" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_10_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= trace_data, Output, tracedq[2]- (Trace Port Databus)</desc>
<sw_param offset="0xf8000728" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_10_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus)
1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus)</desc>
<sw_param offset="0xf8000728" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_10_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf8000728" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_11_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf800072c" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_11_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf800072c" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_11_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf800072c" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_11_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf800072c" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_11_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf800072c" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_11_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0)
0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0)
1= can0, Output, can0_phy_tx- (Can TX signal)
2= i2c0, Input, i2c0_sda_input- (SDA signal)
2= i2c0, Output, i2c0_sda_out- (SDA signal)
3= Not Used
4= sd1, Input, sd1_cmd_in- (Command Indicator)
4= sd1, Output, sd1_cmd_out- (Command Indicator)
5= spi1, Input, spi1_mi- (MISO signal)
5= spi1, Output, spi1_so- (MISO signal)
6= Not Used
7= ua0, Output, ua0_txd- (UART transmitter serial output)</desc>
<sw_param offset="0xf800072c" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_11_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data)
= sram_nor, Output, smc_sram_data_out[4]- (SRAM Data)
2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus)
= nand, Output, smc_nand_data_out[6]- (NAND Data Bus)
3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf800072c" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_11_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= trace_data, Output, tracedq[3]- (Trace Port Databus)</desc>
<sw_param offset="0xf800072c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_11_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus)
1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus)</desc>
<sw_param offset="0xf800072c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_11_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf800072c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_12_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf8000730" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_12_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf8000730" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_12_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf8000730" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_12_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf8000730" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_12_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf8000730" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_12_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0)
0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0)
1= can1, Output, can1_phy_tx- (Can TX signal)
2= i2c1, Input, i2c1_scl_input- (SCL signal)
2= i2c1, Output, i2c1_scl_out- (SCL signal)
3= Not Used
4= sd1, Input, sd1_clk_in- (SDSDIO clock)
4= sd1, Output, sd1_clk_out- (SDSDIO clock)
5= spi1, Input, spi1_sclk_in- (SPI Clock)
5= spi1, Output, spi1_sclk_out- (SPI Clock)
6= Not Used
7= ua1, Output, ua1_txd- (UART transmitter serial output)</desc>
<sw_param offset="0xf8000730" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_12_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Input, smc_sram_wait- (SRAM Wait State indicator)
2= nand, Input, smc_nand_data_in[7]- (NAND Data Bus)
= nand, Output, smc_nand_data_out[7]- (NAND Data Bus)
3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf8000730" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_12_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= trace_ctl, Output, traceclk- (Trace Port Clock)</desc>
<sw_param offset="0xf8000730" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_12_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus)
1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper Databus)</desc>
<sw_param offset="0xf8000730" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_12_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf8000730" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_13_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf8000734" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_13_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf8000734" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_13_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf8000734" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_13_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf8000734" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_13_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf8000734" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_13_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0)
0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0)
1= can1, Input, can1_phy_rx- (Can RX signal)
2= i2c1, Input, i2c1_sda_input- (SDA signal)
2= i2c1, Output, i2c1_sda_out- (SDA signal)
3= Not Used
4= sd1, Input, sd1_data_in[1]- (4-bit Data bus)
4= sd1, Output, sd1_data_out[1]- (4-bit Data bus)
5= spi1, Input, spi1_n_ss_in- (SPI Master Selects)
5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects)
6= Not Used
7= ua1, Input, ua1_rxd- (UART receiver serial input)</desc>
<sw_param offset="0xf8000734" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_13_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Input, smc_sram_data_in[5]- (SRAM Data)
= sram_nor, Output, smc_sram_data_out[5]- (SRAM Data)
2= nand, Input, smc_nand_data_in[3]- (NAND Data Bus)
= nand, Output, smc_nand_data_out[3]- (NAND Data Bus)
3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf8000734" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_13_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= trace_ctl, Output, tracectl- (Trace Port Control Signal)</desc>
<sw_param offset="0xf8000734" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_13_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus)
1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper Databus)</desc>
<sw_param offset="0xf8000734" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_13_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf8000734" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_14_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf8000738" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_14_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf8000738" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_14_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf8000738" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_14_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf8000738" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_14_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf8000738" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_14_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0)
0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0)
1= can0, Input, can0_phy_rx- (Can RX signal)
2= i2c0, Input, i2c0_scl_input- (SCL signal)
2= i2c0, Output, i2c0_scl_out- (SCL signal)
3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock)
4= sd1, Input, sd1_data_in[2]- (4-bit Data bus)
4= sd1, Output, sd1_data_out[2]- (4-bit Data bus)
5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects)
6= Not Used
7= ua0, Input, ua0_rxd- (UART receiver serial input)</desc>
<sw_param offset="0xf8000738" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_14_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock)
2= nand, Input, smc_nand_busy- (NAND Busy)
3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf8000738" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_14_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= trace_data, Output, tracedq[0]- (Trace Port Databus)</desc>
<sw_param offset="0xf8000738" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_14_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= Not Used</desc>
<sw_param offset="0xf8000738" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_14_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf8000738" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_15_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf800073c" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_15_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf800073c" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_15_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf800073c" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_15_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf800073c" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_15_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf800073c" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_15_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0)
0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0)
1= can0, Output, can0_phy_tx- (Can TX signal)
2= i2c0, Input, i2c0_sda_input- (SDA signal)
2= i2c0, Output, i2c0_sda_out- (SDA signal)
3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock)
4= sd1, Input, sd1_data_in[3]- (4-bit Data bus)
4= sd1, Output, sd1_data_out[3]- (4-bit Data bus)
5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects)
6= Not Used
7= ua0, Output, ua0_txd- (UART transmitter serial output)</desc>
<sw_param offset="0xf800073c" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_15_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Output, smc_sram_add[0]- (SRAM Address)
2= Not Used
3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf800073c" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_15_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= trace_data, Output, tracedq[1]- (Trace Port Databus)</desc>
<sw_param offset="0xf800073c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_15_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= Not Used</desc>
<sw_param offset="0xf800073c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_15_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf800073c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_16_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf8000740" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_16_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf8000740" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_16_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf8000740" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_16_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf8000740" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_16_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf8000740" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_16_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0)
0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0)
1= can1, Output, can1_phy_tx- (Can TX signal)
2= i2c1, Input, i2c1_scl_input- (SCL signal)
2= i2c1, Output, i2c1_scl_out- (SCL signal)
3= Not Used
4= sd0, Input, sd0_clk_in- (SDSDIO clock)
4= sd0, Output, sd0_clk_out- (SDSDIO clock)
5= spi0, Input, spi0_sclk_in- (SPI Clock)
5= spi0, Output, spi0_sclk_out- (SPI Clock)
6= ttc1, Output, ttc1_wave_out- (TTC waveform clock)
7= ua1, Output, ua1_txd- (UART transmitter serial output)</desc>
<sw_param offset="0xf8000740" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_16_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Output, smc_sram_add[1]- (SRAM Address)
2= nand, Input, smc_nand_data_in[8]- (NAND Data Bus)
= nand, Output, smc_nand_data_out[8]- (NAND Data Bus)
3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf8000740" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_16_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= trace_data, Output, tracedq[4]- (Trace Port Databus)</desc>
<sw_param offset="0xf8000740" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_16_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)</desc>
<sw_param offset="0xf8000740" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_16_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf8000740" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_17_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf8000744" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_17_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf8000744" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_17_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf8000744" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_17_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf8000744" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_17_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf8000744" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_17_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0)
0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0)
1= can1, Input, can1_phy_rx- (Can RX signal)
2= i2c1, Input, i2c1_sda_input- (SDA signal)
2= i2c1, Output, i2c1_sda_out- (SDA signal)
3= Not Used
4= sd0, Input, sd0_cmd_in- (Command Indicator)
4= sd0, Output, sd0_cmd_out- (Command Indicator)
5= spi0, Input, spi0_mi- (MISO signal)
5= spi0, Output, spi0_so- (MISO signal)
6= ttc1, Input, ttc1_clk_in- (TTC input clock)
7= ua1, Input, ua1_rxd- (UART receiver serial input)</desc>
<sw_param offset="0xf8000744" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_17_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Output, smc_sram_add[2]- (SRAM Address)
2= nand, Input, smc_nand_data_in[9]- (NAND Data Bus)
= nand, Output, smc_nand_data_out[9]- (NAND Data Bus)
3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf8000744" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_17_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= trace_data, Output, tracedq[5]- (Trace Port Databus)</desc>
<sw_param offset="0xf8000744" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_17_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)</desc>
<sw_param offset="0xf8000744" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_17_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf8000744" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_18_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf8000748" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_18_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf8000748" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_18_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf8000748" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_18_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf8000748" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_18_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf8000748" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_18_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0)
0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0)
1= can0, Input, can0_phy_rx- (Can RX signal)
2= i2c0, Input, i2c0_scl_input- (SCL signal)
2= i2c0, Output, i2c0_scl_out- (SCL signal)
3= Not Used
4= sd0, Input, sd0_data_in[0]- (4-bit Data bus)
4= sd0, Output, sd0_data_out[0]- (4-bit Data bus)
5= spi0, Input, spi0_n_ss_in- (SPI Master Selects)
5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects)
6= ttc0, Output, ttc0_wave_out- (TTC waveform clock)
7= ua0, Input, ua0_rxd- (UART receiver serial input)</desc>
<sw_param offset="0xf8000748" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_18_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Output, smc_sram_add[3]- (SRAM Address)
2= nand, Input, smc_nand_data_in[10]- (NAND Data Bus)
= nand, Output, smc_nand_data_out[10]- (NAND Data Bus)
3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf8000748" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_18_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= trace_data, Output, tracedq[6]- (Trace Port Databus)</desc>
<sw_param offset="0xf8000748" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_18_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)</desc>
<sw_param offset="0xf8000748" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_18_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf8000748" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_19_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf800074c" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_19_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf800074c" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_19_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf800074c" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_19_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf800074c" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_19_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf800074c" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_19_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0)
0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0)
1= can0, Output, can0_phy_tx- (Can TX signal)
2= i2c0, Input, i2c0_sda_input- (SDA signal)
2= i2c0, Output, i2c0_sda_out- (SDA signal)
3= Not Used
4= sd0, Input, sd0_data_in[1]- (4-bit Data bus)
4= sd0, Output, sd0_data_out[1]- (4-bit Data bus)
5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects)
6= ttc0, Input, ttc0_clk_in- (TTC input clock)
7= ua0, Output, ua0_txd- (UART transmitter serial output)</desc>
<sw_param offset="0xf800074c" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_19_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Output, smc_sram_add[4]- (SRAM Address)
2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus)
= nand, Output, smc_nand_data_out[11]- (NAND Data Bus)
3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf800074c" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_19_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= trace_data, Output, tracedq[7]- (Trace Port Databus)</desc>
<sw_param offset="0xf800074c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_19_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)</desc>
<sw_param offset="0xf800074c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_19_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf800074c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_20_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf8000750" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_20_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf8000750" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_20_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf8000750" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_20_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf8000750" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_20_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf8000750" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_20_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0)
0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0)
1= can1, Output, can1_phy_tx- (Can TX signal)
2= i2c1, Input, i2c1_scl_input- (SCL signal)
2= i2c1, Output, i2c1_scl_out- (SCL signal)
3= Not Used
4= sd0, Input, sd0_data_in[2]- (4-bit Data bus)
4= sd0, Output, sd0_data_out[2]- (4-bit Data bus)
5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects)
6= Not Used
7= ua1, Output, ua1_txd- (UART transmitter serial output)</desc>
<sw_param offset="0xf8000750" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_20_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Output, smc_sram_add[5]- (SRAM Address)
2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus)
= nand, Output, smc_nand_data_out[12]- (NAND Data Bus)
3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf8000750" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_20_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= Not Used</desc>
<sw_param offset="0xf8000750" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_20_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)</desc>
<sw_param offset="0xf8000750" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_20_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf8000750" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_21_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf8000754" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_21_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf8000754" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_21_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf8000754" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_21_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf8000754" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_21_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf8000754" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_21_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0)
0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0)
1= can1, Input, can1_phy_rx- (Can RX signal)
2= i2c1, Input, i2c1_sda_input- (SDA signal)
2= i2c1, Output, i2c1_sda_out- (SDA signal)
3= Not Used
4= sd0, Input, sd0_data_in[3]- (4-bit Data bus)
4= sd0, Output, sd0_data_out[3]- (4-bit Data bus)
5= spi0, Output, spi0_mo- (MOSI signal)
5= spi0, Input, spi0_si- (MOSI signal)
6= Not Used
7= ua1, Input, ua1_rxd- (UART receiver serial input)</desc>
<sw_param offset="0xf8000754" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_21_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Output, smc_sram_add[6]- (SRAM Address)
2= nand, Input, smc_nand_data_in[13]- (NAND Data Bus)
= nand, Output, smc_nand_data_out[13]- (NAND Data Bus)
3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf8000754" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_21_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= Not Used</desc>
<sw_param offset="0xf8000754" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_21_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)</desc>
<sw_param offset="0xf8000754" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_21_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf8000754" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_22_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf8000758" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_22_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf8000758" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_22_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf8000758" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_22_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf8000758" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_22_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf8000758" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_22_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0)
0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0)
1= can0, Input, can0_phy_rx- (Can RX signal)
2= i2c0, Input, i2c0_scl_input- (SCL signal)
2= i2c0, Output, i2c0_scl_out- (SCL signal)
3= Not Used
4= sd1, Input, sd1_data_in[0]- (4-bit Data bus)
4= sd1, Output, sd1_data_out[0]- (4-bit Data bus)
5= spi1, Output, spi1_mo- (MOSI signal)
5= spi1, Input, spi1_si- (MOSI signal)
6= Not Used
7= ua0, Input, ua0_rxd- (UART receiver serial input)</desc>
<sw_param offset="0xf8000758" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_22_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Output, smc_sram_add[7]- (SRAM Address)
2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus)
= nand, Output, smc_nand_data_out[14]- (NAND Data Bus)
3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf8000758" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_22_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= trace_data, Output, tracedq[2]- (Trace Port Databus)</desc>
<sw_param offset="0xf8000758" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_22_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)</desc>
<sw_param offset="0xf8000758" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_22_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf8000758" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_23_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf800075c" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_23_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf800075c" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_23_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf800075c" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_23_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf800075c" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_23_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf800075c" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_23_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0)
0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0)
1= can0, Output, can0_phy_tx- (Can TX signal)
2= i2c0, Input, i2c0_sda_input- (SDA signal)
2= i2c0, Output, i2c0_sda_out- (SDA signal)
3= Not Used
4= sd1, Input, sd1_cmd_in- (Command Indicator)
4= sd1, Output, sd1_cmd_out- (Command Indicator)
5= spi1, Input, spi1_mi- (MISO signal)
5= spi1, Output, spi1_so- (MISO signal)
6= Not Used
7= ua0, Output, ua0_txd- (UART transmitter serial output)</desc>
<sw_param offset="0xf800075c" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_23_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Output, smc_sram_add[8]- (SRAM Address)
2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus)
= nand, Output, smc_nand_data_out[15]- (NAND Data Bus)
3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf800075c" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_23_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= trace_data, Output, tracedq[3]- (Trace Port Databus)</desc>
<sw_param offset="0xf800075c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_23_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)</desc>
<sw_param offset="0xf800075c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_23_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf800075c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_24_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf8000760" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_24_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf8000760" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_24_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf8000760" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_24_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf8000760" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_24_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf8000760" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_24_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0)
0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0)
1= can1, Output, can1_phy_tx- (Can TX signal)
2= i2c1, Input, i2c1_scl_input- (SCL signal)
2= i2c1, Output, i2c1_scl_out- (SCL signal)
3= Not Used
4= sd1, Input, sd1_clk_in- (SDSDIO clock)
4= sd1, Output, sd1_clk_out- (SDSDIO clock)
5= spi1, Input, spi1_sclk_in- (SPI Clock)
5= spi1, Output, spi1_sclk_out- (SPI Clock)
6= Not Used
7= ua1, Output, ua1_txd- (UART transmitter serial output)</desc>
<sw_param offset="0xf8000760" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_24_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Output, smc_sram_add[9]- (SRAM Address)
2= Not Used
3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf8000760" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_24_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= trace_ctl, Output, traceclk- (Trace Port Clock)</desc>
<sw_param offset="0xf8000760" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_24_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)</desc>
<sw_param offset="0xf8000760" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_24_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf8000760" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_25_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf8000764" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_25_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf8000764" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_25_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf8000764" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_25_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf8000764" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_25_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf8000764" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_25_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0)
0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0)
1= can1, Input, can1_phy_rx- (Can RX signal)
2= i2c1, Input, i2c1_sda_input- (SDA signal)
2= i2c1, Output, i2c1_sda_out- (SDA signal)
3= Not Used
4= sd1, Input, sd1_data_in[1]- (4-bit Data bus)
4= sd1, Output, sd1_data_out[1]- (4-bit Data bus)
5= spi1, Input, spi1_n_ss_in- (SPI Master Selects)
5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects)
6= Not Used
7= ua1, Input, ua1_rxd- (UART receiver serial input)</desc>
<sw_param offset="0xf8000764" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_25_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Output, smc_sram_add[10]- (SRAM Address)
2= Not Used
3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf8000764" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_25_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= trace_ctl, Output, tracectl- (Trace Port Control Signal)</desc>
<sw_param offset="0xf8000764" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_25_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)</desc>
<sw_param offset="0xf8000764" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_25_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf8000764" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_26_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf8000768" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_26_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf8000768" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_26_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf8000768" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_26_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf8000768" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_26_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf8000768" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_26_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0)
0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0)
1= can0, Input, can0_phy_rx- (Can RX signal)
2= i2c0, Input, i2c0_scl_input- (SCL signal)
2= i2c0, Output, i2c0_scl_out- (SCL signal)
3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock)
4= sd1, Input, sd1_data_in[2]- (4-bit Data bus)
4= sd1, Output, sd1_data_out[2]- (4-bit Data bus)
5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects)
6= Not Used
7= ua0, Input, ua0_rxd- (UART receiver serial input)</desc>
<sw_param offset="0xf8000768" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_26_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Output, smc_sram_add[11]- (SRAM Address)
2= Not Used
3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf8000768" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_26_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= trace_data, Output, tracedq[0]- (Trace Port Databus)</desc>
<sw_param offset="0xf8000768" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_26_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)</desc>
<sw_param offset="0xf8000768" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_26_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf8000768" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_27_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf800076c" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_27_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf800076c" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_27_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf800076c" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_27_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf800076c" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_27_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf800076c" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_27_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0)
0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0)
1= can0, Output, can0_phy_tx- (Can TX signal)
2= i2c0, Input, i2c0_sda_input- (SDA signal)
2= i2c0, Output, i2c0_sda_out- (SDA signal)
3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock)
4= sd1, Input, sd1_data_in[3]- (4-bit Data bus)
4= sd1, Output, sd1_data_out[3]- (4-bit Data bus)
5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects)
6= Not Used
7= ua0, Output, ua0_txd- (UART transmitter serial output)</desc>
<sw_param offset="0xf800076c" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_27_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Output, smc_sram_add[12]- (SRAM Address)
2= Not Used
3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf800076c" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_27_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= trace_data, Output, tracedq[1]- (Trace Port Databus)</desc>
<sw_param offset="0xf800076c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_27_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )</desc>
<sw_param offset="0xf800076c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_27_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf800076c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_28_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf8000770" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_28_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf8000770" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_28_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf8000770" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_28_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf8000770" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_28_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf8000770" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_28_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Input, gpio_0_pin_in[28]- (GPIO bank 0)
0= gpio0, Output, gpio_0_pin_out[28]- (GPIO bank 0)
1= can1, Output, can1_phy_tx- (Can TX signal)
2= i2c1, Input, i2c1_scl_input- (SCL signal)
2= i2c1, Output, i2c1_scl_out- (SCL signal)
3= Not Used
4= sd0, Input, sd0_clk_in- (SDSDIO clock)
4= sd0, Output, sd0_clk_out- (SDSDIO clock)
5= spi0, Input, spi0_sclk_in- (SPI Clock)
5= spi0, Output, spi0_sclk_out- (SPI Clock)
6= ttc1, Output, ttc1_wave_out- (TTC waveform clock)
7= ua1, Output, ua1_txd- (UART transmitter serial output)</desc>
<sw_param offset="0xf8000770" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_28_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Output, smc_sram_add[13]- (SRAM Address)
2= Not Used
3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf8000770" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_28_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus)
1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus)</desc>
<sw_param offset="0xf8000770" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_28_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)</desc>
<sw_param offset="0xf8000770" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_28_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf8000770" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_29_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf8000774" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_29_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf8000774" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_29_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf8000774" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_29_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf8000774" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_29_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf8000774" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_29_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Input, gpio_0_pin_in[29]- (GPIO bank 0)
0= gpio0, Output, gpio_0_pin_out[29]- (GPIO bank 0)
1= can1, Input, can1_phy_rx- (Can RX signal)
2= i2c1, Input, i2c1_sda_input- (SDA signal)
2= i2c1, Output, i2c1_sda_out- (SDA signal)
3= Not Used
4= sd0, Input, sd0_cmd_in- (Command Indicator)
4= sd0, Output, sd0_cmd_out- (Command Indicator)
5= spi0, Input, spi0_mi- (MISO signal)
5= spi0, Output, spi0_so- (MISO signal)
6= ttc1, Input, ttc1_clk_in- (TTC input clock)
7= ua1, Input, ua1_rxd- (UART receiver serial input)</desc>
<sw_param offset="0xf8000774" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_29_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Output, smc_sram_add[14]- (SRAM Address)
2= Not Used
3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf8000774" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_29_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)</desc>
<sw_param offset="0xf8000774" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_29_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)</desc>
<sw_param offset="0xf8000774" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_29_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf8000774" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_30_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf8000778" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_30_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf8000778" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_30_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf8000778" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_30_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf8000778" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_30_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf8000778" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_30_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Input, gpio_0_pin_in[30]- (GPIO bank 0)
0= gpio0, Output, gpio_0_pin_out[30]- (GPIO bank 0)
1= can0, Input, can0_phy_rx- (Can RX signal)
2= i2c0, Input, i2c0_scl_input- (SCL signal)
2= i2c0, Output, i2c0_scl_out- (SCL signal)
3= Not Used
4= sd0, Input, sd0_data_in[0]- (4-bit Data bus)
4= sd0, Output, sd0_data_out[0]- (4-bit Data bus)
5= spi0, Input, spi0_n_ss_in- (SPI Master Selects)
5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects)
6= ttc0, Output, ttc0_wave_out- (TTC waveform clock)
7= ua0, Input, ua0_rxd- (UART receiver serial input)</desc>
<sw_param offset="0xf8000778" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_30_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Output, smc_sram_add[15]- (SRAM Address)
2= Not Used
3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf8000778" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_30_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)</desc>
<sw_param offset="0xf8000778" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_30_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)</desc>
<sw_param offset="0xf8000778" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_30_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf8000778" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_31_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf800077c" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_31_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf800077c" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_31_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf800077c" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_31_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf800077c" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_31_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf800077c" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_31_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio0, Input, gpio_0_pin_in[31]- (GPIO bank 0)
0= gpio0, Output, gpio_0_pin_out[31]- (GPIO bank 0)
1= can0, Output, can0_phy_tx- (Can TX signal)
2= i2c0, Input, i2c0_sda_input- (SDA signal)
2= i2c0, Output, i2c0_sda_out- (SDA signal)
3= Not Used
4= sd0, Input, sd0_data_in[1]- (4-bit Data bus)
4= sd0, Output, sd0_data_out[1]- (4-bit Data bus)
5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects)
6= ttc0, Input, ttc0_clk_in- (TTC input clock)
7= ua0, Output, ua0_txd- (UART transmitter serial output)</desc>
<sw_param offset="0xf800077c" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_31_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Output, smc_sram_add[16]- (SRAM Address)
2= Not Used
3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf800077c" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_31_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)</desc>
<sw_param offset="0xf800077c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_31_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)</desc>
<sw_param offset="0xf800077c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_31_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf800077c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_32_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf8000780" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_32_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf8000780" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_32_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf8000780" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_32_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf8000780" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_32_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf8000780" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_32_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1)
0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1)
1= can1, Output, can1_phy_tx- (Can TX signal)
2= i2c1, Input, i2c1_scl_input- (SCL signal)
2= i2c1, Output, i2c1_scl_out- (SCL signal)
3= Not Used
4= sd0, Input, sd0_data_in[2]- (4-bit Data bus)
4= sd0, Output, sd0_data_out[2]- (4-bit Data bus)
5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects)
6= Not Used
7= ua1, Output, ua1_txd- (UART transmitter serial output)</desc>
<sw_param offset="0xf8000780" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_32_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Output, smc_sram_add[17]- (SRAM Address)
2= Not Used
3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf8000780" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_32_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus)
1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus)</desc>
<sw_param offset="0xf8000780" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_32_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)</desc>
<sw_param offset="0xf8000780" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_32_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf8000780" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_33_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf8000784" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_33_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf8000784" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_33_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf8000784" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_33_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf8000784" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_33_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf8000784" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_33_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1)
0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1)
1= can1, Input, can1_phy_rx- (Can RX signal)
2= i2c1, Input, i2c1_sda_input- (SDA signal)
2= i2c1, Output, i2c1_sda_out- (SDA signal)
3= Not Used
4= sd0, Input, sd0_data_in[3]- (4-bit Data bus)
4= sd0, Output, sd0_data_out[3]- (4-bit Data bus)
5= spi0, Output, spi0_mo- (MOSI signal)
5= spi0, Input, spi0_si- (MOSI signal)
6= Not Used
7= ua1, Input, ua1_rxd- (UART receiver serial input)</desc>
<sw_param offset="0xf8000784" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_33_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Output, smc_sram_add[18]- (SRAM Address)
2= Not Used
3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf8000784" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_33_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus)
1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus)</desc>
<sw_param offset="0xf8000784" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_33_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)</desc>
<sw_param offset="0xf8000784" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_33_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf8000784" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_34_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf8000788" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_34_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf8000788" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_34_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf8000788" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_34_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf8000788" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_34_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf8000788" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_34_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1)
0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1)
1= can0, Input, can0_phy_rx- (Can RX signal)
2= i2c0, Input, i2c0_scl_input- (SCL signal)
2= i2c0, Output, i2c0_scl_out- (SCL signal)
3= Not Used
4= sd1, Input, sd1_data_in[0]- (4-bit Data bus)
4= sd1, Output, sd1_data_out[0]- (4-bit Data bus)
5= spi1, Output, spi1_mo- (MOSI signal)
5= spi1, Input, spi1_si- (MOSI signal)
6= Not Used
7= ua0, Input, ua0_rxd- (UART receiver serial input)</desc>
<sw_param offset="0xf8000788" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_34_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Output, smc_sram_add[19]- (SRAM Address)
2= Not Used
3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf8000788" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_34_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus)
1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus)</desc>
<sw_param offset="0xf8000788" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_34_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)</desc>
<sw_param offset="0xf8000788" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_34_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf8000788" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_35_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf800078c" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_35_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf800078c" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_35_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf800078c" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_35_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf800078c" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_35_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf800078c" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_35_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1)
0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1)
1= can0, Output, can0_phy_tx- (Can TX signal)
2= i2c0, Input, i2c0_sda_input- (SDA signal)
2= i2c0, Output, i2c0_sda_out- (SDA signal)
3= Not Used
4= sd1, Input, sd1_cmd_in- (Command Indicator)
4= sd1, Output, sd1_cmd_out- (Command Indicator)
5= spi1, Input, spi1_mi- (MISO signal)
5= spi1, Output, spi1_so- (MISO signal)
6= Not Used
7= ua0, Output, ua0_txd- (UART transmitter serial output)</desc>
<sw_param offset="0xf800078c" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_35_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Output, smc_sram_add[20]- (SRAM Address)
2= Not Used
3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf800078c" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_35_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus)
1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus)</desc>
<sw_param offset="0xf800078c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_35_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)</desc>
<sw_param offset="0xf800078c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_35_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf800078c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_36_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf8000790" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_36_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf8000790" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_36_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf8000790" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_36_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf8000790" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_36_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf8000790" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_36_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1)
0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1)
1= can1, Output, can1_phy_tx- (Can TX signal)
2= i2c1, Input, i2c1_scl_input- (SCL signal)
2= i2c1, Output, i2c1_scl_out- (SCL signal)
3= Not Used
4= sd1, Input, sd1_clk_in- (SDSDIO clock)
4= sd1, Output, sd1_clk_out- (SDSDIO clock)
5= spi1, Input, spi1_sclk_in- (SPI Clock)
5= spi1, Output, spi1_sclk_out- (SPI Clock)
6= Not Used
7= ua1, Output, ua1_txd- (UART transmitter serial output)</desc>
<sw_param offset="0xf8000790" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_36_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Output, smc_sram_add[21]- (SRAM Address)
2= Not Used
3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf8000790" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_36_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= usb0, Input, usb0_xcvr_clk_in- (ULPI clock)
1= usb0, Output, usb0_xcvr_clk_out- (ULPI clock)</desc>
<sw_param offset="0xf8000790" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_36_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)</desc>
<sw_param offset="0xf8000790" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_36_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf8000790" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_37_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf8000794" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_37_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf8000794" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_37_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf8000794" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_37_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf8000794" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_37_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf8000794" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_37_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1)
0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1)
1= can1, Input, can1_phy_rx- (Can RX signal)
2= i2c1, Input, i2c1_sda_input- (SDA signal)
2= i2c1, Output, i2c1_sda_out- (SDA signal)
3= Not Used
4= sd1, Input, sd1_data_in[1]- (4-bit Data bus)
4= sd1, Output, sd1_data_out[1]- (4-bit Data bus)
5= spi1, Input, spi1_n_ss_in- (SPI Master Selects)
5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects)
6= Not Used
7= ua1, Input, ua1_rxd- (UART receiver serial input)</desc>
<sw_param offset="0xf8000794" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_37_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Output, smc_sram_add[22]- (SRAM Address)
2= Not Used
3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf8000794" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_37_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus)
1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus)</desc>
<sw_param offset="0xf8000794" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_37_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)</desc>
<sw_param offset="0xf8000794" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_37_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf8000794" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_38_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf8000798" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_38_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf8000798" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_38_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf8000798" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_38_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf8000798" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_38_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf8000798" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_38_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1)
0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1)
1= can0, Input, can0_phy_rx- (Can RX signal)
2= i2c0, Input, i2c0_scl_input- (SCL signal)
2= i2c0, Output, i2c0_scl_out- (SCL signal)
3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock)
4= sd1, Input, sd1_data_in[2]- (4-bit Data bus)
4= sd1, Output, sd1_data_out[2]- (4-bit Data bus)
5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects)
6= Not Used
7= ua0, Input, ua0_rxd- (UART receiver serial input)</desc>
<sw_param offset="0xf8000798" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_38_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Output, smc_sram_add[23]- (SRAM Address)
2= Not Used
3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf8000798" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_38_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus)
1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus)</desc>
<sw_param offset="0xf8000798" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_38_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)</desc>
<sw_param offset="0xf8000798" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_38_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf8000798" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_39_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf800079c" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_39_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf800079c" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_39_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf800079c" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_39_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf800079c" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_39_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf800079c" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_39_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1)
0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1)
1= can0, Output, can0_phy_tx- (Can TX signal)
2= i2c0, Input, i2c0_sda_input- (SDA signal)
2= i2c0, Output, i2c0_sda_out- (SDA signal)
3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock)
4= sd1, Input, sd1_data_in[3]- (4-bit Data bus)
4= sd1, Output, sd1_data_out[3]- (4-bit Data bus)
5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects)
6= Not Used
7= ua0, Output, ua0_txd- (UART transmitter serial output)</desc>
<sw_param offset="0xf800079c" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_39_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= sram_nor, Output, smc_sram_add[24]- (SRAM Address)
2= Not Used
3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf800079c" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_39_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus)
1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus)</desc>
<sw_param offset="0xf800079c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_39_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )</desc>
<sw_param offset="0xf800079c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_39_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf800079c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_40_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf80007a0" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_40_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf80007a0" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_40_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf80007a0" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_40_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf80007a0" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_40_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf80007a0" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_40_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1)
0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1)
1= can1, Output, can1_phy_tx- (Can TX signal)
2= i2c1, Input, i2c1_scl_input- (SCL signal)
2= i2c1, Output, i2c1_scl_out- (SCL signal)
3= Not Used
4= sd0, Input, sd0_clk_in- (SDSDIO clock)
4= sd0, Output, sd0_clk_out- (SDSDIO clock)
5= spi0, Input, spi0_sclk_in- (SPI Clock)
5= spi0, Output, spi0_sclk_out- (SPI Clock)
6= ttc1, Output, ttc1_wave_out- (TTC waveform clock)
7= ua1, Output, ua1_txd- (UART transmitter serial output)</desc>
<sw_param offset="0xf80007a0" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_40_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= Not Used
2= Not Used
3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf80007a0" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_40_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus)
1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus)</desc>
<sw_param offset="0xf80007a0" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_40_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= Not Used</desc>
<sw_param offset="0xf80007a0" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_40_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf80007a0" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_41_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf80007a4" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_41_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf80007a4" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_41_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf80007a4" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_41_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf80007a4" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_41_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf80007a4" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_41_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1)
0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1)
1= can1, Input, can1_phy_rx- (Can RX signal)
2= i2c1, Input, i2c1_sda_input- (SDA signal)
2= i2c1, Output, i2c1_sda_out- (SDA signal)
3= Not Used
4= sd0, Input, sd0_cmd_in- (Command Indicator)
4= sd0, Output, sd0_cmd_out- (Command Indicator)
5= spi0, Input, spi0_mi- (MISO signal)
5= spi0, Output, spi0_so- (MISO signal)
6= ttc1, Input, ttc1_clk_in- (TTC input clock)
7= ua1, Input, ua1_rxd- (UART receiver serial input)</desc>
<sw_param offset="0xf80007a4" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_41_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= Not Used
2= Not Used
3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf80007a4" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_41_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)</desc>
<sw_param offset="0xf80007a4" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_41_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= Not Used</desc>
<sw_param offset="0xf80007a4" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_41_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf80007a4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_42_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf80007a8" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_42_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf80007a8" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_42_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf80007a8" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_42_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf80007a8" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_42_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf80007a8" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_42_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1)
0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1)
1= can0, Input, can0_phy_rx- (Can RX signal)
2= i2c0, Input, i2c0_scl_input- (SCL signal)
2= i2c0, Output, i2c0_scl_out- (SCL signal)
3= Not Used
4= sd0, Input, sd0_data_in[0]- (4-bit Data bus)
4= sd0, Output, sd0_data_out[0]- (4-bit Data bus)
5= spi0, Input, spi0_n_ss_in- (SPI Master Selects)
5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects)
6= ttc0, Output, ttc0_wave_out- (TTC waveform clock)
7= ua0, Input, ua0_rxd- (UART receiver serial input)</desc>
<sw_param offset="0xf80007a8" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_42_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= Not Used
2= Not Used
3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf80007a8" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_42_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)</desc>
<sw_param offset="0xf80007a8" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_42_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= Not Used</desc>
<sw_param offset="0xf80007a8" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_42_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf80007a8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_43_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf80007ac" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_43_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf80007ac" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_43_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf80007ac" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_43_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf80007ac" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_43_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf80007ac" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_43_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1)
0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1)
1= can0, Output, can0_phy_tx- (Can TX signal)
2= i2c0, Input, i2c0_sda_input- (SDA signal)
2= i2c0, Output, i2c0_sda_out- (SDA signal)
3= Not Used
4= sd0, Input, sd0_data_in[1]- (4-bit Data bus)
4= sd0, Output, sd0_data_out[1]- (4-bit Data bus)
5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects)
6= ttc0, Input, ttc0_clk_in- (TTC input clock)
7= ua0, Output, ua0_txd- (UART transmitter serial output)</desc>
<sw_param offset="0xf80007ac" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_43_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= Not Used
2= Not Used
3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf80007ac" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_43_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)</desc>
<sw_param offset="0xf80007ac" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_43_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= Not Used</desc>
<sw_param offset="0xf80007ac" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_43_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf80007ac" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_44_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf80007b0" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_44_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf80007b0" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_44_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf80007b0" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_44_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf80007b0" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_44_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf80007b0" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_44_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1)
0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1)
1= can1, Output, can1_phy_tx- (Can TX signal)
2= i2c1, Input, i2c1_scl_input- (SCL signal)
2= i2c1, Output, i2c1_scl_out- (SCL signal)
3= Not Used
4= sd0, Input, sd0_data_in[2]- (4-bit Data bus)
4= sd0, Output, sd0_data_out[2]- (4-bit Data bus)
5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects)
6= Not Used
7= ua1, Output, ua1_txd- (UART transmitter serial output)</desc>
<sw_param offset="0xf80007b0" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_44_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= Not Used
2= Not Used
3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf80007b0" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_44_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus)
1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus)</desc>
<sw_param offset="0xf80007b0" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_44_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= Not Used</desc>
<sw_param offset="0xf80007b0" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_44_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf80007b0" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_45_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf80007b4" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_45_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf80007b4" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_45_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf80007b4" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_45_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf80007b4" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_45_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf80007b4" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_45_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1)
0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1)
1= can1, Input, can1_phy_rx- (Can RX signal)
2= i2c1, Input, i2c1_sda_input- (SDA signal)
2= i2c1, Output, i2c1_sda_out- (SDA signal)
3= Not Used
4= sd0, Input, sd0_data_in[3]- (4-bit Data bus)
4= sd0, Output, sd0_data_out[3]- (4-bit Data bus)
5= spi0, Output, spi0_mo- (MOSI signal)
5= spi0, Input, spi0_si- (MOSI signal)
6= Not Used
7= ua1, Input, ua1_rxd- (UART receiver serial input)</desc>
<sw_param offset="0xf80007b4" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_45_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= Not Used
2= Not Used
3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf80007b4" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_45_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus)
1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus)</desc>
<sw_param offset="0xf80007b4" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_45_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= Not Used</desc>
<sw_param offset="0xf80007b4" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_45_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf80007b4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_46_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf80007b8" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_46_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf80007b8" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_46_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf80007b8" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_46_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf80007b8" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_46_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf80007b8" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_46_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1)
0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1)
1= can0, Input, can0_phy_rx- (Can RX signal)
2= i2c0, Input, i2c0_scl_input- (SCL signal)
2= i2c0, Output, i2c0_scl_out- (SCL signal)
3= Not Used
4= sd1, Input, sd1_data_in[0]- (4-bit Data bus)
4= sd1, Output, sd1_data_out[0]- (4-bit Data bus)
5= spi1, Output, spi1_mo- (MOSI signal)
5= spi1, Input, spi1_si- (MOSI signal)
6= Not Used
7= ua0, Input, ua0_rxd- (UART receiver serial input)</desc>
<sw_param offset="0xf80007b8" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_46_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= Not Used
2= Not Used
3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf80007b8" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_46_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus)
1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data bus)</desc>
<sw_param offset="0xf80007b8" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_46_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= Not Used</desc>
<sw_param offset="0xf80007b8" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_46_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf80007b8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_47_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf80007bc" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_47_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf80007bc" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_47_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf80007bc" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_47_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf80007bc" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_47_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf80007bc" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_47_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1)
0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1)
1= can0, Output, can0_phy_tx- (Can TX signal)
2= i2c0, Input, i2c0_sda_input- (SDA signal)
2= i2c0, Output, i2c0_sda_out- (SDA signal)
3= Not Used
4= sd1, Input, sd1_cmd_in- (Command Indicator)
4= sd1, Output, sd1_cmd_out- (Command Indicator)
5= spi1, Input, spi1_mi- (MISO signal)
5= spi1, Output, spi1_so- (MISO signal)
6= Not Used
7= ua0, Output, ua0_txd- (UART transmitter serial output)</desc>
<sw_param offset="0xf80007bc" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_47_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= Not Used
2= Not Used
3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf80007bc" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_47_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus)
1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data bus)</desc>
<sw_param offset="0xf80007bc" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_47_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= Not Used</desc>
<sw_param offset="0xf80007bc" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_47_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf80007bc" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_48_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf80007c0" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_48_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf80007c0" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_48_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf80007c0" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_48_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf80007c0" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_48_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf80007c0" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_48_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1)
0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1)
1= can1, Output, can1_phy_tx- (Can TX signal)
2= i2c1, Input, i2c1_scl_input- (SCL signal)
2= i2c1, Output, i2c1_scl_out- (SCL signal)
3= Not Used
4= sd1, Input, sd1_clk_in- (SDSDIO clock)
4= sd1, Output, sd1_clk_out- (SDSDIO clock)
5= spi1, Input, spi1_sclk_in- (SPI Clock)
5= spi1, Output, spi1_sclk_out- (SPI Clock)
6= Not Used
7= ua1, Output, ua1_txd- (UART transmitter serial output)</desc>
<sw_param offset="0xf80007c0" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_48_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= Not Used
2= Not Used
3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf80007c0" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_48_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock)
1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock)</desc>
<sw_param offset="0xf80007c0" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_48_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= Not Used</desc>
<sw_param offset="0xf80007c0" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_48_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf80007c0" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_49_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf80007c4" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_49_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf80007c4" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_49_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf80007c4" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_49_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf80007c4" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_49_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf80007c4" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_49_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1)
0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1)
1= can1, Input, can1_phy_rx- (Can RX signal)
2= i2c1, Input, i2c1_sda_input- (SDA signal)
2= i2c1, Output, i2c1_sda_out- (SDA signal)
3= Not Used
4= sd1, Input, sd1_data_in[1]- (4-bit Data bus)
4= sd1, Output, sd1_data_out[1]- (4-bit Data bus)
5= spi1, Input, spi1_n_ss_in- (SPI Master Selects)
5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects)
6= Not Used
7= ua1, Input, ua1_rxd- (UART receiver serial input)</desc>
<sw_param offset="0xf80007c4" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_49_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= Not Used
2= Not Used
3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf80007c4" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_49_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus)
1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus)</desc>
<sw_param offset="0xf80007c4" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_49_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= Not Used</desc>
<sw_param offset="0xf80007c4" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_49_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf80007c4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_50_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf80007c8" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_50_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf80007c8" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_50_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf80007c8" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_50_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf80007c8" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_50_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf80007c8" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_50_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1)
0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1)
1= can0, Input, can0_phy_rx- (Can RX signal)
2= i2c0, Input, i2c0_scl_input- (SCL signal)
2= i2c0, Output, i2c0_scl_out- (SCL signal)
3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock)
4= sd1, Input, sd1_data_in[2]- (4-bit Data bus)
4= sd1, Output, sd1_data_out[2]- (4-bit Data bus)
5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects)
6= Not Used
7= ua0, Input, ua0_rxd- (UART receiver serial input)</desc>
<sw_param offset="0xf80007c8" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_50_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= Not Used
2= Not Used
3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf80007c8" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_50_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus)
1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data bus)</desc>
<sw_param offset="0xf80007c8" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_50_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= Not Used</desc>
<sw_param offset="0xf80007c8" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_50_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf80007c8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_51_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf80007cc" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_51_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf80007cc" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_51_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf80007cc" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_51_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf80007cc" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_51_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf80007cc" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_51_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1)
0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1)
1= can0, Output, can0_phy_tx- (Can TX signal)
2= i2c0, Input, i2c0_sda_input- (SDA signal)
2= i2c0, Output, i2c0_sda_out- (SDA signal)
3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock)
4= sd1, Input, sd1_data_in[3]- (4-bit Data bus)
4= sd1, Output, sd1_data_out[3]- (4-bit Data bus)
5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects)
6= Not Used
7= ua0, Output, ua0_txd- (UART transmitter serial output)</desc>
<sw_param offset="0xf80007cc" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_51_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= Not Used
2= Not Used
3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf80007cc" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_51_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus)
1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data bus)</desc>
<sw_param offset="0xf80007cc" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_51_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= Not Used</desc>
<sw_param offset="0xf80007cc" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_51_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf80007cc" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_52_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf80007d0" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_52_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf80007d0" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_52_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf80007d0" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_52_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf80007d0" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_52_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf80007d0" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_52_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1)
0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1)
1= can1, Output, can1_phy_tx- (Can TX signal)
2= i2c1, Input, i2c1_scl_input- (SCL signal)
2= i2c1, Output, i2c1_scl_out- (SCL signal)
3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock)
4= mdio0, Output, gem0_mdc- (MDIO Clock)
5= mdio1, Output, gem1_mdc- (MDIO Clock)
6= Not Used
7= ua1, Output, ua1_txd- (UART transmitter serial output)</desc>
<sw_param offset="0xf80007d0" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_52_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= Not Used
2= Not Used
3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf80007d0" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_52_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= Not Used</desc>
<sw_param offset="0xf80007d0" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_52_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= Not Used</desc>
<sw_param offset="0xf80007d0" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_52_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf80007d0" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_53_reserved">
<name>reserved</name>
<desc>Not Used</desc>
<sw_param offset="0xf80007d4" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_53_DisableRcvr">
<name>DisableRcvr</name>
<desc>Enables the receiver.
If the IO is an output only then the receiver can be disabled and save power
Only used when IO_Type=HSTL
0= Receiver Enabled
1= Receiver disabled</desc>
<sw_param offset="0xf80007d4" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_53_PULLUP">
<name>PULLUP</name>
<desc>Controls the use of a pull-up for the associated GPIOB
0= Pull-up disabled
1= Pull-up enabled</desc>
<sw_param offset="0xf80007d4" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_53_IO_Type">
<name>IO_Type</name>
<desc>Selects the IO Type
0= LVTTL
1= LVCMOS18
2= LVCMOS25
3= LVCMOS33
4= HSTL
5-7= LVCMOS33</desc>
<sw_param offset="0xf80007d4" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_53_Speed">
<name>Speed</name>
<desc>Selects the speed of the I/O when IO_Type=CMOS
0=Slow CMOS
1=Fast CMOS</desc>
<sw_param offset="0xf80007d4" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_53_L3_SEL">
<name>L3_SEL</name>
<desc>Level 3 Mux Select
0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1)
0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1)
1= can1, Input, can1_phy_rx- (Can RX signal)
2= i2c1, Input, i2c1_sda_input- (SDA signal)
2= i2c1, Output, i2c1_sda_out- (SDA signal)
3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock)
4= mdio0, Input, gem0_mdio_in- (MDIO Data)
4= mdio0, Output, gem0_mdio_out- (MDIO Data)
5= mdio1, Input, gem1_mdio_in- (MDIO Data)
5= mdio1, Output, gem1_mdio_out- (MDIO Data)
6= Not Used
7= ua1, Input, ua1_rxd- (UART receiver serial input)</desc>
<sw_param offset="0xf80007d4" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_53_L2_SEL">
<name>L2_SEL</name>
<desc>Level 2 Mux Select
0= Level 3 Mux Output
1= Not Used
2= Not Used
3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</desc>
<sw_param offset="0xf80007d4" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_53_L1_SEL">
<name>L1_SEL</name>
<desc>Level 1 Mux Select
0= Level 2 Mux Output
1= Not Used</desc>
<sw_param offset="0xf80007d4" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_53_L0_SEL">
<name>L0_SEL</name>
<desc>Level 0 Mux Select
0= Level 1 Mux Output
1= Not Used</desc>
<sw_param offset="0xf80007d4" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_PIN_53_TRI_ENABLE">
<name>TRI_ENABLE</name>
<desc>Tri-state enable, active high.</desc>
<sw_param offset="0xf80007d4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_FMIO_GEM_SEL_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8000800" start="31" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_FMIO_GEM_SEL_GEM1_IF_SELECT">
<name>GEM1_IF_SELECT</name>
<desc>GEM 1 Interface selection. 0 = RGMII to/from MIO. 1 = GMII to/from FMIO. The setting for this register generates the
gem0_rx_sel
signals to the GEM core wrappers within the IOU.</desc>
<sw_param offset="0xf8000800" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_FMIO_GEM_SEL_GEM0_IF_SELECT">
<name>GEM0_IF_SELECT</name>
<desc>GEM 0 Interface selection. 0 = RGMII to/from MIO. 1 = GMII to/from FMIO. The setting for this register generates the
gem0_rx_sel
signals to the GEM core wrappers within the IOU.</desc>
<sw_param offset="0xf8000800" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_LOOPBACK_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8000804" start="31" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_LOOPBACK_I2C0_LOOP_I2C1">
<name>I2C0_LOOP_I2C1</name>
<desc>I2C Loopback Control.
0 = Connect I2C inputs according to MIO mapping.
1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outputs
to I2C 0 inputs.</desc>
<sw_param offset="0xf8000804" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_LOOPBACK_CAN0_LOOP_CAN1">
<name>CAN0_LOOP_CAN1</name>
<desc>CAN Loopback Control.
0 = Connect CAN inputs according to MIO mapping.
1 = Loop CAN 0 TX to CAN 1 RX, and CAN 1 TX to CAN 0 RX.</desc>
<sw_param offset="0xf8000804" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_LOOPBACK_UA0_LOOP_UA1">
<name>UA0_LOOP_UA1</name>
<desc>UART Loopback Control.
0 = Connect UART inputs according to MIO mapping.
1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 outputs to UART 0 inputs.
RXD/TXD cross-connected.
RTS/CTS cross-connected.
DSR, DTR, DCD and RI not used.</desc>
<sw_param offset="0xf8000804" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_LOOPBACK_SPI0_LOOP_SPI1">
<name>SPI0_LOOP_SPI1</name>
<desc>SPI Loopback Control.
0 = Connect SPI inputs according to MIO mapping.
1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outputs to SPI 0 inputs.
The other SPI core will always appear on the LS Slave Select.</desc>
<sw_param offset="0xf8000804" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_31_TRI">
<name>PIN_31_TRI</name>
<desc>Master Tri-state Enable for pin 31, active high</desc>
<sw_param offset="0xf800080c" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_30_TRI">
<name>PIN_30_TRI</name>
<desc>Master Tri-state Enable for pin 30, active high</desc>
<sw_param offset="0xf800080c" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_29_TRI">
<name>PIN_29_TRI</name>
<desc>Master Tri-state Enable for pin 29, active high</desc>
<sw_param offset="0xf800080c" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_28_TRI">
<name>PIN_28_TRI</name>
<desc>Master Tri-state Enable for pin 28, active high</desc>
<sw_param offset="0xf800080c" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_27_TRI">
<name>PIN_27_TRI</name>
<desc>Master Tri-state Enable for pin 27, active high</desc>
<sw_param offset="0xf800080c" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_26_TRI">
<name>PIN_26_TRI</name>
<desc>Master Tri-state Enable for pin 26, active high</desc>
<sw_param offset="0xf800080c" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_25_TRI">
<name>PIN_25_TRI</name>
<desc>Master Tri-state Enable for pin 25, active high</desc>
<sw_param offset="0xf800080c" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_24_TRI">
<name>PIN_24_TRI</name>
<desc>Master Tri-state Enable for pin 24, active high</desc>
<sw_param offset="0xf800080c" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_23_TRI">
<name>PIN_23_TRI</name>
<desc>Master Tri-state Enable for pin 23, active high</desc>
<sw_param offset="0xf800080c" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_22_TRI">
<name>PIN_22_TRI</name>
<desc>Master Tri-state Enable for pin 22, active high</desc>
<sw_param offset="0xf800080c" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_21_TRI">
<name>PIN_21_TRI</name>
<desc>Master Tri-state Enable for pin 21, active high</desc>
<sw_param offset="0xf800080c" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_20_TRI">
<name>PIN_20_TRI</name>
<desc>Master Tri-state Enable for pin 20, active high</desc>
<sw_param offset="0xf800080c" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_19_TRI">
<name>PIN_19_TRI</name>
<desc>Master Tri-state Enable for pin 19, active high</desc>
<sw_param offset="0xf800080c" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_18_TRI">
<name>PIN_18_TRI</name>
<desc>Master Tri-state Enable for pin 18, active high</desc>
<sw_param offset="0xf800080c" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_17_TRI">
<name>PIN_17_TRI</name>
<desc>Master Tri-state Enable for pin 17, active high</desc>
<sw_param offset="0xf800080c" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_16_TRI">
<name>PIN_16_TRI</name>
<desc>Master Tri-state Enable for pin 16, active high</desc>
<sw_param offset="0xf800080c" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_15_TRI">
<name>PIN_15_TRI</name>
<desc>Master Tri-state Enable for pin 15, active high</desc>
<sw_param offset="0xf800080c" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_14_TRI">
<name>PIN_14_TRI</name>
<desc>Master Tri-state Enable for pin 14, active high</desc>
<sw_param offset="0xf800080c" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_13_TRI">
<name>PIN_13_TRI</name>
<desc>Master Tri-state Enable for pin 13, active high</desc>
<sw_param offset="0xf800080c" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_12_TRI">
<name>PIN_12_TRI</name>
<desc>Master Tri-state Enable for pin 12, active high</desc>
<sw_param offset="0xf800080c" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_11_TRI">
<name>PIN_11_TRI</name>
<desc>Master Tri-state Enable for pin 11, active high</desc>
<sw_param offset="0xf800080c" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_10_TRI">
<name>PIN_10_TRI</name>
<desc>Master Tri-state Enable for pin 10, active high</desc>
<sw_param offset="0xf800080c" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_09_TRI">
<name>PIN_09_TRI</name>
<desc>Master Tri-state Enable for pin 9, active high</desc>
<sw_param offset="0xf800080c" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_08_TRI">
<name>PIN_08_TRI</name>
<desc>Master Tri-state Enable for pin 8, active high</desc>
<sw_param offset="0xf800080c" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_07_TRI">
<name>PIN_07_TRI</name>
<desc>Master Tri-state Enable for pin 7, active high</desc>
<sw_param offset="0xf800080c" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_06_TRI">
<name>PIN_06_TRI</name>
<desc>Master Tri-state Enable for pin 6, active high</desc>
<sw_param offset="0xf800080c" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_05_TRI">
<name>PIN_05_TRI</name>
<desc>Master Tri-state Enable for pin 5, active high</desc>
<sw_param offset="0xf800080c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_04_TRI">
<name>PIN_04_TRI</name>
<desc>Master Tri-state Enable for pin 4, active high</desc>
<sw_param offset="0xf800080c" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_03_TRI">
<name>PIN_03_TRI</name>
<desc>Master Tri-state Enable for pin 3, active high</desc>
<sw_param offset="0xf800080c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_02_TRI">
<name>PIN_02_TRI</name>
<desc>Master Tri-state Enable for pin 2, active high</desc>
<sw_param offset="0xf800080c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_01_TRI">
<name>PIN_01_TRI</name>
<desc>Master Tri-state Enable for pin 1, active high</desc>
<sw_param offset="0xf800080c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TRI0_PIN_00_TRI">
<name>PIN_00_TRI</name>
<desc>Master Tri-state Enable for pin 0, active high</desc>
<sw_param offset="0xf800080c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_63_TRI">
<name>PIN_63_TRI</name>
<desc>Master Tri-state Enable for pin 63, active high. Unused</desc>
<sw_param offset="0xf8000810" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_62_TRI">
<name>PIN_62_TRI</name>
<desc>Master Tri-state Enable for pin 62, active high. Unused</desc>
<sw_param offset="0xf8000810" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_61_TRI">
<name>PIN_61_TRI</name>
<desc>Master Tri-state Enable for pin 61, active high. Unused</desc>
<sw_param offset="0xf8000810" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_60_TRI">
<name>PIN_60_TRI</name>
<desc>Master Tri-state Enable for pin 60, active high. Unused</desc>
<sw_param offset="0xf8000810" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_59_TRI">
<name>PIN_59_TRI</name>
<desc>Master Tri-state Enable for pin 59, active high. Unused</desc>
<sw_param offset="0xf8000810" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_58_TRI">
<name>PIN_58_TRI</name>
<desc>Master Tri-state Enable for pin 58, active high. Unused</desc>
<sw_param offset="0xf8000810" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_57_TRI">
<name>PIN_57_TRI</name>
<desc>Master Tri-state Enable for pin 57, active high. Unused</desc>
<sw_param offset="0xf8000810" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_56_TRI">
<name>PIN_56_TRI</name>
<desc>Master Tri-state Enable for pin 56 active high. Unused</desc>
<sw_param offset="0xf8000810" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_55_TRI">
<name>PIN_55_TRI</name>
<desc>Master Tri-state Enable for pin 55, active high. Unused</desc>
<sw_param offset="0xf8000810" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_54_TRI">
<name>PIN_54_TRI</name>
<desc>Master Tri-state Enable for pin 54, active high. Unused</desc>
<sw_param offset="0xf8000810" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_53_TRI">
<name>PIN_53_TRI</name>
<desc>Master Tri-state Enable for pin 53, active high</desc>
<sw_param offset="0xf8000810" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_52_TRI">
<name>PIN_52_TRI</name>
<desc>Master Tri-state Enable for pin 52, active high</desc>
<sw_param offset="0xf8000810" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_51_TRI">
<name>PIN_51_TRI</name>
<desc>Master Tri-state Enable for pin 51, active high</desc>
<sw_param offset="0xf8000810" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_50_TRI">
<name>PIN_50_TRI</name>
<desc>Master Tri-state Enable for pin 50, active high</desc>
<sw_param offset="0xf8000810" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_49_TRI">
<name>PIN_49_TRI</name>
<desc>Master Tri-state Enable for pin 49, active high</desc>
<sw_param offset="0xf8000810" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_48_TRI">
<name>PIN_48_TRI</name>
<desc>Master Tri-state Enable for pin 48, active high</desc>
<sw_param offset="0xf8000810" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_47_TRI">
<name>PIN_47_TRI</name>
<desc>Master Tri-state Enable for pin 47, active high</desc>
<sw_param offset="0xf8000810" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_46_TRI">
<name>PIN_46_TRI</name>
<desc>Master Tri-state Enable for pin 46, active high</desc>
<sw_param offset="0xf8000810" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_45_TRI">
<name>PIN_45_TRI</name>
<desc>Master Tri-state Enable for pin 45, active high</desc>
<sw_param offset="0xf8000810" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_44_TRI">
<name>PIN_44_TRI</name>
<desc>Master Tri-state Enable for pin 44, active high</desc>
<sw_param offset="0xf8000810" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_43_TRI">
<name>PIN_43_TRI</name>
<desc>Master Tri-state Enable for pin 43, active high</desc>
<sw_param offset="0xf8000810" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_42_TRI">
<name>PIN_42_TRI</name>
<desc>Master Tri-state Enable for pin 42, active high</desc>
<sw_param offset="0xf8000810" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_41_TRI">
<name>PIN_41_TRI</name>
<desc>Master Tri-state Enable for pin 41, active high</desc>
<sw_param offset="0xf8000810" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_40_TRI">
<name>PIN_40_TRI</name>
<desc>Master Tri-state Enable for pin 40, active high</desc>
<sw_param offset="0xf8000810" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_39_TRI">
<name>PIN_39_TRI</name>
<desc>Master Tri-state Enable for pin 39, active high</desc>
<sw_param offset="0xf8000810" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_38_TRI">
<name>PIN_38_TRI</name>
<desc>Master Tri-state Enable for pin 38, active high</desc>
<sw_param offset="0xf8000810" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_37_TRI">
<name>PIN_37_TRI</name>
<desc>Master Tri-state Enable for pin 37, active high</desc>
<sw_param offset="0xf8000810" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_36_TRI">
<name>PIN_36_TRI</name>
<desc>Master Tri-state Enable for pin 36, active high</desc>
<sw_param offset="0xf8000810" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_35_TRI">
<name>PIN_35_TRI</name>
<desc>Master Tri-state Enable for pin 35, active high</desc>
<sw_param offset="0xf8000810" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_34_TRI">
<name>PIN_34_TRI</name>
<desc>Master Tri-state Enable for pin 34, active high</desc>
<sw_param offset="0xf8000810" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_33_TRI">
<name>PIN_33_TRI</name>
<desc>Master Tri-state Enable for pin 33, active high</desc>
<sw_param offset="0xf8000810" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_MIO_MST_TR11_PIN_32_TRI">
<name>PIN_32_TRI</name>
<desc>Master Tri-state Enable for pin 32, active high</desc>
<sw_param offset="0xf8000810" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_SD0_WP_CD_SEL_reserved_1">
<name>reserved_1</name>
<desc>Not used, tie to zero for read back.</desc>
<sw_param offset="0xf8000830" start="31" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_SD0_WP_CD_SEL_SDIO0_CD_SEL">
<name>SDIO0_CD_SEL</name>
<desc>SDIO0 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source</desc>
<sw_param offset="0xf8000830" start="21" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_SD0_WP_CD_SEL_reserved">
<name>reserved</name>
<desc>Not used, tie to zero for read back.</desc>
<sw_param offset="0xf8000830" start="15" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_SD0_WP_CD_SEL_SDIO0_WP_SEL">
<name>SDIO0_WP_SEL</name>
<desc>SDIO0 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source</desc>
<sw_param offset="0xf8000830" start="5" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_SD1_WP_CD_SEL_reserved_1">
<name>reserved_1</name>
<desc>Not used, tie to zero for read back.</desc>
<sw_param offset="0xf8000834" start="31" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_SD1_WP_CD_SEL_SDIO1_CD_SEL">
<name>SDIO1_CD_SEL</name>
<desc>SDIO1 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source</desc>
<sw_param offset="0xf8000834" start="21" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_SD1_WP_CD_SEL_reserved">
<name>reserved</name>
<desc>Not used, tie to zero for read back.</desc>
<sw_param offset="0xf8000834" start="15" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_SD1_WP_CD_SEL_SDIO1_WP_SEL">
<name>SDIO1_WP_SEL</name>
<desc>SDIO1 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source</desc>
<sw_param offset="0xf8000834" start="5" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_LVL_SHFTR_EN_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000900" start="31" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_LVL_SHFTR_EN_USER_INP_ICT_EN_1">
<name>USER_INP_ICT_EN_1</name>
<desc>Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0].</desc>
<sw_param offset="0xf8000900" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_LVL_SHFTR_EN_USER_INP_ICT_EN_0">
<name>USER_INP_ICT_EN_0</name>
<desc>Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0].</desc>
<sw_param offset="0xf8000900" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_CFG_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000910" start="31" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_CFG_SWAP">
<name>SWAP</name>
<desc>When cleared (0), the RAM is located starting at address 32'h0004_0000. This is the reset state. When set (1), the RAM is 'swapped' with the ROM at the bottom of the OCM address map. The base address for the RAM will now be 32'h0000_0000.</desc>
<sw_param offset="0xf8000910" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_CFG_RAM_HI">
<name>RAM_HI</name>
<desc>Maps the RAM, in 64kByte chunks, to the high address space (1) or the low address space(0). Refer to the OCM spec. for more details.
Note that  the 'RAM_HI' bits are only valid when the 'SWAP' bit is set.</desc>
<sw_param offset="0xf8000910" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM0_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a00" start="23" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM0_EMAS2">
<name>EMAS2</name>
<desc>RAM 2 Extra Margin Adjustment (sensing)</desc>
<sw_param offset="0xf8000a00" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM0_EMAW2">
<name>EMAW2</name>
<desc>RAM 2 Extra Margin Adjustment (writes)</desc>
<sw_param offset="0xf8000a00" start="20" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM0_EMA2">
<name>EMA2</name>
<desc>RAM 2 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a00" start="18" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM0_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a00" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM0_EMAS1">
<name>EMAS1</name>
<desc>RAM 1 Extra Margin Adjustment (sensing)</desc>
<sw_param offset="0xf8000a00" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM0_EMAW1">
<name>EMAW1</name>
<desc>RAM 1 Extra Margin Adjustment (writes)</desc>
<sw_param offset="0xf8000a00" start="12" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM0_EMA1">
<name>EMA1</name>
<desc>RAM 1 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a00" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM0_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a00" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM0_EMAS0">
<name>EMAS0</name>
<desc>RAM 0 Extra Margin Adjustment (sensing)</desc>
<sw_param offset="0xf8000a00" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM0_EMAW0">
<name>EMAW0</name>
<desc>RAM 0 Extra Margin Adjustment (writes)</desc>
<sw_param offset="0xf8000a00" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM0_EMA0">
<name>EMA0</name>
<desc>RAM 0 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a00" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM1_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a04" start="23" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM1_EMAS2">
<name>EMAS2</name>
<desc>RAM 2 Extra Margin Adjustment (sensing)</desc>
<sw_param offset="0xf8000a04" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM1_EMAW2">
<name>EMAW2</name>
<desc>RAM 2 Extra Margin Adjustment (writes)</desc>
<sw_param offset="0xf8000a04" start="20" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM1_EMA2">
<name>EMA2</name>
<desc>RAM 2 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a04" start="18" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM1_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a04" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM1_EMAS1">
<name>EMAS1</name>
<desc>RAM 1 Extra Margin Adjustment (sensing)</desc>
<sw_param offset="0xf8000a04" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM1_EMAW1">
<name>EMAW1</name>
<desc>RAM 1 Extra Margin Adjustment (writes)</desc>
<sw_param offset="0xf8000a04" start="12" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM1_EMA1">
<name>EMA1</name>
<desc>RAM 1 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a04" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM1_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a04" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM1_EMAS0">
<name>EMAS0</name>
<desc>RAM 0 Extra Margin Adjustment (sensing)</desc>
<sw_param offset="0xf8000a04" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM1_EMAW0">
<name>EMAW0</name>
<desc>RAM 0 Extra Margin Adjustment (writes)</desc>
<sw_param offset="0xf8000a04" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM1_EMA0">
<name>EMA0</name>
<desc>RAM 0 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a04" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM2_reserved_3">
<name>reserved_3</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a08" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM2_EMAS3">
<name>EMAS3</name>
<desc>RAM 3 Extra Margin Adjustment (sensing)</desc>
<sw_param offset="0xf8000a08" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM2_EMAW3">
<name>EMAW3</name>
<desc>RAM 3 Extra Margin Adjustment (writes)</desc>
<sw_param offset="0xf8000a08" start="28" end="27" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM2_EMA3">
<name>EMA3</name>
<desc>RAM 3 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a08" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM2_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a08" start="23" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM2_EMAS2">
<name>EMAS2</name>
<desc>RAM 2 Extra Margin Adjustment (sensing)</desc>
<sw_param offset="0xf8000a08" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM2_EMAW2">
<name>EMAW2</name>
<desc>RAM 2 Extra Margin Adjustment (writes)</desc>
<sw_param offset="0xf8000a08" start="20" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM2_EMA2">
<name>EMA2</name>
<desc>RAM 2 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a08" start="18" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM2_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a08" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM2_EMAS1">
<name>EMAS1</name>
<desc>RAM 1 Extra Margin Adjustment (sensing)</desc>
<sw_param offset="0xf8000a08" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM2_EMAW1">
<name>EMAW1</name>
<desc>RAM 1 Extra Margin Adjustment (writes)</desc>
<sw_param offset="0xf8000a08" start="12" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM2_EMA1">
<name>EMA1</name>
<desc>RAM 1 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a08" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM2_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a08" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM2_EMAS0">
<name>EMAS0</name>
<desc>RAM 0 Extra Margin Adjustment (sensing)</desc>
<sw_param offset="0xf8000a08" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM2_EMAW0">
<name>EMAW0</name>
<desc>RAM 0 Extra Margin Adjustment (writes)</desc>
<sw_param offset="0xf8000a08" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU0_RAM2_EMA0">
<name>EMA0</name>
<desc>RAM 0 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a08" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM0_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a0c" start="23" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM0_EMAS2">
<name>EMAS2</name>
<desc>RAM 2 Extra Margin Adjustment (sensing)</desc>
<sw_param offset="0xf8000a0c" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM0_EMAW2">
<name>EMAW2</name>
<desc>RAM 2 Extra Margin Adjustment (writes)</desc>
<sw_param offset="0xf8000a0c" start="20" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM0_EMA2">
<name>EMA2</name>
<desc>RAM 2 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a0c" start="18" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM0_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a0c" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM0_EMAS1">
<name>EMAS1</name>
<desc>RAM 1 Extra Margin Adjustment (sensing)</desc>
<sw_param offset="0xf8000a0c" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM0_EMAW1">
<name>EMAW1</name>
<desc>RAM 1 Extra Margin Adjustment (writes)</desc>
<sw_param offset="0xf8000a0c" start="12" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM0_EMA1">
<name>EMA1</name>
<desc>RAM 1 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a0c" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM0_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a0c" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM0_EMAS0">
<name>EMAS0</name>
<desc>RAM 0 Extra Margin Adjustment (sensing)</desc>
<sw_param offset="0xf8000a0c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM0_EMAW0">
<name>EMAW0</name>
<desc>RAM 0 Extra Margin Adjustment (writes)</desc>
<sw_param offset="0xf8000a0c" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM0_EMA0">
<name>EMA0</name>
<desc>RAM 0 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a0c" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM1_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a10" start="23" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM1_EMAS2">
<name>EMAS2</name>
<desc>RAM 2 Extra Margin Adjustment (sensing)</desc>
<sw_param offset="0xf8000a10" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM1_EMAW2">
<name>EMAW2</name>
<desc>RAM 2 Extra Margin Adjustment (writes)</desc>
<sw_param offset="0xf8000a10" start="20" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM1_EMA2">
<name>EMA2</name>
<desc>RAM 2 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a10" start="18" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM1_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a10" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM1_EMAS1">
<name>EMAS1</name>
<desc>RAM 1 Extra Margin Adjustment (sensing)</desc>
<sw_param offset="0xf8000a10" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM1_EMAW1">
<name>EMAW1</name>
<desc>RAM 1 Extra Margin Adjustment (writes)</desc>
<sw_param offset="0xf8000a10" start="12" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM1_EMA1">
<name>EMA1</name>
<desc>RAM 1 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a10" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM1_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a10" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM1_EMAS0">
<name>EMAS0</name>
<desc>RAM 0 Extra Margin Adjustment (sensing)</desc>
<sw_param offset="0xf8000a10" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM1_EMAW0">
<name>EMAW0</name>
<desc>RAM 0 Extra Margin Adjustment (writes)</desc>
<sw_param offset="0xf8000a10" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM1_EMA0">
<name>EMA0</name>
<desc>RAM 0 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a10" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM2_reserved_3">
<name>reserved_3</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a14" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM2_EMAS3">
<name>EMAS3</name>
<desc>RAM 3 Extra Margin Adjustment (sensing)</desc>
<sw_param offset="0xf8000a14" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM2_EMAW3">
<name>EMAW3</name>
<desc>RAM 3 Extra Margin Adjustment (writes)</desc>
<sw_param offset="0xf8000a14" start="28" end="27" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM2_EMA3">
<name>EMA3</name>
<desc>RAM 3 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a14" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM2_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a14" start="23" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM2_EMAS2">
<name>EMAS2</name>
<desc>RAM 2 Extra Margin Adjustment (sensing)</desc>
<sw_param offset="0xf8000a14" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM2_EMAW2">
<name>EMAW2</name>
<desc>RAM 2 Extra Margin Adjustment (writes)</desc>
<sw_param offset="0xf8000a14" start="20" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM2_EMA2">
<name>EMA2</name>
<desc>RAM 2 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a14" start="18" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM2_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a14" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM2_EMAS1">
<name>EMAS1</name>
<desc>RAM 1 Extra Margin Adjustment (sensing)</desc>
<sw_param offset="0xf8000a14" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM2_EMAW1">
<name>EMAW1</name>
<desc>RAM 1 Extra Margin Adjustment (writes)</desc>
<sw_param offset="0xf8000a14" start="12" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM2_EMA1">
<name>EMA1</name>
<desc>RAM 1 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a14" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM2_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a14" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM2_EMAS0">
<name>EMAS0</name>
<desc>RAM 0 Extra Margin Adjustment (sensing)</desc>
<sw_param offset="0xf8000a14" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM2_EMAW0">
<name>EMAW0</name>
<desc>RAM 0 Extra Margin Adjustment (writes)</desc>
<sw_param offset="0xf8000a14" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_CPU1_RAM2_EMA0">
<name>EMA0</name>
<desc>RAM 0 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a14" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_SCU_RAM_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a18" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_SCU_RAM_EMAS0">
<name>EMAS0</name>
<desc>RAM 0 Extra Margin Adjustment (sensing)</desc>
<sw_param offset="0xf8000a18" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_SCU_RAM_EMAW0">
<name>EMAW0</name>
<desc>RAM 0 Extra Margin Adjustment (writes)</desc>
<sw_param offset="0xf8000a18" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_SCU_RAM_EMA0">
<name>EMA0</name>
<desc>RAM 0 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a18" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_L2C_RAM_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a1c" start="23" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_L2C_RAM_EMAS2">
<name>EMAS2</name>
<desc>RAM 2 Extra Margin Adjustment (sensing)</desc>
<sw_param offset="0xf8000a1c" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_slcr_L2C_RAM_EMAW2">
<name>EMAW2</name>
<desc>RAM 2 Extra Margin Adjustment (writes)</desc>
<sw_param offset="0xf8000a1c" start="20" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_L2C_RAM_EMA2">
<name>EMA2</name>
<desc>RAM 2 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a1c" start="18" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_L2C_RAM_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a1c" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_L2C_RAM_EMAS1">
<name>EMAS1</name>
<desc>RAM 1 Extra Margin Adjustment (sensing)</desc>
<sw_param offset="0xf8000a1c" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_L2C_RAM_EMAW1">
<name>EMAW1</name>
<desc>RAM 1 Extra Margin Adjustment (writes)</desc>
<sw_param offset="0xf8000a1c" start="12" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_L2C_RAM_EMA1">
<name>EMA1</name>
<desc>RAM 1 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a1c" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_L2C_RAM_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a1c" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_L2C_RAM_EMAS0">
<name>EMAS0</name>
<desc>RAM 0 Extra Margin Adjustment (sensing)</desc>
<sw_param offset="0xf8000a1c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_L2C_RAM_EMAW0">
<name>EMAW0</name>
<desc>RAM 0 Extra Margin Adjustment (writes)</desc>
<sw_param offset="0xf8000a1c" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_L2C_RAM_EMA0">
<name>EMA0</name>
<desc>RAM 0 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a1c" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_GEM01_reserved_3">
<name>reserved_3</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a30" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_GEM01_EMAB3">
<name>EMAB3</name>
<desc>RAM 3 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a30" start="29" end="27" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_GEM01_EMAA3">
<name>EMAA3</name>
<desc>RAM 3 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a30" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_GEM01_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a30" start="23" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_GEM01_EMAB2">
<name>EMAB2</name>
<desc>RAM 2 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a30" start="21" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_GEM01_EMAA2">
<name>EMAA2</name>
<desc>RAM 2 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a30" start="18" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_GEM01_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a30" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_GEM01_EMAB1">
<name>EMAB1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a30" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_GEM01_EMAA1">
<name>EMAA1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a30" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_GEM01_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a30" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_GEM01_EMAB0">
<name>EMAB0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a30" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_GEM01_EMAA0">
<name>EMAA0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a30" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_USB01_reserved_3">
<name>reserved_3</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a34" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_USB01_EMAB3">
<name>EMAB3</name>
<desc>RAM 3 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a34" start="29" end="27" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_USB01_EMAA3">
<name>EMAA3</name>
<desc>RAM 3 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a34" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_USB01_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a34" start="23" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_USB01_EMAB2">
<name>EMAB2</name>
<desc>RAM 2 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a34" start="21" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_USB01_EMAA2">
<name>EMAA2</name>
<desc>RAM 2 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a34" start="18" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_USB01_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a34" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_USB01_EMAB1">
<name>EMAB1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a34" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_USB01_EMAA1">
<name>EMAA1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a34" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_USB01_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a34" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_USB01_EMAB0">
<name>EMAB0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a34" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_USB01_EMAA0">
<name>EMAA0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a34" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_SDIO0_reserved_3">
<name>reserved_3</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a38" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_SDIO0_EMAB3">
<name>EMAB3</name>
<desc>RAM 3 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a38" start="29" end="27" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_SDIO0_EMAA3">
<name>EMAA3</name>
<desc>RAM 3 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a38" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_SDIO0_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a38" start="23" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_SDIO0_EMAB2">
<name>EMAB2</name>
<desc>RAM 2 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a38" start="21" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_SDIO0_EMAA2">
<name>EMAA2</name>
<desc>RAM 2 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a38" start="18" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_SDIO0_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a38" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_SDIO0_EMAB1">
<name>EMAB1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a38" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_SDIO0_EMAA1">
<name>EMAA1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a38" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_SDIO0_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a38" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_SDIO0_EMAB0">
<name>EMAB0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a38" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_SDIO0_EMAA0">
<name>EMAA0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a38" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_SDIO1_reserved_3">
<name>reserved_3</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a3c" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_SDIO1_EMAB3">
<name>EMAB3</name>
<desc>RAM 3 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a3c" start="29" end="27" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_SDIO1_EMAA3">
<name>EMAA3</name>
<desc>RAM 3 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a3c" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_SDIO1_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a3c" start="23" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_SDIO1_EMAB2">
<name>EMAB2</name>
<desc>RAM 2 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a3c" start="21" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_SDIO1_EMAA2">
<name>EMAA2</name>
<desc>RAM 2 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a3c" start="18" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_SDIO1_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a3c" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_SDIO1_EMAB1">
<name>EMAB1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a3c" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_SDIO1_EMAA1">
<name>EMAA1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a3c" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_SDIO1_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a3c" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_SDIO1_EMAB0">
<name>EMAB0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a3c" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_SDIO1_EMAA0">
<name>EMAA0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a3c" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_CAN0_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a40" start="23" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_CAN0_EMAB2">
<name>EMAB2</name>
<desc>RAM 2 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a40" start="21" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_CAN0_EMAA2">
<name>EMAA2</name>
<desc>RAM 2 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a40" start="18" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_CAN0_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a40" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_CAN0_EMAB1">
<name>EMAB1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a40" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_CAN0_EMAA1">
<name>EMAA1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a40" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_CAN0_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a40" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_CAN0_EMAB0">
<name>EMAB0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a40" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_CAN0_EMAA0">
<name>EMAA0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a40" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_CAN1_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a44" start="23" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_CAN1_EMAB2">
<name>EMAB2</name>
<desc>RAM 2 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a44" start="21" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_CAN1_EMAA2">
<name>EMAA2</name>
<desc>RAM 2 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a44" start="18" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_CAN1_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a44" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_CAN1_EMAB1">
<name>EMAB1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a44" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_CAN1_EMAA1">
<name>EMAA1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a44" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_CAN1_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a44" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_CAN1_EMAB0">
<name>EMAB0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a44" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_CAN1_EMAA0">
<name>EMAA0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a44" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_LQSPI_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a48" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_LQSPI_EMAB1">
<name>EMAB1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a48" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_LQSPI_EMAA1">
<name>EMAA1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a48" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_LQSPI_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a48" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_LQSPI_EMAB0">
<name>EMAB0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a48" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_IOU_RAM_LQSPI_EMAA0">
<name>EMAA0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a48" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_DMAC_RAM_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a50" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_DMAC_RAM_EMAB0">
<name>EMAB0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a50" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_DMAC_RAM_EMAA0">
<name>EMAA0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a50" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI0_RAM0_reserved_3">
<name>reserved_3</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a60" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI0_RAM0_EMAB3">
<name>EMAB3</name>
<desc>RAM 3 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a60" start="29" end="27" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI0_RAM0_EMAA3">
<name>EMAA3</name>
<desc>RAM 3 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a60" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI0_RAM0_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a60" start="23" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI0_RAM0_EMAB2">
<name>EMAB2</name>
<desc>RAM 2 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a60" start="21" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI0_RAM0_EMAA2">
<name>EMAA2</name>
<desc>RAM 2 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a60" start="18" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI0_RAM0_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a60" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI0_RAM0_EMAB1">
<name>EMAB1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a60" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI0_RAM0_EMAA1">
<name>EMAA1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a60" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI0_RAM0_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a60" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI0_RAM0_EMAB0">
<name>EMAB0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a60" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI0_RAM0_EMAA0">
<name>EMAA0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a60" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI0_RAM1_reserved_3">
<name>reserved_3</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a64" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI0_RAM1_EMAB3">
<name>EMAB3</name>
<desc>RAM 3 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a64" start="29" end="27" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI0_RAM1_EMAA3">
<name>EMAA3</name>
<desc>RAM 3 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a64" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI0_RAM1_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a64" start="23" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI0_RAM1_EMAB2">
<name>EMAB2</name>
<desc>RAM 2 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a64" start="21" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI0_RAM1_EMAA2">
<name>EMAA2</name>
<desc>RAM 2 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a64" start="18" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI0_RAM1_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a64" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI0_RAM1_EMAB1">
<name>EMAB1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a64" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI0_RAM1_EMAA1">
<name>EMAA1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a64" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI0_RAM1_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a64" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI0_RAM1_EMAB0">
<name>EMAB0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a64" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI0_RAM1_EMAA0">
<name>EMAA0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a64" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI0_RAM2_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a68" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI0_RAM2_EMAB1">
<name>EMAB1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a68" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI0_RAM2_EMAA1">
<name>EMAA1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a68" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI0_RAM2_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a68" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI0_RAM2_EMAB0">
<name>EMAB0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a68" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI0_RAM2_EMAA0">
<name>EMAA0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a68" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI1_RAM0_reserved_3">
<name>reserved_3</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a6c" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI1_RAM0_EMAB3">
<name>EMAB3</name>
<desc>RAM 3 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a6c" start="29" end="27" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI1_RAM0_EMAA3">
<name>EMAA3</name>
<desc>RAM 3 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a6c" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI1_RAM0_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a6c" start="23" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI1_RAM0_EMAB2">
<name>EMAB2</name>
<desc>RAM 2 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a6c" start="21" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI1_RAM0_EMAA2">
<name>EMAA2</name>
<desc>RAM 2 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a6c" start="18" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI1_RAM0_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a6c" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI1_RAM0_EMAB1">
<name>EMAB1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a6c" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI1_RAM0_EMAA1">
<name>EMAA1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a6c" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI1_RAM0_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a6c" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI1_RAM0_EMAB0">
<name>EMAB0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a6c" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI1_RAM0_EMAA0">
<name>EMAA0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a6c" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI1_RAM1_reserved_3">
<name>reserved_3</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a70" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI1_RAM1_EMAB3">
<name>EMAB3</name>
<desc>RAM 3 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a70" start="29" end="27" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI1_RAM1_EMAA3">
<name>EMAA3</name>
<desc>RAM 3 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a70" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI1_RAM1_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a70" start="23" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI1_RAM1_EMAB2">
<name>EMAB2</name>
<desc>RAM 2 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a70" start="21" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI1_RAM1_EMAA2">
<name>EMAA2</name>
<desc>RAM 2 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a70" start="18" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI1_RAM1_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a70" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI1_RAM1_EMAB1">
<name>EMAB1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a70" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI1_RAM1_EMAA1">
<name>EMAA1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a70" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI1_RAM1_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a70" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI1_RAM1_EMAB0">
<name>EMAB0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a70" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI1_RAM1_EMAA0">
<name>EMAA0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a70" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI1_RAM2_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a74" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI1_RAM2_EMAB1">
<name>EMAB1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a74" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI1_RAM2_EMAA1">
<name>EMAA1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a74" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI1_RAM2_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a74" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI1_RAM2_EMAB0">
<name>EMAB0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a74" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI1_RAM2_EMAA0">
<name>EMAA0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a74" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI2_RAM0_reserved_3">
<name>reserved_3</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a78" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI2_RAM0_EMAB3">
<name>EMAB3</name>
<desc>RAM 3 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a78" start="29" end="27" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI2_RAM0_EMAA3">
<name>EMAA3</name>
<desc>RAM 3 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a78" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI2_RAM0_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a78" start="23" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI2_RAM0_EMAB2">
<name>EMAB2</name>
<desc>RAM 2 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a78" start="21" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI2_RAM0_EMAA2">
<name>EMAA2</name>
<desc>RAM 2 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a78" start="18" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI2_RAM0_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a78" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI2_RAM0_EMAB1">
<name>EMAB1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a78" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI2_RAM0_EMAA1">
<name>EMAA1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a78" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI2_RAM0_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a78" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI2_RAM0_EMAB0">
<name>EMAB0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a78" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI2_RAM0_EMAA0">
<name>EMAA0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a78" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI2_RAM1_reserved_3">
<name>reserved_3</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a7c" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI2_RAM1_EMAB3">
<name>EMAB3</name>
<desc>RAM 3 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a7c" start="29" end="27" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI2_RAM1_EMAA3">
<name>EMAA3</name>
<desc>RAM 3 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a7c" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI2_RAM1_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a7c" start="23" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI2_RAM1_EMAB2">
<name>EMAB2</name>
<desc>RAM 2 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a7c" start="21" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI2_RAM1_EMAA2">
<name>EMAA2</name>
<desc>RAM 2 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a7c" start="18" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI2_RAM1_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a7c" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI2_RAM1_EMAB1">
<name>EMAB1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a7c" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI2_RAM1_EMAA1">
<name>EMAA1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a7c" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI2_RAM1_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a7c" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI2_RAM1_EMAB0">
<name>EMAB0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a7c" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI2_RAM1_EMAA0">
<name>EMAA0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a7c" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI2_RAM2_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a80" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI2_RAM2_EMAB1">
<name>EMAB1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a80" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI2_RAM2_EMAA1">
<name>EMAA1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a80" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI2_RAM2_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a80" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI2_RAM2_EMAB0">
<name>EMAB0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a80" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI2_RAM2_EMAA0">
<name>EMAA0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a80" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI3_RAM0_reserved_3">
<name>reserved_3</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a84" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI3_RAM0_EMAB3">
<name>EMAB3</name>
<desc>RAM 3 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a84" start="29" end="27" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI3_RAM0_EMAA3">
<name>EMAA3</name>
<desc>RAM 3 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a84" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI3_RAM0_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a84" start="23" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI3_RAM0_EMAB2">
<name>EMAB2</name>
<desc>RAM 2 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a84" start="21" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI3_RAM0_EMAA2">
<name>EMAA2</name>
<desc>RAM 2 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a84" start="18" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI3_RAM0_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a84" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI3_RAM0_EMAB1">
<name>EMAB1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a84" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI3_RAM0_EMAA1">
<name>EMAA1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a84" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI3_RAM0_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a84" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI3_RAM0_EMAB0">
<name>EMAB0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a84" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI3_RAM0_EMAA0">
<name>EMAA0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a84" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI3_RAM1_reserved_3">
<name>reserved_3</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a88" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI3_RAM1_EMAB3">
<name>EMAB3</name>
<desc>RAM 3 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a88" start="29" end="27" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI3_RAM1_EMAA3">
<name>EMAA3</name>
<desc>RAM 3 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a88" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI3_RAM1_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a88" start="23" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI3_RAM1_EMAB2">
<name>EMAB2</name>
<desc>RAM 2 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a88" start="21" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI3_RAM1_EMAA2">
<name>EMAA2</name>
<desc>RAM 2 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a88" start="18" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI3_RAM1_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a88" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI3_RAM1_EMAB1">
<name>EMAB1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a88" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI3_RAM1_EMAA1">
<name>EMAA1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a88" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI3_RAM1_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a88" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI3_RAM1_EMAB0">
<name>EMAB0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a88" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI3_RAM1_EMAA0">
<name>EMAA0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a88" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI3_RAM2_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a8c" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI3_RAM2_EMAB1">
<name>EMAB1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a8c" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI3_RAM2_EMAA1">
<name>EMAA1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a8c" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI3_RAM2_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a8c" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI3_RAM2_EMAB0">
<name>EMAB0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000a8c" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_AFI3_RAM2_EMAA0">
<name>EMAA0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000a8c" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_RAM_reserved_3">
<name>reserved_3</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a90" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_RAM_EMAS3">
<name>EMAS3</name>
<desc>RAM 3 Extra Margin Adjustment (sensing)</desc>
<sw_param offset="0xf8000a90" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_RAM_EMAW3">
<name>EMAW3</name>
<desc>RAM 3 Extra Margin Adjustment (writes)</desc>
<sw_param offset="0xf8000a90" start="28" end="27" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_RAM_EMA3">
<name>EMA3</name>
<desc>RAM 3 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a90" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_RAM_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a90" start="23" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_RAM_EMAS2">
<name>EMAS2</name>
<desc>RAM 2 Extra Margin Adjustment (sensing)</desc>
<sw_param offset="0xf8000a90" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_RAM_EMAW2">
<name>EMAW2</name>
<desc>RAM 2 Extra Margin Adjustment (writes)</desc>
<sw_param offset="0xf8000a90" start="20" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_RAM_EMA2">
<name>EMA2</name>
<desc>RAM 2 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a90" start="18" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_RAM_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a90" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_RAM_EMAS1">
<name>EMAS1</name>
<desc>RAM 1 Extra Margin Adjustment (sensing)</desc>
<sw_param offset="0xf8000a90" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_RAM_EMAW1">
<name>EMAW1</name>
<desc>RAM 1 Extra Margin Adjustment (writes)</desc>
<sw_param offset="0xf8000a90" start="12" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_RAM_EMA1">
<name>EMA1</name>
<desc>RAM 1 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a90" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_RAM_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a90" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_RAM_EMAS0">
<name>EMAS0</name>
<desc>RAM 0 Extra Margin Adjustment (sensing)</desc>
<sw_param offset="0xf8000a90" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_RAM_EMAW0">
<name>EMAW0</name>
<desc>RAM 0 Extra Margin Adjustment (writes)</desc>
<sw_param offset="0xf8000a90" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_RAM_EMA0">
<name>EMA0</name>
<desc>RAM 0 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a90" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_ROM0_reserved_3">
<name>reserved_3</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a94" start="31" end="28" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_ROM0_KEN3">
<name>KEN3</name>
<desc>ROM 3 Keeper Enable</desc>
<sw_param offset="0xf8000a94" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_ROM0_EMA3">
<name>EMA3</name>
<desc>ROM 3 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a94" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_ROM0_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a94" start="23" end="20" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_ROM0_KEN2">
<name>KEN2</name>
<desc>ROM 2 Keeper Enable</desc>
<sw_param offset="0xf8000a94" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_ROM0_EMA2">
<name>EMA2</name>
<desc>ROM 2 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a94" start="18" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_ROM0_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a94" start="15" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_ROM0_KEN1">
<name>KEN1</name>
<desc>ROM 1 Keeper Enable</desc>
<sw_param offset="0xf8000a94" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_ROM0_EMA1">
<name>EMA1</name>
<desc>ROM 1 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a94" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_ROM0_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a94" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_ROM0_KEN0">
<name>KEN0</name>
<desc>ROM 0 Keeper Enable</desc>
<sw_param offset="0xf8000a94" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_ROM0_EMA0">
<name>EMA0</name>
<desc>ROM 0 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a94" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_ROM1_reserved_3">
<name>reserved_3</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a98" start="31" end="28" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_ROM1_KEN3">
<name>KEN3</name>
<desc>ROM 3 Keeper Enable</desc>
<sw_param offset="0xf8000a98" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_ROM1_EMA3">
<name>EMA3</name>
<desc>ROM 3 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a98" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_ROM1_reserved_2">
<name>reserved_2</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a98" start="23" end="20" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_ROM1_KEN2">
<name>KEN2</name>
<desc>ROM 2 Keeper Enable</desc>
<sw_param offset="0xf8000a98" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_ROM1_EMA2">
<name>EMA2</name>
<desc>ROM 2 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a98" start="18" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_ROM1_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a98" start="15" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_ROM1_KEN1">
<name>KEN1</name>
<desc>ROM 1 Keeper Enable</desc>
<sw_param offset="0xf8000a98" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_ROM1_EMA1">
<name>EMA1</name>
<desc>ROM 1 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a98" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_ROM1_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000a98" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_ROM1_KEN0">
<name>KEN0</name>
<desc>ROM 0 Keeper Enable</desc>
<sw_param offset="0xf8000a98" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_OCM_ROM1_EMA0">
<name>EMA0</name>
<desc>ROM 0 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000a98" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_DEVCI_RAM_reserved_1">
<name>reserved_1</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000aa0" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_DEVCI_RAM_EMAB1">
<name>EMAB1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000aa0" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_DEVCI_RAM_EMAA1">
<name>EMAA1</name>
<desc>RAM 1 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000aa0" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_DEVCI_RAM_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000aa0" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_DEVCI_RAM_EMAB0">
<name>EMAB0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAB[0] = LSB)</desc>
<sw_param offset="0xf8000aa0" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_DEVCI_RAM_EMAA0">
<name>EMAA0</name>
<desc>RAM 0 Extra Margin Adjustment (EMAA[0] = LSB)</desc>
<sw_param offset="0xf8000aa0" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_CSG_RAM_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000ab0" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_CSG_RAM_EMAS0">
<name>EMAS0</name>
<desc>RAM 0 Extra Margin Adjustment (sensing)</desc>
<sw_param offset="0xf8000ab0" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_CSG_RAM_EMAW0">
<name>EMAW0</name>
<desc>RAM 0 Extra Margin Adjustment (writes)</desc>
<sw_param offset="0xf8000ab0" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_CSG_RAM_EMA0">
<name>EMA0</name>
<desc>RAM 0 Extra Margin Adjustment (EMA[0] = LSB)</desc>
<sw_param offset="0xf8000ab0" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000b00" start="31" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CTRL_VREF_SW_EN">
<name>VREF_SW_EN</name>
<desc>Enables the VREF switch
0 - internal
1 - external</desc>
<sw_param offset="0xf8000b00" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CTRL_VREF_EXT">
<name>VREF_EXT</name>
<desc>Enables higher performance if needed...uses more power
0 - normal operation (should be sufficient)
1 - higher performance (more power)</desc>
<sw_param offset="0xf8000b00" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CTRL_SRSTN_PULLUP_EN">
<name>SRSTN_PULLUP_EN</name>
<desc>Enables internal pullup. 0 - no pullup. 1 - pullup.</desc>
<sw_param offset="0xf8000b00" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CTRL_CLK_PULLUP_EN">
<name>CLK_PULLUP_EN</name>
<desc>Enables internal pullup. 0 - no pullup. 1 - pullup.</desc>
<sw_param offset="0xf8000b00" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CTRL_VREF_SEL">
<name>VREF_SEL</name>
<desc>Specifies GP
IOB Vref generator output
000000 - VREF = test mode - external VREF selected
000001 - VREF = test mode - 060
000010 - VREF = test mode - 075
000100 - VREF = test mode - 090
001000 - VREF = test mode - 108
010000 - VREF = test mode - 125
100000 - VREF = test mode - 0675</desc>
<sw_param offset="0xf8000b00" start="7" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CTRL_VREF_PULLUP_EN">
<name>VREF_PULLUP_EN</name>
<desc>Enables internal pullup. 0 - no pullup. 1 - pullup.</desc>
<sw_param offset="0xf8000b00" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CTRL_VREF_EN">
<name>VREF_EN</name>
<desc>Enables VREF internal generator</desc>
<sw_param offset="0xf8000b00" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_CMOS18_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000b04" start="31" end="28" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_CMOS18_m_nslew_slow">
<name>m_nslew_slow</name>
<desc>Skew</desc>
<sw_param offset="0xf8000b04" start="27" end="25" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_CMOS18_m_nslew_fast">
<name>m_nslew_fast</name>
<desc>Skew</desc>
<sw_param offset="0xf8000b04" start="24" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_CMOS18_m_pslew_slow">
<name>m_pslew_slow</name>
<desc>Skew</desc>
<sw_param offset="0xf8000b04" start="21" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_CMOS18_m_pslew_fast">
<name>m_pslew_fast</name>
<desc>Skew</desc>
<sw_param offset="0xf8000b04" start="18" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_CMOS18_m_ndrv_slow">
<name>m_ndrv_slow</name>
<desc>N Drive for slow mode</desc>
<sw_param offset="0xf8000b04" start="15" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_CMOS18_m_ndrv_fast">
<name>m_ndrv_fast</name>
<desc>N Drive for fast mode</desc>
<sw_param offset="0xf8000b04" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_CMOS18_m_pdrv_slow">
<name>m_pdrv_slow</name>
<desc>P Drive for slow mode</desc>
<sw_param offset="0xf8000b04" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_CMOS18_m_pdrv_fast">
<name>m_pdrv_fast</name>
<desc>P Drive for fast mode</desc>
<sw_param offset="0xf8000b04" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_CMOS25_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000b08" start="31" end="28" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_CMOS25_m_nslew_slow">
<name>m_nslew_slow</name>
<desc>Skew</desc>
<sw_param offset="0xf8000b08" start="27" end="25" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_CMOS25_m_nslew_fast">
<name>m_nslew_fast</name>
<desc>Skew</desc>
<sw_param offset="0xf8000b08" start="24" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_CMOS25_m_pslew_slow">
<name>m_pslew_slow</name>
<desc>Skew</desc>
<sw_param offset="0xf8000b08" start="21" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_CMOS25_m_pslew_fast">
<name>m_pslew_fast</name>
<desc>Skew</desc>
<sw_param offset="0xf8000b08" start="18" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_CMOS25_m_ndrv_slow">
<name>m_ndrv_slow</name>
<desc>N Drive for slow mode</desc>
<sw_param offset="0xf8000b08" start="15" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_CMOS25_m_ndrv_fast">
<name>m_ndrv_fast</name>
<desc>N Drive for fast mode</desc>
<sw_param offset="0xf8000b08" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_CMOS25_m_pdrv_slow">
<name>m_pdrv_slow</name>
<desc>P Drive for slow mode</desc>
<sw_param offset="0xf8000b08" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_CMOS25_m_pdrv_fast">
<name>m_pdrv_fast</name>
<desc>P Drive for fast mode</desc>
<sw_param offset="0xf8000b08" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_CMOS33_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000b0c" start="31" end="28" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_CMOS33_m_nslew_slow">
<name>m_nslew_slow</name>
<desc>Skew</desc>
<sw_param offset="0xf8000b0c" start="27" end="25" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_CMOS33_m_nslew_fast">
<name>m_nslew_fast</name>
<desc>Skew</desc>
<sw_param offset="0xf8000b0c" start="24" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_CMOS33_m_pslew_slow">
<name>m_pslew_slow</name>
<desc>Skew</desc>
<sw_param offset="0xf8000b0c" start="21" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_CMOS33_m_pslew_fast">
<name>m_pslew_fast</name>
<desc>Skew</desc>
<sw_param offset="0xf8000b0c" start="18" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_CMOS33_m_ndrv_slow">
<name>m_ndrv_slow</name>
<desc>N Drive for slow mode</desc>
<sw_param offset="0xf8000b0c" start="15" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_CMOS33_m_ndrv_fast">
<name>m_ndrv_fast</name>
<desc>N Drive for fast mode</desc>
<sw_param offset="0xf8000b0c" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_CMOS33_m_pdrv_slow">
<name>m_pdrv_slow</name>
<desc>P Drive for slow mode</desc>
<sw_param offset="0xf8000b0c" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_CMOS33_m_pdrv_fast">
<name>m_pdrv_fast</name>
<desc>P Drive for fast mode</desc>
<sw_param offset="0xf8000b0c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_LVTTL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000b10" start="31" end="28" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_LVTTL_m_nslew_slow">
<name>m_nslew_slow</name>
<desc>Skew</desc>
<sw_param offset="0xf8000b10" start="27" end="25" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_LVTTL_m_nslew_fast">
<name>m_nslew_fast</name>
<desc>Skew</desc>
<sw_param offset="0xf8000b10" start="24" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_LVTTL_m_pslew_slow">
<name>m_pslew_slow</name>
<desc>Skew</desc>
<sw_param offset="0xf8000b10" start="21" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_LVTTL_m_pslew_fast">
<name>m_pslew_fast</name>
<desc>Skew</desc>
<sw_param offset="0xf8000b10" start="18" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_LVTTL_m_ndrv_slow">
<name>m_ndrv_slow</name>
<desc>N Drive for slow mode</desc>
<sw_param offset="0xf8000b10" start="15" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_LVTTL_m_ndrv_fast">
<name>m_ndrv_fast</name>
<desc>N Drive for fast mode</desc>
<sw_param offset="0xf8000b10" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_LVTTL_m_pdrv_slow">
<name>m_pdrv_slow</name>
<desc>P Drive for slow mode</desc>
<sw_param offset="0xf8000b10" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_LVTTL_m_pdrv_fast">
<name>m_pdrv_fast</name>
<desc>P Drive for fast mode</desc>
<sw_param offset="0xf8000b10" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_HSTL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000b14" start="31" end="28" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_HSTL_m_nslew_slow">
<name>m_nslew_slow</name>
<desc>Skew</desc>
<sw_param offset="0xf8000b14" start="27" end="25" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_HSTL_m_nslew_fast">
<name>m_nslew_fast</name>
<desc>Skew</desc>
<sw_param offset="0xf8000b14" start="24" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_HSTL_m_pslew_slow">
<name>m_pslew_slow</name>
<desc>Skew</desc>
<sw_param offset="0xf8000b14" start="21" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_HSTL_m_pslew_fast">
<name>m_pslew_fast</name>
<desc>Skew</desc>
<sw_param offset="0xf8000b14" start="18" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_HSTL_m_ndrv_slow">
<name>m_ndrv_slow</name>
<desc>N Drive for slow mode</desc>
<sw_param offset="0xf8000b14" start="15" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_HSTL_m_ndrv_fast">
<name>m_ndrv_fast</name>
<desc>N Drive for fast mode</desc>
<sw_param offset="0xf8000b14" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_HSTL_m_pdrv_slow">
<name>m_pdrv_slow</name>
<desc>P Drive for slow mode</desc>
<sw_param offset="0xf8000b14" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_CFG_HSTL_m_pdrv_fast">
<name>m_pdrv_fast</name>
<desc>P Drive for fast mode</desc>
<sw_param offset="0xf8000b14" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_DRVR_BIAS_CTRL_RB_VCFG">
<name>RB_VCFG</name>
<desc>This is the right BANK's VCFG (Read Only)</desc>
<sw_param offset="0xf8000b18" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_DRVR_BIAS_CTRL_RB_DRVR_BIAS">
<name>RB_DRVR_BIAS</name>
<desc>This is the right BANK's driver bias control</desc>
<sw_param offset="0xf8000b18" start="30" end="16" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_DRVR_BIAS_CTRL_LB_VCFG">
<name>LB_VCFG</name>
<desc>This is the left BANK's VCFG (Read Only)</desc>
<sw_param offset="0xf8000b18" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_slcr_GPIOB_DRVR_BIAS_CTRL_LB_DRVR_BIAS">
<name>LB_DRVR_BIAS</name>
<desc>This is the left BANK's driver bias control</desc>
<sw_param offset="0xf8000b18" start="14" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_ADDR0_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8000b40" start="31" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_ADDR0_PULLUP_EN">
<name>PULLUP_EN</name>
<desc>enables pullup on output 0 - no pullup 1 - pullup enabled</desc>
<sw_param offset="0xf8000b40" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_ADDR0_OUTPUT_EN">
<name>OUTPUT_EN</name>
<desc>Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf</desc>
<sw_param offset="0xf8000b40" start="10" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_ADDR0_TERM_DISABLE_MODE">
<name>TERM_DISABLE_MODE</name>
<desc>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</desc>
<sw_param offset="0xf8000b40" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_ADDR0_IBUF_DISABLE_MODE">
<name>IBUF_DISABLE_MODE</name>
<desc>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</desc>
<sw_param offset="0xf8000b40" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_ADDR0_DCR_TYPE">
<name>DCR_TYPE</name>
<desc>DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)</desc>
<sw_param offset="0xf8000b40" start="6" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_ADDR0_TERM_EN">
<name>TERM_EN</name>
<desc>Tri State Termination Enabled 0 - disabled 1 - enabled</desc>
<sw_param offset="0xf8000b40" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_ADDR0_DCI_UPDATE">
<name>DCI_UPDATE</name>
<desc>DCI Update Enabled 0 - disabled 1 - enabled</desc>
<sw_param offset="0xf8000b40" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_ADDR0_INP_TYPE">
<name>INP_TYPE</name>
<desc>Input buffer controls.
00 - Input off, reads 0.
01 - Vref based differential reciever for SSTL, HSTL.
10 - Differential input reciever.
11- LVCMOS reviever.</desc>
<sw_param offset="0xf8000b40" start="2" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_ADDR0_INP_POWER">
<name>INP_POWER</name>
<desc>Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.</desc>
<sw_param offset="0xf8000b40" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_ADDR1_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8000b44" start="31" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_ADDR1_PULLUP_EN">
<name>PULLUP_EN</name>
<desc>enables pullup on output 0 - no pullup 1 - pullup enabled</desc>
<sw_param offset="0xf8000b44" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_ADDR1_OUTPUT_EN">
<name>OUTPUT_EN</name>
<desc>Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf</desc>
<sw_param offset="0xf8000b44" start="10" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_ADDR1_TERM_DISABLE_MODE">
<name>TERM_DISABLE_MODE</name>
<desc>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</desc>
<sw_param offset="0xf8000b44" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_ADDR1_IBUF_DISABLE_MODE">
<name>IBUF_DISABLE_MODE</name>
<desc>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</desc>
<sw_param offset="0xf8000b44" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_ADDR1_DCR_TYPE">
<name>DCR_TYPE</name>
<desc>DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)</desc>
<sw_param offset="0xf8000b44" start="6" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_ADDR1_TERM_EN">
<name>TERM_EN</name>
<desc>Tri State Termination Enabled 0 - disabled 1 - enabled</desc>
<sw_param offset="0xf8000b44" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_ADDR1_DCI_UPDATE">
<name>DCI_UPDATE</name>
<desc>DCI Update Enabled 0 - disabled 1 - enabled</desc>
<sw_param offset="0xf8000b44" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_ADDR1_INP_TYPE">
<name>INP_TYPE</name>
<desc>Input buffer controls.
00 - Input off, reads 0.
01 - Vref based differential reciever for SSTL, HSTL.
10 - Differential input reciever.
11- LVCMOS reviever.</desc>
<sw_param offset="0xf8000b44" start="2" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_ADDR1_INP_POWER">
<name>INP_POWER</name>
<desc>Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.</desc>
<sw_param offset="0xf8000b44" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DATA0_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8000b48" start="31" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DATA0_PULLUP_EN">
<name>PULLUP_EN</name>
<desc>enables pullup on output 0 - no pullup 1 - pullup enabled</desc>
<sw_param offset="0xf8000b48" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DATA0_OUTPUT_EN">
<name>OUTPUT_EN</name>
<desc>Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf</desc>
<sw_param offset="0xf8000b48" start="10" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DATA0_TERM_DISABLE_MODE">
<name>TERM_DISABLE_MODE</name>
<desc>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</desc>
<sw_param offset="0xf8000b48" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DATA0_IBUF_DISABLE_MODE">
<name>IBUF_DISABLE_MODE</name>
<desc>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</desc>
<sw_param offset="0xf8000b48" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DATA0_DCR_TYPE">
<name>DCR_TYPE</name>
<desc>DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)</desc>
<sw_param offset="0xf8000b48" start="6" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DATA0_TERM_EN">
<name>TERM_EN</name>
<desc>Tri State Termination Enabled 0 - disabled 1 - enabled</desc>
<sw_param offset="0xf8000b48" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DATA0_DCI_UPDATE">
<name>DCI_UPDATE</name>
<desc>DCI Update Enabled 0 - disabled 1 - enabled</desc>
<sw_param offset="0xf8000b48" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DATA0_INP_TYPE">
<name>INP_TYPE</name>
<desc>Input buffer controls.
00 - Input off, reads 0.
01 - Vref based differential reciever for SSTL, HSTL.
10 - Differential input reciever.
11- LVCMOS reviever.</desc>
<sw_param offset="0xf8000b48" start="2" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DATA0_INP_POWER">
<name>INP_POWER</name>
<desc>Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.</desc>
<sw_param offset="0xf8000b48" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DATA1_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8000b4c" start="31" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DATA1_PULLUP_EN">
<name>PULLUP_EN</name>
<desc>enables pullup on output 0 - no pullup 1 - pullup enabled</desc>
<sw_param offset="0xf8000b4c" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DATA1_OUTPUT_EN">
<name>OUTPUT_EN</name>
<desc>Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf</desc>
<sw_param offset="0xf8000b4c" start="10" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DATA1_TERM_DISABLE_MODE">
<name>TERM_DISABLE_MODE</name>
<desc>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</desc>
<sw_param offset="0xf8000b4c" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DATA1_IBUF_DISABLE_MODE">
<name>IBUF_DISABLE_MODE</name>
<desc>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</desc>
<sw_param offset="0xf8000b4c" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DATA1_DCR_TYPE">
<name>DCR_TYPE</name>
<desc>DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)</desc>
<sw_param offset="0xf8000b4c" start="6" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DATA1_TERM_EN">
<name>TERM_EN</name>
<desc>Tri State Termination Enabled 0 - disabled 1 - enabled</desc>
<sw_param offset="0xf8000b4c" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DATA1_DCI_UPDATE">
<name>DCI_UPDATE</name>
<desc>DCI Update Enabled 0 - disabled 1 - enabled</desc>
<sw_param offset="0xf8000b4c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DATA1_INP_TYPE">
<name>INP_TYPE</name>
<desc>Input buffer controls.
00 - Input off, reads 0.
01 - Vref based differential reciever for SSTL, HSTL.
10 - Differential input reciever.
11- LVCMOS reviever.</desc>
<sw_param offset="0xf8000b4c" start="2" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DATA1_INP_POWER">
<name>INP_POWER</name>
<desc>Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.</desc>
<sw_param offset="0xf8000b4c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DIFF0_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8000b50" start="31" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DIFF0_PULLUP_EN">
<name>PULLUP_EN</name>
<desc>enables pullup on output 0 - no pullup 1 - pullup enabled</desc>
<sw_param offset="0xf8000b50" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DIFF0_OUTPUT_EN">
<name>OUTPUT_EN</name>
<desc>Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf</desc>
<sw_param offset="0xf8000b50" start="10" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DIFF0_TERM_DISABLE_MODE">
<name>TERM_DISABLE_MODE</name>
<desc>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</desc>
<sw_param offset="0xf8000b50" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DIFF0_IBUF_DISABLE_MODE">
<name>IBUF_DISABLE_MODE</name>
<desc>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</desc>
<sw_param offset="0xf8000b50" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DIFF0_DCR_TYPE">
<name>DCR_TYPE</name>
<desc>DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)</desc>
<sw_param offset="0xf8000b50" start="6" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DIFF0_TERM_EN">
<name>TERM_EN</name>
<desc>Tri State Termination Enabled 0 - disabled 1 - enabled</desc>
<sw_param offset="0xf8000b50" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DIFF0_DCI_UPDATE">
<name>DCI_UPDATE</name>
<desc>DCI Update Enabled 0 - disabled 1 - enabled</desc>
<sw_param offset="0xf8000b50" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DIFF0_INP_TYPE">
<name>INP_TYPE</name>
<desc>Input buffer controls.
00 - Input off, reads 0.
01 - Vref based differential reciever for SSTL, HSTL.
10 - Differential input reciever.
11- LVCMOS reviever.</desc>
<sw_param offset="0xf8000b50" start="2" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DIFF0_INP_POWER">
<name>INP_POWER</name>
<desc>Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.</desc>
<sw_param offset="0xf8000b50" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DIFF1_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8000b54" start="31" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DIFF1_PULLUP_EN">
<name>PULLUP_EN</name>
<desc>enables pullup on output 0 - no pullup 1 - pullup enabled</desc>
<sw_param offset="0xf8000b54" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DIFF1_OUTPUT_EN">
<name>OUTPUT_EN</name>
<desc>Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf</desc>
<sw_param offset="0xf8000b54" start="10" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DIFF1_TERM_DISABLE_MODE">
<name>TERM_DISABLE_MODE</name>
<desc>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</desc>
<sw_param offset="0xf8000b54" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DIFF1_IBUF_DISABLE_MODE">
<name>IBUF_DISABLE_MODE</name>
<desc>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</desc>
<sw_param offset="0xf8000b54" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DIFF1_DCR_TYPE">
<name>DCR_TYPE</name>
<desc>DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)</desc>
<sw_param offset="0xf8000b54" start="6" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DIFF1_TERM_EN">
<name>TERM_EN</name>
<desc>Tri State Termination Enabled 0 - disabled 1 - enabled</desc>
<sw_param offset="0xf8000b54" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DIFF1_DCI_UPDATE">
<name>DCI_UPDATE</name>
<desc>DCI Update Enabled 0 - disabled 1 - enabled</desc>
<sw_param offset="0xf8000b54" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DIFF1_INP_TYPE">
<name>INP_TYPE</name>
<desc>Input buffer controls.
00 - Input off, reads 0.
01 - Vref based differential reciever for SSTL, HSTL.
10 - Differential input reciever.
11- LVCMOS reviever.</desc>
<sw_param offset="0xf8000b54" start="2" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DIFF1_INP_POWER">
<name>INP_POWER</name>
<desc>Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.</desc>
<sw_param offset="0xf8000b54" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_CLOCK_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8000b58" start="31" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_CLOCK_PULLUP_EN">
<name>PULLUP_EN</name>
<desc>enables pullup on output 0 - no pullup 1 - pullup enabled</desc>
<sw_param offset="0xf8000b58" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_CLOCK_OUTPUT_EN">
<name>OUTPUT_EN</name>
<desc>Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf</desc>
<sw_param offset="0xf8000b58" start="10" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_CLOCK_TERM_DISABLE_MODE">
<name>TERM_DISABLE_MODE</name>
<desc>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</desc>
<sw_param offset="0xf8000b58" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_CLOCK_IBUF_DISABLE_MODE">
<name>IBUF_DISABLE_MODE</name>
<desc>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</desc>
<sw_param offset="0xf8000b58" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_CLOCK_DCR_TYPE">
<name>DCR_TYPE</name>
<desc>DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)</desc>
<sw_param offset="0xf8000b58" start="6" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_CLOCK_TERM_EN">
<name>TERM_EN</name>
<desc>Tri State Termination Enabled 0 - disabled 1 - enabled</desc>
<sw_param offset="0xf8000b58" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_CLOCK_DCI_UPDATE">
<name>DCI_UPDATE</name>
<desc>DCI Update Enabled 0 - disabled 1 - enabled</desc>
<sw_param offset="0xf8000b58" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_CLOCK_INP_TYPE">
<name>INP_TYPE</name>
<desc>Input buffer controls.
00 - Input off, reads 0.
01 - Vref based differential reciever for SSTL, HSTL.
10 - Differential input reciever.
11- LVCMOS reviever.</desc>
<sw_param offset="0xf8000b58" start="2" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_CLOCK_INP_POWER">
<name>INP_POWER</name>
<desc>Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.</desc>
<sw_param offset="0xf8000b58" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DRIVE_SLEW_ADDR_RTERM">
<name>RTERM</name>
<desc>Program the rterm</desc>
<sw_param offset="0xf8000b5c" start="31" end="27" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DRIVE_SLEW_ADDR_GTL">
<name>GTL</name>
<desc>Test Control 000 - Normal Operation 001 : 111 - Test Mode</desc>
<sw_param offset="0xf8000b5c" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DRIVE_SLEW_ADDR_SLEW_N">
<name>SLEW_N</name>
<desc>Programs the DDRIO slew rate for the N devices</desc>
<sw_param offset="0xf8000b5c" start="23" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DRIVE_SLEW_ADDR_SLEW_P">
<name>SLEW_P</name>
<desc>Programs the DDRIO slew rate for the P devices</desc>
<sw_param offset="0xf8000b5c" start="18" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DRIVE_SLEW_ADDR_DRIVE_N">
<name>DRIVE_N</name>
<desc>Programs the DDRIO drive strength for the N devices</desc>
<sw_param offset="0xf8000b5c" start="13" end="7" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DRIVE_SLEW_ADDR_DRIVE_P">
<name>DRIVE_P</name>
<desc>Programs the DDRIO drive strength for the P devices</desc>
<sw_param offset="0xf8000b5c" start="6" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DRIVE_SLEW_DATA_RTERM">
<name>RTERM</name>
<desc>Program the rterm</desc>
<sw_param offset="0xf8000b60" start="31" end="27" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DRIVE_SLEW_DATA_GTL">
<name>GTL</name>
<desc>Test Control 000 - Normal Operation 001 : 111 - Test Mode</desc>
<sw_param offset="0xf8000b60" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DRIVE_SLEW_DATA_SLEW_N">
<name>SLEW_N</name>
<desc>Programs the DDRIO slew rate for the N devices</desc>
<sw_param offset="0xf8000b60" start="23" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DRIVE_SLEW_DATA_SLEW_P">
<name>SLEW_P</name>
<desc>Programs the DDRIO slew rate for the P devices</desc>
<sw_param offset="0xf8000b60" start="18" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DRIVE_SLEW_DATA_DRIVE_N">
<name>DRIVE_N</name>
<desc>Programs the DDRIO drive strength for the N devices</desc>
<sw_param offset="0xf8000b60" start="13" end="7" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DRIVE_SLEW_DATA_DRIVE_P">
<name>DRIVE_P</name>
<desc>Programs the DDRIO drive strength for the P devices</desc>
<sw_param offset="0xf8000b60" start="6" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DRIVE_SLEW_DIFF_RTERM">
<name>RTERM</name>
<desc>Program the rterm</desc>
<sw_param offset="0xf8000b64" start="31" end="27" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DRIVE_SLEW_DIFF_GTL">
<name>GTL</name>
<desc>Test Control 000 - Normal Operation 001 : 111 - Test Mode</desc>
<sw_param offset="0xf8000b64" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DRIVE_SLEW_DIFF_SLEW_N">
<name>SLEW_N</name>
<desc>Programs the DDRIO slew rate for the N devices</desc>
<sw_param offset="0xf8000b64" start="23" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DRIVE_SLEW_DIFF_SLEW_P">
<name>SLEW_P</name>
<desc>Programs the DDRIO slew rate for the P devices</desc>
<sw_param offset="0xf8000b64" start="18" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DRIVE_SLEW_DIFF_DRIVE_N">
<name>DRIVE_N</name>
<desc>Programs the DDRIO drive strength for the N devices</desc>
<sw_param offset="0xf8000b64" start="13" end="7" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DRIVE_SLEW_DIFF_DRIVE_P">
<name>DRIVE_P</name>
<desc>Programs the DDRIO drive strength for the P devices</desc>
<sw_param offset="0xf8000b64" start="6" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DRIVE_SLEW_CLOCK_RTERM">
<name>RTERM</name>
<desc>Program the rterm</desc>
<sw_param offset="0xf8000b68" start="31" end="27" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DRIVE_SLEW_CLOCK_GTL">
<name>GTL</name>
<desc>Test Control 000 - Normal Operation 001 : 111 - Test Mode</desc>
<sw_param offset="0xf8000b68" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DRIVE_SLEW_CLOCK_SLEW_N">
<name>SLEW_N</name>
<desc>Programs the DDRIO slew rate for the N devices</desc>
<sw_param offset="0xf8000b68" start="23" end="19" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DRIVE_SLEW_CLOCK_SLEW_P">
<name>SLEW_P</name>
<desc>Programs the DDRIO slew rate for the P devices</desc>
<sw_param offset="0xf8000b68" start="18" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DRIVE_SLEW_CLOCK_DRIVE_N">
<name>DRIVE_N</name>
<desc>Programs the DDRIO drive strength for the N devices</desc>
<sw_param offset="0xf8000b68" start="13" end="7" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DRIVE_SLEW_CLOCK_DRIVE_P">
<name>DRIVE_P</name>
<desc>Programs the DDRIO drive strength for the P devices</desc>
<sw_param offset="0xf8000b68" start="6" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DDR_CTRL_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8000b6c" start="31" end="15" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DDR_CTRL_CKE_PULLUP_EN">
<name>CKE_PULLUP_EN</name>
<desc>Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors</desc>
<sw_param offset="0xf8000b6c" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DDR_CTRL_DRST_B_PULLUP_EN">
<name>DRST_B_PULLUP_EN</name>
<desc>Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors</desc>
<sw_param offset="0xf8000b6c" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DDR_CTRL_REFIO_PULLUP_EN">
<name>REFIO_PULLUP_EN</name>
<desc>Enables VRP,VRN pull-up resistors 0 -no pull-up 1 - enable pull-up resistors</desc>
<sw_param offset="0xf8000b6c" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DDR_CTRL_REFIO_TSEN">
<name>REFIO_TSEN</name>
<desc>Enables VRP,VRN as normal outputs 00 - VRP/VRN not used 11 - VRP/VRN used as normal IO</desc>
<sw_param offset="0xf8000b6c" start="11" end="10" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DDR_CTRL_REFIO_EN">
<name>REFIO_EN</name>
<desc>Enables VRP,VRN 0 - VRP/VRN not used 1 - VRP/VRN used as refio</desc>
<sw_param offset="0xf8000b6c" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DDR_CTRL_VREF_PULLUP_EN">
<name>VREF_PULLUP_EN</name>
<desc>Enables VREF pull-up resistors X0 - Disable VREF pull-up for lower 16 bits X1 - Enable VREF pull-up for lower 16 bits 0X - Disable VREF pull-up for upper 16 bits 1X - Enable VREF pull-up for upper 16 bits</desc>
<sw_param offset="0xf8000b6c" start="8" end="7" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DDR_CTRL_VREF_EXT_EN">
<name>VREF_EXT_EN</name>
<desc>Enables External VREF input X0 - Disable External VREF for lower 16 bits X1 - Enable External VREF for lower 16 bits 0X - Disable External VREF for upper 16 bits 1X - Enable External VREF for upper 16 bits</desc>
<sw_param offset="0xf8000b6c" start="6" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DDR_CTRL_VREF_SEL">
<name>VREF_SEL</name>
<desc>Specifies DDR IOB Vref generator output 0001 - VREF = 0.6V for LPDDR2 with 1.2V IO 0010 - VREF = 0.675V for LPDDR3 1.35 V IO 0100 - VREF = 0.75V for DDR3 with 1.5V IO 1000 - VREF = 0.90V for DDR2 with 1.8V IO</desc>
<sw_param offset="0xf8000b6c" start="4" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DDR_CTRL_VREF_INT_EN">
<name>VREF_INT_EN</name>
<desc>Enables VREF internal generator</desc>
<sw_param offset="0xf8000b6c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_CTRL_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000b70" start="31" end="27" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_CTRL_INT_DCI_EN">
<name>INT_DCI_EN</name>
<desc>Need explanation here</desc>
<sw_param offset="0xf8000b70" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_CTRL_TST_RST">
<name>TST_RST</name>
<desc>Emulate Reset</desc>
<sw_param offset="0xf8000b70" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_CTRL_TST_HLP">
<name>TST_HLP</name>
<desc>Emulate comparator output (VRP)</desc>
<sw_param offset="0xf8000b70" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_CTRL_TST_HLN">
<name>TST_HLN</name>
<desc>Emulate comparator output (VRN)</desc>
<sw_param offset="0xf8000b70" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_CTRL_TST_CLK">
<name>TST_CLK</name>
<desc>Emulate DCI clock</desc>
<sw_param offset="0xf8000b70" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_CTRL_INIT_COMPLETE">
<name>INIT_COMPLETE</name>
<desc>test Internal to IO bank</desc>
<sw_param offset="0xf8000b70" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_CTRL_UPDATE_CONTROL">
<name>UPDATE_CONTROL</name>
<desc>DCI Update</desc>
<sw_param offset="0xf8000b70" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_CTRL_PREF_OPT2">
<name>PREF_OPT2</name>
<desc>Reserved</desc>
<sw_param offset="0xf8000b70" start="19" end="17" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_CTRL_PREF_OPT1">
<name>PREF_OPT1</name>
<desc>Reserved</desc>
<sw_param offset="0xf8000b70" start="16" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_CTRL_NREF_OPT4">
<name>NREF_OPT4</name>
<desc>Reserved</desc>
<sw_param offset="0xf8000b70" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_CTRL_NREF_OPT2">
<name>NREF_OPT2</name>
<desc>Reserved</desc>
<sw_param offset="0xf8000b70" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_CTRL_NREF_OPT1">
<name>NREF_OPT1</name>
<desc>Reserved</desc>
<sw_param offset="0xf8000b70" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_CTRL_VRN_OUT">
<name>VRN_OUT</name>
<desc>VRN output value</desc>
<sw_param offset="0xf8000b70" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_CTRL_VRP_OUT">
<name>VRP_OUT</name>
<desc>VRP output value</desc>
<sw_param offset="0xf8000b70" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_CTRL_VRN_TRI">
<name>VRN_TRI</name>
<desc>VRN tristate value</desc>
<sw_param offset="0xf8000b70" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_CTRL_VRP_TRI">
<name>VRP_TRI</name>
<desc>VRP tristate value</desc>
<sw_param offset="0xf8000b70" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_CTRL_ENABLE">
<name>ENABLE</name>
<desc>1 if any iob's use a terminate type, or if dci test block used</desc>
<sw_param offset="0xf8000b70" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_CTRL_RESET">
<name>RESET</name>
<desc>At least toggle once to initialise flops in DCI system</desc>
<sw_param offset="0xf8000b70" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_STATUS_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8000b74" start="31" end="14" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_STATUS_DONE">
<name>DONE</name>
<desc>DCI done signal</desc>
<sw_param offset="0xf8000b74" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_STATUS_HL_P_B_INIT">
<name>HL_P_B_INIT</name>
<desc>dci test</desc>
<sw_param offset="0xf8000b74" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_STATUS_HL_N_B_INIT">
<name>HL_N_B_INIT</name>
<desc>dci test</desc>
<sw_param offset="0xf8000b74" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_STATUS_SCK">
<name>SCK</name>
<desc>Clock for Serial data</desc>
<sw_param offset="0xf8000b74" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_STATUS_REFIO_UPDATE">
<name>REFIO_UPDATE</name>
<desc>Update VRN/VRP</desc>
<sw_param offset="0xf8000b74" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_STATUS_NORP">
<name>NORP</name>
<desc>dci test</desc>
<sw_param offset="0xf8000b74" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_STATUS_IO_UPDATE">
<name>IO_UPDATE</name>
<desc>Update IO</desc>
<sw_param offset="0xf8000b74" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_STATUS_DATA">
<name>DATA</name>
<desc>Serial data</desc>
<sw_param offset="0xf8000b74" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_STATUS_ADDR">
<name>ADDR</name>
<desc>DCI address</desc>
<sw_param offset="0xf8000b74" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_STATUS_VRN_IN">
<name>VRN_IN</name>
<desc>Current Value of VRN IO</desc>
<sw_param offset="0xf8000b74" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_STATUS_VRP_IN">
<name>VRP_IN</name>
<desc>Current Value of VRP IO</desc>
<sw_param offset="0xf8000b74" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_slcr_DDRIOB_DCI_STATUS_LOCK">
<name>LOCK</name>
<desc>DCI Status input Read Only</desc>
<sw_param offset="0xf8000b74" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_spi1_Config_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0007000" start="31" end="18" />
</parameter>
<parameter uniqueid="ps7_spi1_Config_reg0_Modefail_gen_en">
<name>Modefail_gen_en</name>
<desc>ModeFail Generation Enable
1 = enable
0 = disable</desc>
<sw_param offset="0xe0007000" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_spi1_Config_reg0_Man_start_com">
<name>Man_start_com</name>
<desc>Manual Start Command
1 = start transmission of data
0 = don't care</desc>
<sw_param offset="0xe0007000" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_spi1_Config_reg0_Man_start_en">
<name>Man_start_en</name>
<desc>Manual Start Enable
1 = enables maual start
0 = auto mode</desc>
<sw_param offset="0xe0007000" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_spi1_Config_reg0_Manual_CS">
<name>Manual_CS</name>
<desc>Manual CS
1 = manual CS mode
0 = auto mode</desc>
<sw_param offset="0xe0007000" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_spi1_Config_reg0_CS">
<name>CS</name>
<desc>Peripheral chip select lines
xxx0 - slave 0 selected
xx01 - slave 1 selected
x011 - slave 2 selected
0111 - slave 3 selected
1111 - No slave selected</desc>
<sw_param offset="0xe0007000" start="13" end="10" />
</parameter>
<parameter uniqueid="ps7_spi1_Config_reg0_PERI_SEL">
<name>PERI_SEL</name>
<desc>Peripheral select decode
1 = allow external 4-to-16 decode
0 = only 1 of 4 selects</desc>
<sw_param offset="0xe0007000" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_spi1_Config_reg0_REF_CLK">
<name>REF_CLK</name>
<desc>Master reference clock select
1 = use ext_clk
0 = use SPI REFERENCE CLOCK</desc>
<sw_param offset="0xe0007000" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_spi1_Config_reg0_FIFO_WIDTH">
<name>FIFO_WIDTH</name>
<desc>FIFO width
00 = 8bits
01 = 16bits
10 = 24bits
11 = 32bits</desc>
<sw_param offset="0xe0007000" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_spi1_Config_reg0_BAUD_RATE_DIV">
<name>BAUD_RATE_DIV</name>
<desc>Master mode baud rate divisor
000 = not supported
001 = divide by 4
010 = divide by 8
011 = divide by 16
100 = divide by 32
101 = divide by 64
110 = divide by 128
111 = divide by 256</desc>
<sw_param offset="0xe0007000" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_spi1_Config_reg0_CLK_PH">
<name>CLK_PH</name>
<desc>Clock phase
1 = the SPI clock is inactive outside the word
0 = the SPI clock is active outside the word</desc>
<sw_param offset="0xe0007000" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_spi1_Config_reg0_CLK_POL">
<name>CLK_POL</name>
<desc>Clock polarity outside SPI word
1 = the SPI clock is quiescent high
0 = the SPI clock is quiescent low</desc>
<sw_param offset="0xe0007000" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_spi1_Config_reg0_MODE_SEL">
<name>MODE_SEL</name>
<desc>Mode select
1 = the SPI is in master mode
0 = the SPI is in slave mode</desc>
<sw_param offset="0xe0007000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_spi1_Intr_status_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0007004" start="31" end="7" />
</parameter>
<parameter uniqueid="ps7_spi1_Intr_status_reg0_TX_FIFO_underflow">
<name>TX_FIFO_underflow</name>
<desc>TX FIFO underflow
1 = underflow is detected
0 = no underflow has been detected</desc>
<sw_param offset="0xe0007004" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_spi1_Intr_status_reg0_RX_FIFO_full">
<name>RX_FIFO_full</name>
<desc>RX FIFO full
1 = FIFO is full
0 = FIFO is not full</desc>
<sw_param offset="0xe0007004" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_spi1_Intr_status_reg0_RX_FIFO_not_empty">
<name>RX_FIFO_not_empty</name>
<desc>RX FIFO not empty
1 = FIFO has more than or equal to THRESHOLD entries
0 = FIFO has less than RX THRESHOLD entries</desc>
<sw_param offset="0xe0007004" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_spi1_Intr_status_reg0_TX_FIFO_full">
<name>TX_FIFO_full</name>
<desc>TX FIFO full
1 = FIFO is full
0 = FIFO is not full</desc>
<sw_param offset="0xe0007004" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_spi1_Intr_status_reg0_TX_FIFO_not_full">
<name>TX_FIFO_not_full</name>
<desc>TX FIFO not full
1 = FIFO has less than THRESHOLD entries
0 = FIFO has more than or equal toTHRESHOLD entries</desc>
<sw_param offset="0xe0007004" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_spi1_Intr_status_reg0_MODE_FAIL">
<name>MODE_FAIL</name>
<desc>ModeFail interrupt
1 = a mode fault has occurred
0 = no mode fault has been detected</desc>
<sw_param offset="0xe0007004" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_spi1_Intr_status_reg0_RX_OVERFLOW">
<name>RX_OVERFLOW</name>
<desc>Receive Overflow interrupt
1 = overflow occured
0 = no overflow occurred</desc>
<sw_param offset="0xe0007004" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_spi1_Intrpt_en_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0007008" start="31" end="7" />
</parameter>
<parameter uniqueid="ps7_spi1_Intrpt_en_reg0_TX_FIFO_underflow">
<name>TX_FIFO_underflow</name>
<desc>TX FIFO underflow
enable
1 = enable the interrupt
0 = no effect</desc>
<sw_param offset="0xe0007008" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_spi1_Intrpt_en_reg0_RX_FIFO_full">
<name>RX_FIFO_full</name>
<desc>RX FIFO full
enable
1 = enable the interrupt
0 = no effect</desc>
<sw_param offset="0xe0007008" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_spi1_Intrpt_en_reg0_RX_FIFO_not_empty">
<name>RX_FIFO_not_empty</name>
<desc>RX FIFO not empty
enable
1 = enable the interrupt
0 = no effect</desc>
<sw_param offset="0xe0007008" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_spi1_Intrpt_en_reg0_TX_FIFO_full">
<name>TX_FIFO_full</name>
<desc>TX FIFO full
enable
1 = enable the interrupt
0 = no effect</desc>
<sw_param offset="0xe0007008" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_spi1_Intrpt_en_reg0_TX_FIFO_not_full">
<name>TX_FIFO_not_full</name>
<desc>TX FIFO not full
enable
1 = enable the interrupt
0 = no effect</desc>
<sw_param offset="0xe0007008" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_spi1_Intrpt_en_reg0_MODE_FAIL">
<name>MODE_FAIL</name>
<desc>ModeFail interrupt
enable
1 = enable the interrupt
0 = no effect</desc>
<sw_param offset="0xe0007008" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_spi1_Intrpt_en_reg0_RX_OVERFLOW">
<name>RX_OVERFLOW</name>
<desc>Receive Overflow interrupt enable
1 = enable the interrupt
0 = no effect</desc>
<sw_param offset="0xe0007008" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_spi1_Intrpt_dis_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe000700c" start="31" end="7" />
</parameter>
<parameter uniqueid="ps7_spi1_Intrpt_dis_reg0_TX_FIFO_underflow">
<name>TX_FIFO_underflow</name>
<desc>TX FIFO underflow
enable
1 = disables the interrupt
0 = no effect</desc>
<sw_param offset="0xe000700c" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_spi1_Intrpt_dis_reg0_RX_FIFO_full">
<name>RX_FIFO_full</name>
<desc>RX FIFO full
enable
1 = disables the interrupt
0 = no effect</desc>
<sw_param offset="0xe000700c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_spi1_Intrpt_dis_reg0_RX_FIFO_not_empty">
<name>RX_FIFO_not_empty</name>
<desc>RX FIFO not empty
enable
1 = disables the interrupt
0 = no effect</desc>
<sw_param offset="0xe000700c" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_spi1_Intrpt_dis_reg0_TX_FIFO_full">
<name>TX_FIFO_full</name>
<desc>TX FIFO full
enable
1 = disables the interrupt
0 = no effect</desc>
<sw_param offset="0xe000700c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_spi1_Intrpt_dis_reg0_TX_FIFO_not_full">
<name>TX_FIFO_not_full</name>
<desc>TX FIFO not full
enable
1 = disables the interrupt
0 = no effect</desc>
<sw_param offset="0xe000700c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_spi1_Intrpt_dis_reg0_MODE_FAIL">
<name>MODE_FAIL</name>
<desc>ModeFail interrupt
enable
1 = disables the interrupt
0 = no effect</desc>
<sw_param offset="0xe000700c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_spi1_Intrpt_dis_reg0_RX_OVERFLOW">
<name>RX_OVERFLOW</name>
<desc>Receive Overflow interrupt enable
1 = disables the interrupt
0 = no effect</desc>
<sw_param offset="0xe000700c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_spi1_Intrpt_mask_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0007010" start="31" end="7" />
</parameter>
<parameter uniqueid="ps7_spi1_Intrpt_mask_reg0_TX_FIFO_underflow">
<name>TX_FIFO_underflow</name>
<desc>TX FIFO underflow
enable
1 = interrupt is disabled
0 = interrupt is enabled</desc>
<sw_param offset="0xe0007010" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_spi1_Intrpt_mask_reg0_RX_FIFO_full">
<name>RX_FIFO_full</name>
<desc>RX FIFO full
enable
1 = interrupt is disabled
0 = interrupt is enabled</desc>
<sw_param offset="0xe0007010" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_spi1_Intrpt_mask_reg0_RX_FIFO_not_empty">
<name>RX_FIFO_not_empty</name>
<desc>RX FIFO not empty
enable
1 = interrupt is disabled
0 = interrupt is enabled</desc>
<sw_param offset="0xe0007010" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_spi1_Intrpt_mask_reg0_TX_FIFO_full">
<name>TX_FIFO_full</name>
<desc>TX FIFO full
enable
1 = interrupt is disabled
0 = interrupt is enabled</desc>
<sw_param offset="0xe0007010" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_spi1_Intrpt_mask_reg0_TX_FIFO_not_full">
<name>TX_FIFO_not_full</name>
<desc>TX FIFO not full
enable
1 = interrupt is disabled
0 = interrupt is enabled</desc>
<sw_param offset="0xe0007010" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_spi1_Intrpt_mask_reg0_MODE_FAIL">
<name>MODE_FAIL</name>
<desc>ModeFail interrupt
enable
1 = interrupt is disabled
0 = interrupt is enabled</desc>
<sw_param offset="0xe0007010" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_spi1_Intrpt_mask_reg0_RX_OVERFLOW">
<name>RX_OVERFLOW</name>
<desc>Receive Overflow interrupt enable
1 = interrupt is disabled
0 = interrupt is enabled</desc>
<sw_param offset="0xe0007010" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_spi1_En_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0007014" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_spi1_En_reg0_SPI_EN">
<name>SPI_EN</name>
<desc>SPI_Enable
1 = enable the SPI
0 = disable the SPI</desc>
<sw_param offset="0xe0007014" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_spi1_Delay_reg0_d_nss">
<name>d_nss</name>
<desc>Delay in SPI REFERENCE CLOCK or ext_clk cycles
for the length that the master mode chip select outputs are de-asserted between words when cpha=0.</desc>
<sw_param offset="0xe0007018" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_spi1_Delay_reg0_d_btwn">
<name>d_btwn</name>
<desc>Delay in SPI REFERENCE CLOCK or ext_clk cycles
between one chip select being de-activated and the
activation of another</desc>
<sw_param offset="0xe0007018" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_spi1_Delay_reg0_d_after">
<name>d_after</name>
<desc>Delay in SPI REFERENCE CLOCK or ext_clk cycles between last bit of current word and the first bit of the next word.</desc>
<sw_param offset="0xe0007018" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_spi1_Delay_reg0_d_int">
<name>d_int</name>
<desc>Added delay in SPI REFERENCE CLOCK or ext_clk
cycles between setting n_ss_out low and first bit
transfer.</desc>
<sw_param offset="0xe0007018" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_spi1_Tx_data_reg0_TX_FIFO_data">
<name>TX_FIFO_data</name>
<desc>Data to TX FIFO</desc>
<sw_param offset="0xe000701c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_spi1_Rx_data_reg0_RX_FIFO_data">
<name>RX_FIFO_data</name>
<desc>Data from TX FIFO</desc>
<sw_param offset="0xe0007020" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_spi1_Slave_Idle_count_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0007024" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_spi1_Slave_Idle_count_reg0_Slave_Idle_coun">
<name>Slave_Idle_coun</name>
<desc>SPI in slave mode detects a start only when the
external SPI master serial clock (sclk_in) is stable
(quiescent state) for SPI REFERENCE CLOCK cycles
specified by slave idle count register or when the SPI
is deselected.</desc>
<sw_param offset="0xe0007024" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_spi1_TX_thres_reg0_DEPTH_of_TX_FIFO">
<name>DEPTH_of_TX_FIFO</name>
<desc>Defines the level at which the TX FIFO not full interrupt is generated</desc>
<sw_param offset="0xe0007028" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_spi1_RX_thres_reg0_DEPTH_of_RX_FIFO">
<name>DEPTH_of_RX_FIFO</name>
<desc>Defines the level at which the RX FIFO not empty interrupt is generated</desc>
<sw_param offset="0xe000702c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_spi1_Mod_id_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe00070fc" start="31" end="25" />
</parameter>
<parameter uniqueid="ps7_spi1_Mod_id_reg0_module_ID">
<name>module_ID</name>
<desc>Module ID number</desc>
<sw_param offset="0xe00070fc" start="24" end="0" />
</parameter>
<parameter uniqueid="ps7_spi0_Config_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0006000" start="31" end="18" />
</parameter>
<parameter uniqueid="ps7_spi0_Config_reg0_Modefail_gen_en">
<name>Modefail_gen_en</name>
<desc>ModeFail Generation Enable
1 = enable
0 = disable</desc>
<sw_param offset="0xe0006000" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_spi0_Config_reg0_Man_start_com">
<name>Man_start_com</name>
<desc>Manual Start Command
1 = start transmission of data
0 = don't care</desc>
<sw_param offset="0xe0006000" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_spi0_Config_reg0_Man_start_en">
<name>Man_start_en</name>
<desc>Manual Start Enable
1 = enables maual start
0 = auto mode</desc>
<sw_param offset="0xe0006000" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_spi0_Config_reg0_Manual_CS">
<name>Manual_CS</name>
<desc>Manual CS
1 = manual CS mode
0 = auto mode</desc>
<sw_param offset="0xe0006000" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_spi0_Config_reg0_CS">
<name>CS</name>
<desc>Peripheral chip select lines
xxx0 - slave 0 selected
xx01 - slave 1 selected
x011 - slave 2 selected
0111 - slave 3 selected
1111 - No slave selected</desc>
<sw_param offset="0xe0006000" start="13" end="10" />
</parameter>
<parameter uniqueid="ps7_spi0_Config_reg0_PERI_SEL">
<name>PERI_SEL</name>
<desc>Peripheral select decode
1 = allow external 4-to-16 decode
0 = only 1 of 4 selects</desc>
<sw_param offset="0xe0006000" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_spi0_Config_reg0_REF_CLK">
<name>REF_CLK</name>
<desc>Master reference clock select
1 = use ext_clk
0 = use SPI REFERENCE CLOCK</desc>
<sw_param offset="0xe0006000" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_spi0_Config_reg0_FIFO_WIDTH">
<name>FIFO_WIDTH</name>
<desc>FIFO width
00 = 8bits
01 = 16bits
10 = 24bits
11 = 32bits</desc>
<sw_param offset="0xe0006000" start="7" end="6" />
</parameter>
<parameter uniqueid="ps7_spi0_Config_reg0_BAUD_RATE_DIV">
<name>BAUD_RATE_DIV</name>
<desc>Master mode baud rate divisor
000 = not supported
001 = divide by 4
010 = divide by 8
011 = divide by 16
100 = divide by 32
101 = divide by 64
110 = divide by 128
111 = divide by 256</desc>
<sw_param offset="0xe0006000" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_spi0_Config_reg0_CLK_PH">
<name>CLK_PH</name>
<desc>Clock phase
1 = the SPI clock is inactive outside the word
0 = the SPI clock is active outside the word</desc>
<sw_param offset="0xe0006000" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_spi0_Config_reg0_CLK_POL">
<name>CLK_POL</name>
<desc>Clock polarity outside SPI word
1 = the SPI clock is quiescent high
0 = the SPI clock is quiescent low</desc>
<sw_param offset="0xe0006000" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_spi0_Config_reg0_MODE_SEL">
<name>MODE_SEL</name>
<desc>Mode select
1 = the SPI is in master mode
0 = the SPI is in slave mode</desc>
<sw_param offset="0xe0006000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_spi0_Intr_status_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0006004" start="31" end="7" />
</parameter>
<parameter uniqueid="ps7_spi0_Intr_status_reg0_TX_FIFO_underflow">
<name>TX_FIFO_underflow</name>
<desc>TX FIFO underflow
1 = underflow is detected
0 = no underflow has been detected</desc>
<sw_param offset="0xe0006004" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_spi0_Intr_status_reg0_RX_FIFO_full">
<name>RX_FIFO_full</name>
<desc>RX FIFO full
1 = FIFO is full
0 = FIFO is not full</desc>
<sw_param offset="0xe0006004" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_spi0_Intr_status_reg0_RX_FIFO_not_empty">
<name>RX_FIFO_not_empty</name>
<desc>RX FIFO not empty
1 = FIFO has more than or equal to THRESHOLD entries
0 = FIFO has less than RX THRESHOLD entries</desc>
<sw_param offset="0xe0006004" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_spi0_Intr_status_reg0_TX_FIFO_full">
<name>TX_FIFO_full</name>
<desc>TX FIFO full
1 = FIFO is full
0 = FIFO is not full</desc>
<sw_param offset="0xe0006004" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_spi0_Intr_status_reg0_TX_FIFO_not_full">
<name>TX_FIFO_not_full</name>
<desc>TX FIFO not full
1 = FIFO has less than THRESHOLD entries
0 = FIFO has more than or equal toTHRESHOLD entries</desc>
<sw_param offset="0xe0006004" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_spi0_Intr_status_reg0_MODE_FAIL">
<name>MODE_FAIL</name>
<desc>ModeFail interrupt
1 = a mode fault has occurred
0 = no mode fault has been detected</desc>
<sw_param offset="0xe0006004" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_spi0_Intr_status_reg0_RX_OVERFLOW">
<name>RX_OVERFLOW</name>
<desc>Receive Overflow interrupt
1 = overflow occured
0 = no overflow occurred</desc>
<sw_param offset="0xe0006004" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_spi0_Intrpt_en_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0006008" start="31" end="7" />
</parameter>
<parameter uniqueid="ps7_spi0_Intrpt_en_reg0_TX_FIFO_underflow">
<name>TX_FIFO_underflow</name>
<desc>TX FIFO underflow
enable
1 = enable the interrupt
0 = no effect</desc>
<sw_param offset="0xe0006008" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_spi0_Intrpt_en_reg0_RX_FIFO_full">
<name>RX_FIFO_full</name>
<desc>RX FIFO full
enable
1 = enable the interrupt
0 = no effect</desc>
<sw_param offset="0xe0006008" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_spi0_Intrpt_en_reg0_RX_FIFO_not_empty">
<name>RX_FIFO_not_empty</name>
<desc>RX FIFO not empty
enable
1 = enable the interrupt
0 = no effect</desc>
<sw_param offset="0xe0006008" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_spi0_Intrpt_en_reg0_TX_FIFO_full">
<name>TX_FIFO_full</name>
<desc>TX FIFO full
enable
1 = enable the interrupt
0 = no effect</desc>
<sw_param offset="0xe0006008" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_spi0_Intrpt_en_reg0_TX_FIFO_not_full">
<name>TX_FIFO_not_full</name>
<desc>TX FIFO not full
enable
1 = enable the interrupt
0 = no effect</desc>
<sw_param offset="0xe0006008" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_spi0_Intrpt_en_reg0_MODE_FAIL">
<name>MODE_FAIL</name>
<desc>ModeFail interrupt
enable
1 = enable the interrupt
0 = no effect</desc>
<sw_param offset="0xe0006008" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_spi0_Intrpt_en_reg0_RX_OVERFLOW">
<name>RX_OVERFLOW</name>
<desc>Receive Overflow interrupt enable
1 = enable the interrupt
0 = no effect</desc>
<sw_param offset="0xe0006008" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_spi0_Intrpt_dis_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe000600c" start="31" end="7" />
</parameter>
<parameter uniqueid="ps7_spi0_Intrpt_dis_reg0_TX_FIFO_underflow">
<name>TX_FIFO_underflow</name>
<desc>TX FIFO underflow
enable
1 = disables the interrupt
0 = no effect</desc>
<sw_param offset="0xe000600c" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_spi0_Intrpt_dis_reg0_RX_FIFO_full">
<name>RX_FIFO_full</name>
<desc>RX FIFO full
enable
1 = disables the interrupt
0 = no effect</desc>
<sw_param offset="0xe000600c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_spi0_Intrpt_dis_reg0_RX_FIFO_not_empty">
<name>RX_FIFO_not_empty</name>
<desc>RX FIFO not empty
enable
1 = disables the interrupt
0 = no effect</desc>
<sw_param offset="0xe000600c" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_spi0_Intrpt_dis_reg0_TX_FIFO_full">
<name>TX_FIFO_full</name>
<desc>TX FIFO full
enable
1 = disables the interrupt
0 = no effect</desc>
<sw_param offset="0xe000600c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_spi0_Intrpt_dis_reg0_TX_FIFO_not_full">
<name>TX_FIFO_not_full</name>
<desc>TX FIFO not full
enable
1 = disables the interrupt
0 = no effect</desc>
<sw_param offset="0xe000600c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_spi0_Intrpt_dis_reg0_MODE_FAIL">
<name>MODE_FAIL</name>
<desc>ModeFail interrupt
enable
1 = disables the interrupt
0 = no effect</desc>
<sw_param offset="0xe000600c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_spi0_Intrpt_dis_reg0_RX_OVERFLOW">
<name>RX_OVERFLOW</name>
<desc>Receive Overflow interrupt enable
1 = disables the interrupt
0 = no effect</desc>
<sw_param offset="0xe000600c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_spi0_Intrpt_mask_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0006010" start="31" end="7" />
</parameter>
<parameter uniqueid="ps7_spi0_Intrpt_mask_reg0_TX_FIFO_underflow">
<name>TX_FIFO_underflow</name>
<desc>TX FIFO underflow
enable
1 = interrupt is disabled
0 = interrupt is enabled</desc>
<sw_param offset="0xe0006010" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_spi0_Intrpt_mask_reg0_RX_FIFO_full">
<name>RX_FIFO_full</name>
<desc>RX FIFO full
enable
1 = interrupt is disabled
0 = interrupt is enabled</desc>
<sw_param offset="0xe0006010" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_spi0_Intrpt_mask_reg0_RX_FIFO_not_empty">
<name>RX_FIFO_not_empty</name>
<desc>RX FIFO not empty
enable
1 = interrupt is disabled
0 = interrupt is enabled</desc>
<sw_param offset="0xe0006010" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_spi0_Intrpt_mask_reg0_TX_FIFO_full">
<name>TX_FIFO_full</name>
<desc>TX FIFO full
enable
1 = interrupt is disabled
0 = interrupt is enabled</desc>
<sw_param offset="0xe0006010" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_spi0_Intrpt_mask_reg0_TX_FIFO_not_full">
<name>TX_FIFO_not_full</name>
<desc>TX FIFO not full
enable
1 = interrupt is disabled
0 = interrupt is enabled</desc>
<sw_param offset="0xe0006010" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_spi0_Intrpt_mask_reg0_MODE_FAIL">
<name>MODE_FAIL</name>
<desc>ModeFail interrupt
enable
1 = interrupt is disabled
0 = interrupt is enabled</desc>
<sw_param offset="0xe0006010" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_spi0_Intrpt_mask_reg0_RX_OVERFLOW">
<name>RX_OVERFLOW</name>
<desc>Receive Overflow interrupt enable
1 = interrupt is disabled
0 = interrupt is enabled</desc>
<sw_param offset="0xe0006010" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_spi0_En_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0006014" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_spi0_En_reg0_SPI_EN">
<name>SPI_EN</name>
<desc>SPI_Enable
1 = enable the SPI
0 = disable the SPI</desc>
<sw_param offset="0xe0006014" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_spi0_Delay_reg0_d_nss">
<name>d_nss</name>
<desc>Delay in SPI REFERENCE CLOCK or ext_clk cycles
for the length that the master mode chip select outputs are de-asserted between words when cpha=0.</desc>
<sw_param offset="0xe0006018" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_spi0_Delay_reg0_d_btwn">
<name>d_btwn</name>
<desc>Delay in SPI REFERENCE CLOCK or ext_clk cycles
between one chip select being de-activated and the
activation of another</desc>
<sw_param offset="0xe0006018" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_spi0_Delay_reg0_d_after">
<name>d_after</name>
<desc>Delay in SPI REFERENCE CLOCK or ext_clk cycles between last bit of current word and the first bit of the next word.</desc>
<sw_param offset="0xe0006018" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_spi0_Delay_reg0_d_int">
<name>d_int</name>
<desc>Added delay in SPI REFERENCE CLOCK or ext_clk
cycles between setting n_ss_out low and first bit
transfer.</desc>
<sw_param offset="0xe0006018" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_spi0_Tx_data_reg0_TX_FIFO_data">
<name>TX_FIFO_data</name>
<desc>Data to TX FIFO</desc>
<sw_param offset="0xe000601c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_spi0_Rx_data_reg0_RX_FIFO_data">
<name>RX_FIFO_data</name>
<desc>Data from TX FIFO</desc>
<sw_param offset="0xe0006020" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_spi0_Slave_Idle_count_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe0006024" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_spi0_Slave_Idle_count_reg0_Slave_Idle_coun">
<name>Slave_Idle_coun</name>
<desc>SPI in slave mode detects a start only when the
external SPI master serial clock (sclk_in) is stable
(quiescent state) for SPI REFERENCE CLOCK cycles
specified by slave idle count register or when the SPI
is deselected.</desc>
<sw_param offset="0xe0006024" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_spi0_TX_thres_reg0_DEPTH_of_TX_FIFO">
<name>DEPTH_of_TX_FIFO</name>
<desc>Defines the level at which the TX FIFO not full interrupt is generated</desc>
<sw_param offset="0xe0006028" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_spi0_RX_thres_reg0_DEPTH_of_RX_FIFO">
<name>DEPTH_of_RX_FIFO</name>
<desc>Defines the level at which the RX FIFO not empty interrupt is generated</desc>
<sw_param offset="0xe000602c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_spi0_Mod_id_reg0_reserved">
<name>reserved</name>
<desc>Reserved, read as zero, ignored on write.</desc>
<sw_param offset="0xe00060fc" start="31" end="25" />
</parameter>
<parameter uniqueid="ps7_spi0_Mod_id_reg0_module_ID">
<name>module_ID</name>
<desc>Module ID number</desc>
<sw_param offset="0xe00060fc" start="24" end="0" />
</parameter>
<parameter uniqueid="ps7_swdt_MODE_ZKEY">
<name>ZKEY</name>
<desc>Zero access key - writes to the zero mode register are only valid if this field is set to 0xABC; this field is write only.</desc>
<sw_param offset="0xf8005000" start="23" end="12" />
</parameter>
<parameter uniqueid="ps7_swdt_MODE_EXTLN">
<name>EXTLN</name>
<desc>External signal length - selects the number of pclk cycles during which the external
signal is held active after it is invoked:
000 = 2
001 = 4
010 = 8
011 = 16
100 = 32
101 = 64
110 = 128
111 = 256</desc>
<sw_param offset="0xf8005000" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_swdt_MODE_IRQLN">
<name>IRQLN</name>
<desc>Interrupt request length - selects the number of pclk cycles during which an interrupt request is held active after it is invoked:
00 = 4
01 = 8
10 = 16
11 = 32</desc>
<sw_param offset="0xf8005000" start="8" end="7" />
</parameter>
<parameter uniqueid="ps7_swdt_MODE_RSTLN">
<name>RSTLN</name>
<desc>Reset length - selects the number of clock cycles (pclk) during which the internal system reset is held active after it is invoked:
000 = 2
001 = 4
010 = 8
011 = 16
100 = 32
101 = 64
110 = 128 111 = 256
Note: The minimum number of cycles required for an AMBA reset is two.</desc>
<sw_param offset="0xf8005000" start="6" end="4" />
</parameter>
<parameter uniqueid="ps7_swdt_MODE_EXTEN">
<name>EXTEN</name>
<desc>External signal enable - if set, the watchdog will issue an external request when the counter reaches zero, if WDEN = 1.</desc>
<sw_param offset="0xf8005000" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_swdt_MODE_IRQEN">
<name>IRQEN</name>
<desc>Interrupt request enable - if set, the watchdog will issue an interrupt request when the counter reaches zero, if WDEN = 1.</desc>
<sw_param offset="0xf8005000" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_swdt_MODE_RSTEN">
<name>RSTEN</name>
<desc>Reset enable - if set, the watchdog will issue an internal reset when the counter reaches zero, if WDEN = 1.</desc>
<sw_param offset="0xf8005000" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_swdt_MODE_WDEN">
<name>WDEN</name>
<desc>Watchdog enable - if set, the watchdog is enabled and can generate any signals that are enabled.</desc>
<sw_param offset="0xf8005000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_swdt_CONTROL_CKEY">
<name>CKEY</name>
<desc>Counter access key - writes to the control register are only valid if this field is set to 0x248; this field is write only.</desc>
<sw_param offset="0xf8005004" start="25" end="14" />
</parameter>
<parameter uniqueid="ps7_swdt_CONTROL_CRV">
<name>CRV</name>
<desc>Counter restart value - the counter is restarted with the value 0xNNNFFF, where NNN is the value of this field.</desc>
<sw_param offset="0xf8005004" start="13" end="2" />
</parameter>
<parameter uniqueid="ps7_swdt_CONTROL_CLKSEL">
<name>CLKSEL</name>
<desc>Counter clock prescale - selects the prescaler division ratio:
00 = pclk divided by 8
01 = pclk divided by 64
10 = pclk divided by 256
11 = pclk divided by 4096
Note: If a restart signal is received the prescaler should be reset.</desc>
<sw_param offset="0xf8005004" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_swdt_RESTART_RSTKEY">
<name>RSTKEY</name>
<desc>Restart key - the watchdog is restarted if this field is set to the value 0x1999</desc>
<sw_param offset="0xf8005008" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_swdt_STATUS_WDZ">
<name>WDZ</name>
<desc>set when the watchdog reaches zero count</desc>
<sw_param offset="0xf800500c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_DSR_reserved">
<name>reserved</name>
<desc>Reserved, read undefined</desc>
<sw_param offset="0xf8004000" start="31" end="10" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_DSR_DNS">
<name>DNS</name>
<desc>Provides the security status of the DMA manager thread:
0 = DMA manager operates in the Secure state
1 = DMA manager operates in the Non-secure state.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004000" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_DSR_Wakeup_event">
<name>Wakeup_event</name>
<desc>When the DMA manager thread executes a DMAWFE instruction, it waits for the following event to occur:
b00000 = event[0]
b00001 = event[1]
b00010 = event[2]
.
.
.
b11111 = event[31].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004000" start="8" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_DSR_DMA_status">
<name>DMA_status</name>
<desc>The operating state of the DMA manager:
b0000 = Stopped
b0001 = Executing
b0010 = Cache miss
b0011 = Updating PC
b0100 = Waiting for event
b0101-b1110 = reserved
b1111 = Faulting.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004000" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_DPC_pc_mgr">
<name>pc_mgr</name>
<desc>Program counter for the DMA manager thread
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004004" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_INTEN_event_irq_select">
<name>event_irq_select</name>
<desc>Program the appropriate bit to control how the DMAC responds when it executes DMASEV:
Bit [N] = 0 If the DMAC executes DMASEV for the event-interrupt resource N then the DMAC signals
event N to all of the threads. Set bit [N] to 0 if your system design does not use irq[N] to
signal an interrupt request.
Bit [N] = 1 If the DMAC executes DMASEV for the event-interrupt resource N then the DMAC sets
irq[N] HIGH. Set bit [N] to 1 if your system design requires irq[N] to signal an interrupt
request.
This bit-field has the following special access attributes:
 srw: During secure access, it is read write.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsrw: During non-secure access, if thread is non-secure, it is read write.
</desc>
<sw_param offset="0xf8004020" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_INT_EVENT_RIS_DMASEV_active">
<name>DMASEV_active</name>
<desc>Returns the status of the event-interrupt resources:
Bit [N] = 0 Event N is inactive or irq[N] is LOW.
Bit [N] = 1 Event N is active or irq[N] is HIGH.
Note
When the DMAC executes a DMASEV N instruction to send event N, the INTEN Register
controls whether the DMAC:
signals an interrupt using the appropriate irq
sends the event to all of the threads.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004024" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_INTMIS_irq_status">
<name>irq_status</name>
<desc>Provides the status of the interrupts that are active in the DMAC:
Bit [N] = 0 Interrupt N is inactive and therefore irq[N] is LOW.
Bit [N] = 1 Interrupt N is active and therefore irq[N] is HIGH.
Note
You must use the INTCLR Register to set bit [N] to 0, see Interrupt Clear Register.
Note
Bit [N] is 0 if the INTEN Register programs DMASEV to signal an event
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004028" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_INTCLR_irq_clr">
<name>irq_clr</name>
<desc>Controls the clearing of the irq outputs:
Bit [N] = 0 The status of irq[N] does not change.
Bit [N] = 1 The DMAC sets irq[N] LOW if the INTEN Register programs the DMAC to signal an interrupt.
Otherwise, the status of irq[N] does not change.
This bit-field has the following special access attributes:
 swo: During secure access, it is  write only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnswo: During non-secure access, if thread is non-secure, it is write only.
</desc>
<sw_param offset="0xf800402c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FSRD_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf8004030" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FSRD_fs_mgr">
<name>fs_mgr</name>
<desc>Provides the fault status of the DMA manager. Read as:
0 = the DMA manager thread is not in the Faulting state
1 = the DMA manager thread is in the Faulting state.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004030" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FSRC_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf8004034" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FSRC_fault_status">
<name>fault_status</name>
<desc>Each bit provides the fault status of the corresponding channel. Read as:
Bit [N] = 0 No fault is present on DMA channel N.
Bit [N] = 1 DMA channel N is in the Faulting or Faulting completing state.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004034" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTRD_reserved">
<name>reserved</name>
<desc>read undefined</desc>
<sw_param offset="0xf8004038" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTRD_dbg_instr">
<name>dbg_instr</name>
<desc>If the DMA manager aborts, this bit indicates whether the erroneous instruction was read from the
system memory or from the debug interface:
0 = instruction that generated an abort was read from system memory
1 = instruction that generated an abort was read from the debug interface.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004038" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTRD_reserved_1">
<name>reserved_1</name>
<desc>read undefined</desc>
<sw_param offset="0xf8004038" start="29" end="17" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTRD_instr_fetch_err">
<name>instr_fetch_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA manager
performs an instruction fetch:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004038" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTRD_reserved_2">
<name>reserved_2</name>
<desc>read undefined</desc>
<sw_param offset="0xf8004038" start="15" end="6" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTRD_mgr_evnt_err">
<name>mgr_evnt_err</name>
<desc>Indicates whether the DMA manager was attempting to execute DMAWFE or DMASEV with inappropriate
security permissions:
0 = the DMA manager has appropriate security to execute DMAWFE or DMASEV
1 = a DMA manager thread in the Non-secure state attempted to execute either:
DMAWFE to wait for a secure event
H18DMASEV to create a secure event or secure interrupt.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004038" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTRD_dmago_err">
<name>dmago_err</name>
<desc>Indicates whether the DMA manager was attempting to execute DMAGO with inappropriate security
permissions:
0 = the DMA manager has appropriate security to execute DMAGO
1 = a DMA manager thread in the Non-secure state attempted to execute DMAGO to create a DMA channel
operating in the Secure state.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004038" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTRD_reserved_3">
<name>reserved_3</name>
<desc>read undefined</desc>
<sw_param offset="0xf8004038" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTRD_operand_invalid">
<name>operand_invalid</name>
<desc>Indicates whether the DMA manager was attempting to execute an instruction operand that was not valid
for the configuration of the DMAC:
0 = valid operand
1 = invalid operand.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004038" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTRD_undef_instr">
<name>undef_instr</name>
<desc>Indicates whether the DMA manager was attempting to execute an undefined instruction:
0 = defined instruction
1 = undefined instruction.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004038" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR0_lockup_err">
<name>lockup_err</name>
<desc>Indicates whether the DMA channel has locked-up because of resource starvation:
0 = DMA channel has adequate resources
1 = DMA channel has locked-up because of insufficient resources.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004040" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR0_dbg_instr">
<name>dbg_instr</name>
<desc>If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the
system memory or from the debug interface:
0 = instruction that generated an abort was read from system memory
1 = instruction that generated an abort was read from the debug interface.
This fault is an imprecise abort but the bit is only valid when a precise abort occurs.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004040" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR0_reserved">
<name>reserved</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004040" start="29" end="19" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR0_data_read_err">
<name>data_read_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs a data read:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004040" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR0_data_write_err">
<name>data_write_err</name>
<desc>Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel
thread performs a data write:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004040" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR0_instr_fetch_err">
<name>instr_fetch_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs an instruction fetch:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004040" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR0_reserved_1">
<name>reserved_1</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004040" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR0_st_data_unavailable">
<name>st_data_unavailable</name>
<desc>Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST:
0 = MFIFO contains all the data to enable the DMAST to complete
1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004040" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR0_mfifo_err">
<name>mfifo_err</name>
<desc>Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST.
Depending on the instruction:
DMALD 0 = MFIFO contains sufficient space
1 = MFIFO is too small to hold the data that DMALD requires.
DMAST 0 = MFIFO contains sufficient data
1 = MFIFO is too small to store the data to enable DMAST to complete.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004040" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR0_reserved_2">
<name>reserved_2</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004040" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR0_ch_rdwr_err">
<name>ch_rdwr_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn
Register to perform a secure read or secure write:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004040" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR0_ch_periph_err">
<name>ch_periph_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP,
DMASTP, or DMAFLUSHP with inappropriate security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFP to wait for a secure peripheral
DMALDP or DMASTP to notify a secure peripheral
DMAFLUSHP to flush a secure peripheral.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004040" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR0_ch_evnt_err">
<name>ch_evnt_err</name>
<desc>Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate
security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFE to wait for a secure event
DMASEV to create a secure event or secure interrupt.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004040" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR0_reserved_3">
<name>reserved_3</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004040" start="4" end="2" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR0_operand_invalid">
<name>operand_invalid</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an instruction operand that was
not valid for the configuration of the DMAC:
0 = valid operand
1 = invalid operand.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004040" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR0_undef_instr">
<name>undef_instr</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an undefined instruction:
0 = defined instruction
1 = undefined instruction.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004040" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR1_lockup_err">
<name>lockup_err</name>
<desc>Indicates whether the DMA channel has locked-up because of resource starvation:
0 = DMA channel has adequate resources
1 = DMA channel has locked-up because of insufficient resources.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004044" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR1_dbg_instr">
<name>dbg_instr</name>
<desc>If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the
system memory or from the debug interface:
0 = instruction that generated an abort was read from system memory
1 = instruction that generated an abort was read from the debug interface.
This fault is an imprecise abort but the bit is only valid when a precise abort occurs.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004044" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR1_reserved">
<name>reserved</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004044" start="29" end="19" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR1_data_read_err">
<name>data_read_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs a data read:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004044" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR1_data_write_err">
<name>data_write_err</name>
<desc>Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel
thread performs a data write:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004044" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR1_instr_fetch_err">
<name>instr_fetch_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs an instruction fetch:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004044" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR1_reserved_1">
<name>reserved_1</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004044" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR1_st_data_unavailable">
<name>st_data_unavailable</name>
<desc>Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST:
0 = MFIFO contains all the data to enable the DMAST to complete
1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004044" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR1_mfifo_err">
<name>mfifo_err</name>
<desc>Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST.
Depending on the instruction:
DMALD 0 = MFIFO contains sufficient space
1 = MFIFO is too small to hold the data that DMALD requires.
DMAST 0 = MFIFO contains sufficient data
1 = MFIFO is too small to store the data to enable DMAST to complete.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004044" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR1_reserved_2">
<name>reserved_2</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004044" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR1_ch_rdwr_err">
<name>ch_rdwr_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn
Register to perform a secure read or secure write:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004044" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR1_ch_periph_err">
<name>ch_periph_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP,
DMASTP, or DMAFLUSHP with inappropriate security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFP to wait for a secure peripheral
DMALDP or DMASTP to notify a secure peripheral
DMAFLUSHP to flush a secure peripheral.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004044" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR1_ch_evnt_err">
<name>ch_evnt_err</name>
<desc>Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate
security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFE to wait for a secure event
DMASEV to create a secure event or secure interrupt.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004044" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR1_reserved_3">
<name>reserved_3</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004044" start="4" end="2" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR1_operand_invalid">
<name>operand_invalid</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an instruction operand that was
not valid for the configuration of the DMAC:
0 = valid operand
1 = invalid operand.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004044" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR1_undef_instr">
<name>undef_instr</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an undefined instruction:
0 = defined instruction
1 = undefined instruction.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004044" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR2_lockup_err">
<name>lockup_err</name>
<desc>Indicates whether the DMA channel has locked-up because of resource starvation:
0 = DMA channel has adequate resources
1 = DMA channel has locked-up because of insufficient resources.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004048" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR2_dbg_instr">
<name>dbg_instr</name>
<desc>If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the
system memory or from the debug interface:
0 = instruction that generated an abort was read from system memory
1 = instruction that generated an abort was read from the debug interface.
This fault is an imprecise abort but the bit is only valid when a precise abort occurs.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004048" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR2_reserved">
<name>reserved</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004048" start="29" end="19" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR2_data_read_err">
<name>data_read_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs a data read:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004048" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR2_data_write_err">
<name>data_write_err</name>
<desc>Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel
thread performs a data write:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004048" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR2_instr_fetch_err">
<name>instr_fetch_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs an instruction fetch:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004048" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR2_reserved_1">
<name>reserved_1</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004048" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR2_st_data_unavailable">
<name>st_data_unavailable</name>
<desc>Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST:
0 = MFIFO contains all the data to enable the DMAST to complete
1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004048" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR2_mfifo_err">
<name>mfifo_err</name>
<desc>Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST.
Depending on the instruction:
DMALD 0 = MFIFO contains sufficient space
1 = MFIFO is too small to hold the data that DMALD requires.
DMAST 0 = MFIFO contains sufficient data
1 = MFIFO is too small to store the data to enable DMAST to complete.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004048" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR2_reserved_2">
<name>reserved_2</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004048" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR2_ch_rdwr_err">
<name>ch_rdwr_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn
Register to perform a secure read or secure write:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004048" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR2_ch_periph_err">
<name>ch_periph_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP,
DMASTP, or DMAFLUSHP with inappropriate security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFP to wait for a secure peripheral
DMALDP or DMASTP to notify a secure peripheral
DMAFLUSHP to flush a secure peripheral.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004048" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR2_ch_evnt_err">
<name>ch_evnt_err</name>
<desc>Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate
security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFE to wait for a secure event
DMASEV to create a secure event or secure interrupt.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004048" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR2_reserved_3">
<name>reserved_3</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004048" start="4" end="2" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR2_operand_invalid">
<name>operand_invalid</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an instruction operand that was
not valid for the configuration of the DMAC:
0 = valid operand
1 = invalid operand.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004048" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR2_undef_instr">
<name>undef_instr</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an undefined instruction:
0 = defined instruction
1 = undefined instruction.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004048" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR3_lockup_err">
<name>lockup_err</name>
<desc>Indicates whether the DMA channel has locked-up because of resource starvation:
0 = DMA channel has adequate resources
1 = DMA channel has locked-up because of insufficient resources.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800404c" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR3_dbg_instr">
<name>dbg_instr</name>
<desc>If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the
system memory or from the debug interface:
0 = instruction that generated an abort was read from system memory
1 = instruction that generated an abort was read from the debug interface.
This fault is an imprecise abort but the bit is only valid when a precise abort occurs.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800404c" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR3_reserved">
<name>reserved</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800404c" start="29" end="19" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR3_data_read_err">
<name>data_read_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs a data read:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800404c" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR3_data_write_err">
<name>data_write_err</name>
<desc>Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel
thread performs a data write:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800404c" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR3_instr_fetch_err">
<name>instr_fetch_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs an instruction fetch:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800404c" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR3_reserved_1">
<name>reserved_1</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800404c" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR3_st_data_unavailable">
<name>st_data_unavailable</name>
<desc>Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST:
0 = MFIFO contains all the data to enable the DMAST to complete
1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800404c" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR3_mfifo_err">
<name>mfifo_err</name>
<desc>Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST.
Depending on the instruction:
DMALD 0 = MFIFO contains sufficient space
1 = MFIFO is too small to hold the data that DMALD requires.
DMAST 0 = MFIFO contains sufficient data
1 = MFIFO is too small to store the data to enable DMAST to complete.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800404c" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR3_reserved_2">
<name>reserved_2</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800404c" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR3_ch_rdwr_err">
<name>ch_rdwr_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn
Register to perform a secure read or secure write:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800404c" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR3_ch_periph_err">
<name>ch_periph_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP,
DMASTP, or DMAFLUSHP with inappropriate security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFP to wait for a secure peripheral
DMALDP or DMASTP to notify a secure peripheral
DMAFLUSHP to flush a secure peripheral.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800404c" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR3_ch_evnt_err">
<name>ch_evnt_err</name>
<desc>Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate
security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFE to wait for a secure event
DMASEV to create a secure event or secure interrupt.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800404c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR3_reserved_3">
<name>reserved_3</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800404c" start="4" end="2" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR3_operand_invalid">
<name>operand_invalid</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an instruction operand that was
not valid for the configuration of the DMAC:
0 = valid operand
1 = invalid operand.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800404c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR3_undef_instr">
<name>undef_instr</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an undefined instruction:
0 = defined instruction
1 = undefined instruction.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800404c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR4_lockup_err">
<name>lockup_err</name>
<desc>Indicates whether the DMA channel has locked-up because of resource starvation:
0 = DMA channel has adequate resources
1 = DMA channel has locked-up because of insufficient resources.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004050" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR4_dbg_instr">
<name>dbg_instr</name>
<desc>If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the
system memory or from the debug interface:
0 = instruction that generated an abort was read from system memory
1 = instruction that generated an abort was read from the debug interface.
This fault is an imprecise abort but the bit is only valid when a precise abort occurs.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004050" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR4_reserved">
<name>reserved</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004050" start="29" end="19" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR4_data_read_err">
<name>data_read_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs a data read:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004050" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR4_data_write_err">
<name>data_write_err</name>
<desc>Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel
thread performs a data write:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004050" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR4_instr_fetch_err">
<name>instr_fetch_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs an instruction fetch:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004050" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR4_reserved_1">
<name>reserved_1</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004050" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR4_st_data_unavailable">
<name>st_data_unavailable</name>
<desc>Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST:
0 = MFIFO contains all the data to enable the DMAST to complete
1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004050" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR4_mfifo_err">
<name>mfifo_err</name>
<desc>Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST.
Depending on the instruction:
DMALD 0 = MFIFO contains sufficient space
1 = MFIFO is too small to hold the data that DMALD requires.
DMAST 0 = MFIFO contains sufficient data
1 = MFIFO is too small to store the data to enable DMAST to complete.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004050" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR4_reserved_2">
<name>reserved_2</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004050" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR4_ch_rdwr_err">
<name>ch_rdwr_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn
Register to perform a secure read or secure write:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004050" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR4_ch_periph_err">
<name>ch_periph_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP,
DMASTP, or DMAFLUSHP with inappropriate security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFP to wait for a secure peripheral
DMALDP or DMASTP to notify a secure peripheral
DMAFLUSHP to flush a secure peripheral.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004050" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR4_ch_evnt_err">
<name>ch_evnt_err</name>
<desc>Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate
security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFE to wait for a secure event
DMASEV to create a secure event or secure interrupt.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004050" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR4_reserved_3">
<name>reserved_3</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004050" start="4" end="2" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR4_operand_invalid">
<name>operand_invalid</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an instruction operand that was
not valid for the configuration of the DMAC:
0 = valid operand
1 = invalid operand.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004050" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR4_undef_instr">
<name>undef_instr</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an undefined instruction:
0 = defined instruction
1 = undefined instruction.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004050" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR5_lockup_err">
<name>lockup_err</name>
<desc>Indicates whether the DMA channel has locked-up because of resource starvation:
0 = DMA channel has adequate resources
1 = DMA channel has locked-up because of insufficient resources.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004054" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR5_dbg_instr">
<name>dbg_instr</name>
<desc>If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the
system memory or from the debug interface:
0 = instruction that generated an abort was read from system memory
1 = instruction that generated an abort was read from the debug interface.
This fault is an imprecise abort but the bit is only valid when a precise abort occurs.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004054" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR5_reserved">
<name>reserved</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004054" start="29" end="19" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR5_data_read_err">
<name>data_read_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs a data read:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004054" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR5_data_write_err">
<name>data_write_err</name>
<desc>Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel
thread performs a data write:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004054" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR5_instr_fetch_err">
<name>instr_fetch_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs an instruction fetch:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004054" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR5_reserved_1">
<name>reserved_1</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004054" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR5_st_data_unavailable">
<name>st_data_unavailable</name>
<desc>Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST:
0 = MFIFO contains all the data to enable the DMAST to complete
1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004054" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR5_mfifo_err">
<name>mfifo_err</name>
<desc>Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST.
Depending on the instruction:
DMALD 0 = MFIFO contains sufficient space
1 = MFIFO is too small to hold the data that DMALD requires.
DMAST 0 = MFIFO contains sufficient data
1 = MFIFO is too small to store the data to enable DMAST to complete.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004054" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR5_reserved_2">
<name>reserved_2</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004054" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR5_ch_rdwr_err">
<name>ch_rdwr_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn
Register to perform a secure read or secure write:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004054" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR5_ch_periph_err">
<name>ch_periph_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP,
DMASTP, or DMAFLUSHP with inappropriate security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFP to wait for a secure peripheral
DMALDP or DMASTP to notify a secure peripheral
DMAFLUSHP to flush a secure peripheral.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004054" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR5_ch_evnt_err">
<name>ch_evnt_err</name>
<desc>Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate
security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFE to wait for a secure event
DMASEV to create a secure event or secure interrupt.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004054" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR5_reserved_3">
<name>reserved_3</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004054" start="4" end="2" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR5_operand_invalid">
<name>operand_invalid</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an instruction operand that was
not valid for the configuration of the DMAC:
0 = valid operand
1 = invalid operand.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004054" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR5_undef_instr">
<name>undef_instr</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an undefined instruction:
0 = defined instruction
1 = undefined instruction.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004054" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR6_lockup_err">
<name>lockup_err</name>
<desc>Indicates whether the DMA channel has locked-up because of resource starvation:
0 = DMA channel has adequate resources
1 = DMA channel has locked-up because of insufficient resources.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004058" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR6_dbg_instr">
<name>dbg_instr</name>
<desc>If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the
system memory or from the debug interface:
0 = instruction that generated an abort was read from system memory
1 = instruction that generated an abort was read from the debug interface.
This fault is an imprecise abort but the bit is only valid when a precise abort occurs.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004058" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR6_reserved">
<name>reserved</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004058" start="29" end="19" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR6_data_read_err">
<name>data_read_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs a data read:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004058" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR6_data_write_err">
<name>data_write_err</name>
<desc>Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel
thread performs a data write:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004058" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR6_instr_fetch_err">
<name>instr_fetch_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs an instruction fetch:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004058" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR6_reserved_1">
<name>reserved_1</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004058" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR6_st_data_unavailable">
<name>st_data_unavailable</name>
<desc>Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST:
0 = MFIFO contains all the data to enable the DMAST to complete
1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004058" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR6_mfifo_err">
<name>mfifo_err</name>
<desc>Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST.
Depending on the instruction:
DMALD 0 = MFIFO contains sufficient space
1 = MFIFO is too small to hold the data that DMALD requires.
DMAST 0 = MFIFO contains sufficient data
1 = MFIFO is too small to store the data to enable DMAST to complete.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004058" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR6_reserved_2">
<name>reserved_2</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004058" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR6_ch_rdwr_err">
<name>ch_rdwr_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn
Register to perform a secure read or secure write:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004058" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR6_ch_periph_err">
<name>ch_periph_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP,
DMASTP, or DMAFLUSHP with inappropriate security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFP to wait for a secure peripheral
DMALDP or DMASTP to notify a secure peripheral
DMAFLUSHP to flush a secure peripheral.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004058" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR6_ch_evnt_err">
<name>ch_evnt_err</name>
<desc>Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate
security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFE to wait for a secure event
DMASEV to create a secure event or secure interrupt.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004058" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR6_reserved_3">
<name>reserved_3</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004058" start="4" end="2" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR6_operand_invalid">
<name>operand_invalid</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an instruction operand that was
not valid for the configuration of the DMAC:
0 = valid operand
1 = invalid operand.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004058" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR6_undef_instr">
<name>undef_instr</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an undefined instruction:
0 = defined instruction
1 = undefined instruction.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004058" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR7_lockup_err">
<name>lockup_err</name>
<desc>Indicates whether the DMA channel has locked-up because of resource starvation:
0 = DMA channel has adequate resources
1 = DMA channel has locked-up because of insufficient resources.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800405c" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR7_dbg_instr">
<name>dbg_instr</name>
<desc>If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the
system memory or from the debug interface:
0 = instruction that generated an abort was read from system memory
1 = instruction that generated an abort was read from the debug interface.
This fault is an imprecise abort but the bit is only valid when a precise abort occurs.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800405c" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR7_reserved">
<name>reserved</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800405c" start="29" end="19" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR7_data_read_err">
<name>data_read_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs a data read:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800405c" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR7_data_write_err">
<name>data_write_err</name>
<desc>Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel
thread performs a data write:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800405c" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR7_instr_fetch_err">
<name>instr_fetch_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs an instruction fetch:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800405c" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR7_reserved_1">
<name>reserved_1</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800405c" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR7_st_data_unavailable">
<name>st_data_unavailable</name>
<desc>Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST:
0 = MFIFO contains all the data to enable the DMAST to complete
1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800405c" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR7_mfifo_err">
<name>mfifo_err</name>
<desc>Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST.
Depending on the instruction:
DMALD 0 = MFIFO contains sufficient space
1 = MFIFO is too small to hold the data that DMALD requires.
DMAST 0 = MFIFO contains sufficient data
1 = MFIFO is too small to store the data to enable DMAST to complete.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800405c" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR7_reserved_2">
<name>reserved_2</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800405c" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR7_ch_rdwr_err">
<name>ch_rdwr_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn
Register to perform a secure read or secure write:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800405c" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR7_ch_periph_err">
<name>ch_periph_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP,
DMASTP, or DMAFLUSHP with inappropriate security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFP to wait for a secure peripheral
DMALDP or DMASTP to notify a secure peripheral
DMAFLUSHP to flush a secure peripheral.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800405c" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR7_ch_evnt_err">
<name>ch_evnt_err</name>
<desc>Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate
security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFE to wait for a secure event
DMASEV to create a secure event or secure interrupt.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800405c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR7_reserved_3">
<name>reserved_3</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800405c" start="4" end="2" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR7_operand_invalid">
<name>operand_invalid</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an instruction operand that was
not valid for the configuration of the DMAC:
0 = valid operand
1 = invalid operand.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800405c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_FTR7_undef_instr">
<name>undef_instr</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an undefined instruction:
0 = defined instruction
1 = undefined instruction.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800405c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR0_reserved">
<name>reserved</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8004100" start="31" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR0_CNS">
<name>CNS</name>
<desc>The channel non-secure bit provides the security of the DMA channel:
0 = DMA channel operates in the Secure state
1 = DMA channel operates in the Non-secure state.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004100" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR0_reserved_1">
<name>reserved_1</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8004100" start="20" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR0_dmawfp_periph">
<name>dmawfp_periph</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set:
0 = DMAWFP executed with the periph operand not set
1 = DMAWFP executed with the periph operand set.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004100" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR0_dmawfp_b_ns">
<name>dmawfp_b_ns</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand
were set:
0 = DMAWFP executed with the single operand set
1 = DMAWFP executed with the burst operand set
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004100" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR0_reserved_2">
<name>reserved_2</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8004100" start="13" end="9" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR0_wakeup_num">
<name>wakeup_num</name>
<desc>If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits
indicate the event or peripheral number that the channel is waiting for:
b00000 = DMA channel is waiting for event, or peripheral, 0
b00001 = DMA channel is waiting for event, or peripheral, 1
b00010 = DMA channel is waiting for event, or peripheral, 2
.
.
.
b11111 = DMA channel is waiting for event, or peripheral, 31.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004100" start="8" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR0_channel_status">
<name>channel_status</name>
<desc>The channel status encoding is:
b0000 = Stopped
b0001 = Executing
b0010 = Cache miss
b0011 = Updating PC
b0100 = Waiting for event
b0101 = At barrier
b0110 = reserved
b0111 = Waiting for peripheral
b1000 = Killing
b1001 = Completing
b1010-b1101 = reserved
b1110 = Faulting completing
b1111 = Faulting.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004100" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CPC0_pc_chnl">
<name>pc_chnl</name>
<desc>Program counter for the DMA channel n thread, where n depends on the address
of the register
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004104" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR1_reserved">
<name>reserved</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8004108" start="31" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR1_CNS">
<name>CNS</name>
<desc>The channel non-secure bit provides the security of the DMA channel:
0 = DMA channel operates in the Secure state
1 = DMA channel operates in the Non-secure state.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004108" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR1_reserved_1">
<name>reserved_1</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8004108" start="20" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR1_dmawfp_periph">
<name>dmawfp_periph</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set:
0 = DMAWFP executed with the periph operand not set
1 = DMAWFP executed with the periph operand set.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004108" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR1_dmawfp_b_ns">
<name>dmawfp_b_ns</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand
were set:
0 = DMAWFP executed with the single operand set
1 = DMAWFP executed with the burst operand set
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004108" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR1_reserved_2">
<name>reserved_2</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8004108" start="13" end="9" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR1_wakeup_num">
<name>wakeup_num</name>
<desc>If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits
indicate the event or peripheral number that the channel is waiting for:
b00000 = DMA channel is waiting for event, or peripheral, 0
b00001 = DMA channel is waiting for event, or peripheral, 1
b00010 = DMA channel is waiting for event, or peripheral, 2
.
.
.
b11111 = DMA channel is waiting for event, or peripheral, 31.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004108" start="8" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR1_channel_status">
<name>channel_status</name>
<desc>The channel status encoding is:
b0000 = Stopped
b0001 = Executing
b0010 = Cache miss
b0011 = Updating PC
b0100 = Waiting for event
b0101 = At barrier
b0110 = reserved
b0111 = Waiting for peripheral
b1000 = Killing
b1001 = Completing
b1010-b1101 = reserved
b1110 = Faulting completing
b1111 = Faulting.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004108" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CPC1_pc_chnl">
<name>pc_chnl</name>
<desc>Program counter for the DMA channel n thread, where n depends on the address
of the register
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800410c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR2_reserved">
<name>reserved</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8004110" start="31" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR2_CNS">
<name>CNS</name>
<desc>The channel non-secure bit provides the security of the DMA channel:
0 = DMA channel operates in the Secure state
1 = DMA channel operates in the Non-secure state.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004110" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR2_reserved_1">
<name>reserved_1</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8004110" start="20" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR2_dmawfp_periph">
<name>dmawfp_periph</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set:
0 = DMAWFP executed with the periph operand not set
1 = DMAWFP executed with the periph operand set.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004110" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR2_dmawfp_b_ns">
<name>dmawfp_b_ns</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand
were set:
0 = DMAWFP executed with the single operand set
1 = DMAWFP executed with the burst operand set
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004110" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR2_reserved_2">
<name>reserved_2</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8004110" start="13" end="9" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR2_wakeup_num">
<name>wakeup_num</name>
<desc>If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits
indicate the event or peripheral number that the channel is waiting for:
b00000 = DMA channel is waiting for event, or peripheral, 0
b00001 = DMA channel is waiting for event, or peripheral, 1
b00010 = DMA channel is waiting for event, or peripheral, 2
.
.
.
b11111 = DMA channel is waiting for event, or peripheral, 31.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004110" start="8" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR2_channel_status">
<name>channel_status</name>
<desc>The channel status encoding is:
b0000 = Stopped
b0001 = Executing
b0010 = Cache miss
b0011 = Updating PC
b0100 = Waiting for event
b0101 = At barrier
b0110 = reserved
b0111 = Waiting for peripheral
b1000 = Killing
b1001 = Completing
b1010-b1101 = reserved
b1110 = Faulting completing
b1111 = Faulting.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004110" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CPC2_pc_chnl">
<name>pc_chnl</name>
<desc>Program counter for the DMA channel n thread, where n depends on the address
of the register
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004114" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR3_reserved">
<name>reserved</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8004118" start="31" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR3_CNS">
<name>CNS</name>
<desc>The channel non-secure bit provides the security of the DMA channel:
0 = DMA channel operates in the Secure state
1 = DMA channel operates in the Non-secure state.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004118" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR3_reserved_1">
<name>reserved_1</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8004118" start="20" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR3_dmawfp_periph">
<name>dmawfp_periph</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set:
0 = DMAWFP executed with the periph operand not set
1 = DMAWFP executed with the periph operand set.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004118" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR3_dmawfp_b_ns">
<name>dmawfp_b_ns</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand
were set:
0 = DMAWFP executed with the single operand set
1 = DMAWFP executed with the burst operand set
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004118" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR3_reserved_2">
<name>reserved_2</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8004118" start="13" end="9" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR3_wakeup_num">
<name>wakeup_num</name>
<desc>If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits
indicate the event or peripheral number that the channel is waiting for:
b00000 = DMA channel is waiting for event, or peripheral, 0
b00001 = DMA channel is waiting for event, or peripheral, 1
b00010 = DMA channel is waiting for event, or peripheral, 2
.
.
.
b11111 = DMA channel is waiting for event, or peripheral, 31.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004118" start="8" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR3_channel_status">
<name>channel_status</name>
<desc>The channel status encoding is:
b0000 = Stopped
b0001 = Executing
b0010 = Cache miss
b0011 = Updating PC
b0100 = Waiting for event
b0101 = At barrier
b0110 = reserved
b0111 = Waiting for peripheral
b1000 = Killing
b1001 = Completing
b1010-b1101 = reserved
b1110 = Faulting completing
b1111 = Faulting.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004118" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CPC3_pc_chnl">
<name>pc_chnl</name>
<desc>Program counter for the DMA channel n thread, where n depends on the address
of the register
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800411c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR4_reserved">
<name>reserved</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8004120" start="31" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR4_CNS">
<name>CNS</name>
<desc>The channel non-secure bit provides the security of the DMA channel:
0 = DMA channel operates in the Secure state
1 = DMA channel operates in the Non-secure state.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004120" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR4_reserved_1">
<name>reserved_1</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8004120" start="20" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR4_dmawfp_periph">
<name>dmawfp_periph</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set:
0 = DMAWFP executed with the periph operand not set
1 = DMAWFP executed with the periph operand set.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004120" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR4_dmawfp_b_ns">
<name>dmawfp_b_ns</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand
were set:
0 = DMAWFP executed with the single operand set
1 = DMAWFP executed with the burst operand set
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004120" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR4_reserved_2">
<name>reserved_2</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8004120" start="13" end="9" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR4_wakeup_num">
<name>wakeup_num</name>
<desc>If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits
indicate the event or peripheral number that the channel is waiting for:
b00000 = DMA channel is waiting for event, or peripheral, 0
b00001 = DMA channel is waiting for event, or peripheral, 1
b00010 = DMA channel is waiting for event, or peripheral, 2
.
.
.
b11111 = DMA channel is waiting for event, or peripheral, 31.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004120" start="8" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR4_channel_status">
<name>channel_status</name>
<desc>The channel status encoding is:
b0000 = Stopped
b0001 = Executing
b0010 = Cache miss
b0011 = Updating PC
b0100 = Waiting for event
b0101 = At barrier
b0110 = reserved
b0111 = Waiting for peripheral
b1000 = Killing
b1001 = Completing
b1010-b1101 = reserved
b1110 = Faulting completing
b1111 = Faulting.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004120" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CPC4_pc_chnl">
<name>pc_chnl</name>
<desc>Program counter for the DMA channel n thread, where n depends on the address
of the register
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004124" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR5_reserved">
<name>reserved</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8004128" start="31" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR5_CNS">
<name>CNS</name>
<desc>The channel non-secure bit provides the security of the DMA channel:
0 = DMA channel operates in the Secure state
1 = DMA channel operates in the Non-secure state.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004128" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR5_reserved_1">
<name>reserved_1</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8004128" start="20" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR5_dmawfp_periph">
<name>dmawfp_periph</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set:
0 = DMAWFP executed with the periph operand not set
1 = DMAWFP executed with the periph operand set.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004128" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR5_dmawfp_b_ns">
<name>dmawfp_b_ns</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand
were set:
0 = DMAWFP executed with the single operand set
1 = DMAWFP executed with the burst operand set
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004128" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR5_reserved_2">
<name>reserved_2</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8004128" start="13" end="9" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR5_wakeup_num">
<name>wakeup_num</name>
<desc>If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits
indicate the event or peripheral number that the channel is waiting for:
b00000 = DMA channel is waiting for event, or peripheral, 0
b00001 = DMA channel is waiting for event, or peripheral, 1
b00010 = DMA channel is waiting for event, or peripheral, 2
.
.
.
b11111 = DMA channel is waiting for event, or peripheral, 31.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004128" start="8" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR5_channel_status">
<name>channel_status</name>
<desc>The channel status encoding is:
b0000 = Stopped
b0001 = Executing
b0010 = Cache miss
b0011 = Updating PC
b0100 = Waiting for event
b0101 = At barrier
b0110 = reserved
b0111 = Waiting for peripheral
b1000 = Killing
b1001 = Completing
b1010-b1101 = reserved
b1110 = Faulting completing
b1111 = Faulting.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004128" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CPC5_pc_chnl">
<name>pc_chnl</name>
<desc>Program counter for the DMA channel n thread, where n depends on the address
of the register
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800412c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR6_reserved">
<name>reserved</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8004130" start="31" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR6_CNS">
<name>CNS</name>
<desc>The channel non-secure bit provides the security of the DMA channel:
0 = DMA channel operates in the Secure state
1 = DMA channel operates in the Non-secure state.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004130" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR6_reserved_1">
<name>reserved_1</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8004130" start="20" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR6_dmawfp_periph">
<name>dmawfp_periph</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set:
0 = DMAWFP executed with the periph operand not set
1 = DMAWFP executed with the periph operand set.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004130" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR6_dmawfp_b_ns">
<name>dmawfp_b_ns</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand
were set:
0 = DMAWFP executed with the single operand set
1 = DMAWFP executed with the burst operand set
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004130" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR6_reserved_2">
<name>reserved_2</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8004130" start="13" end="9" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR6_wakeup_num">
<name>wakeup_num</name>
<desc>If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits
indicate the event or peripheral number that the channel is waiting for:
b00000 = DMA channel is waiting for event, or peripheral, 0
b00001 = DMA channel is waiting for event, or peripheral, 1
b00010 = DMA channel is waiting for event, or peripheral, 2
.
.
.
b11111 = DMA channel is waiting for event, or peripheral, 31.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004130" start="8" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR6_channel_status">
<name>channel_status</name>
<desc>The channel status encoding is:
b0000 = Stopped
b0001 = Executing
b0010 = Cache miss
b0011 = Updating PC
b0100 = Waiting for event
b0101 = At barrier
b0110 = reserved
b0111 = Waiting for peripheral
b1000 = Killing
b1001 = Completing
b1010-b1101 = reserved
b1110 = Faulting completing
b1111 = Faulting.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004130" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CPC6_pc_chnl">
<name>pc_chnl</name>
<desc>Program counter for the DMA channel n thread, where n depends on the address
of the register
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004134" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR7_reserved">
<name>reserved</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8004138" start="31" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR7_CNS">
<name>CNS</name>
<desc>The channel non-secure bit provides the security of the DMA channel:
0 = DMA channel operates in the Secure state
1 = DMA channel operates in the Non-secure state.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004138" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR7_reserved_1">
<name>reserved_1</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8004138" start="20" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR7_dmawfp_periph">
<name>dmawfp_periph</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set:
0 = DMAWFP executed with the periph operand not set
1 = DMAWFP executed with the periph operand set.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004138" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR7_dmawfp_b_ns">
<name>dmawfp_b_ns</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand
were set:
0 = DMAWFP executed with the single operand set
1 = DMAWFP executed with the burst operand set
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004138" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR7_reserved_2">
<name>reserved_2</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8004138" start="13" end="9" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR7_wakeup_num">
<name>wakeup_num</name>
<desc>If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits
indicate the event or peripheral number that the channel is waiting for:
b00000 = DMA channel is waiting for event, or peripheral, 0
b00001 = DMA channel is waiting for event, or peripheral, 1
b00010 = DMA channel is waiting for event, or peripheral, 2
.
.
.
b11111 = DMA channel is waiting for event, or peripheral, 31.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004138" start="8" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CSR7_channel_status">
<name>channel_status</name>
<desc>The channel status encoding is:
b0000 = Stopped
b0001 = Executing
b0010 = Cache miss
b0011 = Updating PC
b0100 = Waiting for event
b0101 = At barrier
b0110 = reserved
b0111 = Waiting for peripheral
b1000 = Killing
b1001 = Completing
b1010-b1101 = reserved
b1110 = Faulting completing
b1111 = Faulting.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004138" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CPC7_pc_chnl">
<name>pc_chnl</name>
<desc>Program counter for the DMA channel n thread, where n depends on the address
of the register
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800413c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_SAR0_src_addr">
<name>src_addr</name>
<desc>Address of the source data for DMA channel n, where n depends on the address
of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004400" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_DAR0_dest_addr">
<name>dest_addr</name>
<desc>Address for the destination data for DMA channel n, where n depends on the
address of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004404" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR0_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf8004408" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR0_endian_swap_size">
<name>endian_swap_size</name>
<desc>Table 3-22 on page 3-29 defines whether data can be swapped between little-endian (LE) and
byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data
independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that b000 indicates that no swap must occur.
Endian swap size Description
b000 No swap, 8-bit data
b001 Swap bytes within 16-bit data
b010 Swap bytes within 32-bit data
b011 Swap bytes within 64-bit data
b100 Swap bytes within 128-bit data
b101 Reserved
b110 Reserved
b111 Reserved
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004408" start="30" end="28" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR0_dst_cache_ctrl">
<name>dst_cache_ctrl</name>
<desc>Programs the state of AWCACHE[3,1:0]a when the DMAC writes the destination data.
Bit [27] 0 = AWCACHE[3] is LOW
1 = AWCACHE[3] is HIGH.
Bit [26] 0 = AWCACHE[1] is LOW
1 = AWCACHE[1] is HIGH.
Bit [25] 0 = AWCACHE[0] is LOW
1 = AWCACHE[0] is HIGH.
Note
AWCACHE[2] is tied LOW by the DMAC.
Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004408" start="27" end="25" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR0_dst_prot_ctrl">
<name>dst_prot_ctrl</name>
<desc>Programs the state of AWPROT[2:0]a when the DMAC writes the destination data.
Bit [24] 0 = AWPROT[2] is LOW
1 = AWPROT[2] is HIGH.
Bit [23] 0 = AWPROT[1] is LOW
1 = AWPROT[1] is HIGH.
Bit [22] 0 = AWPROT[0] is LOW
1 = AWPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If
a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel
aborts
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004408" start="24" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR0_dst_burst_len">
<name>dst_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it writes
the destination data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004408" start="21" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR0_dst_burst_size">
<name>dst_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination:
b000 = writes 1 byte per beat
b001 = writes 2 bytes per beat
b010 = writes 4 bytes per beat
b011 = writes 8 bytes per beat
b100 = writes 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004408" start="17" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR0_dst_inc">
<name>dst_inc</name>
<desc>Programs the burst type that the DMAC performs when it writes the destination data:
0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004408" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR0_src_cache_ctrl">
<name>src_cache_ctrl</name>
<desc>Set the bits to control the state of ARCACHE[2:0]a when the DMAC reads the source data.
Bit [13] 0 = ARCACHE[2] is LOW
1 = ARCACHE[2] is HIGH.
Bit [12] 0 = ARCACHE[1] is LOW
1 = ARCACHE[1] is HIGH.
Bit [11] 0 = ARCACHE[0] is LOW
1 = ARCACHE[0] is HIGH.
Note
The DMAC ties ARCACHE[3] LOW.
Setting ARCACHE[2:1]=b10 violates the AXI protocol.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004408" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR0_src_prot_ctrl">
<name>src_prot_ctrl</name>
<desc>Programs the state of ARPROT[2:0]a when the DMAC reads the source data.
Bit [10] 0 = ARPROT[2] is LOW
1 = ARPROT[2] is HIGH.
Bit [9] 0 = ARPROT[1] is LOW
1 = ARPROT[1] is HIGH.
Bit [8] 0 = ARPROT[0] is LOW
1 = ARPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a
DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004408" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR0_src_burst_len">
<name>src_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it reads
the source data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004408" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR0_src_burst_size">
<name>src_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC reads from the source:
b000 = reads 1 byte per beat
b001 = reads 2 bytes per beat
b010 = reads 4 bytes per beat
b011 = reads 8 bytes per beat
b100 = reads 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004408" start="3" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR0_src_inc">
<name>src_inc</name>
<desc>Programs the burst type that the DMAC performs when it reads the source data:
0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004408" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC0_0_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf800440c" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC0_0_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter zero for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter zero
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800440c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC1_0_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf8004410" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC1_0_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter one for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter one.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004410" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_SAR1_src_addr">
<name>src_addr</name>
<desc>Address of the source data for DMA channel n, where n depends on the address
of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004420" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_DAR1_dest_addr">
<name>dest_addr</name>
<desc>Address for the destination data for DMA channel n, where n depends on the
address of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004424" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR1_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf8004428" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR1_endian_swap_size">
<name>endian_swap_size</name>
<desc>Table 3-22 on page 3-29 defines whether data can be swapped between little-endian (LE) and
byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data
independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that b000 indicates that no swap must occur.
Endian swap size Description
b000 No swap, 8-bit data
b001 Swap bytes within 16-bit data
b010 Swap bytes within 32-bit data
b011 Swap bytes within 64-bit data
b100 Swap bytes within 128-bit data
b101 Reserved
b110 Reserved
b111 Reserved
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004428" start="30" end="28" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR1_dst_cache_ctrl">
<name>dst_cache_ctrl</name>
<desc>Programs the state of AWCACHE[3,1:0]a when the DMAC writes the destination data.
Bit [27] 0 = AWCACHE[3] is LOW
1 = AWCACHE[3] is HIGH.
Bit [26] 0 = AWCACHE[1] is LOW
1 = AWCACHE[1] is HIGH.
Bit [25] 0 = AWCACHE[0] is LOW
1 = AWCACHE[0] is HIGH.
Note
AWCACHE[2] is tied LOW by the DMAC.
Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004428" start="27" end="25" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR1_dst_prot_ctrl">
<name>dst_prot_ctrl</name>
<desc>Programs the state of AWPROT[2:0]a when the DMAC writes the destination data.
Bit [24] 0 = AWPROT[2] is LOW
1 = AWPROT[2] is HIGH.
Bit [23] 0 = AWPROT[1] is LOW
1 = AWPROT[1] is HIGH.
Bit [22] 0 = AWPROT[0] is LOW
1 = AWPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If
a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel
aborts
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004428" start="24" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR1_dst_burst_len">
<name>dst_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it writes
the destination data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004428" start="21" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR1_dst_burst_size">
<name>dst_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination:
b000 = writes 1 byte per beat
b001 = writes 2 bytes per beat
b010 = writes 4 bytes per beat
b011 = writes 8 bytes per beat
b100 = writes 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004428" start="17" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR1_dst_inc">
<name>dst_inc</name>
<desc>Programs the burst type that the DMAC performs when it writes the destination data:
0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004428" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR1_src_cache_ctrl">
<name>src_cache_ctrl</name>
<desc>Set the bits to control the state of ARCACHE[2:0]a when the DMAC reads the source data.
Bit [13] 0 = ARCACHE[2] is LOW
1 = ARCACHE[2] is HIGH.
Bit [12] 0 = ARCACHE[1] is LOW
1 = ARCACHE[1] is HIGH.
Bit [11] 0 = ARCACHE[0] is LOW
1 = ARCACHE[0] is HIGH.
Note
The DMAC ties ARCACHE[3] LOW.
Setting ARCACHE[2:1]=b10 violates the AXI protocol.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004428" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR1_src_prot_ctrl">
<name>src_prot_ctrl</name>
<desc>Programs the state of ARPROT[2:0]a when the DMAC reads the source data.
Bit [10] 0 = ARPROT[2] is LOW
1 = ARPROT[2] is HIGH.
Bit [9] 0 = ARPROT[1] is LOW
1 = ARPROT[1] is HIGH.
Bit [8] 0 = ARPROT[0] is LOW
1 = ARPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a
DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004428" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR1_src_burst_len">
<name>src_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it reads
the source data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004428" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR1_src_burst_size">
<name>src_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC reads from the source:
b000 = reads 1 byte per beat
b001 = reads 2 bytes per beat
b010 = reads 4 bytes per beat
b011 = reads 8 bytes per beat
b100 = reads 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004428" start="3" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR1_src_inc">
<name>src_inc</name>
<desc>Programs the burst type that the DMAC performs when it reads the source data:
0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004428" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC0_1_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf800442c" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC0_1_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter zero for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter zero
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800442c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC1_1_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf8004430" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC1_1_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter one for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter one.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004430" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_SAR2_src_addr">
<name>src_addr</name>
<desc>Address of the source data for DMA channel n, where n depends on the address
of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004440" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_DAR2_dest_addr">
<name>dest_addr</name>
<desc>Address for the destination data for DMA channel n, where n depends on the
address of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004444" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR2_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf8004448" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR2_endian_swap_size">
<name>endian_swap_size</name>
<desc>Table 3-22 on page 3-29 defines whether data can be swapped between little-endian (LE) and
byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data
independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that b000 indicates that no swap must occur.
Endian swap size Description
b000 No swap, 8-bit data
b001 Swap bytes within 16-bit data
b010 Swap bytes within 32-bit data
b011 Swap bytes within 64-bit data
b100 Swap bytes within 128-bit data
b101 Reserved
b110 Reserved
b111 Reserved
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004448" start="30" end="28" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR2_dst_cache_ctrl">
<name>dst_cache_ctrl</name>
<desc>Programs the state of AWCACHE[3,1:0]a when the DMAC writes the destination data.
Bit [27] 0 = AWCACHE[3] is LOW
1 = AWCACHE[3] is HIGH.
Bit [26] 0 = AWCACHE[1] is LOW
1 = AWCACHE[1] is HIGH.
Bit [25] 0 = AWCACHE[0] is LOW
1 = AWCACHE[0] is HIGH.
Note
AWCACHE[2] is tied LOW by the DMAC.
Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004448" start="27" end="25" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR2_dst_prot_ctrl">
<name>dst_prot_ctrl</name>
<desc>Programs the state of AWPROT[2:0]a when the DMAC writes the destination data.
Bit [24] 0 = AWPROT[2] is LOW
1 = AWPROT[2] is HIGH.
Bit [23] 0 = AWPROT[1] is LOW
1 = AWPROT[1] is HIGH.
Bit [22] 0 = AWPROT[0] is LOW
1 = AWPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If
a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel
aborts
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004448" start="24" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR2_dst_burst_len">
<name>dst_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it writes
the destination data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004448" start="21" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR2_dst_burst_size">
<name>dst_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination:
b000 = writes 1 byte per beat
b001 = writes 2 bytes per beat
b010 = writes 4 bytes per beat
b011 = writes 8 bytes per beat
b100 = writes 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004448" start="17" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR2_dst_inc">
<name>dst_inc</name>
<desc>Programs the burst type that the DMAC performs when it writes the destination data:
0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004448" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR2_src_cache_ctrl">
<name>src_cache_ctrl</name>
<desc>Set the bits to control the state of ARCACHE[2:0]a when the DMAC reads the source data.
Bit [13] 0 = ARCACHE[2] is LOW
1 = ARCACHE[2] is HIGH.
Bit [12] 0 = ARCACHE[1] is LOW
1 = ARCACHE[1] is HIGH.
Bit [11] 0 = ARCACHE[0] is LOW
1 = ARCACHE[0] is HIGH.
Note
The DMAC ties ARCACHE[3] LOW.
Setting ARCACHE[2:1]=b10 violates the AXI protocol.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004448" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR2_src_prot_ctrl">
<name>src_prot_ctrl</name>
<desc>Programs the state of ARPROT[2:0]a when the DMAC reads the source data.
Bit [10] 0 = ARPROT[2] is LOW
1 = ARPROT[2] is HIGH.
Bit [9] 0 = ARPROT[1] is LOW
1 = ARPROT[1] is HIGH.
Bit [8] 0 = ARPROT[0] is LOW
1 = ARPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a
DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004448" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR2_src_burst_len">
<name>src_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it reads
the source data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004448" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR2_src_burst_size">
<name>src_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC reads from the source:
b000 = reads 1 byte per beat
b001 = reads 2 bytes per beat
b010 = reads 4 bytes per beat
b011 = reads 8 bytes per beat
b100 = reads 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004448" start="3" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR2_src_inc">
<name>src_inc</name>
<desc>Programs the burst type that the DMAC performs when it reads the source data:
0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004448" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC0_2_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf800444c" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC0_2_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter zero for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter zero
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800444c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC1_2_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf8004450" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC1_2_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter one for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter one.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004450" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_SAR3_src_addr">
<name>src_addr</name>
<desc>Address of the source data for DMA channel n, where n depends on the address
of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004460" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_DAR3_dest_addr">
<name>dest_addr</name>
<desc>Address for the destination data for DMA channel n, where n depends on the
address of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004464" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR3_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf8004468" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR3_endian_swap_size">
<name>endian_swap_size</name>
<desc>Table 3-22 on page 3-29 defines whether data can be swapped between little-endian (LE) and
byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data
independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that b000 indicates that no swap must occur.
Endian swap size Description
b000 No swap, 8-bit data
b001 Swap bytes within 16-bit data
b010 Swap bytes within 32-bit data
b011 Swap bytes within 64-bit data
b100 Swap bytes within 128-bit data
b101 Reserved
b110 Reserved
b111 Reserved
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004468" start="30" end="28" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR3_dst_cache_ctrl">
<name>dst_cache_ctrl</name>
<desc>Programs the state of AWCACHE[3,1:0]a when the DMAC writes the destination data.
Bit [27] 0 = AWCACHE[3] is LOW
1 = AWCACHE[3] is HIGH.
Bit [26] 0 = AWCACHE[1] is LOW
1 = AWCACHE[1] is HIGH.
Bit [25] 0 = AWCACHE[0] is LOW
1 = AWCACHE[0] is HIGH.
Note
AWCACHE[2] is tied LOW by the DMAC.
Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004468" start="27" end="25" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR3_dst_prot_ctrl">
<name>dst_prot_ctrl</name>
<desc>Programs the state of AWPROT[2:0]a when the DMAC writes the destination data.
Bit [24] 0 = AWPROT[2] is LOW
1 = AWPROT[2] is HIGH.
Bit [23] 0 = AWPROT[1] is LOW
1 = AWPROT[1] is HIGH.
Bit [22] 0 = AWPROT[0] is LOW
1 = AWPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If
a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel
aborts
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004468" start="24" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR3_dst_burst_len">
<name>dst_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it writes
the destination data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004468" start="21" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR3_dst_burst_size">
<name>dst_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination:
b000 = writes 1 byte per beat
b001 = writes 2 bytes per beat
b010 = writes 4 bytes per beat
b011 = writes 8 bytes per beat
b100 = writes 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004468" start="17" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR3_dst_inc">
<name>dst_inc</name>
<desc>Programs the burst type that the DMAC performs when it writes the destination data:
0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004468" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR3_src_cache_ctrl">
<name>src_cache_ctrl</name>
<desc>Set the bits to control the state of ARCACHE[2:0]a when the DMAC reads the source data.
Bit [13] 0 = ARCACHE[2] is LOW
1 = ARCACHE[2] is HIGH.
Bit [12] 0 = ARCACHE[1] is LOW
1 = ARCACHE[1] is HIGH.
Bit [11] 0 = ARCACHE[0] is LOW
1 = ARCACHE[0] is HIGH.
Note
The DMAC ties ARCACHE[3] LOW.
Setting ARCACHE[2:1]=b10 violates the AXI protocol.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004468" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR3_src_prot_ctrl">
<name>src_prot_ctrl</name>
<desc>Programs the state of ARPROT[2:0]a when the DMAC reads the source data.
Bit [10] 0 = ARPROT[2] is LOW
1 = ARPROT[2] is HIGH.
Bit [9] 0 = ARPROT[1] is LOW
1 = ARPROT[1] is HIGH.
Bit [8] 0 = ARPROT[0] is LOW
1 = ARPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a
DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004468" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR3_src_burst_len">
<name>src_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it reads
the source data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004468" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR3_src_burst_size">
<name>src_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC reads from the source:
b000 = reads 1 byte per beat
b001 = reads 2 bytes per beat
b010 = reads 4 bytes per beat
b011 = reads 8 bytes per beat
b100 = reads 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004468" start="3" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR3_src_inc">
<name>src_inc</name>
<desc>Programs the burst type that the DMAC performs when it reads the source data:
0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004468" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC0_3_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf800446c" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC0_3_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter zero for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter zero
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800446c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC1_3_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf8004470" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC1_3_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter one for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter one.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004470" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_SAR4_src_addr">
<name>src_addr</name>
<desc>Address of the source data for DMA channel n, where n depends on the address
of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004480" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_DAR4_dest_addr">
<name>dest_addr</name>
<desc>Address for the destination data for DMA channel n, where n depends on the
address of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004484" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR4_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf8004488" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR4_endian_swap_size">
<name>endian_swap_size</name>
<desc>Table 3-22 on page 3-29 defines whether data can be swapped between little-endian (LE) and
byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data
independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that b000 indicates that no swap must occur.
Endian swap size Description
b000 No swap, 8-bit data
b001 Swap bytes within 16-bit data
b010 Swap bytes within 32-bit data
b011 Swap bytes within 64-bit data
b100 Swap bytes within 128-bit data
b101 Reserved
b110 Reserved
b111 Reserved
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004488" start="30" end="28" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR4_dst_cache_ctrl">
<name>dst_cache_ctrl</name>
<desc>Programs the state of AWCACHE[3,1:0]a when the DMAC writes the destination data.
Bit [27] 0 = AWCACHE[3] is LOW
1 = AWCACHE[3] is HIGH.
Bit [26] 0 = AWCACHE[1] is LOW
1 = AWCACHE[1] is HIGH.
Bit [25] 0 = AWCACHE[0] is LOW
1 = AWCACHE[0] is HIGH.
Note
AWCACHE[2] is tied LOW by the DMAC.
Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004488" start="27" end="25" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR4_dst_prot_ctrl">
<name>dst_prot_ctrl</name>
<desc>Programs the state of AWPROT[2:0]a when the DMAC writes the destination data.
Bit [24] 0 = AWPROT[2] is LOW
1 = AWPROT[2] is HIGH.
Bit [23] 0 = AWPROT[1] is LOW
1 = AWPROT[1] is HIGH.
Bit [22] 0 = AWPROT[0] is LOW
1 = AWPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If
a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel
aborts
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004488" start="24" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR4_dst_burst_len">
<name>dst_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it writes
the destination data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004488" start="21" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR4_dst_burst_size">
<name>dst_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination:
b000 = writes 1 byte per beat
b001 = writes 2 bytes per beat
b010 = writes 4 bytes per beat
b011 = writes 8 bytes per beat
b100 = writes 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004488" start="17" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR4_dst_inc">
<name>dst_inc</name>
<desc>Programs the burst type that the DMAC performs when it writes the destination data:
0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004488" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR4_src_cache_ctrl">
<name>src_cache_ctrl</name>
<desc>Set the bits to control the state of ARCACHE[2:0]a when the DMAC reads the source data.
Bit [13] 0 = ARCACHE[2] is LOW
1 = ARCACHE[2] is HIGH.
Bit [12] 0 = ARCACHE[1] is LOW
1 = ARCACHE[1] is HIGH.
Bit [11] 0 = ARCACHE[0] is LOW
1 = ARCACHE[0] is HIGH.
Note
The DMAC ties ARCACHE[3] LOW.
Setting ARCACHE[2:1]=b10 violates the AXI protocol.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004488" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR4_src_prot_ctrl">
<name>src_prot_ctrl</name>
<desc>Programs the state of ARPROT[2:0]a when the DMAC reads the source data.
Bit [10] 0 = ARPROT[2] is LOW
1 = ARPROT[2] is HIGH.
Bit [9] 0 = ARPROT[1] is LOW
1 = ARPROT[1] is HIGH.
Bit [8] 0 = ARPROT[0] is LOW
1 = ARPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a
DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004488" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR4_src_burst_len">
<name>src_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it reads
the source data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004488" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR4_src_burst_size">
<name>src_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC reads from the source:
b000 = reads 1 byte per beat
b001 = reads 2 bytes per beat
b010 = reads 4 bytes per beat
b011 = reads 8 bytes per beat
b100 = reads 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004488" start="3" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR4_src_inc">
<name>src_inc</name>
<desc>Programs the burst type that the DMAC performs when it reads the source data:
0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004488" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC0_4_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf800448c" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC0_4_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter zero for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter zero
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800448c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC1_4_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf8004490" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC1_4_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter one for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter one.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004490" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_SAR5_src_addr">
<name>src_addr</name>
<desc>Address of the source data for DMA channel n, where n depends on the address
of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044a0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_DAR5_dest_addr">
<name>dest_addr</name>
<desc>Address for the destination data for DMA channel n, where n depends on the
address of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044a4" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR5_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf80044a8" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR5_endian_swap_size">
<name>endian_swap_size</name>
<desc>Table 3-22 on page 3-29 defines whether data can be swapped between little-endian (LE) and
byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data
independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that b000 indicates that no swap must occur.
Endian swap size Description
b000 No swap, 8-bit data
b001 Swap bytes within 16-bit data
b010 Swap bytes within 32-bit data
b011 Swap bytes within 64-bit data
b100 Swap bytes within 128-bit data
b101 Reserved
b110 Reserved
b111 Reserved
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044a8" start="30" end="28" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR5_dst_cache_ctrl">
<name>dst_cache_ctrl</name>
<desc>Programs the state of AWCACHE[3,1:0]a when the DMAC writes the destination data.
Bit [27] 0 = AWCACHE[3] is LOW
1 = AWCACHE[3] is HIGH.
Bit [26] 0 = AWCACHE[1] is LOW
1 = AWCACHE[1] is HIGH.
Bit [25] 0 = AWCACHE[0] is LOW
1 = AWCACHE[0] is HIGH.
Note
AWCACHE[2] is tied LOW by the DMAC.
Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044a8" start="27" end="25" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR5_dst_prot_ctrl">
<name>dst_prot_ctrl</name>
<desc>Programs the state of AWPROT[2:0]a when the DMAC writes the destination data.
Bit [24] 0 = AWPROT[2] is LOW
1 = AWPROT[2] is HIGH.
Bit [23] 0 = AWPROT[1] is LOW
1 = AWPROT[1] is HIGH.
Bit [22] 0 = AWPROT[0] is LOW
1 = AWPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If
a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel
aborts
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044a8" start="24" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR5_dst_burst_len">
<name>dst_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it writes
the destination data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044a8" start="21" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR5_dst_burst_size">
<name>dst_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination:
b000 = writes 1 byte per beat
b001 = writes 2 bytes per beat
b010 = writes 4 bytes per beat
b011 = writes 8 bytes per beat
b100 = writes 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044a8" start="17" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR5_dst_inc">
<name>dst_inc</name>
<desc>Programs the burst type that the DMAC performs when it writes the destination data:
0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044a8" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR5_src_cache_ctrl">
<name>src_cache_ctrl</name>
<desc>Set the bits to control the state of ARCACHE[2:0]a when the DMAC reads the source data.
Bit [13] 0 = ARCACHE[2] is LOW
1 = ARCACHE[2] is HIGH.
Bit [12] 0 = ARCACHE[1] is LOW
1 = ARCACHE[1] is HIGH.
Bit [11] 0 = ARCACHE[0] is LOW
1 = ARCACHE[0] is HIGH.
Note
The DMAC ties ARCACHE[3] LOW.
Setting ARCACHE[2:1]=b10 violates the AXI protocol.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044a8" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR5_src_prot_ctrl">
<name>src_prot_ctrl</name>
<desc>Programs the state of ARPROT[2:0]a when the DMAC reads the source data.
Bit [10] 0 = ARPROT[2] is LOW
1 = ARPROT[2] is HIGH.
Bit [9] 0 = ARPROT[1] is LOW
1 = ARPROT[1] is HIGH.
Bit [8] 0 = ARPROT[0] is LOW
1 = ARPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a
DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044a8" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR5_src_burst_len">
<name>src_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it reads
the source data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044a8" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR5_src_burst_size">
<name>src_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC reads from the source:
b000 = reads 1 byte per beat
b001 = reads 2 bytes per beat
b010 = reads 4 bytes per beat
b011 = reads 8 bytes per beat
b100 = reads 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044a8" start="3" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR5_src_inc">
<name>src_inc</name>
<desc>Programs the burst type that the DMAC performs when it reads the source data:
0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044a8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC0_5_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf80044ac" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC0_5_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter zero for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter zero
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044ac" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC1_5_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf80044b0" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC1_5_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter one for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter one.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044b0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_SAR6_src_addr">
<name>src_addr</name>
<desc>Address of the source data for DMA channel n, where n depends on the address
of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044c0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_DAR6_dest_addr">
<name>dest_addr</name>
<desc>Address for the destination data for DMA channel n, where n depends on the
address of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044c4" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR6_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf80044c8" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR6_endian_swap_size">
<name>endian_swap_size</name>
<desc>Table 3-22 on page 3-29 defines whether data can be swapped between little-endian (LE) and
byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data
independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that b000 indicates that no swap must occur.
Endian swap size Description
b000 No swap, 8-bit data
b001 Swap bytes within 16-bit data
b010 Swap bytes within 32-bit data
b011 Swap bytes within 64-bit data
b100 Swap bytes within 128-bit data
b101 Reserved
b110 Reserved
b111 Reserved
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044c8" start="30" end="28" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR6_dst_cache_ctrl">
<name>dst_cache_ctrl</name>
<desc>Programs the state of AWCACHE[3,1:0]a when the DMAC writes the destination data.
Bit [27] 0 = AWCACHE[3] is LOW
1 = AWCACHE[3] is HIGH.
Bit [26] 0 = AWCACHE[1] is LOW
1 = AWCACHE[1] is HIGH.
Bit [25] 0 = AWCACHE[0] is LOW
1 = AWCACHE[0] is HIGH.
Note
AWCACHE[2] is tied LOW by the DMAC.
Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044c8" start="27" end="25" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR6_dst_prot_ctrl">
<name>dst_prot_ctrl</name>
<desc>Programs the state of AWPROT[2:0]a when the DMAC writes the destination data.
Bit [24] 0 = AWPROT[2] is LOW
1 = AWPROT[2] is HIGH.
Bit [23] 0 = AWPROT[1] is LOW
1 = AWPROT[1] is HIGH.
Bit [22] 0 = AWPROT[0] is LOW
1 = AWPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If
a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel
aborts
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044c8" start="24" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR6_dst_burst_len">
<name>dst_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it writes
the destination data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044c8" start="21" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR6_dst_burst_size">
<name>dst_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination:
b000 = writes 1 byte per beat
b001 = writes 2 bytes per beat
b010 = writes 4 bytes per beat
b011 = writes 8 bytes per beat
b100 = writes 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044c8" start="17" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR6_dst_inc">
<name>dst_inc</name>
<desc>Programs the burst type that the DMAC performs when it writes the destination data:
0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044c8" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR6_src_cache_ctrl">
<name>src_cache_ctrl</name>
<desc>Set the bits to control the state of ARCACHE[2:0]a when the DMAC reads the source data.
Bit [13] 0 = ARCACHE[2] is LOW
1 = ARCACHE[2] is HIGH.
Bit [12] 0 = ARCACHE[1] is LOW
1 = ARCACHE[1] is HIGH.
Bit [11] 0 = ARCACHE[0] is LOW
1 = ARCACHE[0] is HIGH.
Note
The DMAC ties ARCACHE[3] LOW.
Setting ARCACHE[2:1]=b10 violates the AXI protocol.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044c8" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR6_src_prot_ctrl">
<name>src_prot_ctrl</name>
<desc>Programs the state of ARPROT[2:0]a when the DMAC reads the source data.
Bit [10] 0 = ARPROT[2] is LOW
1 = ARPROT[2] is HIGH.
Bit [9] 0 = ARPROT[1] is LOW
1 = ARPROT[1] is HIGH.
Bit [8] 0 = ARPROT[0] is LOW
1 = ARPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a
DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044c8" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR6_src_burst_len">
<name>src_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it reads
the source data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044c8" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR6_src_burst_size">
<name>src_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC reads from the source:
b000 = reads 1 byte per beat
b001 = reads 2 bytes per beat
b010 = reads 4 bytes per beat
b011 = reads 8 bytes per beat
b100 = reads 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044c8" start="3" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR6_src_inc">
<name>src_inc</name>
<desc>Programs the burst type that the DMAC performs when it reads the source data:
0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044c8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC0_6_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf80044cc" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC0_6_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter zero for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter zero
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044cc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC1_6_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf80044d0" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC1_6_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter one for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter one.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044d0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_SAR7_src_addr">
<name>src_addr</name>
<desc>Address of the source data for DMA channel n, where n depends on the address
of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044e0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_DAR7_dest_addr">
<name>dest_addr</name>
<desc>Address for the destination data for DMA channel n, where n depends on the
address of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044e4" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR7_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf80044e8" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR7_endian_swap_size">
<name>endian_swap_size</name>
<desc>Table 3-22 on page 3-29 defines whether data can be swapped between little-endian (LE) and
byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data
independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that b000 indicates that no swap must occur.
Endian swap size Description
b000 No swap, 8-bit data
b001 Swap bytes within 16-bit data
b010 Swap bytes within 32-bit data
b011 Swap bytes within 64-bit data
b100 Swap bytes within 128-bit data
b101 Reserved
b110 Reserved
b111 Reserved
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044e8" start="30" end="28" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR7_dst_cache_ctrl">
<name>dst_cache_ctrl</name>
<desc>Programs the state of AWCACHE[3,1:0]a when the DMAC writes the destination data.
Bit [27] 0 = AWCACHE[3] is LOW
1 = AWCACHE[3] is HIGH.
Bit [26] 0 = AWCACHE[1] is LOW
1 = AWCACHE[1] is HIGH.
Bit [25] 0 = AWCACHE[0] is LOW
1 = AWCACHE[0] is HIGH.
Note
AWCACHE[2] is tied LOW by the DMAC.
Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044e8" start="27" end="25" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR7_dst_prot_ctrl">
<name>dst_prot_ctrl</name>
<desc>Programs the state of AWPROT[2:0]a when the DMAC writes the destination data.
Bit [24] 0 = AWPROT[2] is LOW
1 = AWPROT[2] is HIGH.
Bit [23] 0 = AWPROT[1] is LOW
1 = AWPROT[1] is HIGH.
Bit [22] 0 = AWPROT[0] is LOW
1 = AWPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If
a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel
aborts
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044e8" start="24" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR7_dst_burst_len">
<name>dst_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it writes
the destination data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044e8" start="21" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR7_dst_burst_size">
<name>dst_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination:
b000 = writes 1 byte per beat
b001 = writes 2 bytes per beat
b010 = writes 4 bytes per beat
b011 = writes 8 bytes per beat
b100 = writes 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044e8" start="17" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR7_dst_inc">
<name>dst_inc</name>
<desc>Programs the burst type that the DMAC performs when it writes the destination data:
0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044e8" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR7_src_cache_ctrl">
<name>src_cache_ctrl</name>
<desc>Set the bits to control the state of ARCACHE[2:0]a when the DMAC reads the source data.
Bit [13] 0 = ARCACHE[2] is LOW
1 = ARCACHE[2] is HIGH.
Bit [12] 0 = ARCACHE[1] is LOW
1 = ARCACHE[1] is HIGH.
Bit [11] 0 = ARCACHE[0] is LOW
1 = ARCACHE[0] is HIGH.
Note
The DMAC ties ARCACHE[3] LOW.
Setting ARCACHE[2:1]=b10 violates the AXI protocol.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044e8" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR7_src_prot_ctrl">
<name>src_prot_ctrl</name>
<desc>Programs the state of ARPROT[2:0]a when the DMAC reads the source data.
Bit [10] 0 = ARPROT[2] is LOW
1 = ARPROT[2] is HIGH.
Bit [9] 0 = ARPROT[1] is LOW
1 = ARPROT[1] is HIGH.
Bit [8] 0 = ARPROT[0] is LOW
1 = ARPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a
DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044e8" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR7_src_burst_len">
<name>src_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it reads
the source data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044e8" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR7_src_burst_size">
<name>src_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC reads from the source:
b000 = reads 1 byte per beat
b001 = reads 2 bytes per beat
b010 = reads 4 bytes per beat
b011 = reads 8 bytes per beat
b100 = reads 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044e8" start="3" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CCR7_src_inc">
<name>src_inc</name>
<desc>Programs the burst type that the DMAC performs when it reads the source data:
0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044e8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC0_7_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf80044ec" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC0_7_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter zero for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter zero
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044ec" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC1_7_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf80044f0" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_LC1_7_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter one for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter one.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80044f0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_DBGSTATUS_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf8004d00" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_DBGSTATUS_dbgstatus">
<name>dbgstatus</name>
<desc>The debug status encoding is:
0 = Idle
1 = Busy.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004d00" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_DBGCMD_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf8004d04" start="31" end="2" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_DBGCMD_dbgcmd">
<name>dbgcmd</name>
<desc>The debug encoding is as follows:
b00 = execute the instruction that the DBGINST [1:0] Registers contain
b01 = reserved
b10 = reserved
b11 = reserved.
This bit-field has the following special access attributes:
 swo: During secure access, it is  write only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnswo: During non-secure access, if thread is non-secure, it is write only.
</desc>
<sw_param offset="0xf8004d04" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_DBGINST0_instruction_byte1">
<name>instruction_byte1</name>
<desc>instruction byte 1
This bit-field has the following special access attributes:
 swo: During secure access, it is  write only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnswo: During non-secure access, if thread is non-secure, it is write only.
</desc>
<sw_param offset="0xf8004d08" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_DBGINST0_instruction_byte0">
<name>instruction_byte0</name>
<desc>instruction byte 0
This bit-field has the following special access attributes:
 swo: During secure access, it is  write only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnswo: During non-secure access, if thread is non-secure, it is write only.
</desc>
<sw_param offset="0xf8004d08" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_DBGINST0_reserved">
<name>reserved</name>
<desc>reserved, write as 0</desc>
<sw_param offset="0xf8004d08" start="15" end="11" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_DBGINST0_channel_num">
<name>channel_num</name>
<desc>DMA channel number:
b000 = DMA channel 0
b001 = DMA channel 1
b010 = DMA channel 2
.
.
.
b111 = DMA channel 7.
This bit-field has the following special access attributes:
 swo: During secure access, it is  write only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnswo: During non-secure access, if thread is non-secure, it is write only.
</desc>
<sw_param offset="0xf8004d08" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_DBGINST0_reserved_1">
<name>reserved_1</name>
<desc>reserved, write as 0</desc>
<sw_param offset="0xf8004d08" start="7" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_DBGINST0_debug_thread">
<name>debug_thread</name>
<desc>The debug thread encoding is as follows:
0 = DMA manager thread
1 = DMA channel.
Note
When set to 1, the Channel number field selects the DMA channel to debug.
This bit-field has the following special access attributes:
 swo: During secure access, it is  write only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnswo: During non-secure access, if thread is non-secure, it is write only.
</desc>
<sw_param offset="0xf8004d08" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_DBGINST1_instruction_byte5">
<name>instruction_byte5</name>
<desc>instruction byte 5
This bit-field has the following special access attributes:
 swo: During secure access, it is  write only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnswo: During non-secure access, if thread is non-secure, it is write only.
</desc>
<sw_param offset="0xf8004d0c" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_DBGINST1_instruction_byte4">
<name>instruction_byte4</name>
<desc>instruction byte 4
This bit-field has the following special access attributes:
 swo: During secure access, it is  write only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnswo: During non-secure access, if thread is non-secure, it is write only.
</desc>
<sw_param offset="0xf8004d0c" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_DBGINST1_instruction_byte3">
<name>instruction_byte3</name>
<desc>instruction byte 3
This bit-field has the following special access attributes:
 swo: During secure access, it is  write only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnswo: During non-secure access, if thread is non-secure, it is write only.
</desc>
<sw_param offset="0xf8004d0c" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_DBGINST1_instruction_byte2">
<name>instruction_byte2</name>
<desc>instruction byte 2
This bit-field has the following special access attributes:
 swo: During secure access, it is  write only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnswo: During non-secure access, if thread is non-secure, it is write only.
</desc>
<sw_param offset="0xf8004d0c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CR0_reserved">
<name>reserved</name>
<desc>read undefined</desc>
<sw_param offset="0xf8004e00" start="31" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CR0_num_events">
<name>num_events</name>
<desc>Number of interrupt outputs that the DMAC provides:
b00000 = 1 interrupt output, irq[0]
b00001 = 2 interrupt outputs, irq[1:0]
b00010 = 3 interrupt outputs, irq[2:0]
.
.
.
b11111 = 32 interrupt outputs, irq[31:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004e00" start="21" end="17" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CR0_num_periph_req">
<name>num_periph_req</name>
<desc>Number of peripheral request interfaces that the DMAC provides:
b00000 = 1 peripheral request interface
b00001 = 2 peripheral request interfaces
b00010 = 3 peripheral request interfaces
.
.
.
b11111 = 32 peripheral request interfaces.
Note
This field is only valid when the periph_req bit is set to 1.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004e00" start="16" end="12" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CR0_reserved_1">
<name>reserved_1</name>
<desc>read undefined</desc>
<sw_param offset="0xf8004e00" start="11" end="7" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CR0_num_chnls">
<name>num_chnls</name>
<desc>Number of DMA channels that the DMAC supports:
b000 = 1 DMA channel
b001 = 2 DMA channels
b010 = 3 DMA channels
.
.
.
b111 = 8 DMA channels.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004e00" start="6" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CR0_reserved_2">
<name>reserved_2</name>
<desc>read undefined</desc>
<sw_param offset="0xf8004e00" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CR0_mgr_ns_at_rst">
<name>mgr_ns_at_rst</name>
<desc>Indicates the status of the boot_manager_ns signal when the DMAC exited from reset:
0 = boot_manager_ns was LOW
1 = boot_manager_ns was HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004e00" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CR0_boot_en">
<name>boot_en</name>
<desc>Indicates the status of the boot_from_pc signal when the DMAC exited from reset:
0 = boot_from_pc was LOW
1 = boot_from_pc was HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004e00" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CR0_periph_req">
<name>periph_req</name>
<desc>Supports peripheral requests:
0 = the DMAC does not provide a peripheral request interface
1 = the DMAC provides the number of peripheral request interfaces that the num_periph_req field
specifies.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004e00" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CR1_reserved">
<name>reserved</name>
<desc>read undefined</desc>
<sw_param offset="0xf8004e04" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CR1_num_icache_lines">
<name>num_icache_lines</name>
<desc>Number of i-cache lines:
b0000 = 1 i-cache line
b0001 = 2 i-cache lines
b0010 = 3 i-cache lines
.
.
.
b1111 = 16 i-cache lines
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004e04" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CR1_reserved_1">
<name>reserved_1</name>
<desc>read undefined</desc>
<sw_param offset="0xf8004e04" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CR1_icache_len">
<name>icache_len</name>
<desc>The length of an i-cache line:
b000-b001 = reserved
b010 = 4 bytes
b011 = 8 bytes
b100 = 16 bytes
b101 = 32 bytes
b110-b111 = reserved.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004e04" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CR2_boot_addr">
<name>boot_addr</name>
<desc>Provides the value of boot_addr[31:0] when the DMAC exited from reset
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004e08" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CR3_INS">
<name>INS</name>
<desc>Provides the security state of an event-interrupt resource:
Bit [N] = 0 Event&lt;N&gt; or irq[N] is in the Secure state.
Bit [N] = 1 Event&lt;N&gt; or irq[N] is in the Non-secure state.
Note
The boot_irq_ns[x:0] signals initialize the bits in this register when the DMAC exits from reset.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004e0c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CR4_PNS">
<name>PNS</name>
<desc>Provides the security state of the peripheral request interfaces:
Bit [N] = 0 Peripheral request interface N is in the Secure state.
Bit [N] = 1 Peripheral request interface N is in the Non-secure state.
Note
The boot_periph_ns tie-off signals initialize the bits in this register when the DMAC exits from reset. See
Table A-12 on page A-9 for more information.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004e10" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CRD_reserved">
<name>reserved</name>
<desc>read undefined</desc>
<sw_param offset="0xf8004e14" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CRD_data_buffer_dep">
<name>data_buffer_dep</name>
<desc>The number of lines that the data buffer contains:
b000000000 = 1 line
b000000001 = 2 lines
.
.
.
b111111111 = 1024 lines.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004e14" start="29" end="20" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CRD_rd_q_dep">
<name>rd_q_dep</name>
<desc>The depth of the read queue:
b0000 = 1 line
b0001 = 2 lines
.
.
.
b1111 = 16 lines.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004e14" start="19" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CRD_reserved_1">
<name>reserved_1</name>
<desc>read undefined</desc>
<sw_param offset="0xf8004e14" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CRD_rd_cap">
<name>rd_cap</name>
<desc>Read issuing capability that programs the number of outstanding read transactions:
b000 = 1
b001 = 2
.
.
.
b111 = 8.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004e14" start="14" end="12" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CRD_wr_q_dep">
<name>wr_q_dep</name>
<desc>The depth of the write queue:
b0000 = 1 line
b0001 = 2 lines
.
.
.
b1111 = 16 lines.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004e14" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CRD_reserved_2">
<name>reserved_2</name>
<desc>read undefined</desc>
<sw_param offset="0xf8004e14" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CRD_wr_cap">
<name>wr_cap</name>
<desc>Write issuing capability that programs the number of outstanding write transactions:
b000 = 1
b001 = 2
.
.
.
b111 = 8.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004e14" start="6" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CRD_reserved_3">
<name>reserved_3</name>
<desc>read undefined</desc>
<sw_param offset="0xf8004e14" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_CRD_data_width">
<name>data_width</name>
<desc>The data bus width of the AXI master interface:
b000 = reserved
b001 = reserved
b010 = 32-bit
b011 = 64-bit
b100 = 128-bit
b101-b111 = reserved.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004e14" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_WD_reserved">
<name>reserved</name>
<desc>read undefined</desc>
<sw_param offset="0xf8004e80" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_WD_wd_irq_only">
<name>wd_irq_only</name>
<desc>Controls how the DMAC responds when it detects a lock-up condition:
0 = the DMAC aborts all of the contributing DMA channels and sets irq_abort HIGH
1 = the DMAC sets irq_abort HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004e80" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_periph_id_0_reserved">
<name>reserved</name>
<desc>read undefined</desc>
<sw_param offset="0xf8004fe0" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_periph_id_0_part_number_0">
<name>part_number_0</name>
<desc>returns 0x30
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004fe0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_periph_id_1_reserved">
<name>reserved</name>
<desc>read undefined</desc>
<sw_param offset="0xf8004fe4" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_periph_id_1_designer_0">
<name>designer_0</name>
<desc>returns 0x1
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004fe4" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_periph_id_1_part_number_1">
<name>part_number_1</name>
<desc>returns 0x3
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004fe4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_periph_id_2_reserved">
<name>reserved</name>
<desc>read undefined</desc>
<sw_param offset="0xf8004fe8" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_periph_id_2_revision">
<name>revision</name>
<desc>Identifies the revision:
0x0 for r0p0
0x1 for r1p0
0x2 for r1p1.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004fe8" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_periph_id_2_designer_1">
<name>designer_1</name>
<desc>returns 0x4
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004fe8" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_periph_id_3_reserved">
<name>reserved</name>
<desc>read undefined</desc>
<sw_param offset="0xf8004fec" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_periph_id_3_integration_cfg">
<name>integration_cfg</name>
<desc>Returns 0 to indicate that the DMAC does not contain integration test logic
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004fec" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_pcell_id_0_reserved">
<name>reserved</name>
<desc>read undefined</desc>
<sw_param offset="0xf8004ff0" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_pcell_id_0_pcell_id_0">
<name>pcell_id_0</name>
<desc>returnx 0x0d
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004ff0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_pcell_id_1_reserved">
<name>reserved</name>
<desc>read undefined</desc>
<sw_param offset="0xf8004ff4" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_pcell_id_1_pcell_id_1">
<name>pcell_id_1</name>
<desc>returns 0xf0
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004ff4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_pcell_id_2_reserved">
<name>reserved</name>
<desc>read undefined</desc>
<sw_param offset="0xf8004ff8" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_pcell_id_2_pcell_id_2">
<name>pcell_id_2</name>
<desc>returns 0x05
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004ff8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_pcell_id_3_reserved">
<name>reserved</name>
<desc>read undefined</desc>
<sw_param offset="0xf8004ffc" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_ns_pcell_id_3_pcell_id_3">
<name>pcell_id_3</name>
<desc>returns 0xb1
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8004ffc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_DSR_reserved">
<name>reserved</name>
<desc>Reserved, read undefined</desc>
<sw_param offset="0xf8003000" start="31" end="10" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_DSR_DNS">
<name>DNS</name>
<desc>Provides the security status of the DMA manager thread:
0 = DMA manager operates in the Secure state
1 = DMA manager operates in the Non-secure state.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003000" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_DSR_Wakeup_event">
<name>Wakeup_event</name>
<desc>When the DMA manager thread executes a DMAWFE instruction, it waits for the following event to occur:
b00000 = event[0]
b00001 = event[1]
b00010 = event[2]
.
.
.
b11111 = event[31].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003000" start="8" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_DSR_DMA_status">
<name>DMA_status</name>
<desc>The operating state of the DMA manager:
b0000 = Stopped
b0001 = Executing
b0010 = Cache miss
b0011 = Updating PC
b0100 = Waiting for event
b0101-b1110 = reserved
b1111 = Faulting.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003000" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_DPC_pc_mgr">
<name>pc_mgr</name>
<desc>Program counter for the DMA manager thread
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003004" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_INTEN_event_irq_select">
<name>event_irq_select</name>
<desc>Program the appropriate bit to control how the DMAC responds when it executes DMASEV:
Bit [N] = 0 If the DMAC executes DMASEV for the event-interrupt resource N then the DMAC signals
event N to all of the threads. Set bit [N] to 0 if your system design does not use irq[N] to
signal an interrupt request.
Bit [N] = 1 If the DMAC executes DMASEV for the event-interrupt resource N then the DMAC sets
irq[N] HIGH. Set bit [N] to 1 if your system design requires irq[N] to signal an interrupt
request.
This bit-field has the following special access attributes:
 srw: During secure access, it is read write.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsrw: During non-secure access, if thread is non-secure, it is read write.
</desc>
<sw_param offset="0xf8003020" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_INT_EVENT_RIS_DMASEV_active">
<name>DMASEV_active</name>
<desc>Returns the status of the event-interrupt resources:
Bit [N] = 0 Event N is inactive or irq[N] is LOW.
Bit [N] = 1 Event N is active or irq[N] is HIGH.
Note
When the DMAC executes a DMASEV N instruction to send event N, the INTEN Register
controls whether the DMAC:
signals an interrupt using the appropriate irq
sends the event to all of the threads.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003024" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_INTMIS_irq_status">
<name>irq_status</name>
<desc>Provides the status of the interrupts that are active in the DMAC:
Bit [N] = 0 Interrupt N is inactive and therefore irq[N] is LOW.
Bit [N] = 1 Interrupt N is active and therefore irq[N] is HIGH.
Note
You must use the INTCLR Register to set bit [N] to 0, see Interrupt Clear Register.
Note
Bit [N] is 0 if the INTEN Register programs DMASEV to signal an event
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003028" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_INTCLR_irq_clr">
<name>irq_clr</name>
<desc>Controls the clearing of the irq outputs:
Bit [N] = 0 The status of irq[N] does not change.
Bit [N] = 1 The DMAC sets irq[N] LOW if the INTEN Register programs the DMAC to signal an interrupt.
Otherwise, the status of irq[N] does not change.
This bit-field has the following special access attributes:
 swo: During secure access, it is  write only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnswo: During non-secure access, if thread is non-secure, it is write only.
</desc>
<sw_param offset="0xf800302c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FSRD_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf8003030" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FSRD_fs_mgr">
<name>fs_mgr</name>
<desc>Provides the fault status of the DMA manager. Read as:
0 = the DMA manager thread is not in the Faulting state
1 = the DMA manager thread is in the Faulting state.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003030" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FSRC_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf8003034" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FSRC_fault_status">
<name>fault_status</name>
<desc>Each bit provides the fault status of the corresponding channel. Read as:
Bit [N] = 0 No fault is present on DMA channel N.
Bit [N] = 1 DMA channel N is in the Faulting or Faulting completing state.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003034" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTRD_reserved">
<name>reserved</name>
<desc>read undefined</desc>
<sw_param offset="0xf8003038" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTRD_dbg_instr">
<name>dbg_instr</name>
<desc>If the DMA manager aborts, this bit indicates whether the erroneous instruction was read from the
system memory or from the debug interface:
0 = instruction that generated an abort was read from system memory
1 = instruction that generated an abort was read from the debug interface.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003038" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTRD_reserved_1">
<name>reserved_1</name>
<desc>read undefined</desc>
<sw_param offset="0xf8003038" start="29" end="17" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTRD_instr_fetch_err">
<name>instr_fetch_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA manager
performs an instruction fetch:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003038" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTRD_reserved_2">
<name>reserved_2</name>
<desc>read undefined</desc>
<sw_param offset="0xf8003038" start="15" end="6" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTRD_mgr_evnt_err">
<name>mgr_evnt_err</name>
<desc>Indicates whether the DMA manager was attempting to execute DMAWFE or DMASEV with inappropriate
security permissions:
0 = the DMA manager has appropriate security to execute DMAWFE or DMASEV
1 = a DMA manager thread in the Non-secure state attempted to execute either:
DMAWFE to wait for a secure event
H18DMASEV to create a secure event or secure interrupt.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003038" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTRD_dmago_err">
<name>dmago_err</name>
<desc>Indicates whether the DMA manager was attempting to execute DMAGO with inappropriate security
permissions:
0 = the DMA manager has appropriate security to execute DMAGO
1 = a DMA manager thread in the Non-secure state attempted to execute DMAGO to create a DMA channel
operating in the Secure state.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003038" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTRD_reserved_3">
<name>reserved_3</name>
<desc>read undefined</desc>
<sw_param offset="0xf8003038" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTRD_operand_invalid">
<name>operand_invalid</name>
<desc>Indicates whether the DMA manager was attempting to execute an instruction operand that was not valid
for the configuration of the DMAC:
0 = valid operand
1 = invalid operand.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003038" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTRD_undef_instr">
<name>undef_instr</name>
<desc>Indicates whether the DMA manager was attempting to execute an undefined instruction:
0 = defined instruction
1 = undefined instruction.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003038" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR0_lockup_err">
<name>lockup_err</name>
<desc>Indicates whether the DMA channel has locked-up because of resource starvation:
0 = DMA channel has adequate resources
1 = DMA channel has locked-up because of insufficient resources.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003040" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR0_dbg_instr">
<name>dbg_instr</name>
<desc>If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the
system memory or from the debug interface:
0 = instruction that generated an abort was read from system memory
1 = instruction that generated an abort was read from the debug interface.
This fault is an imprecise abort but the bit is only valid when a precise abort occurs.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003040" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR0_reserved">
<name>reserved</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003040" start="29" end="19" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR0_data_read_err">
<name>data_read_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs a data read:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003040" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR0_data_write_err">
<name>data_write_err</name>
<desc>Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel
thread performs a data write:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003040" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR0_instr_fetch_err">
<name>instr_fetch_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs an instruction fetch:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003040" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR0_reserved_1">
<name>reserved_1</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003040" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR0_st_data_unavailable">
<name>st_data_unavailable</name>
<desc>Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST:
0 = MFIFO contains all the data to enable the DMAST to complete
1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003040" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR0_mfifo_err">
<name>mfifo_err</name>
<desc>Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST.
Depending on the instruction:
DMALD 0 = MFIFO contains sufficient space
1 = MFIFO is too small to hold the data that DMALD requires.
DMAST 0 = MFIFO contains sufficient data
1 = MFIFO is too small to store the data to enable DMAST to complete.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003040" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR0_reserved_2">
<name>reserved_2</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003040" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR0_ch_rdwr_err">
<name>ch_rdwr_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn
Register to perform a secure read or secure write:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003040" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR0_ch_periph_err">
<name>ch_periph_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP,
DMASTP, or DMAFLUSHP with inappropriate security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFP to wait for a secure peripheral
DMALDP or DMASTP to notify a secure peripheral
DMAFLUSHP to flush a secure peripheral.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003040" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR0_ch_evnt_err">
<name>ch_evnt_err</name>
<desc>Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate
security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFE to wait for a secure event
DMASEV to create a secure event or secure interrupt.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003040" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR0_reserved_3">
<name>reserved_3</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003040" start="4" end="2" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR0_operand_invalid">
<name>operand_invalid</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an instruction operand that was
not valid for the configuration of the DMAC:
0 = valid operand
1 = invalid operand.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003040" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR0_undef_instr">
<name>undef_instr</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an undefined instruction:
0 = defined instruction
1 = undefined instruction.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003040" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR1_lockup_err">
<name>lockup_err</name>
<desc>Indicates whether the DMA channel has locked-up because of resource starvation:
0 = DMA channel has adequate resources
1 = DMA channel has locked-up because of insufficient resources.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003044" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR1_dbg_instr">
<name>dbg_instr</name>
<desc>If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the
system memory or from the debug interface:
0 = instruction that generated an abort was read from system memory
1 = instruction that generated an abort was read from the debug interface.
This fault is an imprecise abort but the bit is only valid when a precise abort occurs.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003044" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR1_reserved">
<name>reserved</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003044" start="29" end="19" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR1_data_read_err">
<name>data_read_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs a data read:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003044" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR1_data_write_err">
<name>data_write_err</name>
<desc>Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel
thread performs a data write:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003044" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR1_instr_fetch_err">
<name>instr_fetch_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs an instruction fetch:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003044" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR1_reserved_1">
<name>reserved_1</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003044" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR1_st_data_unavailable">
<name>st_data_unavailable</name>
<desc>Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST:
0 = MFIFO contains all the data to enable the DMAST to complete
1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003044" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR1_mfifo_err">
<name>mfifo_err</name>
<desc>Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST.
Depending on the instruction:
DMALD 0 = MFIFO contains sufficient space
1 = MFIFO is too small to hold the data that DMALD requires.
DMAST 0 = MFIFO contains sufficient data
1 = MFIFO is too small to store the data to enable DMAST to complete.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003044" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR1_reserved_2">
<name>reserved_2</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003044" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR1_ch_rdwr_err">
<name>ch_rdwr_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn
Register to perform a secure read or secure write:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003044" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR1_ch_periph_err">
<name>ch_periph_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP,
DMASTP, or DMAFLUSHP with inappropriate security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFP to wait for a secure peripheral
DMALDP or DMASTP to notify a secure peripheral
DMAFLUSHP to flush a secure peripheral.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003044" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR1_ch_evnt_err">
<name>ch_evnt_err</name>
<desc>Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate
security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFE to wait for a secure event
DMASEV to create a secure event or secure interrupt.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003044" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR1_reserved_3">
<name>reserved_3</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003044" start="4" end="2" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR1_operand_invalid">
<name>operand_invalid</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an instruction operand that was
not valid for the configuration of the DMAC:
0 = valid operand
1 = invalid operand.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003044" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR1_undef_instr">
<name>undef_instr</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an undefined instruction:
0 = defined instruction
1 = undefined instruction.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003044" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR2_lockup_err">
<name>lockup_err</name>
<desc>Indicates whether the DMA channel has locked-up because of resource starvation:
0 = DMA channel has adequate resources
1 = DMA channel has locked-up because of insufficient resources.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003048" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR2_dbg_instr">
<name>dbg_instr</name>
<desc>If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the
system memory or from the debug interface:
0 = instruction that generated an abort was read from system memory
1 = instruction that generated an abort was read from the debug interface.
This fault is an imprecise abort but the bit is only valid when a precise abort occurs.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003048" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR2_reserved">
<name>reserved</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003048" start="29" end="19" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR2_data_read_err">
<name>data_read_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs a data read:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003048" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR2_data_write_err">
<name>data_write_err</name>
<desc>Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel
thread performs a data write:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003048" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR2_instr_fetch_err">
<name>instr_fetch_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs an instruction fetch:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003048" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR2_reserved_1">
<name>reserved_1</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003048" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR2_st_data_unavailable">
<name>st_data_unavailable</name>
<desc>Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST:
0 = MFIFO contains all the data to enable the DMAST to complete
1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003048" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR2_mfifo_err">
<name>mfifo_err</name>
<desc>Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST.
Depending on the instruction:
DMALD 0 = MFIFO contains sufficient space
1 = MFIFO is too small to hold the data that DMALD requires.
DMAST 0 = MFIFO contains sufficient data
1 = MFIFO is too small to store the data to enable DMAST to complete.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003048" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR2_reserved_2">
<name>reserved_2</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003048" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR2_ch_rdwr_err">
<name>ch_rdwr_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn
Register to perform a secure read or secure write:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003048" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR2_ch_periph_err">
<name>ch_periph_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP,
DMASTP, or DMAFLUSHP with inappropriate security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFP to wait for a secure peripheral
DMALDP or DMASTP to notify a secure peripheral
DMAFLUSHP to flush a secure peripheral.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003048" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR2_ch_evnt_err">
<name>ch_evnt_err</name>
<desc>Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate
security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFE to wait for a secure event
DMASEV to create a secure event or secure interrupt.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003048" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR2_reserved_3">
<name>reserved_3</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003048" start="4" end="2" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR2_operand_invalid">
<name>operand_invalid</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an instruction operand that was
not valid for the configuration of the DMAC:
0 = valid operand
1 = invalid operand.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003048" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR2_undef_instr">
<name>undef_instr</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an undefined instruction:
0 = defined instruction
1 = undefined instruction.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003048" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR3_lockup_err">
<name>lockup_err</name>
<desc>Indicates whether the DMA channel has locked-up because of resource starvation:
0 = DMA channel has adequate resources
1 = DMA channel has locked-up because of insufficient resources.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800304c" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR3_dbg_instr">
<name>dbg_instr</name>
<desc>If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the
system memory or from the debug interface:
0 = instruction that generated an abort was read from system memory
1 = instruction that generated an abort was read from the debug interface.
This fault is an imprecise abort but the bit is only valid when a precise abort occurs.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800304c" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR3_reserved">
<name>reserved</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800304c" start="29" end="19" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR3_data_read_err">
<name>data_read_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs a data read:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800304c" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR3_data_write_err">
<name>data_write_err</name>
<desc>Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel
thread performs a data write:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800304c" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR3_instr_fetch_err">
<name>instr_fetch_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs an instruction fetch:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800304c" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR3_reserved_1">
<name>reserved_1</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800304c" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR3_st_data_unavailable">
<name>st_data_unavailable</name>
<desc>Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST:
0 = MFIFO contains all the data to enable the DMAST to complete
1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800304c" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR3_mfifo_err">
<name>mfifo_err</name>
<desc>Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST.
Depending on the instruction:
DMALD 0 = MFIFO contains sufficient space
1 = MFIFO is too small to hold the data that DMALD requires.
DMAST 0 = MFIFO contains sufficient data
1 = MFIFO is too small to store the data to enable DMAST to complete.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800304c" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR3_reserved_2">
<name>reserved_2</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800304c" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR3_ch_rdwr_err">
<name>ch_rdwr_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn
Register to perform a secure read or secure write:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800304c" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR3_ch_periph_err">
<name>ch_periph_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP,
DMASTP, or DMAFLUSHP with inappropriate security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFP to wait for a secure peripheral
DMALDP or DMASTP to notify a secure peripheral
DMAFLUSHP to flush a secure peripheral.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800304c" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR3_ch_evnt_err">
<name>ch_evnt_err</name>
<desc>Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate
security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFE to wait for a secure event
DMASEV to create a secure event or secure interrupt.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800304c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR3_reserved_3">
<name>reserved_3</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800304c" start="4" end="2" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR3_operand_invalid">
<name>operand_invalid</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an instruction operand that was
not valid for the configuration of the DMAC:
0 = valid operand
1 = invalid operand.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800304c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR3_undef_instr">
<name>undef_instr</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an undefined instruction:
0 = defined instruction
1 = undefined instruction.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800304c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR4_lockup_err">
<name>lockup_err</name>
<desc>Indicates whether the DMA channel has locked-up because of resource starvation:
0 = DMA channel has adequate resources
1 = DMA channel has locked-up because of insufficient resources.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003050" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR4_dbg_instr">
<name>dbg_instr</name>
<desc>If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the
system memory or from the debug interface:
0 = instruction that generated an abort was read from system memory
1 = instruction that generated an abort was read from the debug interface.
This fault is an imprecise abort but the bit is only valid when a precise abort occurs.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003050" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR4_reserved">
<name>reserved</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003050" start="29" end="19" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR4_data_read_err">
<name>data_read_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs a data read:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003050" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR4_data_write_err">
<name>data_write_err</name>
<desc>Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel
thread performs a data write:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003050" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR4_instr_fetch_err">
<name>instr_fetch_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs an instruction fetch:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003050" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR4_reserved_1">
<name>reserved_1</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003050" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR4_st_data_unavailable">
<name>st_data_unavailable</name>
<desc>Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST:
0 = MFIFO contains all the data to enable the DMAST to complete
1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003050" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR4_mfifo_err">
<name>mfifo_err</name>
<desc>Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST.
Depending on the instruction:
DMALD 0 = MFIFO contains sufficient space
1 = MFIFO is too small to hold the data that DMALD requires.
DMAST 0 = MFIFO contains sufficient data
1 = MFIFO is too small to store the data to enable DMAST to complete.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003050" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR4_reserved_2">
<name>reserved_2</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003050" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR4_ch_rdwr_err">
<name>ch_rdwr_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn
Register to perform a secure read or secure write:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003050" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR4_ch_periph_err">
<name>ch_periph_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP,
DMASTP, or DMAFLUSHP with inappropriate security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFP to wait for a secure peripheral
DMALDP or DMASTP to notify a secure peripheral
DMAFLUSHP to flush a secure peripheral.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003050" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR4_ch_evnt_err">
<name>ch_evnt_err</name>
<desc>Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate
security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFE to wait for a secure event
DMASEV to create a secure event or secure interrupt.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003050" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR4_reserved_3">
<name>reserved_3</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003050" start="4" end="2" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR4_operand_invalid">
<name>operand_invalid</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an instruction operand that was
not valid for the configuration of the DMAC:
0 = valid operand
1 = invalid operand.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003050" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR4_undef_instr">
<name>undef_instr</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an undefined instruction:
0 = defined instruction
1 = undefined instruction.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003050" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR5_lockup_err">
<name>lockup_err</name>
<desc>Indicates whether the DMA channel has locked-up because of resource starvation:
0 = DMA channel has adequate resources
1 = DMA channel has locked-up because of insufficient resources.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003054" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR5_dbg_instr">
<name>dbg_instr</name>
<desc>If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the
system memory or from the debug interface:
0 = instruction that generated an abort was read from system memory
1 = instruction that generated an abort was read from the debug interface.
This fault is an imprecise abort but the bit is only valid when a precise abort occurs.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003054" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR5_reserved">
<name>reserved</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003054" start="29" end="19" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR5_data_read_err">
<name>data_read_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs a data read:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003054" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR5_data_write_err">
<name>data_write_err</name>
<desc>Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel
thread performs a data write:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003054" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR5_instr_fetch_err">
<name>instr_fetch_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs an instruction fetch:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003054" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR5_reserved_1">
<name>reserved_1</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003054" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR5_st_data_unavailable">
<name>st_data_unavailable</name>
<desc>Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST:
0 = MFIFO contains all the data to enable the DMAST to complete
1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003054" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR5_mfifo_err">
<name>mfifo_err</name>
<desc>Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST.
Depending on the instruction:
DMALD 0 = MFIFO contains sufficient space
1 = MFIFO is too small to hold the data that DMALD requires.
DMAST 0 = MFIFO contains sufficient data
1 = MFIFO is too small to store the data to enable DMAST to complete.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003054" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR5_reserved_2">
<name>reserved_2</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003054" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR5_ch_rdwr_err">
<name>ch_rdwr_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn
Register to perform a secure read or secure write:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003054" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR5_ch_periph_err">
<name>ch_periph_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP,
DMASTP, or DMAFLUSHP with inappropriate security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFP to wait for a secure peripheral
DMALDP or DMASTP to notify a secure peripheral
DMAFLUSHP to flush a secure peripheral.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003054" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR5_ch_evnt_err">
<name>ch_evnt_err</name>
<desc>Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate
security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFE to wait for a secure event
DMASEV to create a secure event or secure interrupt.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003054" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR5_reserved_3">
<name>reserved_3</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003054" start="4" end="2" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR5_operand_invalid">
<name>operand_invalid</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an instruction operand that was
not valid for the configuration of the DMAC:
0 = valid operand
1 = invalid operand.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003054" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR5_undef_instr">
<name>undef_instr</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an undefined instruction:
0 = defined instruction
1 = undefined instruction.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003054" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR6_lockup_err">
<name>lockup_err</name>
<desc>Indicates whether the DMA channel has locked-up because of resource starvation:
0 = DMA channel has adequate resources
1 = DMA channel has locked-up because of insufficient resources.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003058" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR6_dbg_instr">
<name>dbg_instr</name>
<desc>If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the
system memory or from the debug interface:
0 = instruction that generated an abort was read from system memory
1 = instruction that generated an abort was read from the debug interface.
This fault is an imprecise abort but the bit is only valid when a precise abort occurs.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003058" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR6_reserved">
<name>reserved</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003058" start="29" end="19" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR6_data_read_err">
<name>data_read_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs a data read:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003058" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR6_data_write_err">
<name>data_write_err</name>
<desc>Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel
thread performs a data write:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003058" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR6_instr_fetch_err">
<name>instr_fetch_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs an instruction fetch:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003058" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR6_reserved_1">
<name>reserved_1</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003058" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR6_st_data_unavailable">
<name>st_data_unavailable</name>
<desc>Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST:
0 = MFIFO contains all the data to enable the DMAST to complete
1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003058" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR6_mfifo_err">
<name>mfifo_err</name>
<desc>Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST.
Depending on the instruction:
DMALD 0 = MFIFO contains sufficient space
1 = MFIFO is too small to hold the data that DMALD requires.
DMAST 0 = MFIFO contains sufficient data
1 = MFIFO is too small to store the data to enable DMAST to complete.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003058" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR6_reserved_2">
<name>reserved_2</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003058" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR6_ch_rdwr_err">
<name>ch_rdwr_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn
Register to perform a secure read or secure write:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003058" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR6_ch_periph_err">
<name>ch_periph_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP,
DMASTP, or DMAFLUSHP with inappropriate security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFP to wait for a secure peripheral
DMALDP or DMASTP to notify a secure peripheral
DMAFLUSHP to flush a secure peripheral.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003058" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR6_ch_evnt_err">
<name>ch_evnt_err</name>
<desc>Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate
security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFE to wait for a secure event
DMASEV to create a secure event or secure interrupt.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003058" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR6_reserved_3">
<name>reserved_3</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003058" start="4" end="2" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR6_operand_invalid">
<name>operand_invalid</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an instruction operand that was
not valid for the configuration of the DMAC:
0 = valid operand
1 = invalid operand.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003058" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR6_undef_instr">
<name>undef_instr</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an undefined instruction:
0 = defined instruction
1 = undefined instruction.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003058" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR7_lockup_err">
<name>lockup_err</name>
<desc>Indicates whether the DMA channel has locked-up because of resource starvation:
0 = DMA channel has adequate resources
1 = DMA channel has locked-up because of insufficient resources.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800305c" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR7_dbg_instr">
<name>dbg_instr</name>
<desc>If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the
system memory or from the debug interface:
0 = instruction that generated an abort was read from system memory
1 = instruction that generated an abort was read from the debug interface.
This fault is an imprecise abort but the bit is only valid when a precise abort occurs.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800305c" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR7_reserved">
<name>reserved</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800305c" start="29" end="19" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR7_data_read_err">
<name>data_read_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs a data read:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800305c" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR7_data_write_err">
<name>data_write_err</name>
<desc>Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel
thread performs a data write:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800305c" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR7_instr_fetch_err">
<name>instr_fetch_err</name>
<desc>Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel
thread performs an instruction fetch:
0 = OKAY response
1 = EXOKAY, SLVERR, or DECERR response.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800305c" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR7_reserved_1">
<name>reserved_1</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800305c" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR7_st_data_unavailable">
<name>st_data_unavailable</name>
<desc>Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST:
0 = MFIFO contains all the data to enable the DMAST to complete
1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800305c" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR7_mfifo_err">
<name>mfifo_err</name>
<desc>Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST.
Depending on the instruction:
DMALD 0 = MFIFO contains sufficient space
1 = MFIFO is too small to hold the data that DMALD requires.
DMAST 0 = MFIFO contains sufficient data
1 = MFIFO is too small to store the data to enable DMAST to complete.
This fault is an imprecise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800305c" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR7_reserved_2">
<name>reserved_2</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800305c" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR7_ch_rdwr_err">
<name>ch_rdwr_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn
Register to perform a secure read or secure write:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800305c" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR7_ch_periph_err">
<name>ch_periph_err</name>
<desc>Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP,
DMASTP, or DMAFLUSHP with inappropriate security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFP to wait for a secure peripheral
DMALDP or DMASTP to notify a secure peripheral
DMAFLUSHP to flush a secure peripheral.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800305c" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR7_ch_evnt_err">
<name>ch_evnt_err</name>
<desc>Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate
security permissions:
0 = a DMA channel thread in the Non-secure state is not violating the security permissions
1 = a DMA channel thread in the Non-secure state attempted to execute either:
DMAWFE to wait for a secure event
DMASEV to create a secure event or secure interrupt.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800305c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR7_reserved_3">
<name>reserved_3</name>
<desc>read undefined
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800305c" start="4" end="2" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR7_operand_invalid">
<name>operand_invalid</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an instruction operand that was
not valid for the configuration of the DMAC:
0 = valid operand
1 = invalid operand.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800305c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_FTR7_undef_instr">
<name>undef_instr</name>
<desc>Indicates whether the DMA channel thread was attempting to execute an undefined instruction:
0 = defined instruction
1 = undefined instruction.
This fault is a precise abort.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800305c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR0_reserved">
<name>reserved</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8003100" start="31" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR0_CNS">
<name>CNS</name>
<desc>The channel non-secure bit provides the security of the DMA channel:
0 = DMA channel operates in the Secure state
1 = DMA channel operates in the Non-secure state.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003100" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR0_reserved_1">
<name>reserved_1</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8003100" start="20" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR0_dmawfp_periph">
<name>dmawfp_periph</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set:
0 = DMAWFP executed with the periph operand not set
1 = DMAWFP executed with the periph operand set.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003100" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR0_dmawfp_b_ns">
<name>dmawfp_b_ns</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand
were set:
0 = DMAWFP executed with the single operand set
1 = DMAWFP executed with the burst operand set
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003100" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR0_reserved_2">
<name>reserved_2</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8003100" start="13" end="9" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR0_wakeup_num">
<name>wakeup_num</name>
<desc>If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits
indicate the event or peripheral number that the channel is waiting for:
b00000 = DMA channel is waiting for event, or peripheral, 0
b00001 = DMA channel is waiting for event, or peripheral, 1
b00010 = DMA channel is waiting for event, or peripheral, 2
.
.
.
b11111 = DMA channel is waiting for event, or peripheral, 31.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003100" start="8" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR0_channel_status">
<name>channel_status</name>
<desc>The channel status encoding is:
b0000 = Stopped
b0001 = Executing
b0010 = Cache miss
b0011 = Updating PC
b0100 = Waiting for event
b0101 = At barrier
b0110 = reserved
b0111 = Waiting for peripheral
b1000 = Killing
b1001 = Completing
b1010-b1101 = reserved
b1110 = Faulting completing
b1111 = Faulting.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003100" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CPC0_pc_chnl">
<name>pc_chnl</name>
<desc>Program counter for the DMA channel n thread, where n depends on the address
of the register
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003104" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR1_reserved">
<name>reserved</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8003108" start="31" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR1_CNS">
<name>CNS</name>
<desc>The channel non-secure bit provides the security of the DMA channel:
0 = DMA channel operates in the Secure state
1 = DMA channel operates in the Non-secure state.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003108" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR1_reserved_1">
<name>reserved_1</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8003108" start="20" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR1_dmawfp_periph">
<name>dmawfp_periph</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set:
0 = DMAWFP executed with the periph operand not set
1 = DMAWFP executed with the periph operand set.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003108" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR1_dmawfp_b_ns">
<name>dmawfp_b_ns</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand
were set:
0 = DMAWFP executed with the single operand set
1 = DMAWFP executed with the burst operand set
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003108" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR1_reserved_2">
<name>reserved_2</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8003108" start="13" end="9" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR1_wakeup_num">
<name>wakeup_num</name>
<desc>If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits
indicate the event or peripheral number that the channel is waiting for:
b00000 = DMA channel is waiting for event, or peripheral, 0
b00001 = DMA channel is waiting for event, or peripheral, 1
b00010 = DMA channel is waiting for event, or peripheral, 2
.
.
.
b11111 = DMA channel is waiting for event, or peripheral, 31.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003108" start="8" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR1_channel_status">
<name>channel_status</name>
<desc>The channel status encoding is:
b0000 = Stopped
b0001 = Executing
b0010 = Cache miss
b0011 = Updating PC
b0100 = Waiting for event
b0101 = At barrier
b0110 = reserved
b0111 = Waiting for peripheral
b1000 = Killing
b1001 = Completing
b1010-b1101 = reserved
b1110 = Faulting completing
b1111 = Faulting.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003108" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CPC1_pc_chnl">
<name>pc_chnl</name>
<desc>Program counter for the DMA channel n thread, where n depends on the address
of the register
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800310c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR2_reserved">
<name>reserved</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8003110" start="31" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR2_CNS">
<name>CNS</name>
<desc>The channel non-secure bit provides the security of the DMA channel:
0 = DMA channel operates in the Secure state
1 = DMA channel operates in the Non-secure state.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003110" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR2_reserved_1">
<name>reserved_1</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8003110" start="20" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR2_dmawfp_periph">
<name>dmawfp_periph</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set:
0 = DMAWFP executed with the periph operand not set
1 = DMAWFP executed with the periph operand set.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003110" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR2_dmawfp_b_ns">
<name>dmawfp_b_ns</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand
were set:
0 = DMAWFP executed with the single operand set
1 = DMAWFP executed with the burst operand set
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003110" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR2_reserved_2">
<name>reserved_2</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8003110" start="13" end="9" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR2_wakeup_num">
<name>wakeup_num</name>
<desc>If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits
indicate the event or peripheral number that the channel is waiting for:
b00000 = DMA channel is waiting for event, or peripheral, 0
b00001 = DMA channel is waiting for event, or peripheral, 1
b00010 = DMA channel is waiting for event, or peripheral, 2
.
.
.
b11111 = DMA channel is waiting for event, or peripheral, 31.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003110" start="8" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR2_channel_status">
<name>channel_status</name>
<desc>The channel status encoding is:
b0000 = Stopped
b0001 = Executing
b0010 = Cache miss
b0011 = Updating PC
b0100 = Waiting for event
b0101 = At barrier
b0110 = reserved
b0111 = Waiting for peripheral
b1000 = Killing
b1001 = Completing
b1010-b1101 = reserved
b1110 = Faulting completing
b1111 = Faulting.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003110" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CPC2_pc_chnl">
<name>pc_chnl</name>
<desc>Program counter for the DMA channel n thread, where n depends on the address
of the register
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003114" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR3_reserved">
<name>reserved</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8003118" start="31" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR3_CNS">
<name>CNS</name>
<desc>The channel non-secure bit provides the security of the DMA channel:
0 = DMA channel operates in the Secure state
1 = DMA channel operates in the Non-secure state.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003118" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR3_reserved_1">
<name>reserved_1</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8003118" start="20" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR3_dmawfp_periph">
<name>dmawfp_periph</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set:
0 = DMAWFP executed with the periph operand not set
1 = DMAWFP executed with the periph operand set.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003118" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR3_dmawfp_b_ns">
<name>dmawfp_b_ns</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand
were set:
0 = DMAWFP executed with the single operand set
1 = DMAWFP executed with the burst operand set
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003118" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR3_reserved_2">
<name>reserved_2</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8003118" start="13" end="9" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR3_wakeup_num">
<name>wakeup_num</name>
<desc>If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits
indicate the event or peripheral number that the channel is waiting for:
b00000 = DMA channel is waiting for event, or peripheral, 0
b00001 = DMA channel is waiting for event, or peripheral, 1
b00010 = DMA channel is waiting for event, or peripheral, 2
.
.
.
b11111 = DMA channel is waiting for event, or peripheral, 31.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003118" start="8" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR3_channel_status">
<name>channel_status</name>
<desc>The channel status encoding is:
b0000 = Stopped
b0001 = Executing
b0010 = Cache miss
b0011 = Updating PC
b0100 = Waiting for event
b0101 = At barrier
b0110 = reserved
b0111 = Waiting for peripheral
b1000 = Killing
b1001 = Completing
b1010-b1101 = reserved
b1110 = Faulting completing
b1111 = Faulting.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003118" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CPC3_pc_chnl">
<name>pc_chnl</name>
<desc>Program counter for the DMA channel n thread, where n depends on the address
of the register
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800311c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR4_reserved">
<name>reserved</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8003120" start="31" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR4_CNS">
<name>CNS</name>
<desc>The channel non-secure bit provides the security of the DMA channel:
0 = DMA channel operates in the Secure state
1 = DMA channel operates in the Non-secure state.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003120" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR4_reserved_1">
<name>reserved_1</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8003120" start="20" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR4_dmawfp_periph">
<name>dmawfp_periph</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set:
0 = DMAWFP executed with the periph operand not set
1 = DMAWFP executed with the periph operand set.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003120" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR4_dmawfp_b_ns">
<name>dmawfp_b_ns</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand
were set:
0 = DMAWFP executed with the single operand set
1 = DMAWFP executed with the burst operand set
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003120" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR4_reserved_2">
<name>reserved_2</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8003120" start="13" end="9" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR4_wakeup_num">
<name>wakeup_num</name>
<desc>If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits
indicate the event or peripheral number that the channel is waiting for:
b00000 = DMA channel is waiting for event, or peripheral, 0
b00001 = DMA channel is waiting for event, or peripheral, 1
b00010 = DMA channel is waiting for event, or peripheral, 2
.
.
.
b11111 = DMA channel is waiting for event, or peripheral, 31.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003120" start="8" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR4_channel_status">
<name>channel_status</name>
<desc>The channel status encoding is:
b0000 = Stopped
b0001 = Executing
b0010 = Cache miss
b0011 = Updating PC
b0100 = Waiting for event
b0101 = At barrier
b0110 = reserved
b0111 = Waiting for peripheral
b1000 = Killing
b1001 = Completing
b1010-b1101 = reserved
b1110 = Faulting completing
b1111 = Faulting.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003120" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CPC4_pc_chnl">
<name>pc_chnl</name>
<desc>Program counter for the DMA channel n thread, where n depends on the address
of the register
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003124" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR5_reserved">
<name>reserved</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8003128" start="31" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR5_CNS">
<name>CNS</name>
<desc>The channel non-secure bit provides the security of the DMA channel:
0 = DMA channel operates in the Secure state
1 = DMA channel operates in the Non-secure state.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003128" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR5_reserved_1">
<name>reserved_1</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8003128" start="20" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR5_dmawfp_periph">
<name>dmawfp_periph</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set:
0 = DMAWFP executed with the periph operand not set
1 = DMAWFP executed with the periph operand set.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003128" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR5_dmawfp_b_ns">
<name>dmawfp_b_ns</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand
were set:
0 = DMAWFP executed with the single operand set
1 = DMAWFP executed with the burst operand set
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003128" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR5_reserved_2">
<name>reserved_2</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8003128" start="13" end="9" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR5_wakeup_num">
<name>wakeup_num</name>
<desc>If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits
indicate the event or peripheral number that the channel is waiting for:
b00000 = DMA channel is waiting for event, or peripheral, 0
b00001 = DMA channel is waiting for event, or peripheral, 1
b00010 = DMA channel is waiting for event, or peripheral, 2
.
.
.
b11111 = DMA channel is waiting for event, or peripheral, 31.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003128" start="8" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR5_channel_status">
<name>channel_status</name>
<desc>The channel status encoding is:
b0000 = Stopped
b0001 = Executing
b0010 = Cache miss
b0011 = Updating PC
b0100 = Waiting for event
b0101 = At barrier
b0110 = reserved
b0111 = Waiting for peripheral
b1000 = Killing
b1001 = Completing
b1010-b1101 = reserved
b1110 = Faulting completing
b1111 = Faulting.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003128" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CPC5_pc_chnl">
<name>pc_chnl</name>
<desc>Program counter for the DMA channel n thread, where n depends on the address
of the register
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800312c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR6_reserved">
<name>reserved</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8003130" start="31" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR6_CNS">
<name>CNS</name>
<desc>The channel non-secure bit provides the security of the DMA channel:
0 = DMA channel operates in the Secure state
1 = DMA channel operates in the Non-secure state.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003130" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR6_reserved_1">
<name>reserved_1</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8003130" start="20" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR6_dmawfp_periph">
<name>dmawfp_periph</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set:
0 = DMAWFP executed with the periph operand not set
1 = DMAWFP executed with the periph operand set.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003130" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR6_dmawfp_b_ns">
<name>dmawfp_b_ns</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand
were set:
0 = DMAWFP executed with the single operand set
1 = DMAWFP executed with the burst operand set
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003130" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR6_reserved_2">
<name>reserved_2</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8003130" start="13" end="9" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR6_wakeup_num">
<name>wakeup_num</name>
<desc>If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits
indicate the event or peripheral number that the channel is waiting for:
b00000 = DMA channel is waiting for event, or peripheral, 0
b00001 = DMA channel is waiting for event, or peripheral, 1
b00010 = DMA channel is waiting for event, or peripheral, 2
.
.
.
b11111 = DMA channel is waiting for event, or peripheral, 31.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003130" start="8" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR6_channel_status">
<name>channel_status</name>
<desc>The channel status encoding is:
b0000 = Stopped
b0001 = Executing
b0010 = Cache miss
b0011 = Updating PC
b0100 = Waiting for event
b0101 = At barrier
b0110 = reserved
b0111 = Waiting for peripheral
b1000 = Killing
b1001 = Completing
b1010-b1101 = reserved
b1110 = Faulting completing
b1111 = Faulting.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003130" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CPC6_pc_chnl">
<name>pc_chnl</name>
<desc>Program counter for the DMA channel n thread, where n depends on the address
of the register
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003134" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR7_reserved">
<name>reserved</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8003138" start="31" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR7_CNS">
<name>CNS</name>
<desc>The channel non-secure bit provides the security of the DMA channel:
0 = DMA channel operates in the Secure state
1 = DMA channel operates in the Non-secure state.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003138" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR7_reserved_1">
<name>reserved_1</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8003138" start="20" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR7_dmawfp_periph">
<name>dmawfp_periph</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set:
0 = DMAWFP executed with the periph operand not set
1 = DMAWFP executed with the periph operand set.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003138" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR7_dmawfp_b_ns">
<name>dmawfp_b_ns</name>
<desc>When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand
were set:
0 = DMAWFP executed with the single operand set
1 = DMAWFP executed with the burst operand set
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003138" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR7_reserved_2">
<name>reserved_2</name>
<desc>reserved,read undefined</desc>
<sw_param offset="0xf8003138" start="13" end="9" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR7_wakeup_num">
<name>wakeup_num</name>
<desc>If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits
indicate the event or peripheral number that the channel is waiting for:
b00000 = DMA channel is waiting for event, or peripheral, 0
b00001 = DMA channel is waiting for event, or peripheral, 1
b00010 = DMA channel is waiting for event, or peripheral, 2
.
.
.
b11111 = DMA channel is waiting for event, or peripheral, 31.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003138" start="8" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CSR7_channel_status">
<name>channel_status</name>
<desc>The channel status encoding is:
b0000 = Stopped
b0001 = Executing
b0010 = Cache miss
b0011 = Updating PC
b0100 = Waiting for event
b0101 = At barrier
b0110 = reserved
b0111 = Waiting for peripheral
b1000 = Killing
b1001 = Completing
b1010-b1101 = reserved
b1110 = Faulting completing
b1111 = Faulting.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003138" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CPC7_pc_chnl">
<name>pc_chnl</name>
<desc>Program counter for the DMA channel n thread, where n depends on the address
of the register
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800313c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_SAR0_src_addr">
<name>src_addr</name>
<desc>Address of the source data for DMA channel n, where n depends on the address
of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003400" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_DAR0_dest_addr">
<name>dest_addr</name>
<desc>Address for the destination data for DMA channel n, where n depends on the
address of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003404" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR0_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf8003408" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR0_endian_swap_size">
<name>endian_swap_size</name>
<desc>Table 3-22 on page 3-29 defines whether data can be swapped between little-endian (LE) and
byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data
independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that b000 indicates that no swap must occur.
Endian swap size Description
b000 No swap, 8-bit data
b001 Swap bytes within 16-bit data
b010 Swap bytes within 32-bit data
b011 Swap bytes within 64-bit data
b100 Swap bytes within 128-bit data
b101 Reserved
b110 Reserved
b111 Reserved
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003408" start="30" end="28" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR0_dst_cache_ctrl">
<name>dst_cache_ctrl</name>
<desc>Programs the state of AWCACHE[3,1:0]a when the DMAC writes the destination data.
Bit [27] 0 = AWCACHE[3] is LOW
1 = AWCACHE[3] is HIGH.
Bit [26] 0 = AWCACHE[1] is LOW
1 = AWCACHE[1] is HIGH.
Bit [25] 0 = AWCACHE[0] is LOW
1 = AWCACHE[0] is HIGH.
Note
AWCACHE[2] is tied LOW by the DMAC.
Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003408" start="27" end="25" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR0_dst_prot_ctrl">
<name>dst_prot_ctrl</name>
<desc>Programs the state of AWPROT[2:0]a when the DMAC writes the destination data.
Bit [24] 0 = AWPROT[2] is LOW
1 = AWPROT[2] is HIGH.
Bit [23] 0 = AWPROT[1] is LOW
1 = AWPROT[1] is HIGH.
Bit [22] 0 = AWPROT[0] is LOW
1 = AWPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If
a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel
aborts
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003408" start="24" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR0_dst_burst_len">
<name>dst_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it writes
the destination data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003408" start="21" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR0_dst_burst_size">
<name>dst_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination:
b000 = writes 1 byte per beat
b001 = writes 2 bytes per beat
b010 = writes 4 bytes per beat
b011 = writes 8 bytes per beat
b100 = writes 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003408" start="17" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR0_dst_inc">
<name>dst_inc</name>
<desc>Programs the burst type that the DMAC performs when it writes the destination data:
0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003408" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR0_src_cache_ctrl">
<name>src_cache_ctrl</name>
<desc>Set the bits to control the state of ARCACHE[2:0]a when the DMAC reads the source data.
Bit [13] 0 = ARCACHE[2] is LOW
1 = ARCACHE[2] is HIGH.
Bit [12] 0 = ARCACHE[1] is LOW
1 = ARCACHE[1] is HIGH.
Bit [11] 0 = ARCACHE[0] is LOW
1 = ARCACHE[0] is HIGH.
Note
The DMAC ties ARCACHE[3] LOW.
Setting ARCACHE[2:1]=b10 violates the AXI protocol.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003408" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR0_src_prot_ctrl">
<name>src_prot_ctrl</name>
<desc>Programs the state of ARPROT[2:0]a when the DMAC reads the source data.
Bit [10] 0 = ARPROT[2] is LOW
1 = ARPROT[2] is HIGH.
Bit [9] 0 = ARPROT[1] is LOW
1 = ARPROT[1] is HIGH.
Bit [8] 0 = ARPROT[0] is LOW
1 = ARPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a
DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003408" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR0_src_burst_len">
<name>src_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it reads
the source data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003408" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR0_src_burst_size">
<name>src_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC reads from the source:
b000 = reads 1 byte per beat
b001 = reads 2 bytes per beat
b010 = reads 4 bytes per beat
b011 = reads 8 bytes per beat
b100 = reads 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003408" start="3" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR0_src_inc">
<name>src_inc</name>
<desc>Programs the burst type that the DMAC performs when it reads the source data:
0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003408" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC0_0_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf800340c" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC0_0_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter zero for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter zero
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800340c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC1_0_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf8003410" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC1_0_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter one for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter one.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003410" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_SAR1_src_addr">
<name>src_addr</name>
<desc>Address of the source data for DMA channel n, where n depends on the address
of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003420" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_DAR1_dest_addr">
<name>dest_addr</name>
<desc>Address for the destination data for DMA channel n, where n depends on the
address of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003424" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR1_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf8003428" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR1_endian_swap_size">
<name>endian_swap_size</name>
<desc>Table 3-22 on page 3-29 defines whether data can be swapped between little-endian (LE) and
byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data
independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that b000 indicates that no swap must occur.
Endian swap size Description
b000 No swap, 8-bit data
b001 Swap bytes within 16-bit data
b010 Swap bytes within 32-bit data
b011 Swap bytes within 64-bit data
b100 Swap bytes within 128-bit data
b101 Reserved
b110 Reserved
b111 Reserved
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003428" start="30" end="28" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR1_dst_cache_ctrl">
<name>dst_cache_ctrl</name>
<desc>Programs the state of AWCACHE[3,1:0]a when the DMAC writes the destination data.
Bit [27] 0 = AWCACHE[3] is LOW
1 = AWCACHE[3] is HIGH.
Bit [26] 0 = AWCACHE[1] is LOW
1 = AWCACHE[1] is HIGH.
Bit [25] 0 = AWCACHE[0] is LOW
1 = AWCACHE[0] is HIGH.
Note
AWCACHE[2] is tied LOW by the DMAC.
Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003428" start="27" end="25" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR1_dst_prot_ctrl">
<name>dst_prot_ctrl</name>
<desc>Programs the state of AWPROT[2:0]a when the DMAC writes the destination data.
Bit [24] 0 = AWPROT[2] is LOW
1 = AWPROT[2] is HIGH.
Bit [23] 0 = AWPROT[1] is LOW
1 = AWPROT[1] is HIGH.
Bit [22] 0 = AWPROT[0] is LOW
1 = AWPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If
a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel
aborts
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003428" start="24" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR1_dst_burst_len">
<name>dst_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it writes
the destination data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003428" start="21" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR1_dst_burst_size">
<name>dst_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination:
b000 = writes 1 byte per beat
b001 = writes 2 bytes per beat
b010 = writes 4 bytes per beat
b011 = writes 8 bytes per beat
b100 = writes 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003428" start="17" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR1_dst_inc">
<name>dst_inc</name>
<desc>Programs the burst type that the DMAC performs when it writes the destination data:
0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003428" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR1_src_cache_ctrl">
<name>src_cache_ctrl</name>
<desc>Set the bits to control the state of ARCACHE[2:0]a when the DMAC reads the source data.
Bit [13] 0 = ARCACHE[2] is LOW
1 = ARCACHE[2] is HIGH.
Bit [12] 0 = ARCACHE[1] is LOW
1 = ARCACHE[1] is HIGH.
Bit [11] 0 = ARCACHE[0] is LOW
1 = ARCACHE[0] is HIGH.
Note
The DMAC ties ARCACHE[3] LOW.
Setting ARCACHE[2:1]=b10 violates the AXI protocol.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003428" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR1_src_prot_ctrl">
<name>src_prot_ctrl</name>
<desc>Programs the state of ARPROT[2:0]a when the DMAC reads the source data.
Bit [10] 0 = ARPROT[2] is LOW
1 = ARPROT[2] is HIGH.
Bit [9] 0 = ARPROT[1] is LOW
1 = ARPROT[1] is HIGH.
Bit [8] 0 = ARPROT[0] is LOW
1 = ARPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a
DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003428" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR1_src_burst_len">
<name>src_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it reads
the source data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003428" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR1_src_burst_size">
<name>src_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC reads from the source:
b000 = reads 1 byte per beat
b001 = reads 2 bytes per beat
b010 = reads 4 bytes per beat
b011 = reads 8 bytes per beat
b100 = reads 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003428" start="3" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR1_src_inc">
<name>src_inc</name>
<desc>Programs the burst type that the DMAC performs when it reads the source data:
0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003428" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC0_1_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf800342c" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC0_1_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter zero for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter zero
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800342c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC1_1_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf8003430" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC1_1_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter one for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter one.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003430" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_SAR2_src_addr">
<name>src_addr</name>
<desc>Address of the source data for DMA channel n, where n depends on the address
of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003440" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_DAR2_dest_addr">
<name>dest_addr</name>
<desc>Address for the destination data for DMA channel n, where n depends on the
address of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003444" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR2_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf8003448" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR2_endian_swap_size">
<name>endian_swap_size</name>
<desc>Table 3-22 on page 3-29 defines whether data can be swapped between little-endian (LE) and
byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data
independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that b000 indicates that no swap must occur.
Endian swap size Description
b000 No swap, 8-bit data
b001 Swap bytes within 16-bit data
b010 Swap bytes within 32-bit data
b011 Swap bytes within 64-bit data
b100 Swap bytes within 128-bit data
b101 Reserved
b110 Reserved
b111 Reserved
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003448" start="30" end="28" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR2_dst_cache_ctrl">
<name>dst_cache_ctrl</name>
<desc>Programs the state of AWCACHE[3,1:0]a when the DMAC writes the destination data.
Bit [27] 0 = AWCACHE[3] is LOW
1 = AWCACHE[3] is HIGH.
Bit [26] 0 = AWCACHE[1] is LOW
1 = AWCACHE[1] is HIGH.
Bit [25] 0 = AWCACHE[0] is LOW
1 = AWCACHE[0] is HIGH.
Note
AWCACHE[2] is tied LOW by the DMAC.
Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003448" start="27" end="25" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR2_dst_prot_ctrl">
<name>dst_prot_ctrl</name>
<desc>Programs the state of AWPROT[2:0]a when the DMAC writes the destination data.
Bit [24] 0 = AWPROT[2] is LOW
1 = AWPROT[2] is HIGH.
Bit [23] 0 = AWPROT[1] is LOW
1 = AWPROT[1] is HIGH.
Bit [22] 0 = AWPROT[0] is LOW
1 = AWPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If
a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel
aborts
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003448" start="24" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR2_dst_burst_len">
<name>dst_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it writes
the destination data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003448" start="21" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR2_dst_burst_size">
<name>dst_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination:
b000 = writes 1 byte per beat
b001 = writes 2 bytes per beat
b010 = writes 4 bytes per beat
b011 = writes 8 bytes per beat
b100 = writes 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003448" start="17" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR2_dst_inc">
<name>dst_inc</name>
<desc>Programs the burst type that the DMAC performs when it writes the destination data:
0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003448" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR2_src_cache_ctrl">
<name>src_cache_ctrl</name>
<desc>Set the bits to control the state of ARCACHE[2:0]a when the DMAC reads the source data.
Bit [13] 0 = ARCACHE[2] is LOW
1 = ARCACHE[2] is HIGH.
Bit [12] 0 = ARCACHE[1] is LOW
1 = ARCACHE[1] is HIGH.
Bit [11] 0 = ARCACHE[0] is LOW
1 = ARCACHE[0] is HIGH.
Note
The DMAC ties ARCACHE[3] LOW.
Setting ARCACHE[2:1]=b10 violates the AXI protocol.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003448" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR2_src_prot_ctrl">
<name>src_prot_ctrl</name>
<desc>Programs the state of ARPROT[2:0]a when the DMAC reads the source data.
Bit [10] 0 = ARPROT[2] is LOW
1 = ARPROT[2] is HIGH.
Bit [9] 0 = ARPROT[1] is LOW
1 = ARPROT[1] is HIGH.
Bit [8] 0 = ARPROT[0] is LOW
1 = ARPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a
DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003448" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR2_src_burst_len">
<name>src_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it reads
the source data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003448" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR2_src_burst_size">
<name>src_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC reads from the source:
b000 = reads 1 byte per beat
b001 = reads 2 bytes per beat
b010 = reads 4 bytes per beat
b011 = reads 8 bytes per beat
b100 = reads 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003448" start="3" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR2_src_inc">
<name>src_inc</name>
<desc>Programs the burst type that the DMAC performs when it reads the source data:
0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003448" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC0_2_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf800344c" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC0_2_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter zero for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter zero
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800344c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC1_2_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf8003450" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC1_2_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter one for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter one.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003450" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_SAR3_src_addr">
<name>src_addr</name>
<desc>Address of the source data for DMA channel n, where n depends on the address
of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003460" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_DAR3_dest_addr">
<name>dest_addr</name>
<desc>Address for the destination data for DMA channel n, where n depends on the
address of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003464" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR3_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf8003468" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR3_endian_swap_size">
<name>endian_swap_size</name>
<desc>Table 3-22 on page 3-29 defines whether data can be swapped between little-endian (LE) and
byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data
independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that b000 indicates that no swap must occur.
Endian swap size Description
b000 No swap, 8-bit data
b001 Swap bytes within 16-bit data
b010 Swap bytes within 32-bit data
b011 Swap bytes within 64-bit data
b100 Swap bytes within 128-bit data
b101 Reserved
b110 Reserved
b111 Reserved
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003468" start="30" end="28" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR3_dst_cache_ctrl">
<name>dst_cache_ctrl</name>
<desc>Programs the state of AWCACHE[3,1:0]a when the DMAC writes the destination data.
Bit [27] 0 = AWCACHE[3] is LOW
1 = AWCACHE[3] is HIGH.
Bit [26] 0 = AWCACHE[1] is LOW
1 = AWCACHE[1] is HIGH.
Bit [25] 0 = AWCACHE[0] is LOW
1 = AWCACHE[0] is HIGH.
Note
AWCACHE[2] is tied LOW by the DMAC.
Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003468" start="27" end="25" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR3_dst_prot_ctrl">
<name>dst_prot_ctrl</name>
<desc>Programs the state of AWPROT[2:0]a when the DMAC writes the destination data.
Bit [24] 0 = AWPROT[2] is LOW
1 = AWPROT[2] is HIGH.
Bit [23] 0 = AWPROT[1] is LOW
1 = AWPROT[1] is HIGH.
Bit [22] 0 = AWPROT[0] is LOW
1 = AWPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If
a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel
aborts
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003468" start="24" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR3_dst_burst_len">
<name>dst_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it writes
the destination data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003468" start="21" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR3_dst_burst_size">
<name>dst_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination:
b000 = writes 1 byte per beat
b001 = writes 2 bytes per beat
b010 = writes 4 bytes per beat
b011 = writes 8 bytes per beat
b100 = writes 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003468" start="17" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR3_dst_inc">
<name>dst_inc</name>
<desc>Programs the burst type that the DMAC performs when it writes the destination data:
0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003468" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR3_src_cache_ctrl">
<name>src_cache_ctrl</name>
<desc>Set the bits to control the state of ARCACHE[2:0]a when the DMAC reads the source data.
Bit [13] 0 = ARCACHE[2] is LOW
1 = ARCACHE[2] is HIGH.
Bit [12] 0 = ARCACHE[1] is LOW
1 = ARCACHE[1] is HIGH.
Bit [11] 0 = ARCACHE[0] is LOW
1 = ARCACHE[0] is HIGH.
Note
The DMAC ties ARCACHE[3] LOW.
Setting ARCACHE[2:1]=b10 violates the AXI protocol.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003468" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR3_src_prot_ctrl">
<name>src_prot_ctrl</name>
<desc>Programs the state of ARPROT[2:0]a when the DMAC reads the source data.
Bit [10] 0 = ARPROT[2] is LOW
1 = ARPROT[2] is HIGH.
Bit [9] 0 = ARPROT[1] is LOW
1 = ARPROT[1] is HIGH.
Bit [8] 0 = ARPROT[0] is LOW
1 = ARPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a
DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003468" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR3_src_burst_len">
<name>src_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it reads
the source data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003468" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR3_src_burst_size">
<name>src_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC reads from the source:
b000 = reads 1 byte per beat
b001 = reads 2 bytes per beat
b010 = reads 4 bytes per beat
b011 = reads 8 bytes per beat
b100 = reads 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003468" start="3" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR3_src_inc">
<name>src_inc</name>
<desc>Programs the burst type that the DMAC performs when it reads the source data:
0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003468" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC0_3_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf800346c" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC0_3_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter zero for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter zero
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800346c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC1_3_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf8003470" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC1_3_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter one for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter one.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003470" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_SAR4_src_addr">
<name>src_addr</name>
<desc>Address of the source data for DMA channel n, where n depends on the address
of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003480" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_DAR4_dest_addr">
<name>dest_addr</name>
<desc>Address for the destination data for DMA channel n, where n depends on the
address of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003484" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR4_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf8003488" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR4_endian_swap_size">
<name>endian_swap_size</name>
<desc>Table 3-22 on page 3-29 defines whether data can be swapped between little-endian (LE) and
byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data
independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that b000 indicates that no swap must occur.
Endian swap size Description
b000 No swap, 8-bit data
b001 Swap bytes within 16-bit data
b010 Swap bytes within 32-bit data
b011 Swap bytes within 64-bit data
b100 Swap bytes within 128-bit data
b101 Reserved
b110 Reserved
b111 Reserved
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003488" start="30" end="28" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR4_dst_cache_ctrl">
<name>dst_cache_ctrl</name>
<desc>Programs the state of AWCACHE[3,1:0]a when the DMAC writes the destination data.
Bit [27] 0 = AWCACHE[3] is LOW
1 = AWCACHE[3] is HIGH.
Bit [26] 0 = AWCACHE[1] is LOW
1 = AWCACHE[1] is HIGH.
Bit [25] 0 = AWCACHE[0] is LOW
1 = AWCACHE[0] is HIGH.
Note
AWCACHE[2] is tied LOW by the DMAC.
Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003488" start="27" end="25" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR4_dst_prot_ctrl">
<name>dst_prot_ctrl</name>
<desc>Programs the state of AWPROT[2:0]a when the DMAC writes the destination data.
Bit [24] 0 = AWPROT[2] is LOW
1 = AWPROT[2] is HIGH.
Bit [23] 0 = AWPROT[1] is LOW
1 = AWPROT[1] is HIGH.
Bit [22] 0 = AWPROT[0] is LOW
1 = AWPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If
a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel
aborts
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003488" start="24" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR4_dst_burst_len">
<name>dst_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it writes
the destination data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003488" start="21" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR4_dst_burst_size">
<name>dst_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination:
b000 = writes 1 byte per beat
b001 = writes 2 bytes per beat
b010 = writes 4 bytes per beat
b011 = writes 8 bytes per beat
b100 = writes 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003488" start="17" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR4_dst_inc">
<name>dst_inc</name>
<desc>Programs the burst type that the DMAC performs when it writes the destination data:
0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003488" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR4_src_cache_ctrl">
<name>src_cache_ctrl</name>
<desc>Set the bits to control the state of ARCACHE[2:0]a when the DMAC reads the source data.
Bit [13] 0 = ARCACHE[2] is LOW
1 = ARCACHE[2] is HIGH.
Bit [12] 0 = ARCACHE[1] is LOW
1 = ARCACHE[1] is HIGH.
Bit [11] 0 = ARCACHE[0] is LOW
1 = ARCACHE[0] is HIGH.
Note
The DMAC ties ARCACHE[3] LOW.
Setting ARCACHE[2:1]=b10 violates the AXI protocol.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003488" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR4_src_prot_ctrl">
<name>src_prot_ctrl</name>
<desc>Programs the state of ARPROT[2:0]a when the DMAC reads the source data.
Bit [10] 0 = ARPROT[2] is LOW
1 = ARPROT[2] is HIGH.
Bit [9] 0 = ARPROT[1] is LOW
1 = ARPROT[1] is HIGH.
Bit [8] 0 = ARPROT[0] is LOW
1 = ARPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a
DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003488" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR4_src_burst_len">
<name>src_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it reads
the source data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003488" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR4_src_burst_size">
<name>src_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC reads from the source:
b000 = reads 1 byte per beat
b001 = reads 2 bytes per beat
b010 = reads 4 bytes per beat
b011 = reads 8 bytes per beat
b100 = reads 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003488" start="3" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR4_src_inc">
<name>src_inc</name>
<desc>Programs the burst type that the DMAC performs when it reads the source data:
0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003488" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC0_4_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf800348c" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC0_4_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter zero for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter zero
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf800348c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC1_4_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf8003490" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC1_4_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter one for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter one.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003490" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_SAR5_src_addr">
<name>src_addr</name>
<desc>Address of the source data for DMA channel n, where n depends on the address
of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034a0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_DAR5_dest_addr">
<name>dest_addr</name>
<desc>Address for the destination data for DMA channel n, where n depends on the
address of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034a4" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR5_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf80034a8" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR5_endian_swap_size">
<name>endian_swap_size</name>
<desc>Table 3-22 on page 3-29 defines whether data can be swapped between little-endian (LE) and
byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data
independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that b000 indicates that no swap must occur.
Endian swap size Description
b000 No swap, 8-bit data
b001 Swap bytes within 16-bit data
b010 Swap bytes within 32-bit data
b011 Swap bytes within 64-bit data
b100 Swap bytes within 128-bit data
b101 Reserved
b110 Reserved
b111 Reserved
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034a8" start="30" end="28" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR5_dst_cache_ctrl">
<name>dst_cache_ctrl</name>
<desc>Programs the state of AWCACHE[3,1:0]a when the DMAC writes the destination data.
Bit [27] 0 = AWCACHE[3] is LOW
1 = AWCACHE[3] is HIGH.
Bit [26] 0 = AWCACHE[1] is LOW
1 = AWCACHE[1] is HIGH.
Bit [25] 0 = AWCACHE[0] is LOW
1 = AWCACHE[0] is HIGH.
Note
AWCACHE[2] is tied LOW by the DMAC.
Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034a8" start="27" end="25" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR5_dst_prot_ctrl">
<name>dst_prot_ctrl</name>
<desc>Programs the state of AWPROT[2:0]a when the DMAC writes the destination data.
Bit [24] 0 = AWPROT[2] is LOW
1 = AWPROT[2] is HIGH.
Bit [23] 0 = AWPROT[1] is LOW
1 = AWPROT[1] is HIGH.
Bit [22] 0 = AWPROT[0] is LOW
1 = AWPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If
a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel
aborts
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034a8" start="24" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR5_dst_burst_len">
<name>dst_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it writes
the destination data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034a8" start="21" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR5_dst_burst_size">
<name>dst_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination:
b000 = writes 1 byte per beat
b001 = writes 2 bytes per beat
b010 = writes 4 bytes per beat
b011 = writes 8 bytes per beat
b100 = writes 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034a8" start="17" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR5_dst_inc">
<name>dst_inc</name>
<desc>Programs the burst type that the DMAC performs when it writes the destination data:
0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034a8" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR5_src_cache_ctrl">
<name>src_cache_ctrl</name>
<desc>Set the bits to control the state of ARCACHE[2:0]a when the DMAC reads the source data.
Bit [13] 0 = ARCACHE[2] is LOW
1 = ARCACHE[2] is HIGH.
Bit [12] 0 = ARCACHE[1] is LOW
1 = ARCACHE[1] is HIGH.
Bit [11] 0 = ARCACHE[0] is LOW
1 = ARCACHE[0] is HIGH.
Note
The DMAC ties ARCACHE[3] LOW.
Setting ARCACHE[2:1]=b10 violates the AXI protocol.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034a8" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR5_src_prot_ctrl">
<name>src_prot_ctrl</name>
<desc>Programs the state of ARPROT[2:0]a when the DMAC reads the source data.
Bit [10] 0 = ARPROT[2] is LOW
1 = ARPROT[2] is HIGH.
Bit [9] 0 = ARPROT[1] is LOW
1 = ARPROT[1] is HIGH.
Bit [8] 0 = ARPROT[0] is LOW
1 = ARPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a
DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034a8" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR5_src_burst_len">
<name>src_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it reads
the source data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034a8" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR5_src_burst_size">
<name>src_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC reads from the source:
b000 = reads 1 byte per beat
b001 = reads 2 bytes per beat
b010 = reads 4 bytes per beat
b011 = reads 8 bytes per beat
b100 = reads 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034a8" start="3" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR5_src_inc">
<name>src_inc</name>
<desc>Programs the burst type that the DMAC performs when it reads the source data:
0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034a8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC0_5_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf80034ac" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC0_5_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter zero for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter zero
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034ac" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC1_5_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf80034b0" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC1_5_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter one for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter one.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034b0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_SAR6_src_addr">
<name>src_addr</name>
<desc>Address of the source data for DMA channel n, where n depends on the address
of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034c0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_DAR6_dest_addr">
<name>dest_addr</name>
<desc>Address for the destination data for DMA channel n, where n depends on the
address of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034c4" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR6_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf80034c8" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR6_endian_swap_size">
<name>endian_swap_size</name>
<desc>Table 3-22 on page 3-29 defines whether data can be swapped between little-endian (LE) and
byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data
independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that b000 indicates that no swap must occur.
Endian swap size Description
b000 No swap, 8-bit data
b001 Swap bytes within 16-bit data
b010 Swap bytes within 32-bit data
b011 Swap bytes within 64-bit data
b100 Swap bytes within 128-bit data
b101 Reserved
b110 Reserved
b111 Reserved
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034c8" start="30" end="28" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR6_dst_cache_ctrl">
<name>dst_cache_ctrl</name>
<desc>Programs the state of AWCACHE[3,1:0]a when the DMAC writes the destination data.
Bit [27] 0 = AWCACHE[3] is LOW
1 = AWCACHE[3] is HIGH.
Bit [26] 0 = AWCACHE[1] is LOW
1 = AWCACHE[1] is HIGH.
Bit [25] 0 = AWCACHE[0] is LOW
1 = AWCACHE[0] is HIGH.
Note
AWCACHE[2] is tied LOW by the DMAC.
Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034c8" start="27" end="25" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR6_dst_prot_ctrl">
<name>dst_prot_ctrl</name>
<desc>Programs the state of AWPROT[2:0]a when the DMAC writes the destination data.
Bit [24] 0 = AWPROT[2] is LOW
1 = AWPROT[2] is HIGH.
Bit [23] 0 = AWPROT[1] is LOW
1 = AWPROT[1] is HIGH.
Bit [22] 0 = AWPROT[0] is LOW
1 = AWPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If
a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel
aborts
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034c8" start="24" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR6_dst_burst_len">
<name>dst_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it writes
the destination data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034c8" start="21" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR6_dst_burst_size">
<name>dst_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination:
b000 = writes 1 byte per beat
b001 = writes 2 bytes per beat
b010 = writes 4 bytes per beat
b011 = writes 8 bytes per beat
b100 = writes 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034c8" start="17" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR6_dst_inc">
<name>dst_inc</name>
<desc>Programs the burst type that the DMAC performs when it writes the destination data:
0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034c8" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR6_src_cache_ctrl">
<name>src_cache_ctrl</name>
<desc>Set the bits to control the state of ARCACHE[2:0]a when the DMAC reads the source data.
Bit [13] 0 = ARCACHE[2] is LOW
1 = ARCACHE[2] is HIGH.
Bit [12] 0 = ARCACHE[1] is LOW
1 = ARCACHE[1] is HIGH.
Bit [11] 0 = ARCACHE[0] is LOW
1 = ARCACHE[0] is HIGH.
Note
The DMAC ties ARCACHE[3] LOW.
Setting ARCACHE[2:1]=b10 violates the AXI protocol.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034c8" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR6_src_prot_ctrl">
<name>src_prot_ctrl</name>
<desc>Programs the state of ARPROT[2:0]a when the DMAC reads the source data.
Bit [10] 0 = ARPROT[2] is LOW
1 = ARPROT[2] is HIGH.
Bit [9] 0 = ARPROT[1] is LOW
1 = ARPROT[1] is HIGH.
Bit [8] 0 = ARPROT[0] is LOW
1 = ARPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a
DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034c8" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR6_src_burst_len">
<name>src_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it reads
the source data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034c8" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR6_src_burst_size">
<name>src_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC reads from the source:
b000 = reads 1 byte per beat
b001 = reads 2 bytes per beat
b010 = reads 4 bytes per beat
b011 = reads 8 bytes per beat
b100 = reads 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034c8" start="3" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR6_src_inc">
<name>src_inc</name>
<desc>Programs the burst type that the DMAC performs when it reads the source data:
0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034c8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC0_6_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf80034cc" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC0_6_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter zero for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter zero
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034cc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC1_6_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf80034d0" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC1_6_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter one for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter one.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034d0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_SAR7_src_addr">
<name>src_addr</name>
<desc>Address of the source data for DMA channel n, where n depends on the address
of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034e0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_DAR7_dest_addr">
<name>dest_addr</name>
<desc>Address for the destination data for DMA channel n, where n depends on the
address of the register.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034e4" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR7_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf80034e8" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR7_endian_swap_size">
<name>endian_swap_size</name>
<desc>Table 3-22 on page 3-29 defines whether data can be swapped between little-endian (LE) and
byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data
independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that b000 indicates that no swap must occur.
Endian swap size Description
b000 No swap, 8-bit data
b001 Swap bytes within 16-bit data
b010 Swap bytes within 32-bit data
b011 Swap bytes within 64-bit data
b100 Swap bytes within 128-bit data
b101 Reserved
b110 Reserved
b111 Reserved
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034e8" start="30" end="28" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR7_dst_cache_ctrl">
<name>dst_cache_ctrl</name>
<desc>Programs the state of AWCACHE[3,1:0]a when the DMAC writes the destination data.
Bit [27] 0 = AWCACHE[3] is LOW
1 = AWCACHE[3] is HIGH.
Bit [26] 0 = AWCACHE[1] is LOW
1 = AWCACHE[1] is HIGH.
Bit [25] 0 = AWCACHE[0] is LOW
1 = AWCACHE[0] is HIGH.
Note
AWCACHE[2] is tied LOW by the DMAC.
Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034e8" start="27" end="25" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR7_dst_prot_ctrl">
<name>dst_prot_ctrl</name>
<desc>Programs the state of AWPROT[2:0]a when the DMAC writes the destination data.
Bit [24] 0 = AWPROT[2] is LOW
1 = AWPROT[2] is HIGH.
Bit [23] 0 = AWPROT[1] is LOW
1 = AWPROT[1] is HIGH.
Bit [22] 0 = AWPROT[0] is LOW
1 = AWPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If
a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel
aborts
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034e8" start="24" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR7_dst_burst_len">
<name>dst_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it writes
the destination data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034e8" start="21" end="18" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR7_dst_burst_size">
<name>dst_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination:
b000 = writes 1 byte per beat
b001 = writes 2 bytes per beat
b010 = writes 4 bytes per beat
b011 = writes 8 bytes per beat
b100 = writes 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction
is the product of dst_burst_len and dst_burst_size.
Note
These bits control the state of AWSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034e8" start="17" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR7_dst_inc">
<name>dst_inc</name>
<desc>Programs the burst type that the DMAC performs when it writes the destination data:
0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034e8" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR7_src_cache_ctrl">
<name>src_cache_ctrl</name>
<desc>Set the bits to control the state of ARCACHE[2:0]a when the DMAC reads the source data.
Bit [13] 0 = ARCACHE[2] is LOW
1 = ARCACHE[2] is HIGH.
Bit [12] 0 = ARCACHE[1] is LOW
1 = ARCACHE[1] is HIGH.
Bit [11] 0 = ARCACHE[0] is LOW
1 = ARCACHE[0] is HIGH.
Note
The DMAC ties ARCACHE[3] LOW.
Setting ARCACHE[2:1]=b10 violates the AXI protocol.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034e8" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR7_src_prot_ctrl">
<name>src_prot_ctrl</name>
<desc>Programs the state of ARPROT[2:0]a when the DMAC reads the source data.
Bit [10] 0 = ARPROT[2] is LOW
1 = ARPROT[2] is HIGH.
Bit [9] 0 = ARPROT[1] is LOW
1 = ARPROT[1] is HIGH.
Bit [8] 0 = ARPROT[0] is LOW
1 = ARPROT[0] is HIGH.
Note
Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a
DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034e8" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR7_src_burst_len">
<name>src_burst_len</name>
<desc>For each burst, these bits program the number of data transfers that the DMAC performs when it reads
the source data:
b0000 = 1 data transfer
b0001 = 2 data transfers
b0010 = 3 data transfers
.
.
.
b1111 = 16 data transfers.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARLEN[3:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034e8" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR7_src_burst_size">
<name>src_burst_size</name>
<desc>For each beat within a burst, it programs the number of bytes that the DMAC reads from the source:
b000 = reads 1 byte per beat
b001 = reads 2 bytes per beat
b010 = reads 4 bytes per beat
b011 = reads 8 bytes per beat
b100 = reads 16 bytes per beat
b101-b111 = reserved.
The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction
is the product of src_burst_len and src_burst_size.
Note
These bits control the state of ARSIZE[2:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034e8" start="3" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CCR7_src_inc">
<name>src_inc</name>
<desc>Programs the burst type that the DMAC performs when it reads the source data:
0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW.
1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034e8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC0_7_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf80034ec" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC0_7_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter zero for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter zero
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034ec" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC1_7_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf80034f0" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_LC1_7_loop_counter_iteration">
<name>loop_counter_iteration</name>
<desc>Provides the status of loop counter one for the DMA channel. The DMAC
updates this register when it executes DMALPEND[S|B], and the DMA
channel thread is programmed to use loop counter one.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf80034f0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_DBGSTATUS_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf8003d00" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_DBGSTATUS_dbgstatus">
<name>dbgstatus</name>
<desc>The debug status encoding is:
0 = Idle
1 = Busy.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003d00" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_DBGCMD_reserved">
<name>reserved</name>
<desc>reserved, read undefined</desc>
<sw_param offset="0xf8003d04" start="31" end="2" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_DBGCMD_dbgcmd">
<name>dbgcmd</name>
<desc>The debug encoding is as follows:
b00 = execute the instruction that the DBGINST [1:0] Registers contain
b01 = reserved
b10 = reserved
b11 = reserved.
This bit-field has the following special access attributes:
 swo: During secure access, it is  write only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnswo: During non-secure access, if thread is non-secure, it is write only.
</desc>
<sw_param offset="0xf8003d04" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_DBGINST0_instruction_byte1">
<name>instruction_byte1</name>
<desc>instruction byte 1
This bit-field has the following special access attributes:
 swo: During secure access, it is  write only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnswo: During non-secure access, if thread is non-secure, it is write only.
</desc>
<sw_param offset="0xf8003d08" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_DBGINST0_instruction_byte0">
<name>instruction_byte0</name>
<desc>instruction byte 0
This bit-field has the following special access attributes:
 swo: During secure access, it is  write only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnswo: During non-secure access, if thread is non-secure, it is write only.
</desc>
<sw_param offset="0xf8003d08" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_DBGINST0_reserved">
<name>reserved</name>
<desc>reserved, write as 0</desc>
<sw_param offset="0xf8003d08" start="15" end="11" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_DBGINST0_channel_num">
<name>channel_num</name>
<desc>DMA channel number:
b000 = DMA channel 0
b001 = DMA channel 1
b010 = DMA channel 2
.
.
.
b111 = DMA channel 7.
This bit-field has the following special access attributes:
 swo: During secure access, it is  write only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnswo: During non-secure access, if thread is non-secure, it is write only.
</desc>
<sw_param offset="0xf8003d08" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_DBGINST0_reserved_1">
<name>reserved_1</name>
<desc>reserved, write as 0</desc>
<sw_param offset="0xf8003d08" start="7" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_DBGINST0_debug_thread">
<name>debug_thread</name>
<desc>The debug thread encoding is as follows:
0 = DMA manager thread
1 = DMA channel.
Note
When set to 1, the Channel number field selects the DMA channel to debug.
This bit-field has the following special access attributes:
 swo: During secure access, it is  write only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnswo: During non-secure access, if thread is non-secure, it is write only.
</desc>
<sw_param offset="0xf8003d08" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_DBGINST1_instruction_byte5">
<name>instruction_byte5</name>
<desc>instruction byte 5
This bit-field has the following special access attributes:
 swo: During secure access, it is  write only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnswo: During non-secure access, if thread is non-secure, it is write only.
</desc>
<sw_param offset="0xf8003d0c" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_DBGINST1_instruction_byte4">
<name>instruction_byte4</name>
<desc>instruction byte 4
This bit-field has the following special access attributes:
 swo: During secure access, it is  write only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnswo: During non-secure access, if thread is non-secure, it is write only.
</desc>
<sw_param offset="0xf8003d0c" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_DBGINST1_instruction_byte3">
<name>instruction_byte3</name>
<desc>instruction byte 3
This bit-field has the following special access attributes:
 swo: During secure access, it is  write only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnswo: During non-secure access, if thread is non-secure, it is write only.
</desc>
<sw_param offset="0xf8003d0c" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_DBGINST1_instruction_byte2">
<name>instruction_byte2</name>
<desc>instruction byte 2
This bit-field has the following special access attributes:
 swo: During secure access, it is  write only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnswo: During non-secure access, if thread is non-secure, it is write only.
</desc>
<sw_param offset="0xf8003d0c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CR0_reserved">
<name>reserved</name>
<desc>read undefined</desc>
<sw_param offset="0xf8003e00" start="31" end="22" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CR0_num_events">
<name>num_events</name>
<desc>Number of interrupt outputs that the DMAC provides:
b00000 = 1 interrupt output, irq[0]
b00001 = 2 interrupt outputs, irq[1:0]
b00010 = 3 interrupt outputs, irq[2:0]
.
.
.
b11111 = 32 interrupt outputs, irq[31:0].
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003e00" start="21" end="17" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CR0_num_periph_req">
<name>num_periph_req</name>
<desc>Number of peripheral request interfaces that the DMAC provides:
b00000 = 1 peripheral request interface
b00001 = 2 peripheral request interfaces
b00010 = 3 peripheral request interfaces
.
.
.
b11111 = 32 peripheral request interfaces.
Note
This field is only valid when the periph_req bit is set to 1.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003e00" start="16" end="12" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CR0_reserved_1">
<name>reserved_1</name>
<desc>read undefined</desc>
<sw_param offset="0xf8003e00" start="11" end="7" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CR0_num_chnls">
<name>num_chnls</name>
<desc>Number of DMA channels that the DMAC supports:
b000 = 1 DMA channel
b001 = 2 DMA channels
b010 = 3 DMA channels
.
.
.
b111 = 8 DMA channels.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003e00" start="6" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CR0_reserved_2">
<name>reserved_2</name>
<desc>read undefined</desc>
<sw_param offset="0xf8003e00" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CR0_mgr_ns_at_rst">
<name>mgr_ns_at_rst</name>
<desc>Indicates the status of the boot_manager_ns signal when the DMAC exited from reset:
0 = boot_manager_ns was LOW
1 = boot_manager_ns was HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003e00" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CR0_boot_en">
<name>boot_en</name>
<desc>Indicates the status of the boot_from_pc signal when the DMAC exited from reset:
0 = boot_from_pc was LOW
1 = boot_from_pc was HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003e00" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CR0_periph_req">
<name>periph_req</name>
<desc>Supports peripheral requests:
0 = the DMAC does not provide a peripheral request interface
1 = the DMAC provides the number of peripheral request interfaces that the num_periph_req field
specifies.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003e00" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CR1_reserved">
<name>reserved</name>
<desc>read undefined</desc>
<sw_param offset="0xf8003e04" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CR1_num_icache_lines">
<name>num_icache_lines</name>
<desc>Number of i-cache lines:
b0000 = 1 i-cache line
b0001 = 2 i-cache lines
b0010 = 3 i-cache lines
.
.
.
b1111 = 16 i-cache lines
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003e04" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CR1_reserved_1">
<name>reserved_1</name>
<desc>read undefined</desc>
<sw_param offset="0xf8003e04" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CR1_icache_len">
<name>icache_len</name>
<desc>The length of an i-cache line:
b000-b001 = reserved
b010 = 4 bytes
b011 = 8 bytes
b100 = 16 bytes
b101 = 32 bytes
b110-b111 = reserved.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003e04" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CR2_boot_addr">
<name>boot_addr</name>
<desc>Provides the value of boot_addr[31:0] when the DMAC exited from reset
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003e08" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CR3_INS">
<name>INS</name>
<desc>Provides the security state of an event-interrupt resource:
Bit [N] = 0 Event&lt;N&gt; or irq[N] is in the Secure state.
Bit [N] = 1 Event&lt;N&gt; or irq[N] is in the Non-secure state.
Note
The boot_irq_ns[x:0] signals initialize the bits in this register when the DMAC exits from reset.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003e0c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CR4_PNS">
<name>PNS</name>
<desc>Provides the security state of the peripheral request interfaces:
Bit [N] = 0 Peripheral request interface N is in the Secure state.
Bit [N] = 1 Peripheral request interface N is in the Non-secure state.
Note
The boot_periph_ns tie-off signals initialize the bits in this register when the DMAC exits from reset. See
Table A-12 on page A-9 for more information.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003e10" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CRD_reserved">
<name>reserved</name>
<desc>read undefined</desc>
<sw_param offset="0xf8003e14" start="31" end="30" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CRD_data_buffer_dep">
<name>data_buffer_dep</name>
<desc>The number of lines that the data buffer contains:
b000000000 = 1 line
b000000001 = 2 lines
.
.
.
b111111111 = 1024 lines.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003e14" start="29" end="20" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CRD_rd_q_dep">
<name>rd_q_dep</name>
<desc>The depth of the read queue:
b0000 = 1 line
b0001 = 2 lines
.
.
.
b1111 = 16 lines.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003e14" start="19" end="16" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CRD_reserved_1">
<name>reserved_1</name>
<desc>read undefined</desc>
<sw_param offset="0xf8003e14" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CRD_rd_cap">
<name>rd_cap</name>
<desc>Read issuing capability that programs the number of outstanding read transactions:
b000 = 1
b001 = 2
.
.
.
b111 = 8.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003e14" start="14" end="12" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CRD_wr_q_dep">
<name>wr_q_dep</name>
<desc>The depth of the write queue:
b0000 = 1 line
b0001 = 2 lines
.
.
.
b1111 = 16 lines.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003e14" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CRD_reserved_2">
<name>reserved_2</name>
<desc>read undefined</desc>
<sw_param offset="0xf8003e14" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CRD_wr_cap">
<name>wr_cap</name>
<desc>Write issuing capability that programs the number of outstanding write transactions:
b000 = 1
b001 = 2
.
.
.
b111 = 8.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003e14" start="6" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CRD_reserved_3">
<name>reserved_3</name>
<desc>read undefined</desc>
<sw_param offset="0xf8003e14" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_CRD_data_width">
<name>data_width</name>
<desc>The data bus width of the AXI master interface:
b000 = reserved
b001 = reserved
b010 = 32-bit
b011 = 64-bit
b100 = 128-bit
b101-b111 = reserved.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003e14" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_WD_reserved">
<name>reserved</name>
<desc>read undefined</desc>
<sw_param offset="0xf8003e80" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_WD_wd_irq_only">
<name>wd_irq_only</name>
<desc>Controls how the DMAC responds when it detects a lock-up condition:
0 = the DMAC aborts all of the contributing DMA channels and sets irq_abort HIGH
1 = the DMAC sets irq_abort HIGH.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003e80" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_periph_id_0_reserved">
<name>reserved</name>
<desc>read undefined</desc>
<sw_param offset="0xf8003fe0" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_periph_id_0_part_number_0">
<name>part_number_0</name>
<desc>returns 0x30
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003fe0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_periph_id_1_reserved">
<name>reserved</name>
<desc>read undefined</desc>
<sw_param offset="0xf8003fe4" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_periph_id_1_designer_0">
<name>designer_0</name>
<desc>returns 0x1
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003fe4" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_periph_id_1_part_number_1">
<name>part_number_1</name>
<desc>returns 0x3
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003fe4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_periph_id_2_reserved">
<name>reserved</name>
<desc>read undefined</desc>
<sw_param offset="0xf8003fe8" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_periph_id_2_revision">
<name>revision</name>
<desc>Identifies the revision:
0x0 for r0p0
0x1 for r1p0
0x2 for r1p1.
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003fe8" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_periph_id_2_designer_1">
<name>designer_1</name>
<desc>returns 0x4
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003fe8" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_periph_id_3_reserved">
<name>reserved</name>
<desc>read undefined</desc>
<sw_param offset="0xf8003fec" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_periph_id_3_integration_cfg">
<name>integration_cfg</name>
<desc>Returns 0 to indicate that the DMAC does not contain integration test logic
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003fec" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_pcell_id_0_reserved">
<name>reserved</name>
<desc>read undefined</desc>
<sw_param offset="0xf8003ff0" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_pcell_id_0_pcell_id_0">
<name>pcell_id_0</name>
<desc>returnx 0x0d
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003ff0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_pcell_id_1_reserved">
<name>reserved</name>
<desc>read undefined</desc>
<sw_param offset="0xf8003ff4" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_pcell_id_1_pcell_id_1">
<name>pcell_id_1</name>
<desc>returns 0xf0
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003ff4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_pcell_id_2_reserved">
<name>reserved</name>
<desc>read undefined</desc>
<sw_param offset="0xf8003ff8" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_pcell_id_2_pcell_id_2">
<name>pcell_id_2</name>
<desc>returns 0x05
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003ff8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_pcell_id_3_reserved">
<name>reserved</name>
<desc>read undefined</desc>
<sw_param offset="0xf8003ffc" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_dmac0_s_pcell_id_3_pcell_id_3">
<name>pcell_id_3</name>
<desc>returns 0xb1
This bit-field has the following special access attributes:
 sro: During secure access, it is read only.
 nssraz: During non-secure access, if thread is secure, it is read as zero.
 nsnsro: During non-secure access, if thread is non-secure, it is read only.
</desc>
<sw_param offset="0xf8003ffc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Clock_Control_1_Ex_E">
<name>Ex_E</name>
<desc>External Clock Edge: when this bit is set and the extend clock is selected, the counter clocks on the negative going edge of the external clock input.</desc>
<sw_param offset="0xf8002000" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_ttc1_Clock_Control_1_C_Src">
<name>C_Src</name>
<desc>Clock Source: when this bit is set the counter uses the external clock input, ext_clk; the default clock source is pclk.</desc>
<sw_param offset="0xf8002000" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_ttc1_Clock_Control_1_PS_V">
<name>PS_V</name>
<desc>Prescale value (N): if prescale is enabled, the count rate is divided by 2N+1 (divided by 2 to 65536)</desc>
<sw_param offset="0xf8002000" start="4" end="1" />
</parameter>
<parameter uniqueid="ps7_ttc1_Clock_Control_1_PS_En">
<name>PS_En</name>
<desc>Prescale enable: when this bit is set the counter, clock source is prescaled; the default clock source is that defined by C_Src.the default</desc>
<sw_param offset="0xf8002000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Clock_Control_2_Ex_E">
<name>Ex_E</name>
<desc>External Clock Edge: when this bit is set and the extend clock is selected, the counter clocks on the negative going edge of the external clock input.</desc>
<sw_param offset="0xf8002004" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_ttc1_Clock_Control_2_C_Src">
<name>C_Src</name>
<desc>Clock Source: when this bit is set the counter uses the external clock input, ext_clk; the default clock source is pclk.</desc>
<sw_param offset="0xf8002004" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_ttc1_Clock_Control_2_PS_V">
<name>PS_V</name>
<desc>Prescale value (N): if prescale is enabled, the count rate is divided by 2N+1 (divided by 2 to 65536)</desc>
<sw_param offset="0xf8002004" start="4" end="1" />
</parameter>
<parameter uniqueid="ps7_ttc1_Clock_Control_2_PS_En">
<name>PS_En</name>
<desc>Prescale enable: when this bit is set the counter, clock source is prescaled; the default clock source is that defined by C_Src.the default</desc>
<sw_param offset="0xf8002004" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Clock_Control_3_Ex_E">
<name>Ex_E</name>
<desc>External Clock Edge: when this bit is set and the extend clock is selected, the counter clocks on the negative going edge of the external clock input.</desc>
<sw_param offset="0xf8002008" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_ttc1_Clock_Control_3_C_Src">
<name>C_Src</name>
<desc>Clock Source: when this bit is set the counter uses the external clock input, ext_clk; the default clock source is pclk.</desc>
<sw_param offset="0xf8002008" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_ttc1_Clock_Control_3_PS_V">
<name>PS_V</name>
<desc>Prescale value (N): if prescale is enabled, the count rate is divided by 2N+1 (divided by 2 to 65536)</desc>
<sw_param offset="0xf8002008" start="4" end="1" />
</parameter>
<parameter uniqueid="ps7_ttc1_Clock_Control_3_PS_En">
<name>PS_En</name>
<desc>Prescale enable: when this bit is set the counter, clock source is prescaled; the default clock source is that defined by C_Src.the default</desc>
<sw_param offset="0xf8002008" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Counter_Control_1_Wave_pol">
<name>Wave_pol</name>
<desc>Waveform polarity: When this bit is high, the waveform output goes from high to low on Match_1 interrupt and returns high on overflow or interval interrupt; when low, the waveform goes from low to high on Match_1 interrupt and returns low on overflow or interval interrupt.</desc>
<sw_param offset="0xf800200c" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_ttc1_Counter_Control_1_Wave_en">
<name>Wave_en</name>
<desc>Output waveform enable, active low.</desc>
<sw_param offset="0xf800200c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_ttc1_Counter_Control_1_RST">
<name>RST</name>
<desc>Setting this bit high resets the counter value and restarts counting; the RST bit is automatically cleared on restart.</desc>
<sw_param offset="0xf800200c" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_ttc1_Counter_Control_1_Match">
<name>Match</name>
<desc>Register Match mode: when Match is set, an interrupt is generated when the count value matches one of the three match registers and the corresponding bit is set in the Interrupt Enable register.</desc>
<sw_param offset="0xf800200c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_ttc1_Counter_Control_1_DEC">
<name>DEC</name>
<desc>Decrement: when this bit is high the counter counts down.</desc>
<sw_param offset="0xf800200c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_ttc1_Counter_Control_1_INT">
<name>INT</name>
<desc>When this bit is high, the timer is in Interval Mode, and the counter generates interrupts at regular intervals; when low, the timer is in overflow mode.</desc>
<sw_param offset="0xf800200c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ttc1_Counter_Control_1_DIS">
<name>DIS</name>
<desc>Disable counter: when this bit is high, the counter is stopped, holding its last value until reset, restarted or enabled again.</desc>
<sw_param offset="0xf800200c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Counter_Control_2_Wave_pol">
<name>Wave_pol</name>
<desc>Waveform polarity: When this bit is high, the waveform output goes from high to low on Match_1 interrupt and returns high on overflow or interval interrupt; when low, the waveform goes from low to high on Match_1 interrupt and returns low on overflow or interval interrupt.</desc>
<sw_param offset="0xf8002010" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_ttc1_Counter_Control_2_Wave_en">
<name>Wave_en</name>
<desc>Output waveform enable, active low.</desc>
<sw_param offset="0xf8002010" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_ttc1_Counter_Control_2_RST">
<name>RST</name>
<desc>Setting this bit high resets the counter value and restarts counting; the RST bit is automatically cleared on restart.</desc>
<sw_param offset="0xf8002010" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_ttc1_Counter_Control_2_Match">
<name>Match</name>
<desc>Register Match mode: when Match is set, an interrupt is generated when the count value matches one of the three match registers and the corresponding bit is set in the Interrupt Enable register.</desc>
<sw_param offset="0xf8002010" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_ttc1_Counter_Control_2_DEC">
<name>DEC</name>
<desc>Decrement: when this bit is high the counter counts down.</desc>
<sw_param offset="0xf8002010" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_ttc1_Counter_Control_2_INT">
<name>INT</name>
<desc>When this bit is high, the timer is in Interval Mode, and the counter generates interrupts at regular intervals; when low, the timer is in overflow mode.</desc>
<sw_param offset="0xf8002010" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ttc1_Counter_Control_2_DIS">
<name>DIS</name>
<desc>Disable counter: when this bit is high, the counter is stopped, holding its last value until reset, restarted or enabled again.</desc>
<sw_param offset="0xf8002010" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Counter_Control_3_Wave_pol">
<name>Wave_pol</name>
<desc>Waveform polarity: When this bit is high, the waveform output goes from high to low on Match_1 interrupt and returns high on overflow or interval interrupt; when low, the waveform goes from low to high on Match_1 interrupt and returns low on overflow or interval interrupt.</desc>
<sw_param offset="0xf8002014" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_ttc1_Counter_Control_3_Wave_en">
<name>Wave_en</name>
<desc>Output waveform enable, active low.</desc>
<sw_param offset="0xf8002014" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_ttc1_Counter_Control_3_RST">
<name>RST</name>
<desc>Setting this bit high resets the counter value and restarts counting; the RST bit is automatically cleared on restart.</desc>
<sw_param offset="0xf8002014" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_ttc1_Counter_Control_3_Match">
<name>Match</name>
<desc>Register Match mode: when Match is set, an interrupt is generated when the count value matches one of the three match registers and the corresponding bit is set in the Interrupt Enable register.</desc>
<sw_param offset="0xf8002014" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_ttc1_Counter_Control_3_DEC">
<name>DEC</name>
<desc>Decrement: when this bit is high the counter counts down.</desc>
<sw_param offset="0xf8002014" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_ttc1_Counter_Control_3_INT">
<name>INT</name>
<desc>When this bit is high, the timer is in Interval Mode, and the counter generates interrupts at regular intervals; when low, the timer is in overflow mode.</desc>
<sw_param offset="0xf8002014" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ttc1_Counter_Control_3_DIS">
<name>DIS</name>
<desc>Disable counter: when this bit is high, the counter is stopped, holding its last value until reset, restarted or enabled again.</desc>
<sw_param offset="0xf8002014" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Counter_Value_1_Value">
<name>Value</name>
<desc>At any time, a Timer Counter's count value can be read from its Counter Value Register.</desc>
<sw_param offset="0xf8002018" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Counter_Value_2_Value">
<name>Value</name>
<desc>At any time, a Timer Counter's count value can be read from its Counter Value Register.</desc>
<sw_param offset="0xf800201c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Counter_Value_3_Value">
<name>Value</name>
<desc>At any time, a Timer Counter's count value can be read from its Counter Value Register.</desc>
<sw_param offset="0xf8002020" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Interval_Counter_1_Interval">
<name>Interval</name>
<desc>If interval is enabled, this is the maximum value that the counter will count up to or down from.</desc>
<sw_param offset="0xf8002024" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Interval_Counter_2_Interval">
<name>Interval</name>
<desc>If interval is enabled, this is the maximum value that the counter will count up to or down from.</desc>
<sw_param offset="0xf8002028" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Interval_Counter_3_Interval">
<name>Interval</name>
<desc>If interval is enabled, this is the maximum value that the counter will count up to or down from.</desc>
<sw_param offset="0xf800202c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Match_1_Counter_1_Match">
<name>Match</name>
<desc>When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.</desc>
<sw_param offset="0xf8002030" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Match_1_Counter_2_Match">
<name>Match</name>
<desc>When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.</desc>
<sw_param offset="0xf8002034" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Match_1_Counter_3_Match">
<name>Match</name>
<desc>When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.</desc>
<sw_param offset="0xf8002038" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Match_2_Counter_1_Match">
<name>Match</name>
<desc>When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.</desc>
<sw_param offset="0xf800203c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Match_2_Counter_2_Match">
<name>Match</name>
<desc>When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.</desc>
<sw_param offset="0xf8002040" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Match_2_Counter_3_Match">
<name>Match</name>
<desc>When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.</desc>
<sw_param offset="0xf8002044" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Match_3_Counter_1_Match">
<name>Match</name>
<desc>When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.</desc>
<sw_param offset="0xf8002048" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Match_3_Counter_2_Match">
<name>Match</name>
<desc>When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.</desc>
<sw_param offset="0xf800204c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Match_3_Counter_3_Match">
<name>Match</name>
<desc>When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.</desc>
<sw_param offset="0xf8002050" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Interrupt_Register_1_Ev">
<name>Ev</name>
<desc>Event timer overflow interrupt</desc>
<sw_param offset="0xf8002054" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_ttc1_Interrupt_Register_1_Ov">
<name>Ov</name>
<desc>Counter overflow</desc>
<sw_param offset="0xf8002054" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_ttc1_Interrupt_Register_1_M3">
<name>M3</name>
<desc>Match 3 interrupt</desc>
<sw_param offset="0xf8002054" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_ttc1_Interrupt_Register_1_M2">
<name>M2</name>
<desc>Match 2 interrupt</desc>
<sw_param offset="0xf8002054" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_ttc1_Interrupt_Register_1_M1">
<name>M1</name>
<desc>Match 1 interrupt</desc>
<sw_param offset="0xf8002054" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ttc1_Interrupt_Register_1_Iv">
<name>Iv</name>
<desc>Interval interrupt</desc>
<sw_param offset="0xf8002054" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Interrupt_Register_2_Ev">
<name>Ev</name>
<desc>Event timer overflow interrupt</desc>
<sw_param offset="0xf8002058" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_ttc1_Interrupt_Register_2_Ov">
<name>Ov</name>
<desc>Counter overflow</desc>
<sw_param offset="0xf8002058" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_ttc1_Interrupt_Register_2_M3">
<name>M3</name>
<desc>Match 3 interrupt</desc>
<sw_param offset="0xf8002058" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_ttc1_Interrupt_Register_2_M2">
<name>M2</name>
<desc>Match 2 interrupt</desc>
<sw_param offset="0xf8002058" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_ttc1_Interrupt_Register_2_M1">
<name>M1</name>
<desc>Match 1 interrupt</desc>
<sw_param offset="0xf8002058" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ttc1_Interrupt_Register_2_Iv">
<name>Iv</name>
<desc>Interval interrupt</desc>
<sw_param offset="0xf8002058" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Interrupt_Register_3_Ev">
<name>Ev</name>
<desc>Event timer overflow interrupt</desc>
<sw_param offset="0xf800205c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_ttc1_Interrupt_Register_3_Ov">
<name>Ov</name>
<desc>Counter overflow</desc>
<sw_param offset="0xf800205c" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_ttc1_Interrupt_Register_3_M3">
<name>M3</name>
<desc>Match 3 interrupt</desc>
<sw_param offset="0xf800205c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_ttc1_Interrupt_Register_3_M2">
<name>M2</name>
<desc>Match 2 interrupt</desc>
<sw_param offset="0xf800205c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_ttc1_Interrupt_Register_3_M1">
<name>M1</name>
<desc>Match 1 interrupt</desc>
<sw_param offset="0xf800205c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ttc1_Interrupt_Register_3_Iv">
<name>Iv</name>
<desc>Interval interrupt</desc>
<sw_param offset="0xf800205c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Interrupt_Enable_1_IEN">
<name>IEN</name>
<desc>Enables for bits 05:00 in Interrupt Register: corresponding bits must be set to enable the
interrupt.</desc>
<sw_param offset="0xf8002060" start="5" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Interrupt_Enable_2_IEN">
<name>IEN</name>
<desc>Enables for bits 05:00 in Interrupt Register: corresponding bits must be set to enable the interrupt.</desc>
<sw_param offset="0xf8002064" start="5" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Interrupt_Enable_3_IEN">
<name>IEN</name>
<desc>Enables for bits 05:00 in Interrupt Register: corresponding bits must be set to enable the interrupt.</desc>
<sw_param offset="0xf8002068" start="5" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Event_Control_Timer_1_E_Ov">
<name>E_Ov</name>
<desc>When this bit is low, the event timer is disabled and set to zero when an Event Timer Register overflow occurs; when set high, the timer continues counting on overflow.</desc>
<sw_param offset="0xf800206c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_ttc1_Event_Control_Timer_1_E_Lo">
<name>E_Lo</name>
<desc>When this bit is high, the timer counts pclk cycles during the low level duration of ext_clk; when low, the event timer counts the high level duration of ext_clk.</desc>
<sw_param offset="0xf800206c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ttc1_Event_Control_Timer_1_E_En">
<name>E_En</name>
<desc>Enable timer: when this bit is high, the event timer is enabled.</desc>
<sw_param offset="0xf800206c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Event_Control_Timer_2_E_Ov">
<name>E_Ov</name>
<desc>When this bit is low, the event timer is disabled and set to zero when an Event Timer Register overflow occurs; when set high, the timer continues counting on overflow.</desc>
<sw_param offset="0xf8002070" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_ttc1_Event_Control_Timer_2_E_Lo">
<name>E_Lo</name>
<desc>When this bit is high, the timer counts pclk cycles during the low level duration of ext_clk; when low, the event timer counts the high level duration of ext_clk.</desc>
<sw_param offset="0xf8002070" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ttc1_Event_Control_Timer_2_E_En">
<name>E_En</name>
<desc>Enable timer: when this bit is high, the event timer is enabled.</desc>
<sw_param offset="0xf8002070" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Event_Control_Timer_3_E_Ov">
<name>E_Ov</name>
<desc>When this bit is low, the event timer is disabled and set to zero when an Event Timer Register overflow occurs; when set high, the timer continues counting on overflow.</desc>
<sw_param offset="0xf8002074" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_ttc1_Event_Control_Timer_3_E_Lo">
<name>E_Lo</name>
<desc>When this bit is high, the timer counts pclk cycles during the low level duration of ext_clk; when low, the event timer counts the high level duration of ext_clk.</desc>
<sw_param offset="0xf8002074" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ttc1_Event_Control_Timer_3_E_En">
<name>E_En</name>
<desc>Enable timer: when this bit is high, the event timer is enabled.</desc>
<sw_param offset="0xf8002074" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Event_Register_1_Event">
<name>Event</name>
<desc>This register stores the result of the pclk count during the ext_clk high or low pulse.</desc>
<sw_param offset="0xf8002078" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Event_Register_2_Event">
<name>Event</name>
<desc>This register stores the result of the pclk count during the ext_clk high or low pulse.</desc>
<sw_param offset="0xf800207c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc1_Event_Register_3_Event">
<name>Event</name>
<desc>This register stores the result of the pclk count during the ext_clk high or low pulse.</desc>
<sw_param offset="0xf8002080" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Clock_Control_1_Ex_E">
<name>Ex_E</name>
<desc>External Clock Edge: when this bit is set and the extend clock is selected, the counter clocks on the negative going edge of the external clock input.</desc>
<sw_param offset="0xf8001000" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_ttc0_Clock_Control_1_C_Src">
<name>C_Src</name>
<desc>Clock Source: when this bit is set the counter uses the external clock input, ext_clk; the default clock source is pclk.</desc>
<sw_param offset="0xf8001000" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_ttc0_Clock_Control_1_PS_V">
<name>PS_V</name>
<desc>Prescale value (N): if prescale is enabled, the count rate is divided by 2N+1 (divided by 2 to 65536)</desc>
<sw_param offset="0xf8001000" start="4" end="1" />
</parameter>
<parameter uniqueid="ps7_ttc0_Clock_Control_1_PS_En">
<name>PS_En</name>
<desc>Prescale enable: when this bit is set the counter, clock source is prescaled; the default clock source is that defined by C_Src.the default</desc>
<sw_param offset="0xf8001000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Clock_Control_2_Ex_E">
<name>Ex_E</name>
<desc>External Clock Edge: when this bit is set and the extend clock is selected, the counter clocks on the negative going edge of the external clock input.</desc>
<sw_param offset="0xf8001004" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_ttc0_Clock_Control_2_C_Src">
<name>C_Src</name>
<desc>Clock Source: when this bit is set the counter uses the external clock input, ext_clk; the default clock source is pclk.</desc>
<sw_param offset="0xf8001004" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_ttc0_Clock_Control_2_PS_V">
<name>PS_V</name>
<desc>Prescale value (N): if prescale is enabled, the count rate is divided by 2N+1 (divided by 2 to 65536)</desc>
<sw_param offset="0xf8001004" start="4" end="1" />
</parameter>
<parameter uniqueid="ps7_ttc0_Clock_Control_2_PS_En">
<name>PS_En</name>
<desc>Prescale enable: when this bit is set the counter, clock source is prescaled; the default clock source is that defined by C_Src.the default</desc>
<sw_param offset="0xf8001004" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Clock_Control_3_Ex_E">
<name>Ex_E</name>
<desc>External Clock Edge: when this bit is set and the extend clock is selected, the counter clocks on the negative going edge of the external clock input.</desc>
<sw_param offset="0xf8001008" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_ttc0_Clock_Control_3_C_Src">
<name>C_Src</name>
<desc>Clock Source: when this bit is set the counter uses the external clock input, ext_clk; the default clock source is pclk.</desc>
<sw_param offset="0xf8001008" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_ttc0_Clock_Control_3_PS_V">
<name>PS_V</name>
<desc>Prescale value (N): if prescale is enabled, the count rate is divided by 2N+1 (divided by 2 to 65536)</desc>
<sw_param offset="0xf8001008" start="4" end="1" />
</parameter>
<parameter uniqueid="ps7_ttc0_Clock_Control_3_PS_En">
<name>PS_En</name>
<desc>Prescale enable: when this bit is set the counter, clock source is prescaled; the default clock source is that defined by C_Src.the default</desc>
<sw_param offset="0xf8001008" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Counter_Control_1_Wave_pol">
<name>Wave_pol</name>
<desc>Waveform polarity: When this bit is high, the waveform output goes from high to low on Match_1 interrupt and returns high on overflow or interval interrupt; when low, the waveform goes from low to high on Match_1 interrupt and returns low on overflow or interval interrupt.</desc>
<sw_param offset="0xf800100c" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_ttc0_Counter_Control_1_Wave_en">
<name>Wave_en</name>
<desc>Output waveform enable, active low.</desc>
<sw_param offset="0xf800100c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_ttc0_Counter_Control_1_RST">
<name>RST</name>
<desc>Setting this bit high resets the counter value and restarts counting; the RST bit is automatically cleared on restart.</desc>
<sw_param offset="0xf800100c" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_ttc0_Counter_Control_1_Match">
<name>Match</name>
<desc>Register Match mode: when Match is set, an interrupt is generated when the count value matches one of the three match registers and the corresponding bit is set in the Interrupt Enable register.</desc>
<sw_param offset="0xf800100c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_ttc0_Counter_Control_1_DEC">
<name>DEC</name>
<desc>Decrement: when this bit is high the counter counts down.</desc>
<sw_param offset="0xf800100c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_ttc0_Counter_Control_1_INT">
<name>INT</name>
<desc>When this bit is high, the timer is in Interval Mode, and the counter generates interrupts at regular intervals; when low, the timer is in overflow mode.</desc>
<sw_param offset="0xf800100c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ttc0_Counter_Control_1_DIS">
<name>DIS</name>
<desc>Disable counter: when this bit is high, the counter is stopped, holding its last value until reset, restarted or enabled again.</desc>
<sw_param offset="0xf800100c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Counter_Control_2_Wave_pol">
<name>Wave_pol</name>
<desc>Waveform polarity: When this bit is high, the waveform output goes from high to low on Match_1 interrupt and returns high on overflow or interval interrupt; when low, the waveform goes from low to high on Match_1 interrupt and returns low on overflow or interval interrupt.</desc>
<sw_param offset="0xf8001010" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_ttc0_Counter_Control_2_Wave_en">
<name>Wave_en</name>
<desc>Output waveform enable, active low.</desc>
<sw_param offset="0xf8001010" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_ttc0_Counter_Control_2_RST">
<name>RST</name>
<desc>Setting this bit high resets the counter value and restarts counting; the RST bit is automatically cleared on restart.</desc>
<sw_param offset="0xf8001010" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_ttc0_Counter_Control_2_Match">
<name>Match</name>
<desc>Register Match mode: when Match is set, an interrupt is generated when the count value matches one of the three match registers and the corresponding bit is set in the Interrupt Enable register.</desc>
<sw_param offset="0xf8001010" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_ttc0_Counter_Control_2_DEC">
<name>DEC</name>
<desc>Decrement: when this bit is high the counter counts down.</desc>
<sw_param offset="0xf8001010" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_ttc0_Counter_Control_2_INT">
<name>INT</name>
<desc>When this bit is high, the timer is in Interval Mode, and the counter generates interrupts at regular intervals; when low, the timer is in overflow mode.</desc>
<sw_param offset="0xf8001010" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ttc0_Counter_Control_2_DIS">
<name>DIS</name>
<desc>Disable counter: when this bit is high, the counter is stopped, holding its last value until reset, restarted or enabled again.</desc>
<sw_param offset="0xf8001010" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Counter_Control_3_Wave_pol">
<name>Wave_pol</name>
<desc>Waveform polarity: When this bit is high, the waveform output goes from high to low on Match_1 interrupt and returns high on overflow or interval interrupt; when low, the waveform goes from low to high on Match_1 interrupt and returns low on overflow or interval interrupt.</desc>
<sw_param offset="0xf8001014" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_ttc0_Counter_Control_3_Wave_en">
<name>Wave_en</name>
<desc>Output waveform enable, active low.</desc>
<sw_param offset="0xf8001014" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_ttc0_Counter_Control_3_RST">
<name>RST</name>
<desc>Setting this bit high resets the counter value and restarts counting; the RST bit is automatically cleared on restart.</desc>
<sw_param offset="0xf8001014" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_ttc0_Counter_Control_3_Match">
<name>Match</name>
<desc>Register Match mode: when Match is set, an interrupt is generated when the count value matches one of the three match registers and the corresponding bit is set in the Interrupt Enable register.</desc>
<sw_param offset="0xf8001014" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_ttc0_Counter_Control_3_DEC">
<name>DEC</name>
<desc>Decrement: when this bit is high the counter counts down.</desc>
<sw_param offset="0xf8001014" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_ttc0_Counter_Control_3_INT">
<name>INT</name>
<desc>When this bit is high, the timer is in Interval Mode, and the counter generates interrupts at regular intervals; when low, the timer is in overflow mode.</desc>
<sw_param offset="0xf8001014" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ttc0_Counter_Control_3_DIS">
<name>DIS</name>
<desc>Disable counter: when this bit is high, the counter is stopped, holding its last value until reset, restarted or enabled again.</desc>
<sw_param offset="0xf8001014" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Counter_Value_1_Value">
<name>Value</name>
<desc>At any time, a Timer Counter's count value can be read from its Counter Value Register.</desc>
<sw_param offset="0xf8001018" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Counter_Value_2_Value">
<name>Value</name>
<desc>At any time, a Timer Counter's count value can be read from its Counter Value Register.</desc>
<sw_param offset="0xf800101c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Counter_Value_3_Value">
<name>Value</name>
<desc>At any time, a Timer Counter's count value can be read from its Counter Value Register.</desc>
<sw_param offset="0xf8001020" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Interval_Counter_1_Interval">
<name>Interval</name>
<desc>If interval is enabled, this is the maximum value that the counter will count up to or down from.</desc>
<sw_param offset="0xf8001024" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Interval_Counter_2_Interval">
<name>Interval</name>
<desc>If interval is enabled, this is the maximum value that the counter will count up to or down from.</desc>
<sw_param offset="0xf8001028" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Interval_Counter_3_Interval">
<name>Interval</name>
<desc>If interval is enabled, this is the maximum value that the counter will count up to or down from.</desc>
<sw_param offset="0xf800102c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Match_1_Counter_1_Match">
<name>Match</name>
<desc>When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.</desc>
<sw_param offset="0xf8001030" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Match_1_Counter_2_Match">
<name>Match</name>
<desc>When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.</desc>
<sw_param offset="0xf8001034" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Match_1_Counter_3_Match">
<name>Match</name>
<desc>When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.</desc>
<sw_param offset="0xf8001038" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Match_2_Counter_1_Match">
<name>Match</name>
<desc>When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.</desc>
<sw_param offset="0xf800103c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Match_2_Counter_2_Match">
<name>Match</name>
<desc>When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.</desc>
<sw_param offset="0xf8001040" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Match_2_Counter_3_Match">
<name>Match</name>
<desc>When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.</desc>
<sw_param offset="0xf8001044" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Match_3_Counter_1_Match">
<name>Match</name>
<desc>When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.</desc>
<sw_param offset="0xf8001048" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Match_3_Counter_2_Match">
<name>Match</name>
<desc>When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.</desc>
<sw_param offset="0xf800104c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Match_3_Counter_3_Match">
<name>Match</name>
<desc>When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.</desc>
<sw_param offset="0xf8001050" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Interrupt_Register_1_Ev">
<name>Ev</name>
<desc>Event timer overflow interrupt</desc>
<sw_param offset="0xf8001054" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_ttc0_Interrupt_Register_1_Ov">
<name>Ov</name>
<desc>Counter overflow</desc>
<sw_param offset="0xf8001054" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_ttc0_Interrupt_Register_1_M3">
<name>M3</name>
<desc>Match 3 interrupt</desc>
<sw_param offset="0xf8001054" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_ttc0_Interrupt_Register_1_M2">
<name>M2</name>
<desc>Match 2 interrupt</desc>
<sw_param offset="0xf8001054" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_ttc0_Interrupt_Register_1_M1">
<name>M1</name>
<desc>Match 1 interrupt</desc>
<sw_param offset="0xf8001054" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ttc0_Interrupt_Register_1_Iv">
<name>Iv</name>
<desc>Interval interrupt</desc>
<sw_param offset="0xf8001054" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Interrupt_Register_2_Ev">
<name>Ev</name>
<desc>Event timer overflow interrupt</desc>
<sw_param offset="0xf8001058" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_ttc0_Interrupt_Register_2_Ov">
<name>Ov</name>
<desc>Counter overflow</desc>
<sw_param offset="0xf8001058" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_ttc0_Interrupt_Register_2_M3">
<name>M3</name>
<desc>Match 3 interrupt</desc>
<sw_param offset="0xf8001058" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_ttc0_Interrupt_Register_2_M2">
<name>M2</name>
<desc>Match 2 interrupt</desc>
<sw_param offset="0xf8001058" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_ttc0_Interrupt_Register_2_M1">
<name>M1</name>
<desc>Match 1 interrupt</desc>
<sw_param offset="0xf8001058" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ttc0_Interrupt_Register_2_Iv">
<name>Iv</name>
<desc>Interval interrupt</desc>
<sw_param offset="0xf8001058" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Interrupt_Register_3_Ev">
<name>Ev</name>
<desc>Event timer overflow interrupt</desc>
<sw_param offset="0xf800105c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_ttc0_Interrupt_Register_3_Ov">
<name>Ov</name>
<desc>Counter overflow</desc>
<sw_param offset="0xf800105c" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_ttc0_Interrupt_Register_3_M3">
<name>M3</name>
<desc>Match 3 interrupt</desc>
<sw_param offset="0xf800105c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_ttc0_Interrupt_Register_3_M2">
<name>M2</name>
<desc>Match 2 interrupt</desc>
<sw_param offset="0xf800105c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_ttc0_Interrupt_Register_3_M1">
<name>M1</name>
<desc>Match 1 interrupt</desc>
<sw_param offset="0xf800105c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ttc0_Interrupt_Register_3_Iv">
<name>Iv</name>
<desc>Interval interrupt</desc>
<sw_param offset="0xf800105c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Interrupt_Enable_1_IEN">
<name>IEN</name>
<desc>Enables for bits 05:00 in Interrupt Register: corresponding bits must be set to enable the
interrupt.</desc>
<sw_param offset="0xf8001060" start="5" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Interrupt_Enable_2_IEN">
<name>IEN</name>
<desc>Enables for bits 05:00 in Interrupt Register: corresponding bits must be set to enable the interrupt.</desc>
<sw_param offset="0xf8001064" start="5" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Interrupt_Enable_3_IEN">
<name>IEN</name>
<desc>Enables for bits 05:00 in Interrupt Register: corresponding bits must be set to enable the interrupt.</desc>
<sw_param offset="0xf8001068" start="5" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Event_Control_Timer_1_E_Ov">
<name>E_Ov</name>
<desc>When this bit is low, the event timer is disabled and set to zero when an Event Timer Register overflow occurs; when set high, the timer continues counting on overflow.</desc>
<sw_param offset="0xf800106c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_ttc0_Event_Control_Timer_1_E_Lo">
<name>E_Lo</name>
<desc>When this bit is high, the timer counts pclk cycles during the low level duration of ext_clk; when low, the event timer counts the high level duration of ext_clk.</desc>
<sw_param offset="0xf800106c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ttc0_Event_Control_Timer_1_E_En">
<name>E_En</name>
<desc>Enable timer: when this bit is high, the event timer is enabled.</desc>
<sw_param offset="0xf800106c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Event_Control_Timer_2_E_Ov">
<name>E_Ov</name>
<desc>When this bit is low, the event timer is disabled and set to zero when an Event Timer Register overflow occurs; when set high, the timer continues counting on overflow.</desc>
<sw_param offset="0xf8001070" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_ttc0_Event_Control_Timer_2_E_Lo">
<name>E_Lo</name>
<desc>When this bit is high, the timer counts pclk cycles during the low level duration of ext_clk; when low, the event timer counts the high level duration of ext_clk.</desc>
<sw_param offset="0xf8001070" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ttc0_Event_Control_Timer_2_E_En">
<name>E_En</name>
<desc>Enable timer: when this bit is high, the event timer is enabled.</desc>
<sw_param offset="0xf8001070" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Event_Control_Timer_3_E_Ov">
<name>E_Ov</name>
<desc>When this bit is low, the event timer is disabled and set to zero when an Event Timer Register overflow occurs; when set high, the timer continues counting on overflow.</desc>
<sw_param offset="0xf8001074" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_ttc0_Event_Control_Timer_3_E_Lo">
<name>E_Lo</name>
<desc>When this bit is high, the timer counts pclk cycles during the low level duration of ext_clk; when low, the event timer counts the high level duration of ext_clk.</desc>
<sw_param offset="0xf8001074" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ttc0_Event_Control_Timer_3_E_En">
<name>E_En</name>
<desc>Enable timer: when this bit is high, the event timer is enabled.</desc>
<sw_param offset="0xf8001074" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Event_Register_1_Event">
<name>Event</name>
<desc>This register stores the result of the pclk count during the ext_clk high or low pulse.</desc>
<sw_param offset="0xf8001078" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Event_Register_2_Event">
<name>Event</name>
<desc>This register stores the result of the pclk count during the ext_clk high or low pulse.</desc>
<sw_param offset="0xf800107c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ttc0_Event_Register_3_Event">
<name>Event</name>
<desc>This register stores the result of the pclk count during the ext_clk high or low pulse.</desc>
<sw_param offset="0xf8001080" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_ddrc_ctrl_reg_ddrc_dis_auto_refresh">
<name>reg_ddrc_dis_auto_refresh</name>
<desc>Disable auto-refresh.
0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly.
1 = disable auto-refresh generated by the controller. This input is changeable on the fly.
Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.</desc>
<sw_param offset="0xf8006000" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_ddrc_ctrl_reg_ddrc_dis_act_bypass">
<name>reg_ddrc_dis_act_bypass</name>
<desc>Only present in designs supporting activate bypass. For Debug only.
0 = Do not disable bypass path for high priority read activates.
1 = disable bypass path for high priority read activates.</desc>
<sw_param offset="0xf8006000" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_ddrc_ddrc_ctrl_reg_ddrc_dis_rd_bypass">
<name>reg_ddrc_dis_rd_bypass</name>
<desc>Only present in designs supporting read bypass. For Debug only.
0 = Do not disable bypass path for high priority read page hits.
1 = disable bypass path for high priority read page hits.</desc>
<sw_param offset="0xf8006000" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_ddrc_ddrc_ctrl_reg_ddrc_rdwr_idle_gap">
<name>reg_ddrc_rdwr_idle_gap</name>
<desc>When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.</desc>
<sw_param offset="0xf8006000" start="13" end="7" />
</parameter>
<parameter uniqueid="ps7_ddrc_ddrc_ctrl_reg_ddrc_burst8_refresh">
<name>reg_ddrc_burst8_refresh</name>
<desc>Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes.
0 = single refresh
1 = burst-of-2
.
7 = burst-of-8 refresh</desc>
<sw_param offset="0xf8006000" start="6" end="4" />
</parameter>
<parameter uniqueid="ps7_ddrc_ddrc_ctrl_reg_ddrc_data_bus_width">
<name>reg_ddrc_data_bus_width</name>
<desc>DDR bus width control
00 = 32 bit DDR bus
01 = 16 bit DDR bus
1x = reserved</desc>
<sw_param offset="0xf8006000" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_ddrc_ddrc_ctrl_reg_ddrc_powerdown_en">
<name>reg_ddrc_powerdown_en</name>
<desc>Controller power down control.
0 = DDRC powerdown disabled
1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32).
Note: This register bit may be reprogrammed during the course of normal operation.</desc>
<sw_param offset="0xf8006000" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ddrc_ddrc_ctrl_reg_ddrc_soft_rstb">
<name>reg_ddrc_soft_rstb</name>
<desc>Active low soft reset.
0 = Resets the controller
1 = Takes the controller out of reset
Note: Controller must be taken out of reset only after all other registers have been programmed.</desc>
<sw_param offset="0xf8006000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_Two_rank_cfg_reg_ddrc_addrmap_4bank_ram">
<name>reg_ddrc_addrmap_4bank_ram</name>
<desc>Only present if MEMC_SIMPLE_ADDR_MAP is defined.
Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved
1 = Set the address map for 4 Bank RAMs</desc>
<sw_param offset="0xf8006004" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_ddrc_Two_rank_cfg_reg_ddrc_addrmap_open_bank">
<name>reg_ddrc_addrmap_open_bank</name>
<desc>Only present if MEMC_SIMPLE_ADDR_MAP is defined.
Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved
1 = Set the address map to Open Bank mode</desc>
<sw_param offset="0xf8006004" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_ddrc_Two_rank_cfg_reg_ddrc_addrmap_cs_bit1">
<name>reg_ddrc_addrmap_cs_bit1</name>
<desc>Only present for multi-rank configurations.
Selects the address bit used as rank address bit 1.
Valid Range: 0 to 25, and 31
Internal Base: 10
The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0.</desc>
<sw_param offset="0xf8006004" start="26" end="22" />
</parameter>
<parameter uniqueid="ps7_ddrc_Two_rank_cfg_reg_ddrc_diff_rank_rd_2cycle_gap">
<name>reg_ddrc_diff_rank_rd_2cycle_gap</name>
<desc>Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR.
0 = schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks
1 = schedule 2 cycle gap for the same</desc>
<sw_param offset="0xf8006004" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_ddrc_Two_rank_cfg_reg_ddrc_wr_odt_block">
<name>reg_ddrc_wr_odt_block</name>
<desc>00 = block read/write scheduling for 1-cycle when
Write requires changing ODT settings
01 = block read/write scheduling for 2 cycles when Write requires changing ODT settings
10 = block read/write scheduling for 3 cycles when Write requires changing ODT settings
11 = Reserved</desc>
<sw_param offset="0xf8006004" start="20" end="19" />
</parameter>
<parameter uniqueid="ps7_ddrc_Two_rank_cfg_reg_ddrc_addrmap_cs_bit0">
<name>reg_ddrc_addrmap_cs_bit0</name>
<desc>Only present for multi-rank configurations.
Selects the address bit used as rank address bit 0.
Valid Range: 0 to 25, and 31
Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field.
If set to 31, rank address bit 0 is set to 0.</desc>
<sw_param offset="0xf8006004" start="18" end="14" />
</parameter>
<parameter uniqueid="ps7_ddrc_Two_rank_cfg_reg_ddrc_active_ranks">
<name>reg_ddrc_active_ranks</name>
<desc>Only present for multi-rank configurations.
Each bit represents one rank.
1=populated; 0=unpopulated
01 = One Rank
11 = Two Ranks
Others = Reserved</desc>
<sw_param offset="0xf8006004" start="13" end="12" />
</parameter>
<parameter uniqueid="ps7_ddrc_Two_rank_cfg_reg_ddrc_t_rfc_nom_x32">
<name>reg_ddrc_t_rfc_nom_x32</name>
<desc>tREFI - Average time between refreshes. Unit: in multiples of 32 clocks.
DRAM RELATED.
Default value is set for DDR3.</desc>
<sw_param offset="0xf8006004" start="11" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_HPR_reg_reg_ddrc_hpr_xact_run_length">
<name>reg_ddrc_hpr_xact_run_length</name>
<desc>Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available.</desc>
<sw_param offset="0xf8006008" start="25" end="22" />
</parameter>
<parameter uniqueid="ps7_ddrc_HPR_reg_reg_ddrc_hpr_max_starve_x32">
<name>reg_ddrc_hpr_max_starve_x32</name>
<desc>Number of clocks that the HPR queue can be starved
before it goes critical.
Unit: 32 clocks</desc>
<sw_param offset="0xf8006008" start="21" end="11" />
</parameter>
<parameter uniqueid="ps7_ddrc_HPR_reg_reg_ddrc_hpr_min_non_critical_x32">
<name>reg_ddrc_hpr_min_non_critical_x32</name>
<desc>Number of clocks that the HPR queue is guaranteed to
be non-critical.
Unit: 32 clocks</desc>
<sw_param offset="0xf8006008" start="10" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_LPR_reg_reg_ddrc_lpr_xact_run_length">
<name>reg_ddrc_lpr_xact_run_length</name>
<desc>Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available</desc>
<sw_param offset="0xf800600c" start="25" end="22" />
</parameter>
<parameter uniqueid="ps7_ddrc_LPR_reg_reg_ddrc_lpr_max_starve_x32">
<name>reg_ddrc_lpr_max_starve_x32</name>
<desc>Number of clocks that the LPR queue can be starved before it goes critical.
Unit: 32 clocks</desc>
<sw_param offset="0xf800600c" start="21" end="11" />
</parameter>
<parameter uniqueid="ps7_ddrc_LPR_reg_reg_ddrc_lpr_min_non_critical_x32">
<name>reg_ddrc_lpr_min_non_critical_x32</name>
<desc>Number of clocks that the LPR queue is guaranteed to be non-critical.
Unit: 32 clocks</desc>
<sw_param offset="0xf800600c" start="10" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_WR_reg_reg_ddrc_w_max_starve_x32">
<name>reg_ddrc_w_max_starve_x32</name>
<desc>Number of clocks that the Write queue can be starved before it goes critical.
Unit: 32 clocks.
FOR PERFORMANCE ONLY.</desc>
<sw_param offset="0xf8006010" start="25" end="15" />
</parameter>
<parameter uniqueid="ps7_ddrc_WR_reg_reg_ddrc_w_xact_run_length">
<name>reg_ddrc_w_xact_run_length</name>
<desc>Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available</desc>
<sw_param offset="0xf8006010" start="14" end="11" />
</parameter>
<parameter uniqueid="ps7_ddrc_WR_reg_reg_ddrc_w_min_non_critical_x32">
<name>reg_ddrc_w_min_non_critical_x32</name>
<desc>Number of clock cycles that the WR queue is
guaranteed to be non-critical.</desc>
<sw_param offset="0xf8006010" start="10" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg0_reg_ddrc_post_selfref_gap_x32">
<name>reg_ddrc_post_selfref_gap_x32</name>
<desc>Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks).
Unit: in multiples of 32 clocks
DRAM RELATED</desc>
<sw_param offset="0xf8006014" start="20" end="14" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg0_reg_ddrc_t_rfc_min">
<name>reg_ddrc_t_rfc_min</name>
<desc>tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns).
DRAM RELATED.
Default value is set for DDR3.</desc>
<sw_param offset="0xf8006014" start="13" end="6" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg0_reg_ddrc_t_rc">
<name>reg_ddrc_t_rc</name>
<desc>tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts).
DRAM RELATED.
Default value is set for DDR3.</desc>
<sw_param offset="0xf8006014" start="5" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg1_reg_ddrc_t_cke">
<name>reg_ddrc_t_cke</name>
<desc>Minimum number of cycles of CKE HIGH/LOW during power down and self refresh.
LPDDR2 mode: Set this to the larger of tCKE or tCKESR. Non-LPDDR2 designs: Set this to tCKE value.
Unit: clocks.</desc>
<sw_param offset="0xf8006018" start="31" end="28" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg1_reg_ddrc_t_ras_min">
<name>reg_ddrc_t_ras_min</name>
<desc>tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns).
Unit: clocks
DRAM RELATED.
Default value is set for DDR3.</desc>
<sw_param offset="0xf8006018" start="26" end="22" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg1_reg_ddrc_t_ras_max">
<name>reg_ddrc_t_ras_max</name>
<desc>tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction.
Unit: Multiples of 1024 clocks
DRAM RELATED.</desc>
<sw_param offset="0xf8006018" start="21" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg1_reg_ddrc_t_faw">
<name>reg_ddrc_t_faw</name>
<desc>tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles.
Unit: clocks
DRAM RELATED.</desc>
<sw_param offset="0xf8006018" start="15" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg1_reg_ddrc_powerdown_to_x32">
<name>reg_ddrc_powerdown_to_x32</name>
<desc>After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register.
Unit: Multiples of 32 clocks.</desc>
<sw_param offset="0xf8006018" start="9" end="5" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg1_reg_ddrc_wr2pre">
<name>reg_ddrc_wr2pre</name>
<desc>Minimum time between write and precharge to same bank
Non-LPDDR2 -&gt; WL + BL/2 + tWR
LPDDR2 -&gt; WL + BL/2 + tWR + 1
Unit: Clocks where, WL = write latency. BL = burst length.
This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs.</desc>
<sw_param offset="0xf8006018" start="4" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg2_reg_ddrc_t_rcd">
<name>reg_ddrc_t_rcd</name>
<desc>tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1.
AL = Additive Latency
DRAM RELATED</desc>
<sw_param offset="0xf800601c" start="31" end="28" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg2_reg_ddrc_rd2pre">
<name>reg_ddrc_rd2pre</name>
<desc>Minimum time from read to precharge of same bank
DDR2 -&gt; AL + BL/2 + max(tRTP, 2) - 2
DDR3 -&gt; AL + max (tRTP, 4)
mDDR -&gt; BL/2
LPDDR2 -&gt; BL/2 + tRTP - 1
AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED</desc>
<sw_param offset="0xf800601c" start="27" end="23" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg2_reg_ddrc_pad_pd">
<name>reg_ddrc_pad_pd</name>
<desc>If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs.
Unit: clocks.</desc>
<sw_param offset="0xf800601c" start="22" end="20" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg2_reg_ddrc_t_xp">
<name>reg_ddrc_t_xp</name>
<desc>tXP: Minimum time after power down exit to any operation.
DRAM RELATED.</desc>
<sw_param offset="0xf800601c" start="19" end="15" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg2_reg_ddrc_wr2rd">
<name>reg_ddrc_wr2rd</name>
<desc>Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints.
non-LPDDR2 -&gt; WL + tWTR + BL/2
LPDDR2 -&gt; WL + tWTR + BL/2 + 1
Unit: clocks. Where, WL = Write latency, BL = burst length.
This should match the value. Programmed in the BL bit of the mode register to the DRAM.
tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs.</desc>
<sw_param offset="0xf800601c" start="14" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg2_reg_ddrc_rd2wr">
<name>reg_ddrc_rd2wr</name>
<desc>Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints.
non-LPDDR2
-&gt;
RL + BL/2 + 2 - WL
LPDDR2 -&gt; RL + BL/2 + RU(tDQSCKmax / tCK) + 1 - WL
Write Pre-amble and DQ/DQS jitter timer is included in the above equation.
DRAM RELATED.</desc>
<sw_param offset="0xf800601c" start="9" end="5" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg2_reg_ddrc_write_latency">
<name>reg_ddrc_write_latency</name>
<desc>Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself).
DDR2/3 -&gt; WL -1
LPDDR
-&gt; 1
LPDDR2 -&gt;WL Where WL = Write Latency of DRAM
DRAM RELATED.</desc>
<sw_param offset="0xf800601c" start="4" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg3_reg_ddrc_loopback">
<name>reg_ddrc_loopback</name>
<desc>unused</desc>
<sw_param offset="0xf8006020" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg3_reg_ddrc_dis_pad_pd">
<name>reg_ddrc_dis_pad_pd</name>
<desc>1 = disable the pad power down feature
0 = Enable the pad power down feature.</desc>
<sw_param offset="0xf8006020" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg3_reg_phy_mode_ddr1_ddr2">
<name>reg_phy_mode_ddr1_ddr2</name>
<desc>unused</desc>
<sw_param offset="0xf8006020" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg3_reg_ddrc_read_latency">
<name>reg_ddrc_read_latency</name>
<desc>Set to RL. Time from Read command to Read data on
DRAM interface.
Unit: clocks
This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. RL = Read Latency of DRAM
Note: This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped.</desc>
<sw_param offset="0xf8006020" start="28" end="24" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg3_reg_ddrc_clock_stop_en">
<name>reg_ddrc_clock_stop_en</name>
<desc>1=enable the assertion of stop_clk to the PHY whenever a clock is not required by LPDDR/ LPDDR2.
0=stop_clk will never be asserted.
Note: This is only present for implementations supporting LPDDR/LPDDR2 devices.</desc>
<sw_param offset="0xf8006020" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg3_reg_ddrc_mobile">
<name>reg_ddrc_mobile</name>
<desc>1= mobile/LPDDR DRAM device in use.
0=non-mobile DRAM device in use.</desc>
<sw_param offset="0xf8006020" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg3_reg_ddrc_sdram">
<name>reg_ddrc_sdram</name>
<desc>1 = sdram device
0 = non-sdram device</desc>
<sw_param offset="0xf8006020" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg3_reg_ddrc_refresh_to_x32">
<name>reg_ddrc_refresh_to_x32</name>
<desc>If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller.</desc>
<sw_param offset="0xf8006020" start="20" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg3_reg_ddrc_t_rp">
<name>reg_ddrc_t_rp</name>
<desc>tRP - Minimum time from precharge to activate of same bank.
DRAM RELATED</desc>
<sw_param offset="0xf8006020" start="15" end="12" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg3_reg_ddrc_refresh_margin">
<name>reg_ddrc_refresh_margin</name>
<desc>Issue critical refresh or page close this many cycles
before the critical refresh or page timer expires. It is recommended that this not be changed from the default value.</desc>
<sw_param offset="0xf8006020" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg3_reg_ddrc_t_rrd">
<name>reg_ddrc_t_rrd</name>
<desc>tRRD - Minimum time between activates from bank a
to bank b. (spec: 10ns or less)
DRAM RELATED</desc>
<sw_param offset="0xf8006020" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg3_reg_ddrc_t_ccd">
<name>reg_ddrc_t_ccd</name>
<desc>tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1
DRAM RELATED</desc>
<sw_param offset="0xf8006020" start="4" end="2" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg3_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006020" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg4_reg_ddrc_mr_rdata_valid">
<name>reg_ddrc_mr_rdata_valid</name>
<desc>This bit indicates whether the Mode Register Read
Data present at address 0xA9 is valid or not. This bit is 1'b0 by default. This bit will be cleared (1'b0), whenever a Mode Register Read command is issued. This bit will be set to 1'b1, when the Mode Register Read Data is written to register 0xA9.</desc>
<sw_param offset="0xf8006024" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg4_reg_ddrc_mr_type">
<name>reg_ddrc_mr_type</name>
<desc>Indicates whether the Mode register operation is read
or write
1 = read
0 = write</desc>
<sw_param offset="0xf8006024" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg4_ddrc_reg_mr_wr_busy">
<name>ddrc_reg_mr_wr_busy</name>
<desc>Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted.
1 = Indicates that mode register write / read operation is in progress.
0 = Indicates that the core can initiate a mode register write / read operation.</desc>
<sw_param offset="0xf8006024" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg4_reg_ddrc_mr_data">
<name>reg_ddrc_mr_data</name>
<desc>Mode register write data - for non-LPDDR2 modes.
For LPDDR2, these 16-bits are interpreted as
Writes: \'7bMR Addr[7:0], MR Data[7:0]\'7d.
Reads: \'7bMR Addr[7:0], Don't Care[7:0]\'7d</desc>
<sw_param offset="0xf8006024" start="24" end="9" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg4_reg_ddrc_mr_addr">
<name>reg_ddrc_mr_addr</name>
<desc>Mode register address - for non-LPDDR2 modes.
This register is don't care in LPDDR2 mode
00 = MR0
01 = MR1
10 = MR2
11 = MR3</desc>
<sw_param offset="0xf8006024" start="8" end="7" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg4_reg_ddrc_mr_wr">
<name>reg_ddrc_mr_wr</name>
<desc>A low to high signal on this signal will do a mode
register write or read. Controller will accept this command, if this signal is detected high and 'ddrc_reg_mr_wr_busy' is detected low.</desc>
<sw_param offset="0xf8006024" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg4_reg_ddrc_max_rank_rd">
<name>reg_ddrc_max_rank_rd</name>
<desc>Only present for multi-rank configurations
Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY.</desc>
<sw_param offset="0xf8006024" start="5" end="2" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg4_reg_ddrc_prefer_write">
<name>reg_ddrc_prefer_write</name>
<desc>1 = Bank selector prefers writes over reads</desc>
<sw_param offset="0xf8006024" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_param_reg4_reg_ddrc_en_2t_timing_mode">
<name>reg_ddrc_en_2t_timing_mode</name>
<desc>1 = DDRC will use 2T timing
0 = DDRC will use 1T timing</desc>
<sw_param offset="0xf8006024" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_init_param_reg_ddrc_t_mrd">
<name>reg_ddrc_t_mrd</name>
<desc>tMRD - Cycles between Load Mode commands DRAM RELATED Default value is set for DDR3.</desc>
<sw_param offset="0xf8006028" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_init_param_reg_ddrc_pre_ocd_x32">
<name>reg_ddrc_pre_ocd_x32</name>
<desc>Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero.</desc>
<sw_param offset="0xf8006028" start="10" end="7" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_init_param_reg_ddrc_final_wait_x32">
<name>reg_ddrc_final_wait_x32</name>
<desc>Cycles to wait after completing the DRAM init sequence
before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3.</desc>
<sw_param offset="0xf8006028" start="6" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_EMR_reg_reg_ddrc_emr3">
<name>reg_ddrc_emr3</name>
<desc>Non LPDDR2- Value to be loaded into DRAM EMR3 registers. Used in non-LPDDR2 designs only.</desc>
<sw_param offset="0xf800602c" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_EMR_reg_reg_ddrc_emr2">
<name>reg_ddrc_emr2</name>
<desc>Non LPDDR2- Value to be loaded into DRAM EMR2 registers. For LPDDR2 - Value to Write to the MR3 register</desc>
<sw_param offset="0xf800602c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_EMR_MR_reg_reg_ddrc_emr">
<name>reg_ddrc_emr</name>
<desc>Non LPDDR2-Value
to be loaded into DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. For LPDDR2 - Value to Write to the MR2 register</desc>
<sw_param offset="0xf8006030" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_EMR_MR_reg_reg_ddrc_mr">
<name>reg_ddrc_mr</name>
<desc>Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register</desc>
<sw_param offset="0xf8006030" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_burst8_rdwr_reg_ddrc_burstchop">
<name>reg_ddrc_burstchop</name>
<desc>Feature not supported. When 1, Controller is out in burstchop mode.</desc>
<sw_param offset="0xf8006034" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_burst8_rdwr_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006034" start="27" end="26" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_burst8_rdwr_reg_ddrc_post_cke_x1024">
<name>reg_ddrc_post_cke_x1024</name>
<desc>Cycles to wait after driving CKE high to start the DRAM initialization sequence.
Units: 1024 clocks.
DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us.</desc>
<sw_param offset="0xf8006034" start="25" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_burst8_rdwr_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006034" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_burst8_rdwr_reg_ddrc_pre_cke_x1024">
<name>reg_ddrc_pre_cke_x1024</name>
<desc>Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence.
Units: 1024 clock cycles.
DDR2 Specifications typically require this to be programmed for a delay of &gt;= 200 us.
LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min)</desc>
<sw_param offset="0xf8006034" start="13" end="4" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_burst8_rdwr_reg_ddrc_burst_rdwr">
<name>reg_ddrc_burst_rdwr</name>
<desc>This controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. In LPDDR and LPDDR2, Burst length of 16 is supported only in Half Bus Width mode. Every input read/write command has 4 cycles of data associated with it and that is not enough data for doing Burst Length16 in Full Bus Width mode.
0010 - Burst length of 4
0100 - Burst length of 8
1000 - Burst length of 16 (only supported for LPDDR AND LPDDR2)
All other values are reserved</desc>
<sw_param offset="0xf8006034" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_disable_DQ_reg_phy_dq0_wait_t">
<name>reg_phy_dq0_wait_t</name>
<desc>Not Applicable in this PHY.</desc>
<sw_param offset="0xf8006038" start="12" end="9" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_disable_DQ_reg_phy_rd_level_start">
<name>reg_phy_rd_level_start</name>
<desc>Not Applicable in this PHY.</desc>
<sw_param offset="0xf8006038" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_disable_DQ_reg_phy_wr_level_start">
<name>reg_phy_wr_level_start</name>
<desc>Not Applicable in this PHY.</desc>
<sw_param offset="0xf8006038" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_disable_DQ_reg_phy_debug_mode">
<name>reg_phy_debug_mode</name>
<desc>Not Applicable in this PHY.</desc>
<sw_param offset="0xf8006038" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_disable_DQ_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006038" start="5" end="2" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_disable_DQ_reg_ddrc_dis_dq">
<name>reg_ddrc_dis_dq</name>
<desc>When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. This bit is intended to be switched on-the-fly</desc>
<sw_param offset="0xf8006038" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_disable_DQ_reg_ddrc_force_low_pri_n">
<name>reg_ddrc_force_low_pri_n</name>
<desc>Active Low signal. When asserted (0), all incoming transactions will be forced to low priority. Forcing the incoming transactions to low priority implicitly turns OFF Bypass. Otherwise, HPR is allowed if enabled in the AXI priority read registers.</desc>
<sw_param offset="0xf8006038" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_addr_map_bank_reg_ddrc_addrmap_col_b6">
<name>reg_ddrc_addrmap_col_b6</name>
<desc>Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode:
Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.
Internal base: 9</desc>
<sw_param offset="0xf800603c" start="19" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_addr_map_bank_reg_ddrc_addrmap_col_b5">
<name>reg_ddrc_addrmap_col_b5</name>
<desc>Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode:
Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.
Internal base: 9</desc>
<sw_param offset="0xf800603c" start="15" end="12" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_addr_map_bank_reg_ddrc_addrmap_bank_b2">
<name>reg_ddrc_addrmap_bank_b2</name>
<desc>Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0.</desc>
<sw_param offset="0xf800603c" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_addr_map_bank_reg_ddrc_addrmap_bank_b1">
<name>reg_ddrc_addrmap_bank_b1</name>
<desc>Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6.
The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.</desc>
<sw_param offset="0xf800603c" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_addr_map_bank_reg_ddrc_addrmap_bank_b0">
<name>reg_ddrc_addrmap_bank_b0</name>
<desc>Selects the address bits used as bank address bit 0. Valid Range: 0 to 14 Internal Base: 5
The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.</desc>
<sw_param offset="0xf800603c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_addr_map_col_reg_ddrc_addrmap_col_b11">
<name>reg_ddrc_addrmap_col_b11</name>
<desc>Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode)
Valid Range: 0 to 7, and 15.
Internal Base: 14.
The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</desc>
<sw_param offset="0xf8006040" start="31" end="28" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_addr_map_col_reg_ddrc_addrmap_col_b10">
<name>reg_ddrc_addrmap_col_b10</name>
<desc>Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15.
Internal Base: 13
The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</desc>
<sw_param offset="0xf8006040" start="27" end="24" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_addr_map_col_reg_ddrc_addrmap_col_b9">
<name>reg_ddrc_addrmap_col_b9</name>
<desc>Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode)
Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode)
Valid Range: 0 to 7, and 15
Internal Base: 12
The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0.
Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</desc>
<sw_param offset="0xf8006040" start="23" end="20" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_addr_map_col_reg_ddrc_addrmap_col_b8">
<name>reg_ddrc_addrmap_col_b8</name>
<desc>Full bus width mode: Selects the address bit used as column address bit 9.
Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode)
Valid Range: 0 to 7, and 15
Internal Base: 11
The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0.
Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</desc>
<sw_param offset="0xf8006040" start="19" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_addr_map_col_reg_ddrc_addrmap_col_b7">
<name>reg_ddrc_addrmap_col_b7</name>
<desc>Full bus width mode: Selects the address bit used as column address bit 8.
Half bus width mode: Selects the address bit used as column address bit 9.
Valid Range: 0 to 7, and 15.
Internal Base: 10.
The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0.
Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</desc>
<sw_param offset="0xf8006040" start="15" end="12" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_addr_map_col_reg_ddrc_addrmap_col_b4">
<name>reg_ddrc_addrmap_col_b4</name>
<desc>Full bus width mode: Selects the address bit used as column address bit 5.
Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7.
Internal Base: 7.
The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.</desc>
<sw_param offset="0xf8006040" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_addr_map_col_reg_ddrc_addrmap_col_b3">
<name>reg_ddrc_addrmap_col_b3</name>
<desc>Full bus width mode: Selects the address bit used as column address bit 4.
Half bus width mode: Selects the address bit used as column address bit 5.
Valid Range: 0 to 7
Internal Base: 6
The selected address bit is determined by adding the Internal Base to the value of this field.</desc>
<sw_param offset="0xf8006040" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_addr_map_col_reg_ddrc_addrmap_col_b2">
<name>reg_ddrc_addrmap_col_b2</name>
<desc>Full bus width mode: Selects the address bit used as column address bit 3.
Half bus width mode: Selects the address bit used as column address bit 4.
Valid Range: 0 to 7. Internal Base: 5
The selected address bit is determined by adding the Internal Base to the value of this field.</desc>
<sw_param offset="0xf8006040" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_addr_map_row_reg_ddrc_addrmap_row_b15">
<name>reg_ddrc_addrmap_row_b15</name>
<desc>Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0.</desc>
<sw_param offset="0xf8006044" start="27" end="24" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_addr_map_row_reg_ddrc_addrmap_row_b14">
<name>reg_ddrc_addrmap_row_b14</name>
<desc>Selects theAXI
address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0.</desc>
<sw_param offset="0xf8006044" start="23" end="20" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_addr_map_row_reg_ddrc_addrmap_row_b13">
<name>reg_ddrc_addrmap_row_b13</name>
<desc>Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0.</desc>
<sw_param offset="0xf8006044" start="19" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_addr_map_row_reg_ddrc_addrmap_row_b12">
<name>reg_ddrc_addrmap_row_b12</name>
<desc>Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0.</desc>
<sw_param offset="0xf8006044" start="15" end="12" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_addr_map_row_reg_ddrc_addrmap_row_b2_11">
<name>reg_ddrc_addrmap_row_b2_11</name>
<desc>Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.</desc>
<sw_param offset="0xf8006044" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_addr_map_row_reg_ddrc_addrmap_row_b1">
<name>reg_ddrc_addrmap_row_b1</name>
<desc>Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.</desc>
<sw_param offset="0xf8006044" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_addr_map_row_reg_ddrc_addrmap_row_b0">
<name>reg_ddrc_addrmap_row_b0</name>
<desc>Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9
The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field</desc>
<sw_param offset="0xf8006044" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_ODT_reg_reg_ddrc_rank3_wr_odt">
<name>reg_ddrc_rank3_wr_odt</name>
<desc>Unused</desc>
<sw_param offset="0xf8006048" start="29" end="27" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_ODT_reg_reg_ddrc_rank3_rd_odt">
<name>reg_ddrc_rank3_rd_odt</name>
<desc>Unused</desc>
<sw_param offset="0xf8006048" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_ODT_reg_reg_ddrc_rank2_wr_odt">
<name>reg_ddrc_rank2_wr_odt</name>
<desc>Unused</desc>
<sw_param offset="0xf8006048" start="23" end="21" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_ODT_reg_reg_ddrc_rank2_rd_odt">
<name>reg_ddrc_rank2_rd_odt</name>
<desc>Unused</desc>
<sw_param offset="0xf8006048" start="20" end="18" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_ODT_reg_reg_phy_idle_local_odt">
<name>reg_phy_idle_local_odt</name>
<desc>Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle.</desc>
<sw_param offset="0xf8006048" start="17" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_ODT_reg_reg_phy_wr_local_odt">
<name>reg_phy_wr_local_odt</name>
<desc>Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS.</desc>
<sw_param offset="0xf8006048" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_ODT_reg_reg_phy_rd_local_odt">
<name>reg_phy_rd_local_odt</name>
<desc>Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage.</desc>
<sw_param offset="0xf8006048" start="13" end="12" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_ODT_reg_reg_ddrc_rank1_wr_odt">
<name>reg_ddrc_rank1_wr_odt</name>
<desc>Unused</desc>
<sw_param offset="0xf8006048" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_ODT_reg_reg_ddrc_rank1_rd_odt">
<name>reg_ddrc_rank1_rd_odt</name>
<desc>Unused</desc>
<sw_param offset="0xf8006048" start="8" end="6" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_ODT_reg_reg_ddrc_rank0_wr_odt">
<name>reg_ddrc_rank0_wr_odt</name>
<desc>[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB.
For each rank, set its bit to 1 to enable its ODT.
[2] - If 1 then local ODT is enabled during writes to rank 0.</desc>
<sw_param offset="0xf8006048" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_ddrc_DRAM_ODT_reg_reg_ddrc_rank0_rd_odt">
<name>reg_ddrc_rank0_rd_odt</name>
<desc>Unused.
[1:0] - Indicates which remote ODT's must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT.
[2] - If 1 then local ODT is enabled during reads to rank 0.</desc>
<sw_param offset="0xf8006048" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_dbg_reg_phy_reg_bc_fifo_re3">
<name>phy_reg_bc_fifo_re3</name>
<desc>Debug read capture FIFO read enable for data slice 3.</desc>
<sw_param offset="0xf800604c" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_dbg_reg_phy_reg_bc_fifo_we3">
<name>phy_reg_bc_fifo_we3</name>
<desc>Debug read capture FIFO write enable, for data slice 3.</desc>
<sw_param offset="0xf800604c" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_dbg_reg_phy_reg_bc_dqs_oe3">
<name>phy_reg_bc_dqs_oe3</name>
<desc>Debug DQS output enable for data slice 3.</desc>
<sw_param offset="0xf800604c" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_dbg_reg_phy_reg_bc_dq_oe3">
<name>phy_reg_bc_dq_oe3</name>
<desc>Debug DQ output enable for data slice 3.</desc>
<sw_param offset="0xf800604c" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_dbg_reg_phy_reg_bc_fifo_re2">
<name>phy_reg_bc_fifo_re2</name>
<desc>Debug read capture FIFO read enable for data slice 2.</desc>
<sw_param offset="0xf800604c" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_dbg_reg_phy_reg_bc_fifo_we2">
<name>phy_reg_bc_fifo_we2</name>
<desc>Debug read capture FIFO write enable, for data slice 2.</desc>
<sw_param offset="0xf800604c" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_dbg_reg_phy_reg_bc_dqs_oe2">
<name>phy_reg_bc_dqs_oe2</name>
<desc>Debug DQS output enable for data slice 2.</desc>
<sw_param offset="0xf800604c" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_dbg_reg_phy_reg_bc_dq_oe2">
<name>phy_reg_bc_dq_oe2</name>
<desc>Debug DQ output enable for data slice 2.</desc>
<sw_param offset="0xf800604c" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_dbg_reg_phy_reg_bc_fifo_re1">
<name>phy_reg_bc_fifo_re1</name>
<desc>Debug read capture FIFO read enable for data slice 1.</desc>
<sw_param offset="0xf800604c" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_dbg_reg_phy_reg_bc_fifo_we1">
<name>phy_reg_bc_fifo_we1</name>
<desc>Debug read capture FIFO write enable, for data slice 1.</desc>
<sw_param offset="0xf800604c" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_dbg_reg_phy_reg_bc_dqs_oe1">
<name>phy_reg_bc_dqs_oe1</name>
<desc>Debug DQS output enable for data slice 1.</desc>
<sw_param offset="0xf800604c" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_dbg_reg_phy_reg_bc_dq_oe1">
<name>phy_reg_bc_dq_oe1</name>
<desc>Debug DQ output enable for data slice 1.</desc>
<sw_param offset="0xf800604c" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_dbg_reg_phy_reg_bc_fifo_re0">
<name>phy_reg_bc_fifo_re0</name>
<desc>Debug read capture FIFO read enable for data slice 0.</desc>
<sw_param offset="0xf800604c" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_dbg_reg_phy_reg_bc_fifo_we0">
<name>phy_reg_bc_fifo_we0</name>
<desc>Debug read capture FIFO write enable, for data slice 0.</desc>
<sw_param offset="0xf800604c" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_dbg_reg_phy_reg_bc_dqs_oe0">
<name>phy_reg_bc_dqs_oe0</name>
<desc>Debug DQS output enable for data slice 0.</desc>
<sw_param offset="0xf800604c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_dbg_reg_phy_reg_bc_dq_oe0">
<name>phy_reg_bc_dq_oe0</name>
<desc>Debug DQ output enable for data slice 0.</desc>
<sw_param offset="0xf800604c" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_dbg_reg_phy_reg_rdc_fifo_rst_err_cnt">
<name>phy_reg_rdc_fifo_rst_err_cnt</name>
<desc>Counter for counting how many times the pointers of read capture FIFO differ when they are reset by dll_calib.</desc>
<sw_param offset="0xf800604c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_cmd_timeout_rddata_cpt_reg_phy_wrlvl_num_of_dq0">
<name>reg_phy_wrlvl_num_of_dq0</name>
<desc>This register value determines register determines the number of samples used for each ratio increment during Write Leveling.
Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1
The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.</desc>
<sw_param offset="0xf8006050" start="31" end="28" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_cmd_timeout_rddata_cpt_reg_phy_gatelvl_num_of_dq0">
<name>reg_phy_gatelvl_num_of_dq0</name>
<desc>This register value determines register determines the number of samples used for each ratio increment during
Gate Training.
Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.</desc>
<sw_param offset="0xf8006050" start="27" end="24" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_cmd_timeout_rddata_cpt_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006050" start="23" end="20" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_cmd_timeout_rddata_cpt_reg_phy_clk_stall_level">
<name>reg_phy_clk_stall_level</name>
<desc>1 = stall clock, for DLL aging control</desc>
<sw_param offset="0xf8006050" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_cmd_timeout_rddata_cpt_reg_phy_dis_phy_ctrl_rstn">
<name>reg_phy_dis_phy_ctrl_rstn</name>
<desc>Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset.</desc>
<sw_param offset="0xf8006050" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_cmd_timeout_rddata_cpt_reg_phy_rdc_fifo_rst_err_cnt_clr">
<name>reg_phy_rdc_fifo_rst_err_cnt_clr</name>
<desc>Clear/reset for counter rdc_fifo_rst_err_cnt[3:0].
0: no clear, 1: clear.
Note: This is a synchronous dynamic signal that must have timing closed.</desc>
<sw_param offset="0xf8006050" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_cmd_timeout_rddata_cpt_reg_phy_use_fixed_re">
<name>reg_phy_use_fixed_re</name>
<desc>When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0].
When 0: PHY uses the not_empty method to do the read enable generation.
Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH.</desc>
<sw_param offset="0xf8006050" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_cmd_timeout_rddata_cpt_reg_phy_rdc_fifo_rst_disable">
<name>reg_phy_rdc_fifo_rst_disable</name>
<desc>When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty.</desc>
<sw_param offset="0xf8006050" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_cmd_timeout_rddata_cpt_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006050" start="14" end="12" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_cmd_timeout_rddata_cpt_reg_phy_rdc_we_to_re_delay">
<name>reg_phy_rdc_we_to_re_delay</name>
<desc>This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation.
The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc.
This is used only if reg_phy_use_fixed_re=1.</desc>
<sw_param offset="0xf8006050" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_cmd_timeout_rddata_cpt_reg_phy_wr_cmd_to_data">
<name>reg_phy_wr_cmd_to_data</name>
<desc>Not used in DFI PHY.</desc>
<sw_param offset="0xf8006050" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_cmd_timeout_rddata_cpt_reg_phy_rd_cmd_to_data">
<name>reg_phy_rd_cmd_to_data</name>
<desc>Not used in DFI PHY.</desc>
<sw_param offset="0xf8006050" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_mode_sts_reg_ddrc_reg_dbg_hpr_q_depth">
<name>ddrc_reg_dbg_hpr_q_depth</name>
<desc>Indicates the number of entries currently in the HPR CAM.</desc>
<sw_param offset="0xf8006054" start="20" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_mode_sts_reg_ddrc_reg_dbg_lpr_q_depth">
<name>ddrc_reg_dbg_lpr_q_depth</name>
<desc>Indicates the number of entries currently in the LPR CAM.</desc>
<sw_param offset="0xf8006054" start="15" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_mode_sts_reg_ddrc_reg_dbg_wr_q_depth">
<name>ddrc_reg_dbg_wr_q_depth</name>
<desc>Indicates the number of entries currently in the WR CAM.</desc>
<sw_param offset="0xf8006054" start="9" end="4" />
</parameter>
<parameter uniqueid="ps7_ddrc_mode_sts_reg_ddrc_reg_dbg_stall">
<name>ddrc_reg_dbg_stall</name>
<desc>1 indicates that no commands are accepted by the controller.
0 indicates that commands are being accepted.</desc>
<sw_param offset="0xf8006054" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_ddrc_mode_sts_reg_ddrc_reg_operating_mode">
<name>ddrc_reg_operating_mode</name>
<desc>Gives the status of the controller.
0 = DDRC Init
1 = Normal operation
2 = Power-down mode
3 = Self-refresh mode
4 and above = deep power down mode (LPDDR2 only)</desc>
<sw_param offset="0xf8006054" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_DLL_calib_reg_ddrc_dis_dll_calib">
<name>reg_ddrc_dis_dll_calib</name>
<desc>When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly.
When 0, controller will issue dll_calib periodically</desc>
<sw_param offset="0xf8006058" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_DLL_calib_reg_ddrc_dll_calib_to_max_x1024">
<name>reg_ddrc_dll_calib_to_max_x1024</name>
<desc>Unused in DFI Controller.</desc>
<sw_param offset="0xf8006058" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_ddrc_DLL_calib_reg_ddrc_dll_calib_to_min_x1024">
<name>reg_ddrc_dll_calib_to_min_x1024</name>
<desc>Unused in DFI Controller.</desc>
<sw_param offset="0xf8006058" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_ODT_delay_hold_reg_ddrc_wr_odt_hold">
<name>reg_ddrc_wr_odt_hold</name>
<desc>Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4</desc>
<sw_param offset="0xf800605c" start="15" end="12" />
</parameter>
<parameter uniqueid="ps7_ddrc_ODT_delay_hold_reg_ddrc_rd_odt_hold">
<name>reg_ddrc_rd_odt_hold</name>
<desc>Unused</desc>
<sw_param offset="0xf800605c" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_ddrc_ODT_delay_hold_reg_ddrc_wr_odt_delay">
<name>reg_ddrc_wr_odt_delay</name>
<desc>The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay.
ODT is not applicable for LPDDR and LPDDR2 modes.</desc>
<sw_param offset="0xf800605c" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_ddrc_ODT_delay_hold_reg_ddrc_rd_odt_delay">
<name>reg_ddrc_rd_odt_delay</name>
<desc>UNUSED</desc>
<sw_param offset="0xf800605c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_ctrl_reg1_reg_ddrc_selfref_en">
<name>reg_ddrc_selfref_en</name>
<desc>If 1, then the controller will put the DRAM into self refresh when the transaction store is empty.</desc>
<sw_param offset="0xf8006060" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_ddrc_ctrl_reg1_reserved">
<name>reserved</name>
<desc>Always keep this set to 0x0</desc>
<sw_param offset="0xf8006060" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_ddrc_ctrl_reg1_reg_ddrc_dis_collision_page_opt">
<name>reg_ddrc_dis_collision_page_opt</name>
<desc>When this is set to '0', auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word).</desc>
<sw_param offset="0xf8006060" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_ctrl_reg1_reg_ddrc_dis_wc">
<name>reg_ddrc_dis_wc</name>
<desc>When 1, disable Write Combine</desc>
<sw_param offset="0xf8006060" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_ddrc_ctrl_reg1_reg_ddrc_refresh_update_level">
<name>reg_ddrc_refresh_update_level</name>
<desc>Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially.</desc>
<sw_param offset="0xf8006060" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_ddrc_ctrl_reg1_reg_ddrc_auto_pre_en">
<name>reg_ddrc_auto_pre_en</name>
<desc>When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.)</desc>
<sw_param offset="0xf8006060" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_ddrc_ctrl_reg1_reg_ddrc_lpr_num_entries">
<name>reg_ddrc_lpr_num_entries</name>
<desc>Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored.</desc>
<sw_param offset="0xf8006060" start="6" end="1" />
</parameter>
<parameter uniqueid="ps7_ddrc_ctrl_reg1_reg_ddrc_pageclose">
<name>reg_ddrc_pageclose</name>
<desc>If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used.</desc>
<sw_param offset="0xf8006060" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_ctrl_reg2_reg_arb_go2critical_en">
<name>reg_arb_go2critical_en</name>
<desc>1 - Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on 'urgent' input coming from AXI master. 0 - Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 1'b0.</desc>
<sw_param offset="0xf8006064" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_ddrc_ctrl_reg2_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006064" start="16" end="13" />
</parameter>
<parameter uniqueid="ps7_ddrc_ctrl_reg2_reg_ddrc_go2critical_hysteresis">
<name>reg_ddrc_go2critical_hysteresis</name>
<desc>Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0.</desc>
<sw_param offset="0xf8006064" start="12" end="5" />
</parameter>
<parameter uniqueid="ps7_ddrc_ctrl_reg2_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006064" start="4" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_ctrl_reg3_reg_ddrc_dfi_t_wlmrd">
<name>reg_ddrc_dfi_t_wlmrd</name>
<desc>First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec.
Only present in designs that support DDR3 devices.</desc>
<sw_param offset="0xf8006068" start="25" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_ctrl_reg3_reg_ddrc_rdlvl_rr">
<name>reg_ddrc_rdlvl_rr</name>
<desc>Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Only present in designs that support DDR3 devices</desc>
<sw_param offset="0xf8006068" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_ddrc_ctrl_reg3_reg_ddrc_wrlvl_ww">
<name>reg_ddrc_wrlvl_ww</name>
<desc>Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode.
Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50)
Only present in designs that support DDR3 and LPDDR2 devices.</desc>
<sw_param offset="0xf8006068" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_ctrl_reg4_dfi_t_ctrlupd_interval_max_x1024">
<name>dfi_t_ctrlupd_interval_max_x1024</name>
<desc>This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks</desc>
<sw_param offset="0xf800606c" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_ddrc_ctrl_reg4_dfi_t_ctrlupd_interval_min_x1024">
<name>dfi_t_ctrlupd_interval_min_x1024</name>
<desc>This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks</desc>
<sw_param offset="0xf800606c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_CHE_REFRESH_TIMER01_refresh_timer1_start_value_x32">
<name>refresh_timer1_start_value_x32</name>
<desc>Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY.</desc>
<sw_param offset="0xf80060a0" start="23" end="12" />
</parameter>
<parameter uniqueid="ps7_ddrc_CHE_REFRESH_TIMER01_refresh_timer0_start_value_x32">
<name>refresh_timer0_start_value_x32</name>
<desc>Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY.</desc>
<sw_param offset="0xf80060a0" start="11" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_CHE_T_ZQ_reg_ddrc_t_zq_short_nop">
<name>reg_ddrc_t_zq_short_nop</name>
<desc>Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices.</desc>
<sw_param offset="0xf80060a4" start="31" end="22" />
</parameter>
<parameter uniqueid="ps7_ddrc_CHE_T_ZQ_reg_ddrc_t_zq_long_nop">
<name>reg_ddrc_t_zq_long_nop</name>
<desc>Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices.</desc>
<sw_param offset="0xf80060a4" start="21" end="12" />
</parameter>
<parameter uniqueid="ps7_ddrc_CHE_T_ZQ_reg_ddrc_t_mod">
<name>reg_ddrc_t_mod</name>
<desc>Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns)</desc>
<sw_param offset="0xf80060a4" start="11" end="2" />
</parameter>
<parameter uniqueid="ps7_ddrc_CHE_T_ZQ_reg_ddrc_ddr3">
<name>reg_ddrc_ddr3</name>
<desc>Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3.</desc>
<sw_param offset="0xf80060a4" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ddrc_CHE_T_ZQ_reg_ddrc_dis_auto_zq">
<name>reg_ddrc_dis_auto_zq</name>
<desc>1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices.</desc>
<sw_param offset="0xf80060a4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_CHE_T_ZQ_Short_Interval_Reg_dram_rstn_x1024">
<name>dram_rstn_x1024</name>
<desc>Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only.</desc>
<sw_param offset="0xf80060a8" start="27" end="20" />
</parameter>
<parameter uniqueid="ps7_ddrc_CHE_T_ZQ_Short_Interval_Reg_t_zq_short_interval_x1024">
<name>t_zq_short_interval_x1024</name>
<desc>Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices.</desc>
<sw_param offset="0xf80060a8" start="19" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_deep_pwrdwn_reg_deeppowerdown_to_x1024">
<name>deeppowerdown_to_x1024</name>
<desc>Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY.</desc>
<sw_param offset="0xf80060ac" start="8" end="1" />
</parameter>
<parameter uniqueid="ps7_ddrc_deep_pwrdwn_reg_deeppowerdown_en">
<name>deeppowerdown_en</name>
<desc>1 - Controller puts the DRAM into Deep Powerdown mode when the transaction store is empty. 0 - Brings Controller out of Deep Powerdown mode Present only in designs configured to support LPDDR or LPDDR2 FOR PERFORMANCE ONLY.</desc>
<sw_param offset="0xf80060ac" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_2c_reg_ddrc_dfi_rd_data_eye_train">
<name>reg_ddrc_dfi_rd_data_eye_train</name>
<desc>1 = Read Data Eye training mode has been enabled as part of init sequence. Only present in designs that support DDR3 or LPDDR2 devices.</desc>
<sw_param offset="0xf80060b0" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_2c_reg_ddrc_dfi_rd_dqs_gate_level">
<name>reg_ddrc_dfi_rd_dqs_gate_level</name>
<desc>1 = Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0= Read DQS gate leveling is disabled.</desc>
<sw_param offset="0xf80060b0" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_2c_reg_ddrc_dfi_wr_level_en">
<name>reg_ddrc_dfi_wr_level_en</name>
<desc>1 = Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0 = Write leveling disabled.</desc>
<sw_param offset="0xf80060b0" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_2c_ddrc_reg_trdlvl_max_error">
<name>ddrc_reg_trdlvl_max_error</name>
<desc>When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared.
Clearing is done by writing a '0' to this register.
Only present in designs that support DDR3 or LPDDR2 devices.</desc>
<sw_param offset="0xf80060b0" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_2c_ddrc_reg_twrlvl_max_error">
<name>ddrc_reg_twrlvl_max_error</name>
<desc>When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared.
Clearing is done by writing a '0' to this register.
Only present in designs that support DDR3.</desc>
<sw_param offset="0xf80060b0" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_2c_dfi_rdlvl_max_x1024">
<name>dfi_rdlvl_max_x1024</name>
<desc>Read leveling maximum time.
Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks</desc>
<sw_param offset="0xf80060b0" start="23" end="12" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_2c_dfi_wrlvl_max_x1024">
<name>dfi_wrlvl_max_x1024</name>
<desc>Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks</desc>
<sw_param offset="0xf80060b0" start="11" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_2d_reg_ddrc_dis_pre_bypass">
<name>reg_ddrc_dis_pre_bypass</name>
<desc>Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY.</desc>
<sw_param offset="0xf80060b4" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_2d_reg_ddrc_skip_ocd">
<name>reg_ddrc_skip_ocd</name>
<desc>This register must be kept at 1'b1. 1'b0 is NOT supported. 1 - Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0 - Not supported.</desc>
<sw_param offset="0xf80060b4" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_2d_reg_ddrc_2t_delay">
<name>reg_ddrc_2t_delay</name>
<desc>Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature.</desc>
<sw_param offset="0xf80060b4" start="8" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_dfi_timing_reg_ddrc_dfi_t_ctrlup_max">
<name>reg_ddrc_dfi_t_ctrlup_max</name>
<desc>Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert.</desc>
<sw_param offset="0xf80060b8" start="24" end="15" />
</parameter>
<parameter uniqueid="ps7_ddrc_dfi_timing_reg_ddrc_dfi_t_ctrlup_min">
<name>reg_ddrc_dfi_t_ctrlup_min</name>
<desc>Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted.</desc>
<sw_param offset="0xf80060b8" start="14" end="5" />
</parameter>
<parameter uniqueid="ps7_ddrc_dfi_timing_reg_ddrc_dfi_t_rddata_en">
<name>reg_ddrc_dfi_t_rddata_en</name>
<desc>Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal.
Non-LPDDR -&gt; RL-1
LPDDR -&gt; RL
Where RL is read latency of DRAM.</desc>
<sw_param offset="0xf80060b8" start="4" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_refresh_timer_2_reg_ddrc_refresh_timer3_start_value_x32">
<name>reg_ddrc_refresh_timer3_start_value_x32</name>
<desc>Refresh Timer for Rank 3 (Only present in 4-rank configurations). Unit: in multiples of 32 clocks (Only present in multi-rank configurations). FOR PERFORMANCE ONLY.</desc>
<sw_param offset="0xf80060bc" start="23" end="12" />
</parameter>
<parameter uniqueid="ps7_ddrc_refresh_timer_2_reg_ddrc_refresh_timer2_start_value_x32">
<name>reg_ddrc_refresh_timer2_start_value_x32</name>
<desc>Refresh Timer for Rank 2 (Only present in 4-rank configurations). Unit: in multiples of 32 clocks (Only present in multi-rank configurations). FOR PERFORMANCE ONLY.</desc>
<sw_param offset="0xf80060bc" start="11" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_nc_timing_reg_ddrc_lpr_min_non_critical">
<name>reg_ddrc_lpr_min_non_critical</name>
<desc>Unused.</desc>
<sw_param offset="0xf80060c0" start="21" end="11" />
</parameter>
<parameter uniqueid="ps7_ddrc_nc_timing_reg_ddrc_hpr_min_non_critical">
<name>reg_ddrc_hpr_min_non_critical</name>
<desc>Unused.</desc>
<sw_param offset="0xf80060c0" start="10" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_CHE_ECC_CONTROL_REG_OFFSET_Clear_Correctable_DRAM_ECC_error">
<name>Clear_Correctable_DRAM_ECC_error</name>
<desc>Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters.</desc>
<sw_param offset="0xf80060c4" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ddrc_CHE_ECC_CONTROL_REG_OFFSET_Clear_Uncorrectable_DRAM_ECC_error">
<name>Clear_Uncorrectable_DRAM_ECC_error</name>
<desc>Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters.</desc>
<sw_param offset="0xf80060c4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_CHE_CORR_ECC_LOG_REG_OFFSET_ECC_CORRECTED_BIT_NUM">
<name>ECC_CORRECTED_BIT_NUM</name>
<desc>Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data.
This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined.</desc>
<sw_param offset="0xf80060c8" start="7" end="1" />
</parameter>
<parameter uniqueid="ps7_ddrc_CHE_CORR_ECC_LOG_REG_OFFSET_CORR_ECC_LOG_VALID">
<name>CORR_ECC_LOG_VALID</name>
<desc>Set to '1' when a correctable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x31)</desc>
<sw_param offset="0xf80060c8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_CHE_CORR_ECC_ADDR_REG_OFFSET_CORR_ECC_LOG_BANK">
<name>CORR_ECC_LOG_BANK</name>
<desc>Bank[2:0]</desc>
<sw_param offset="0xf80060cc" start="30" end="28" />
</parameter>
<parameter uniqueid="ps7_ddrc_CHE_CORR_ECC_ADDR_REG_OFFSET_CORR_ECC_LOG_ROW">
<name>CORR_ECC_LOG_ROW</name>
<desc>Row[15:0]</desc>
<sw_param offset="0xf80060cc" start="27" end="12" />
</parameter>
<parameter uniqueid="ps7_ddrc_CHE_CORR_ECC_ADDR_REG_OFFSET_CORR_ECC_LOG_COL">
<name>CORR_ECC_LOG_COL</name>
<desc>Col[11:0]</desc>
<sw_param offset="0xf80060cc" start="11" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_CHE_CORR_ECC_DATA_31_0_REG_OFFSET_CORR_ECC_LOG_DAT_31_0">
<name>CORR_ECC_LOG_DAT_31_0</name>
<desc>bits [31:0] of the data that caused the captured correctable ECC error. (Data associated with the first ECC error if multiple errors occurred since CORR_ECC_LOG_VALID was cleared). Since each ECC engine handles 8-bits of data, only the lower 8-bits of this register have valid data. The upper 24-bits will always be 0.</desc>
<sw_param offset="0xf80060d0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_CHE_CORR_ECC_DATA_63_32_REG_OFFSET_CORR_ECC_LOG_DAT_63_32">
<name>CORR_ECC_LOG_DAT_63_32</name>
<desc>bits [63:32] of the data that caused the captured correctable ECC error. (Data associated with the first ECC error if multiple errors occurred since CORR_ECC_LOG_VALID was cleared) Since each ECC engine handles 8-bits of data and that is logged in register 0x34, all the 32-bits of this register will always be 0.</desc>
<sw_param offset="0xf80060d4" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_CHE_CORR_ECC_DATA_71_64_REG_OFFSET_CORR_ECC_LOG_DAT_71_64">
<name>CORR_ECC_LOG_DAT_71_64</name>
<desc>bits [71:64] of the data that caused the captured correctable ECC error. (Data associated with the first ECC error if multiple errors occurred since CORR_ECC_LOG_VALID was cleared) 5-bits of ECC are calculated over 8-bits of data. Bits[68:64] carries these 5-bits. Bits[71:69] are always 0.</desc>
<sw_param offset="0xf80060d8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_CHE_UNCORR_ECC_LOG_REG_OFFSET_UNCORR_ECC_LOG_VALID">
<name>UNCORR_ECC_LOG_VALID</name>
<desc>Set to '1' when an uncorrectable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x31).</desc>
<sw_param offset="0xf80060dc" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_CHE_UNCORR_ECC_ADDR_REG_OFFSET_UNCORR_ECC_LOG_BANK">
<name>UNCORR_ECC_LOG_BANK</name>
<desc>Bank[2:0]</desc>
<sw_param offset="0xf80060e0" start="30" end="28" />
</parameter>
<parameter uniqueid="ps7_ddrc_CHE_UNCORR_ECC_ADDR_REG_OFFSET_UNCORR_ECC_LOG_ROW">
<name>UNCORR_ECC_LOG_ROW</name>
<desc>Row[15:0]</desc>
<sw_param offset="0xf80060e0" start="27" end="12" />
</parameter>
<parameter uniqueid="ps7_ddrc_CHE_UNCORR_ECC_ADDR_REG_OFFSET_UNCORR_ECC_LOG_COL">
<name>UNCORR_ECC_LOG_COL</name>
<desc>Col[11:0]</desc>
<sw_param offset="0xf80060e0" start="11" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET_UNCORR_ECC_LOG_DAT_31_0">
<name>UNCORR_ECC_LOG_DAT_31_0</name>
<desc>bits [31:0] of the data that caused the captured uncorrectable ECC error. (Data associated with the first ECC error if multiple errors occurred since UNCORR_ECC_LOG_VALID was cleared). Since each ECC engine handles 8-bits of data, only the lower 8-bits of this register have valid data. The upper 24-bits will always be 0.</desc>
<sw_param offset="0xf80060e4" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET_UNCORR_ECC_LOG_DAT_63_32">
<name>UNCORR_ECC_LOG_DAT_63_32</name>
<desc>bits [63:32] of the data that caused the captured uncorrectable ECC error. (Data associated with the first ECC error if multiple errors occurred since CORR_ECC_LOG_VALID was cleared) Since each ECC engine handles 8-bits of data and that is logged in register 0x34, all the 32-bits of this register will always be 0.</desc>
<sw_param offset="0xf80060e8" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET_UNCORR_ECC_LOG_DAT_71_64">
<name>UNCORR_ECC_LOG_DAT_71_64</name>
<desc>bits [71:64] of the data that caused the captured uncorrectable ECC error. (Data associated with the first ECC error if multiple errors occurred since UNCORR_ECC_LOG_VALID was cleared) 5-bits of ECC are calculated over 8-bits of data. Bits[68:64] carries these 5-bits. Bits[71:69] are always 0.</desc>
<sw_param offset="0xf80060ec" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_CHE_ECC_STATS_REG_OFFSET_STAT_NUM_CORR_ERR">
<name>STAT_NUM_CORR_ERR</name>
<desc>Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x58).</desc>
<sw_param offset="0xf80060f0" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_ddrc_CHE_ECC_STATS_REG_OFFSET_STAT_NUM_UNCORR_ERR">
<name>STAT_NUM_UNCORR_ERR</name>
<desc>Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x58).</desc>
<sw_param offset="0xf80060f0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_ECC_scrub_reg_ddrc_dis_scrub">
<name>reg_ddrc_dis_scrub</name>
<desc>This feature is NOT supported. Only default value works.
1 - Disable ECC scrubs
0 - Enable ECC scrubs Valid only when reg_ddrc_ecc_mode = 3'b100.</desc>
<sw_param offset="0xf80060f4" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_ddrc_ECC_scrub_reg_ddrc_ecc_mode">
<name>reg_ddrc_ecc_mode</name>
<desc>DRAM ECC Mode. The only valid values that works for this project are 3'b000 (No ECC) and 3'b100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 3'b100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON.
000 - No ECC,
001 - Reserved
010 - Parity
011 - Reserved
100 - SEC/DED over 1-beat
101 - SEC/DED over multiple beats
110 - Device Correction
111 - Reserved</desc>
<sw_param offset="0xf80060f4" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET_ddrc_reg_ecc_corr_bit_mask">
<name>ddrc_reg_ecc_corr_bit_mask</name>
<desc>Bits [31:0] of ddrc_reg_ecc_corr_bit_mask register. Indicates the mask of the corrected data. 1 - on any bit indicates that the bit has been corrected by the DRAM ECC logic 0 - on any bit indicates that the bit has NOT been corrected by the DRAM ECC logic. Valid when any bit of 'ddrc_reg_ecc_corrected_err' is high.This mask doesn't indicate any correction that has been made in the ECC check bits. If there are errors in multiple lanes, then this signal will have the mask for the lowest lane. Each ECC engine works on 8-bits of data. Hence only the lower 8-bits carry valid information. Upper 24-bits are always 0.</desc>
<sw_param offset="0xf80060f8" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET_ddrc_reg_ecc_corr_bit_mask">
<name>ddrc_reg_ecc_corr_bit_mask</name>
<desc>Bits [63:32] of ddrc_reg_ecc_corr_bit_mask register. Indicates the mask of the corrected data. 1 - on any bit indicates that the bit has been corrected by the DRAM ECC logic 0 - on any bit indicates that the bit has NOT been corrected by the DRAM ECC logic. Valid when any bit of 'ddrc_reg_ecc_corrected_err' is high. This mask doesn't indicate any correction that has been made in the ECC check bits. If there are errors in multiple lanes, then this signal will have the mask for the lowest lane. Each ECC engine works on 8-bits of data and this is reported in register 0x3E. All 32-bits of this register are 0 always.</desc>
<sw_param offset="0xf80060fc" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_rcvr_enable_reg_phy_dif_off">
<name>reg_phy_dif_off</name>
<desc>Value to drive to IO receiver enable pins when turning it OFF.
When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off.
IOD is the size specified by the IO_DIFEN_SIZE parameter.
Depending on the IO, one of these signals dif_on or dif_off can be used.</desc>
<sw_param offset="0xf8006114" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_rcvr_enable_reg_phy_dif_on">
<name>reg_phy_dif_on</name>
<desc>Value to drive to IO receiver enable pins when turning it ON.
When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off.
IOD is the size specified by the IO_DIFEN_SIZE parameter.</desc>
<sw_param offset="0xf8006114" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config0_reg_phy_dq_offset">
<name>reg_phy_dq_offset</name>
<desc>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift).
This is only used when reg_phy_use_wr_level=1.
#Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</desc>
<sw_param offset="0xf8006118" start="30" end="24" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config0_reg_phy_bist_err_clr">
<name>reg_phy_bist_err_clr</name>
<desc>Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect</desc>
<sw_param offset="0xf8006118" start="23" end="15" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config0_reg_phy_bist_shift_dq">
<name>reg_phy_bist_shift_dq</name>
<desc>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift.</desc>
<sw_param offset="0xf8006118" start="14" end="6" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config0_reg_phy_board_lpbk_rx">
<name>reg_phy_board_lpbk_rx</name>
<desc>External Board Loopback testing.
1: This Slice behaves as Receiver for board loopback. 0: disable
This port must be set '0' always except when in external board level loopback test mode.</desc>
<sw_param offset="0xf8006118" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config0_reg_phy_board_lpbk_tx">
<name>reg_phy_board_lpbk_tx</name>
<desc>External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable
This port must be set '0' always except when in external board level loopback test mode.</desc>
<sw_param offset="0xf8006118" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config0_reg_phy_wrlvl_inc_mode">
<name>reg_phy_wrlvl_inc_mode</name>
<desc>RESERVED</desc>
<sw_param offset="0xf8006118" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config0_reg_phy_gatelvl_inc_mode">
<name>reg_phy_gatelvl_inc_mode</name>
<desc>RESERVED</desc>
<sw_param offset="0xf8006118" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config0_reg_phy_rdlvl_inc_mode">
<name>reg_phy_rdlvl_inc_mode</name>
<desc>RESERVED</desc>
<sw_param offset="0xf8006118" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config0_reg_phy_data_slice_in_use">
<name>reg_phy_data_slice_in_use</name>
<desc>Data bus width selection for Read FIFO RE generation. One bit for each data slice.
1: data slice is valid.
0: read data responses are ignored.
Note: The Phy Data Slice 0 must always be enabled.</desc>
<sw_param offset="0xf8006118" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config1_reg_phy_dq_offset">
<name>reg_phy_dq_offset</name>
<desc>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift).
This is only used when reg_phy_use_wr_level=1.
#Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</desc>
<sw_param offset="0xf800611c" start="30" end="24" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config1_reg_phy_bist_err_clr">
<name>reg_phy_bist_err_clr</name>
<desc>Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect</desc>
<sw_param offset="0xf800611c" start="23" end="15" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config1_reg_phy_bist_shift_dq">
<name>reg_phy_bist_shift_dq</name>
<desc>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift.</desc>
<sw_param offset="0xf800611c" start="14" end="6" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config1_reg_phy_board_lpbk_rx">
<name>reg_phy_board_lpbk_rx</name>
<desc>External Board Loopback testing.
1: This Slice behaves as Receiver for board loopback. 0: disable
This port must be set '0' always except when in external board level loopback test mode.</desc>
<sw_param offset="0xf800611c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config1_reg_phy_board_lpbk_tx">
<name>reg_phy_board_lpbk_tx</name>
<desc>External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable
This port must be set '0' always except when in external board level loopback test mode.</desc>
<sw_param offset="0xf800611c" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config1_reg_phy_wrlvl_inc_mode">
<name>reg_phy_wrlvl_inc_mode</name>
<desc>RESERVED</desc>
<sw_param offset="0xf800611c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config1_reg_phy_gatelvl_inc_mode">
<name>reg_phy_gatelvl_inc_mode</name>
<desc>RESERVED</desc>
<sw_param offset="0xf800611c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config1_reg_phy_rdlvl_inc_mode">
<name>reg_phy_rdlvl_inc_mode</name>
<desc>RESERVED</desc>
<sw_param offset="0xf800611c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config1_reg_phy_data_slice_in_use">
<name>reg_phy_data_slice_in_use</name>
<desc>Data bus width selection for Read FIFO RE generation. One bit for each data slice.
1: data slice is valid.
0: read data responses are ignored.
Note: The Phy Data Slice 0 must always be enabled.</desc>
<sw_param offset="0xf800611c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config2_reg_phy_dq_offset">
<name>reg_phy_dq_offset</name>
<desc>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift).
This is only used when reg_phy_use_wr_level=1.
#Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</desc>
<sw_param offset="0xf8006120" start="30" end="24" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config2_reg_phy_bist_err_clr">
<name>reg_phy_bist_err_clr</name>
<desc>Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect</desc>
<sw_param offset="0xf8006120" start="23" end="15" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config2_reg_phy_bist_shift_dq">
<name>reg_phy_bist_shift_dq</name>
<desc>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift.</desc>
<sw_param offset="0xf8006120" start="14" end="6" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config2_reg_phy_board_lpbk_rx">
<name>reg_phy_board_lpbk_rx</name>
<desc>External Board Loopback testing.
1: This Slice behaves as Receiver for board loopback. 0: disable
This port must be set '0' always except when in external board level loopback test mode.</desc>
<sw_param offset="0xf8006120" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config2_reg_phy_board_lpbk_tx">
<name>reg_phy_board_lpbk_tx</name>
<desc>External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable
This port must be set '0' always except when in external board level loopback test mode.</desc>
<sw_param offset="0xf8006120" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config2_reg_phy_wrlvl_inc_mode">
<name>reg_phy_wrlvl_inc_mode</name>
<desc>RESERVED</desc>
<sw_param offset="0xf8006120" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config2_reg_phy_gatelvl_inc_mode">
<name>reg_phy_gatelvl_inc_mode</name>
<desc>RESERVED</desc>
<sw_param offset="0xf8006120" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config2_reg_phy_rdlvl_inc_mode">
<name>reg_phy_rdlvl_inc_mode</name>
<desc>RESERVED</desc>
<sw_param offset="0xf8006120" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config2_reg_phy_data_slice_in_use">
<name>reg_phy_data_slice_in_use</name>
<desc>Data bus width selection for Read FIFO RE generation. One bit for each data slice.
1: data slice is valid.
0: read data responses are ignored.
Note: The Phy Data Slice 0 must always be enabled.</desc>
<sw_param offset="0xf8006120" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config3_reg_phy_dq_offset">
<name>reg_phy_dq_offset</name>
<desc>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift).
This is only used when reg_phy_use_wr_level=1.
#Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</desc>
<sw_param offset="0xf8006124" start="30" end="24" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config3_reg_phy_bist_err_clr">
<name>reg_phy_bist_err_clr</name>
<desc>Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect</desc>
<sw_param offset="0xf8006124" start="23" end="15" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config3_reg_phy_bist_shift_dq">
<name>reg_phy_bist_shift_dq</name>
<desc>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift.</desc>
<sw_param offset="0xf8006124" start="14" end="6" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config3_reg_phy_board_lpbk_rx">
<name>reg_phy_board_lpbk_rx</name>
<desc>External Board Loopback testing.
1: This Slice behaves as Receiver for board loopback. 0: disable
This port must be set '0' always except when in external board level loopback test mode.</desc>
<sw_param offset="0xf8006124" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config3_reg_phy_board_lpbk_tx">
<name>reg_phy_board_lpbk_tx</name>
<desc>External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable
This port must be set '0' always except when in external board level loopback test mode.</desc>
<sw_param offset="0xf8006124" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config3_reg_phy_wrlvl_inc_mode">
<name>reg_phy_wrlvl_inc_mode</name>
<desc>RESERVED</desc>
<sw_param offset="0xf8006124" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config3_reg_phy_gatelvl_inc_mode">
<name>reg_phy_gatelvl_inc_mode</name>
<desc>RESERVED</desc>
<sw_param offset="0xf8006124" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config3_reg_phy_rdlvl_inc_mode">
<name>reg_phy_rdlvl_inc_mode</name>
<desc>RESERVED</desc>
<sw_param offset="0xf8006124" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ddrc_PHY_Config3_reg_phy_data_slice_in_use">
<name>reg_phy_data_slice_in_use</name>
<desc>Data bus width selection for Read FIFO RE generation. One bit for each data slice.
1: data slice is valid.
0: read data responses are ignored.
Note: The Phy Data Slice 0 must always be enabled.</desc>
<sw_param offset="0xf8006124" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_init_ratio0_reg_phy_gatelvl_init_ratio">
<name>reg_phy_gatelvl_init_ratio</name>
<desc>The user programmable init ratio used Gate Leveling FSM</desc>
<sw_param offset="0xf800612c" start="19" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_init_ratio0_reg_phy_wrlvl_init_ratio">
<name>reg_phy_wrlvl_init_ratio</name>
<desc>The user programmable init ratio used by Write Leveling FSM</desc>
<sw_param offset="0xf800612c" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_init_ratio1_reg_phy_gatelvl_init_ratio">
<name>reg_phy_gatelvl_init_ratio</name>
<desc>The user programmable init ratio used Gate Leveling FSM</desc>
<sw_param offset="0xf8006130" start="19" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_init_ratio1_reg_phy_wrlvl_init_ratio">
<name>reg_phy_wrlvl_init_ratio</name>
<desc>The user programmable init ratio used by Write Leveling FSM</desc>
<sw_param offset="0xf8006130" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_init_ratio2_reg_phy_gatelvl_init_ratio">
<name>reg_phy_gatelvl_init_ratio</name>
<desc>The user programmable init ratio used Gate Leveling FSM</desc>
<sw_param offset="0xf8006134" start="19" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_init_ratio2_reg_phy_wrlvl_init_ratio">
<name>reg_phy_wrlvl_init_ratio</name>
<desc>The user programmable init ratio used by Write Leveling FSM</desc>
<sw_param offset="0xf8006134" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_init_ratio3_reg_phy_gatelvl_init_ratio">
<name>reg_phy_gatelvl_init_ratio</name>
<desc>The user programmable init ratio used Gate Leveling FSM</desc>
<sw_param offset="0xf8006138" start="19" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_init_ratio3_reg_phy_wrlvl_init_ratio">
<name>reg_phy_wrlvl_init_ratio</name>
<desc>The user programmable init ratio used by Write Leveling FSM</desc>
<sw_param offset="0xf8006138" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_rd_dqs_cfg0_reg_phy_rd_dqs_slave_delay">
<name>reg_phy_rd_dqs_slave_delay</name>
<desc>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</desc>
<sw_param offset="0xf8006140" start="19" end="11" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_rd_dqs_cfg0_reg_phy_rd_dqs_slave_force">
<name>reg_phy_rd_dqs_slave_force</name>
<desc>1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.</desc>
<sw_param offset="0xf8006140" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_rd_dqs_cfg0_reg_phy_rd_dqs_slave_ratio">
<name>reg_phy_rd_dqs_slave_ratio</name>
<desc>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</desc>
<sw_param offset="0xf8006140" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_rd_dqs_cfg1_reg_phy_rd_dqs_slave_delay">
<name>reg_phy_rd_dqs_slave_delay</name>
<desc>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</desc>
<sw_param offset="0xf8006144" start="19" end="11" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_rd_dqs_cfg1_reg_phy_rd_dqs_slave_force">
<name>reg_phy_rd_dqs_slave_force</name>
<desc>1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.</desc>
<sw_param offset="0xf8006144" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_rd_dqs_cfg1_reg_phy_rd_dqs_slave_ratio">
<name>reg_phy_rd_dqs_slave_ratio</name>
<desc>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</desc>
<sw_param offset="0xf8006144" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_rd_dqs_cfg2_reg_phy_rd_dqs_slave_delay">
<name>reg_phy_rd_dqs_slave_delay</name>
<desc>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</desc>
<sw_param offset="0xf8006148" start="19" end="11" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_rd_dqs_cfg2_reg_phy_rd_dqs_slave_force">
<name>reg_phy_rd_dqs_slave_force</name>
<desc>1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.</desc>
<sw_param offset="0xf8006148" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_rd_dqs_cfg2_reg_phy_rd_dqs_slave_ratio">
<name>reg_phy_rd_dqs_slave_ratio</name>
<desc>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</desc>
<sw_param offset="0xf8006148" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_rd_dqs_cfg3_reg_phy_rd_dqs_slave_delay">
<name>reg_phy_rd_dqs_slave_delay</name>
<desc>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</desc>
<sw_param offset="0xf800614c" start="19" end="11" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_rd_dqs_cfg3_reg_phy_rd_dqs_slave_force">
<name>reg_phy_rd_dqs_slave_force</name>
<desc>1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.</desc>
<sw_param offset="0xf800614c" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_rd_dqs_cfg3_reg_phy_rd_dqs_slave_ratio">
<name>reg_phy_rd_dqs_slave_ratio</name>
<desc>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</desc>
<sw_param offset="0xf800614c" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_wr_dqs_cfg0_reg_phy_wr_dqs_slave_delay">
<name>reg_phy_wr_dqs_slave_delay</name>
<desc>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</desc>
<sw_param offset="0xf8006154" start="19" end="11" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_wr_dqs_cfg0_reg_phy_wr_dqs_slave_force">
<name>reg_phy_wr_dqs_slave_force</name>
<desc>1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</desc>
<sw_param offset="0xf8006154" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_wr_dqs_cfg0_reg_phy_wr_dqs_slave_ratio">
<name>reg_phy_wr_dqs_slave_ratio</name>
<desc>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</desc>
<sw_param offset="0xf8006154" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_wr_dqs_cfg1_reg_phy_wr_dqs_slave_delay">
<name>reg_phy_wr_dqs_slave_delay</name>
<desc>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</desc>
<sw_param offset="0xf8006158" start="19" end="11" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_wr_dqs_cfg1_reg_phy_wr_dqs_slave_force">
<name>reg_phy_wr_dqs_slave_force</name>
<desc>1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</desc>
<sw_param offset="0xf8006158" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_wr_dqs_cfg1_reg_phy_wr_dqs_slave_ratio">
<name>reg_phy_wr_dqs_slave_ratio</name>
<desc>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</desc>
<sw_param offset="0xf8006158" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_wr_dqs_cfg2_reg_phy_wr_dqs_slave_delay">
<name>reg_phy_wr_dqs_slave_delay</name>
<desc>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</desc>
<sw_param offset="0xf800615c" start="19" end="11" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_wr_dqs_cfg2_reg_phy_wr_dqs_slave_force">
<name>reg_phy_wr_dqs_slave_force</name>
<desc>1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</desc>
<sw_param offset="0xf800615c" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_wr_dqs_cfg2_reg_phy_wr_dqs_slave_ratio">
<name>reg_phy_wr_dqs_slave_ratio</name>
<desc>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</desc>
<sw_param offset="0xf800615c" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_wr_dqs_cfg3_reg_phy_wr_dqs_slave_delay">
<name>reg_phy_wr_dqs_slave_delay</name>
<desc>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</desc>
<sw_param offset="0xf8006160" start="19" end="11" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_wr_dqs_cfg3_reg_phy_wr_dqs_slave_force">
<name>reg_phy_wr_dqs_slave_force</name>
<desc>1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</desc>
<sw_param offset="0xf8006160" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_wr_dqs_cfg3_reg_phy_wr_dqs_slave_ratio">
<name>reg_phy_wr_dqs_slave_ratio</name>
<desc>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</desc>
<sw_param offset="0xf8006160" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_we_cfg0_reg_phy_fifo_we_in_delay">
<name>reg_phy_fifo_we_in_delay</name>
<desc>Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.</desc>
<sw_param offset="0xf8006168" start="20" end="12" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_we_cfg0_reg_phy_fifo_we_in_force">
<name>reg_phy_fifo_we_in_force</name>
<desc>1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.</desc>
<sw_param offset="0xf8006168" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_we_cfg0_reg_phy_fifo_we_slave_ratio">
<name>reg_phy_fifo_we_slave_ratio</name>
<desc>Ratio value to be used when fifo_we_X_force_mode is set to 0.</desc>
<sw_param offset="0xf8006168" start="10" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_we_cfg1_reg_phy_fifo_we_in_delay">
<name>reg_phy_fifo_we_in_delay</name>
<desc>Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.</desc>
<sw_param offset="0xf800616c" start="20" end="12" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_we_cfg1_reg_phy_fifo_we_in_force">
<name>reg_phy_fifo_we_in_force</name>
<desc>1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.</desc>
<sw_param offset="0xf800616c" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_we_cfg1_reg_phy_fifo_we_slave_ratio">
<name>reg_phy_fifo_we_slave_ratio</name>
<desc>Ratio value to be used when fifo_we_X_force_mode is set to 0.</desc>
<sw_param offset="0xf800616c" start="10" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_we_cfg2_reg_phy_fifo_we_in_delay">
<name>reg_phy_fifo_we_in_delay</name>
<desc>Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.</desc>
<sw_param offset="0xf8006170" start="20" end="12" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_we_cfg2_reg_phy_fifo_we_in_force">
<name>reg_phy_fifo_we_in_force</name>
<desc>1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.</desc>
<sw_param offset="0xf8006170" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_we_cfg2_reg_phy_fifo_we_slave_ratio">
<name>reg_phy_fifo_we_slave_ratio</name>
<desc>Ratio value to be used when fifo_we_X_force_mode is set to 0.</desc>
<sw_param offset="0xf8006170" start="10" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_we_cfg3_reg_phy_fifo_we_in_delay">
<name>reg_phy_fifo_we_in_delay</name>
<desc>Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.</desc>
<sw_param offset="0xf8006174" start="20" end="12" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_we_cfg3_reg_phy_fifo_we_in_force">
<name>reg_phy_fifo_we_in_force</name>
<desc>1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.</desc>
<sw_param offset="0xf8006174" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_we_cfg3_reg_phy_fifo_we_slave_ratio">
<name>reg_phy_fifo_we_slave_ratio</name>
<desc>Ratio value to be used when fifo_we_X_force_mode is set to 0.</desc>
<sw_param offset="0xf8006174" start="10" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_wr_data_slv0_reg_phy_wr_data_slave_delay">
<name>reg_phy_wr_data_slave_delay</name>
<desc>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</desc>
<sw_param offset="0xf800617c" start="19" end="11" />
</parameter>
<parameter uniqueid="ps7_ddrc_wr_data_slv0_reg_phy_wr_data_slave_force">
<name>reg_phy_wr_data_slave_force</name>
<desc>1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</desc>
<sw_param offset="0xf800617c" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_wr_data_slv0_reg_phy_wr_data_slave_ratio">
<name>reg_phy_wr_data_slave_ratio</name>
<desc>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</desc>
<sw_param offset="0xf800617c" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_wr_data_slv1_reg_phy_wr_data_slave_delay">
<name>reg_phy_wr_data_slave_delay</name>
<desc>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</desc>
<sw_param offset="0xf8006180" start="19" end="11" />
</parameter>
<parameter uniqueid="ps7_ddrc_wr_data_slv1_reg_phy_wr_data_slave_force">
<name>reg_phy_wr_data_slave_force</name>
<desc>1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</desc>
<sw_param offset="0xf8006180" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_wr_data_slv1_reg_phy_wr_data_slave_ratio">
<name>reg_phy_wr_data_slave_ratio</name>
<desc>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</desc>
<sw_param offset="0xf8006180" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_wr_data_slv2_reg_phy_wr_data_slave_delay">
<name>reg_phy_wr_data_slave_delay</name>
<desc>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</desc>
<sw_param offset="0xf8006184" start="19" end="11" />
</parameter>
<parameter uniqueid="ps7_ddrc_wr_data_slv2_reg_phy_wr_data_slave_force">
<name>reg_phy_wr_data_slave_force</name>
<desc>1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</desc>
<sw_param offset="0xf8006184" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_wr_data_slv2_reg_phy_wr_data_slave_ratio">
<name>reg_phy_wr_data_slave_ratio</name>
<desc>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</desc>
<sw_param offset="0xf8006184" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_wr_data_slv3_reg_phy_wr_data_slave_delay">
<name>reg_phy_wr_data_slave_delay</name>
<desc>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</desc>
<sw_param offset="0xf8006188" start="19" end="11" />
</parameter>
<parameter uniqueid="ps7_ddrc_wr_data_slv3_reg_phy_wr_data_slave_force">
<name>reg_phy_wr_data_slave_force</name>
<desc>1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</desc>
<sw_param offset="0xf8006188" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_wr_data_slv3_reg_phy_wr_data_slave_ratio">
<name>reg_phy_wr_data_slave_ratio</name>
<desc>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</desc>
<sw_param offset="0xf8006188" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_64_reg_phy_int_lpbk">
<name>reg_phy_int_lpbk</name>
<desc>1=enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0.</desc>
<sw_param offset="0xf8006190" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_64_reg_phy_cmd_latency">
<name>reg_phy_cmd_latency</name>
<desc>If set to 1, command comes to phy_ctrl through a flop.</desc>
<sw_param offset="0xf8006190" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_64_reg_phy_lpddr">
<name>reg_phy_lpddr</name>
<desc>1= mobile/LPDDR DRAM device in use. 0=non-LPDDR DRAM device in use.</desc>
<sw_param offset="0xf8006190" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_64_reg_phy_use_rank0_delays">
<name>reg_phy_use_rank0_delays</name>
<desc>Delay selection 1- Rank 0 delays are used for all ranks 0- Each Rank uses its own delay</desc>
<sw_param offset="0xf8006190" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_64_reg_phy_ctrl_slave_delay">
<name>reg_phy_ctrl_slave_delay</name>
<desc>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18].</desc>
<sw_param offset="0xf8006190" start="27" end="21" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_64_reg_phy_ctrl_slave_force">
<name>reg_phy_ctrl_slave_force</name>
<desc>1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.</desc>
<sw_param offset="0xf8006190" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_64_reg_phy_ctrl_slave_ratio">
<name>reg_phy_ctrl_slave_ratio</name>
<desc>Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</desc>
<sw_param offset="0xf8006190" start="19" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_64_reg_phy_sel_logic">
<name>reg_phy_sel_logic</name>
<desc>Selects one of the two read leveling algorithms.'b0 = Select algorithm # 1'b1 = Select algorithm # 2
Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms</desc>
<sw_param offset="0xf8006190" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_64_reg_phy_all_dq_mpr_rd_resp">
<name>reg_phy_all_dq_mpr_rd_resp</name>
<desc>1=assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.)
0=(default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.)</desc>
<sw_param offset="0xf8006190" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_64_reg_phy_invert_clkout">
<name>reg_phy_invert_clkout</name>
<desc>Inverts the polarity of DRAM clock.
0: core clock is passed on to DRAM
1: inverted core clock is passed on to DRAM.
Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling.</desc>
<sw_param offset="0xf8006190" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_64_reg_phy_bist_mode">
<name>reg_phy_bist_mode</name>
<desc>The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled.
2'b00: constant pattern (0 repeated on each DQ bit)
2'b01: low freq pattern (00001111 repeated on each DQ bit)
2'b10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested</desc>
<sw_param offset="0xf8006190" start="6" end="5" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_64_reg_phy_bist_force_err">
<name>reg_phy_bist_force_err</name>
<desc>This register bit is used to check that BIST checker is not giving false pass.
When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error.</desc>
<sw_param offset="0xf8006190" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_64_reg_phy_bist_enable">
<name>reg_phy_bist_enable</name>
<desc>Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker.
In order to run BIST tests, this port must be set along with reg_phy_loopback.</desc>
<sw_param offset="0xf8006190" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_64_reg_phy_at_spd_atpg">
<name>reg_phy_at_spd_atpg</name>
<desc>1 = run scan test at full clock speed but with less coverage
0 = run scan test at slow clock speed but with high coverage
During normal function mode, this port must be set 0.</desc>
<sw_param offset="0xf8006190" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_64_reg_phy_bl2">
<name>reg_phy_bl2</name>
<desc>Reserved for future Use.</desc>
<sw_param offset="0xf8006190" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_64_reg_phy_loopback">
<name>reg_phy_loopback</name>
<desc>Loopback testing. 1: enable, 0: disable</desc>
<sw_param offset="0xf8006190" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_65_reg_phy_ctrl_slave_delay">
<name>reg_phy_ctrl_slave_delay</name>
<desc>If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value</desc>
<sw_param offset="0xf8006194" start="19" end="18" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_65_reg_phy_dis_calib_rst">
<name>reg_phy_dis_calib_rst</name>
<desc>Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data.
Note: dll_calib is
(i) generated by dfi_ctrl_upd_req or
(ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or
(iii) periodically throughout the leveling process.
dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs</desc>
<sw_param offset="0xf8006194" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_65_reg_phy_use_rd_data_eye_level">
<name>reg_phy_use_rd_data_eye_level</name>
<desc>Read Data Eye training control.
0: Use register programmed ratio values
1: Use ratio for delay line calculated by data eye leveling
Note: This is a Synchronous dynamic signal that requires timing closure</desc>
<sw_param offset="0xf8006194" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_65_reg_phy_use_rd_dqs_gate_level">
<name>reg_phy_use_rd_dqs_gate_level</name>
<desc>Read DQS Gate training control.
0: Use register programmed ratio values
1: Use ratio for delay line calculated by DQS gate leveling
Note: This is a Synchronous dynamic signal that requires timing closure.</desc>
<sw_param offset="0xf8006194" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_65_reg_phy_use_wr_level">
<name>reg_phy_use_wr_level</name>
<desc>Write Leveling training control.
0: Use register programmed ratio values
1: Use ratio for delay line calculated by write leveling
Note: This is a Synchronous dynamic signal that requires timing closure.</desc>
<sw_param offset="0xf8006194" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_65_reg_phy_dll_lock_diff">
<name>reg_phy_dll_lock_diff</name>
<desc>The Maximum number of delay line taps variation allowed while maintaining the master DLL lock.
When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted</desc>
<sw_param offset="0xf8006194" start="13" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_65_reg_phy_rd_rl_delay">
<name>reg_phy_rd_rl_delay</name>
<desc>This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface.
The programmed value must be (Read Latency - 3) with a minimum value of 1.</desc>
<sw_param offset="0xf8006194" start="9" end="5" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg_65_reg_phy_wr_rl_delay">
<name>reg_phy_wr_rl_delay</name>
<desc>This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface.
The programmed value must be (Write Latency - 4) with a minimum value of 1.</desc>
<sw_param offset="0xf8006194" start="4" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg69_6c0_phy_reg_status_fifo_we_slave_dll_value">
<name>phy_reg_status_fifo_we_slave_dll_value</name>
<desc>Delay value applied to FIFO WE slave DLL.</desc>
<sw_param offset="0xf80061a4" start="28" end="20" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg69_6c0_phy_reg_rdlvl_fifowein_ratio">
<name>phy_reg_rdlvl_fifowein_ratio</name>
<desc>Ratio value generated by Read Gate training FSM.</desc>
<sw_param offset="0xf80061a4" start="19" end="9" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg69_6c0_phy_reg_bist_err">
<name>phy_reg_bist_err</name>
<desc>Mismatch error flag from the BIST Checker. 1 bit per data slice. 1'b1: Pattern mismatch error 1'b0: All patterns matched This is a sticky flag. In order to clear this bit, port reg_phy_bist_err_clr must be set HIGH.</desc>
<sw_param offset="0xf80061a4" start="8" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg69_6c1_phy_reg_status_fifo_we_slave_dll_value">
<name>phy_reg_status_fifo_we_slave_dll_value</name>
<desc>Delay value applied to FIFO WE slave DLL.</desc>
<sw_param offset="0xf80061a8" start="28" end="20" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg69_6c1_phy_reg_rdlvl_fifowein_ratio">
<name>phy_reg_rdlvl_fifowein_ratio</name>
<desc>Ratio value generated by Read Gate training FSM.</desc>
<sw_param offset="0xf80061a8" start="19" end="9" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg69_6c1_phy_reg_bist_err">
<name>phy_reg_bist_err</name>
<desc>Mismatch error flag from the BIST Checker. 1 bit per data slice. 1'b1: Pattern mismatch error 1'b0: All patterns matched This is a sticky flag. In order to clear this bit, port reg_phy_bist_err_clr must be set HIGH.</desc>
<sw_param offset="0xf80061a8" start="8" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg69_6c2_phy_reg_status_fifo_we_slave_dll_value">
<name>phy_reg_status_fifo_we_slave_dll_value</name>
<desc>Delay value applied to FIFO WE slave DLL.</desc>
<sw_param offset="0xf80061ac" start="28" end="20" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg69_6c2_phy_reg_rdlvl_fifowein_ratio">
<name>phy_reg_rdlvl_fifowein_ratio</name>
<desc>Ratio value generated by Read Gate training FSM.</desc>
<sw_param offset="0xf80061ac" start="19" end="9" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg69_6c2_phy_reg_bist_err">
<name>phy_reg_bist_err</name>
<desc>Mismatch error flag from the BIST Checker. 1 bit per data slice. 1'b1: Pattern mismatch error 1'b0: All patterns matched This is a sticky flag. In order to clear this bit, port reg_phy_bist_err_clr must be set HIGH.</desc>
<sw_param offset="0xf80061ac" start="8" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg69_6c3_phy_reg_status_fifo_we_slave_dll_value">
<name>phy_reg_status_fifo_we_slave_dll_value</name>
<desc>Delay value applied to FIFO WE slave DLL.</desc>
<sw_param offset="0xf80061b0" start="28" end="20" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg69_6c3_phy_reg_rdlvl_fifowein_ratio">
<name>phy_reg_rdlvl_fifowein_ratio</name>
<desc>Ratio value generated by Read Gate training FSM.</desc>
<sw_param offset="0xf80061b0" start="19" end="9" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg69_6c3_phy_reg_bist_err">
<name>phy_reg_bist_err</name>
<desc>Mismatch error flag from the BIST Checker. 1 bit per data slice. 1'b1: Pattern mismatch error 1'b0: All patterns matched This is a sticky flag. In order to clear this bit, port reg_phy_bist_err_clr must be set HIGH.</desc>
<sw_param offset="0xf80061b0" start="8" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg6e_710_phy_reg_rdlvl_dqs_ratio">
<name>phy_reg_rdlvl_dqs_ratio</name>
<desc>Ratio value generated by Read Data Eye training FSM.</desc>
<sw_param offset="0xf80061b8" start="29" end="20" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg6e_710_phy_reg_wrlvl_dq_ratio">
<name>phy_reg_wrlvl_dq_ratio</name>
<desc>Ratio value generated by the write leveling FSM for Write Data.</desc>
<sw_param offset="0xf80061b8" start="19" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg6e_710_phy_reg_wrlvl_dqs_ratio">
<name>phy_reg_wrlvl_dqs_ratio</name>
<desc>Ratio value generated by the write leveling FSM for Write DQS.</desc>
<sw_param offset="0xf80061b8" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg6e_711_phy_reg_rdlvl_dqs_ratio">
<name>phy_reg_rdlvl_dqs_ratio</name>
<desc>Ratio value generated by Read Data Eye training FSM.</desc>
<sw_param offset="0xf80061bc" start="29" end="20" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg6e_711_phy_reg_wrlvl_dq_ratio">
<name>phy_reg_wrlvl_dq_ratio</name>
<desc>Ratio value generated by the write leveling FSM for Write Data.</desc>
<sw_param offset="0xf80061bc" start="19" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg6e_711_phy_reg_wrlvl_dqs_ratio">
<name>phy_reg_wrlvl_dqs_ratio</name>
<desc>Ratio value generated by the write leveling FSM for Write DQS.</desc>
<sw_param offset="0xf80061bc" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg6e_712_phy_reg_rdlvl_dqs_ratio">
<name>phy_reg_rdlvl_dqs_ratio</name>
<desc>Ratio value generated by Read Data Eye training FSM.</desc>
<sw_param offset="0xf80061c0" start="29" end="20" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg6e_712_phy_reg_wrlvl_dq_ratio">
<name>phy_reg_wrlvl_dq_ratio</name>
<desc>Ratio value generated by the write leveling FSM for Write Data.</desc>
<sw_param offset="0xf80061c0" start="19" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg6e_712_phy_reg_wrlvl_dqs_ratio">
<name>phy_reg_wrlvl_dqs_ratio</name>
<desc>Ratio value generated by the write leveling FSM for Write DQS.</desc>
<sw_param offset="0xf80061c0" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg6e_713_phy_reg_rdlvl_dqs_ratio">
<name>phy_reg_rdlvl_dqs_ratio</name>
<desc>Ratio value generated by Read Data Eye training FSM.</desc>
<sw_param offset="0xf80061c4" start="29" end="20" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg6e_713_phy_reg_wrlvl_dq_ratio">
<name>phy_reg_wrlvl_dq_ratio</name>
<desc>Ratio value generated by the write leveling FSM for Write Data.</desc>
<sw_param offset="0xf80061c4" start="19" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_reg6e_713_phy_reg_wrlvl_dqs_ratio">
<name>phy_reg_wrlvl_dqs_ratio</name>
<desc>Ratio value generated by the write leveling FSM for Write DQS.</desc>
<sw_param offset="0xf80061c4" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_dll_sts0_phy_reg_status_wr_dqs_slave_dll_value">
<name>phy_reg_status_wr_dqs_slave_dll_value</name>
<desc>Delay value applied to write DQS slave DLL</desc>
<sw_param offset="0xf80061cc" start="26" end="18" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_dll_sts0_phy_reg_status_wr_data_slave_dll_value">
<name>phy_reg_status_wr_data_slave_dll_value</name>
<desc>Delay value applied to write data slave DLL</desc>
<sw_param offset="0xf80061cc" start="17" end="9" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_dll_sts0_phy_reg_status_rd_dqs_slave_dll_value">
<name>phy_reg_status_rd_dqs_slave_dll_value</name>
<desc>Delay value applied to read data slave DLL</desc>
<sw_param offset="0xf80061cc" start="8" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_dll_sts1_phy_reg_status_wr_dqs_slave_dll_value">
<name>phy_reg_status_wr_dqs_slave_dll_value</name>
<desc>Delay value applied to write DQS slave DLL</desc>
<sw_param offset="0xf80061d0" start="26" end="18" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_dll_sts1_phy_reg_status_wr_data_slave_dll_value">
<name>phy_reg_status_wr_data_slave_dll_value</name>
<desc>Delay value applied to write data slave DLL</desc>
<sw_param offset="0xf80061d0" start="17" end="9" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_dll_sts1_phy_reg_status_rd_dqs_slave_dll_value">
<name>phy_reg_status_rd_dqs_slave_dll_value</name>
<desc>Delay value applied to read data slave DLL</desc>
<sw_param offset="0xf80061d0" start="8" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_dll_sts2_phy_reg_status_wr_dqs_slave_dll_value">
<name>phy_reg_status_wr_dqs_slave_dll_value</name>
<desc>Delay value applied to write DQS slave DLL</desc>
<sw_param offset="0xf80061d4" start="26" end="18" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_dll_sts2_phy_reg_status_wr_data_slave_dll_value">
<name>phy_reg_status_wr_data_slave_dll_value</name>
<desc>Delay value applied to write data slave DLL</desc>
<sw_param offset="0xf80061d4" start="17" end="9" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_dll_sts2_phy_reg_status_rd_dqs_slave_dll_value">
<name>phy_reg_status_rd_dqs_slave_dll_value</name>
<desc>Delay value applied to read data slave DLL</desc>
<sw_param offset="0xf80061d4" start="8" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_dll_sts3_phy_reg_status_wr_dqs_slave_dll_value">
<name>phy_reg_status_wr_dqs_slave_dll_value</name>
<desc>Delay value applied to write DQS slave DLL</desc>
<sw_param offset="0xf80061d8" start="26" end="18" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_dll_sts3_phy_reg_status_wr_data_slave_dll_value">
<name>phy_reg_status_wr_data_slave_dll_value</name>
<desc>Delay value applied to write data slave DLL</desc>
<sw_param offset="0xf80061d8" start="17" end="9" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_dll_sts3_phy_reg_status_rd_dqs_slave_dll_value">
<name>phy_reg_status_rd_dqs_slave_dll_value</name>
<desc>Delay value applied to read data slave DLL</desc>
<sw_param offset="0xf80061d8" start="8" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_dll_lock_sts_phy_reg_status_of_in_lock_state">
<name>phy_reg_status_of_in_lock_state</name>
<desc>Lock status from the Output Filter module inside the Master DLL. Bit[0] - Fine delay line lock status. 1: locked, 0: unlocked. Bit[1] - Coarse delay line lock status. 1: locked, 0: unlocked.</desc>
<sw_param offset="0xf80061e0" start="11" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_dll_lock_sts_phy_reg_status_dll_slave_value">
<name>phy_reg_status_dll_slave_value</name>
<desc>Shows the current Coarse and Fine delay values going to all the Slave DLLs [1:0] - Fine value [8:2] - Coarse value</desc>
<sw_param offset="0xf80061e0" start="9" end="1" />
</parameter>
<parameter uniqueid="ps7_ddrc_dll_lock_sts_phy_reg_status_dll_lock">
<name>phy_reg_status_dll_lock</name>
<desc>Status signal: 1 - Master DLL is locked 0 - Master DLL is not locked</desc>
<sw_param offset="0xf80061e0" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_ctrl_sts_phy_reg_status_phy_ctrl_of_in_lock_state">
<name>phy_reg_status_phy_ctrl_of_in_lock_state</name>
<desc>Lock status from the Output Filter module inside the PHY_CTRL Master DLL. Bit[0] - Fine delay line lock status. 1: locked, 0: unlocked. Bit[1] - Coarse delay line lock status. 1: locked, 0: unlocked.</desc>
<sw_param offset="0xf80061e4" start="29" end="28" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_ctrl_sts_phy_reg_status_phy_ctrl_dll_slave_value">
<name>phy_reg_status_phy_ctrl_dll_slave_value</name>
<desc>Shows the current Coarse and Fine delay value going to the PHY_CTRL Slave DLL [1:0] - Fine value [8:2] - Coarse value</desc>
<sw_param offset="0xf80061e4" start="27" end="20" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_ctrl_sts_phy_reg_status_phy_ctrl_dll_lock">
<name>phy_reg_status_phy_ctrl_dll_lock</name>
<desc>PHY_CTRL Master DLL Status signal: 1 - Master DLL is locked 0 - Master DLL is not locked</desc>
<sw_param offset="0xf80061e4" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_ctrl_sts_phy_reg_status_of_out_delay_value">
<name>phy_reg_status_of_out_delay_value</name>
<desc>The Coarse and Fine values coming out of the Output Filter in Master DLL. \'7bcoarse[6:0],fine[1:0]\'7d Note: No default value recommended for this register.</desc>
<sw_param offset="0xf80061e4" start="18" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_ctrl_sts_phy_reg_status_of_in_delay_value">
<name>phy_reg_status_of_in_delay_value</name>
<desc>The Coarse and Fine values going into the Output Filter in Master DLL. \'7bcoarse[6:0],fine[1:0]\'7d
Note: No default value recommended for this register.</desc>
<sw_param offset="0xf80061e4" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_ctrl_sts_reg2_phy_reg_status_phy_ctrl_slave_dll_value">
<name>phy_reg_status_phy_ctrl_slave_dll_value</name>
<desc>Delay value applied to read DQS slave DLL.</desc>
<sw_param offset="0xf80061e8" start="26" end="18" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_ctrl_sts_reg2_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf80061e8" start="17" end="9" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_ctrl_sts_reg2_phy_reg_status_phy_ctrl_of_in_delay_value">
<name>phy_reg_status_phy_ctrl_of_in_delay_value</name>
<desc>The Coarse and Fine values going into the Output Filter in PHY_CTRL Master DLL. \'7bcoarse[6:0],fine[1:0]\'7d</desc>
<sw_param offset="0xf80061e8" start="8" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_id_reg_arb_rev_num">
<name>reg_arb_rev_num</name>
<desc>Revision Number</desc>
<sw_param offset="0xf8006200" start="25" end="20" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_id_reg_arb_prov_num">
<name>reg_arb_prov_num</name>
<desc>Prov number</desc>
<sw_param offset="0xf8006200" start="19" end="12" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_id_reg_arb_part_num">
<name>reg_arb_part_num</name>
<desc>Part Number</desc>
<sw_param offset="0xf8006200" start="11" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_page_mask_reg_arb_page_addr_mask">
<name>reg_arb_page_addr_mask</name>
<desc>This register must be set based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1.
This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address.
Setting this value to 0 disables transaction prioritization based on page/bank match.</desc>
<sw_param offset="0xf8006204" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_wr_port0_reg_arb_dis_rmw_portn">
<name>reg_arb_dis_rmw_portn</name>
<desc>FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.</desc>
<sw_param offset="0xf8006208" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_wr_port0_reg_arb_dis_page_match_wr_portn">
<name>reg_arb_dis_page_match_wr_portn</name>
<desc>Disable the page match feature.</desc>
<sw_param offset="0xf8006208" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_wr_port0_reg_arb_disable_urgent_wr_portn">
<name>reg_arb_disable_urgent_wr_portn</name>
<desc>Disable urgent for this Write Port.</desc>
<sw_param offset="0xf8006208" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_wr_port0_reg_arb_disable_aging_wr_portn">
<name>reg_arb_disable_aging_wr_portn</name>
<desc>Disable aging for this Write Port.</desc>
<sw_param offset="0xf8006208" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_wr_port0_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006208" start="15" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_wr_port0_reg_arb_pri_wr_portn">
<name>reg_arb_pri_wr_portn</name>
<desc>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</desc>
<sw_param offset="0xf8006208" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_wr_port1_reg_arb_dis_rmw_portn">
<name>reg_arb_dis_rmw_portn</name>
<desc>FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.</desc>
<sw_param offset="0xf800620c" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_wr_port1_reg_arb_dis_page_match_wr_portn">
<name>reg_arb_dis_page_match_wr_portn</name>
<desc>Disable the page match feature.</desc>
<sw_param offset="0xf800620c" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_wr_port1_reg_arb_disable_urgent_wr_portn">
<name>reg_arb_disable_urgent_wr_portn</name>
<desc>Disable urgent for this Write Port.</desc>
<sw_param offset="0xf800620c" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_wr_port1_reg_arb_disable_aging_wr_portn">
<name>reg_arb_disable_aging_wr_portn</name>
<desc>Disable aging for this Write Port.</desc>
<sw_param offset="0xf800620c" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_wr_port1_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf800620c" start="15" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_wr_port1_reg_arb_pri_wr_portn">
<name>reg_arb_pri_wr_portn</name>
<desc>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</desc>
<sw_param offset="0xf800620c" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_wr_port2_reg_arb_dis_rmw_portn">
<name>reg_arb_dis_rmw_portn</name>
<desc>FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.</desc>
<sw_param offset="0xf8006210" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_wr_port2_reg_arb_dis_page_match_wr_portn">
<name>reg_arb_dis_page_match_wr_portn</name>
<desc>Disable the page match feature.</desc>
<sw_param offset="0xf8006210" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_wr_port2_reg_arb_disable_urgent_wr_portn">
<name>reg_arb_disable_urgent_wr_portn</name>
<desc>Disable urgent for this Write Port.</desc>
<sw_param offset="0xf8006210" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_wr_port2_reg_arb_disable_aging_wr_portn">
<name>reg_arb_disable_aging_wr_portn</name>
<desc>Disable aging for this Write Port.</desc>
<sw_param offset="0xf8006210" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_wr_port2_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006210" start="15" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_wr_port2_reg_arb_pri_wr_portn">
<name>reg_arb_pri_wr_portn</name>
<desc>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</desc>
<sw_param offset="0xf8006210" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_wr_port3_reg_arb_dis_rmw_portn">
<name>reg_arb_dis_rmw_portn</name>
<desc>FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.</desc>
<sw_param offset="0xf8006214" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_wr_port3_reg_arb_dis_page_match_wr_portn">
<name>reg_arb_dis_page_match_wr_portn</name>
<desc>Disable the page match feature.</desc>
<sw_param offset="0xf8006214" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_wr_port3_reg_arb_disable_urgent_wr_portn">
<name>reg_arb_disable_urgent_wr_portn</name>
<desc>Disable urgent for this Write Port.</desc>
<sw_param offset="0xf8006214" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_wr_port3_reg_arb_disable_aging_wr_portn">
<name>reg_arb_disable_aging_wr_portn</name>
<desc>Disable aging for this Write Port.</desc>
<sw_param offset="0xf8006214" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_wr_port3_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006214" start="15" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_wr_port3_reg_arb_pri_wr_portn">
<name>reg_arb_pri_wr_portn</name>
<desc>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</desc>
<sw_param offset="0xf8006214" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_rd_port0_reg_arb_set_hpr_rd_portn">
<name>reg_arb_set_hpr_rd_portn</name>
<desc>Enable reads to be generated as HPR for this Read Port.</desc>
<sw_param offset="0xf8006218" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_rd_port0_reg_arb_dis_page_match_rd_portn">
<name>reg_arb_dis_page_match_rd_portn</name>
<desc>Disable the page match feature.</desc>
<sw_param offset="0xf8006218" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_rd_port0_reg_arb_disable_urgent_rd_portn">
<name>reg_arb_disable_urgent_rd_portn</name>
<desc>Disable urgent for this Read Port.</desc>
<sw_param offset="0xf8006218" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_rd_port0_reg_arb_disable_aging_rd_portn">
<name>reg_arb_disable_aging_rd_portn</name>
<desc>Disable aging for this Read Port.</desc>
<sw_param offset="0xf8006218" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_rd_port0_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006218" start="15" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_rd_port0_reg_arb_pri_rd_portn">
<name>reg_arb_pri_rd_portn</name>
<desc>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</desc>
<sw_param offset="0xf8006218" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_rd_port1_reg_arb_set_hpr_rd_portn">
<name>reg_arb_set_hpr_rd_portn</name>
<desc>Enable reads to be generated as HPR for this Read Port.</desc>
<sw_param offset="0xf800621c" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_rd_port1_reg_arb_dis_page_match_rd_portn">
<name>reg_arb_dis_page_match_rd_portn</name>
<desc>Disable the page match feature.</desc>
<sw_param offset="0xf800621c" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_rd_port1_reg_arb_disable_urgent_rd_portn">
<name>reg_arb_disable_urgent_rd_portn</name>
<desc>Disable urgent for this Read Port.</desc>
<sw_param offset="0xf800621c" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_rd_port1_reg_arb_disable_aging_rd_portn">
<name>reg_arb_disable_aging_rd_portn</name>
<desc>Disable aging for this Read Port.</desc>
<sw_param offset="0xf800621c" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_rd_port1_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf800621c" start="15" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_rd_port1_reg_arb_pri_rd_portn">
<name>reg_arb_pri_rd_portn</name>
<desc>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</desc>
<sw_param offset="0xf800621c" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_rd_port2_reg_arb_set_hpr_rd_portn">
<name>reg_arb_set_hpr_rd_portn</name>
<desc>Enable reads to be generated as HPR for this Read Port.</desc>
<sw_param offset="0xf8006220" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_rd_port2_reg_arb_dis_page_match_rd_portn">
<name>reg_arb_dis_page_match_rd_portn</name>
<desc>Disable the page match feature.</desc>
<sw_param offset="0xf8006220" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_rd_port2_reg_arb_disable_urgent_rd_portn">
<name>reg_arb_disable_urgent_rd_portn</name>
<desc>Disable urgent for this Read Port.</desc>
<sw_param offset="0xf8006220" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_rd_port2_reg_arb_disable_aging_rd_portn">
<name>reg_arb_disable_aging_rd_portn</name>
<desc>Disable aging for this Read Port.</desc>
<sw_param offset="0xf8006220" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_rd_port2_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006220" start="15" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_rd_port2_reg_arb_pri_rd_portn">
<name>reg_arb_pri_rd_portn</name>
<desc>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</desc>
<sw_param offset="0xf8006220" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_rd_port3_reg_arb_set_hpr_rd_portn">
<name>reg_arb_set_hpr_rd_portn</name>
<desc>Enable reads to be generated as HPR for this Read Port.</desc>
<sw_param offset="0xf8006224" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_rd_port3_reg_arb_dis_page_match_rd_portn">
<name>reg_arb_dis_page_match_rd_portn</name>
<desc>Disable the page match feature.</desc>
<sw_param offset="0xf8006224" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_rd_port3_reg_arb_disable_urgent_rd_portn">
<name>reg_arb_disable_urgent_rd_portn</name>
<desc>Disable urgent for this Read Port.</desc>
<sw_param offset="0xf8006224" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_rd_port3_reg_arb_disable_aging_rd_portn">
<name>reg_arb_disable_aging_rd_portn</name>
<desc>Disable aging for this Read Port.</desc>
<sw_param offset="0xf8006224" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_rd_port3_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006224" start="15" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_axi_priority_rd_port3_reg_arb_pri_rd_portn">
<name>reg_arb_pri_rd_portn</name>
<desc>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</desc>
<sw_param offset="0xf8006224" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_AHB_priority_cfg0_reg_arb_set_hpr_ahb_portn">
<name>reg_arb_set_hpr_ahb_portn</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006248" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_ddrc_AHB_priority_cfg0_reg_arb_dis_page_match_ahb_portn">
<name>reg_arb_dis_page_match_ahb_portn</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006248" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_ddrc_AHB_priority_cfg0_reg_arb_disable_urgent_ahb_portn">
<name>reg_arb_disable_urgent_ahb_portn</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006248" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_ddrc_AHB_priority_cfg0_reg_arb_disable_aging_ahb_portn">
<name>reg_arb_disable_aging_ahb_portn</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006248" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_AHB_priority_cfg0_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006248" start="15" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_AHB_priority_cfg0_reg_arb_pri_ahb_portn">
<name>reg_arb_pri_ahb_portn</name>
<desc>Unused</desc>
<sw_param offset="0xf8006248" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_AHB_priority_cfg1_reg_arb_set_hpr_ahb_portn">
<name>reg_arb_set_hpr_ahb_portn</name>
<desc>Reserved</desc>
<sw_param offset="0xf800624c" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_ddrc_AHB_priority_cfg1_reg_arb_dis_page_match_ahb_portn">
<name>reg_arb_dis_page_match_ahb_portn</name>
<desc>Reserved</desc>
<sw_param offset="0xf800624c" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_ddrc_AHB_priority_cfg1_reg_arb_disable_urgent_ahb_portn">
<name>reg_arb_disable_urgent_ahb_portn</name>
<desc>Reserved</desc>
<sw_param offset="0xf800624c" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_ddrc_AHB_priority_cfg1_reg_arb_disable_aging_ahb_portn">
<name>reg_arb_disable_aging_ahb_portn</name>
<desc>Reserved</desc>
<sw_param offset="0xf800624c" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_AHB_priority_cfg1_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf800624c" start="15" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_AHB_priority_cfg1_reg_arb_pri_ahb_portn">
<name>reg_arb_pri_ahb_portn</name>
<desc>Unused</desc>
<sw_param offset="0xf800624c" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_AHB_priority_cfg2_reg_arb_set_hpr_ahb_portn">
<name>reg_arb_set_hpr_ahb_portn</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006250" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_ddrc_AHB_priority_cfg2_reg_arb_dis_page_match_ahb_portn">
<name>reg_arb_dis_page_match_ahb_portn</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006250" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_ddrc_AHB_priority_cfg2_reg_arb_disable_urgent_ahb_portn">
<name>reg_arb_disable_urgent_ahb_portn</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006250" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_ddrc_AHB_priority_cfg2_reg_arb_disable_aging_ahb_portn">
<name>reg_arb_disable_aging_ahb_portn</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006250" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_AHB_priority_cfg2_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006250" start="15" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_AHB_priority_cfg2_reg_arb_pri_ahb_portn">
<name>reg_arb_pri_ahb_portn</name>
<desc>Unused</desc>
<sw_param offset="0xf8006250" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_AHB_priority_cfg3_reg_arb_set_hpr_ahb_portn">
<name>reg_arb_set_hpr_ahb_portn</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006254" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_ddrc_AHB_priority_cfg3_reg_arb_dis_page_match_ahb_portn">
<name>reg_arb_dis_page_match_ahb_portn</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006254" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_ddrc_AHB_priority_cfg3_reg_arb_disable_urgent_ahb_portn">
<name>reg_arb_disable_urgent_ahb_portn</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006254" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_ddrc_AHB_priority_cfg3_reg_arb_disable_aging_ahb_portn">
<name>reg_arb_disable_aging_ahb_portn</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006254" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_AHB_priority_cfg3_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006254" start="15" end="10" />
</parameter>
<parameter uniqueid="ps7_ddrc_AHB_priority_cfg3_reg_arb_pri_ahb_portn">
<name>reg_arb_pri_ahb_portn</name>
<desc>Unused</desc>
<sw_param offset="0xf8006254" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_perf_mon0_reg_max_read_latency_portn">
<name>reg_max_read_latency_portn</name>
<desc>Measured Maximum Read latency.</desc>
<sw_param offset="0xf8006260" start="30" end="20" />
</parameter>
<parameter uniqueid="ps7_ddrc_perf_mon0_reg_min_read_latency_portn">
<name>reg_min_read_latency_portn</name>
<desc>Measured Minimum Read latency.</desc>
<sw_param offset="0xf8006260" start="19" end="9" />
</parameter>
<parameter uniqueid="ps7_ddrc_perf_mon0_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006260" start="8" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_perf_mon1_reg_max_read_latency_portn">
<name>reg_max_read_latency_portn</name>
<desc>Measured Maximum Read latency.</desc>
<sw_param offset="0xf8006264" start="30" end="20" />
</parameter>
<parameter uniqueid="ps7_ddrc_perf_mon1_reg_min_read_latency_portn">
<name>reg_min_read_latency_portn</name>
<desc>Measured Minimum Read latency.</desc>
<sw_param offset="0xf8006264" start="19" end="9" />
</parameter>
<parameter uniqueid="ps7_ddrc_perf_mon1_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006264" start="8" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_perf_mon2_reg_max_read_latency_portn">
<name>reg_max_read_latency_portn</name>
<desc>Measured Maximum Read latency.</desc>
<sw_param offset="0xf8006268" start="30" end="20" />
</parameter>
<parameter uniqueid="ps7_ddrc_perf_mon2_reg_min_read_latency_portn">
<name>reg_min_read_latency_portn</name>
<desc>Measured Minimum Read latency.</desc>
<sw_param offset="0xf8006268" start="19" end="9" />
</parameter>
<parameter uniqueid="ps7_ddrc_perf_mon2_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006268" start="8" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_perf_mon3_reg_max_read_latency_portn">
<name>reg_max_read_latency_portn</name>
<desc>Measured Maximum Read latency.</desc>
<sw_param offset="0xf800626c" start="30" end="20" />
</parameter>
<parameter uniqueid="ps7_ddrc_perf_mon3_reg_min_read_latency_portn">
<name>reg_min_read_latency_portn</name>
<desc>Measured Minimum Read latency.</desc>
<sw_param offset="0xf800626c" start="19" end="9" />
</parameter>
<parameter uniqueid="ps7_ddrc_perf_mon3_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf800626c" start="8" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_perf_mon20_reg_measure_axi_id_portn">
<name>reg_measure_axi_id_portn</name>
<desc>Performance measurements done on this programmable 15-bit AXI ID.</desc>
<sw_param offset="0xf8006270" start="31" end="17" />
</parameter>
<parameter uniqueid="ps7_ddrc_perf_mon20_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006270" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_perf_mon20_reg_num_words_wr_portn">
<name>reg_num_words_wr_portn</name>
<desc>Counter reflects the number of write transactions for the write AXI ID mentioned in register 'reg_measure_axi_id'.</desc>
<sw_param offset="0xf8006270" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_perf_mon21_reg_measure_axi_id_portn">
<name>reg_measure_axi_id_portn</name>
<desc>Performance measurements done on this programmable 15-bit AXI ID.</desc>
<sw_param offset="0xf8006274" start="31" end="17" />
</parameter>
<parameter uniqueid="ps7_ddrc_perf_mon21_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006274" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_perf_mon21_reg_num_words_wr_portn">
<name>reg_num_words_wr_portn</name>
<desc>Counter reflects the number of write transactions for the write AXI ID mentioned in register 'reg_measure_axi_id'.</desc>
<sw_param offset="0xf8006274" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_perf_mon22_reg_measure_axi_id_portn">
<name>reg_measure_axi_id_portn</name>
<desc>Performance measurements done on this programmable 15-bit AXI ID.</desc>
<sw_param offset="0xf8006278" start="31" end="17" />
</parameter>
<parameter uniqueid="ps7_ddrc_perf_mon22_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006278" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_perf_mon22_reg_num_words_wr_portn">
<name>reg_num_words_wr_portn</name>
<desc>Counter reflects the number of write transactions for the write AXI ID mentioned in register 'reg_measure_axi_id'.</desc>
<sw_param offset="0xf8006278" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_perf_mon23_reg_measure_axi_id_portn">
<name>reg_measure_axi_id_portn</name>
<desc>Performance measurements done on this programmable 15-bit AXI ID.</desc>
<sw_param offset="0xf800627c" start="31" end="17" />
</parameter>
<parameter uniqueid="ps7_ddrc_perf_mon23_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf800627c" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_ddrc_perf_mon23_reg_num_words_wr_portn">
<name>reg_num_words_wr_portn</name>
<desc>Counter reflects the number of write transactions for the write AXI ID mentioned in register 'reg_measure_axi_id'.</desc>
<sw_param offset="0xf800627c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_perf_mon30_reg_num_words_rd_portn">
<name>reg_num_words_rd_portn</name>
<desc>Counter reflects the number of read transactions for the read AXI ID mentioned in register 'reg_measure_axi_id'</desc>
<sw_param offset="0xf8006280" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_perf_mon31_reg_num_words_rd_portn">
<name>reg_num_words_rd_portn</name>
<desc>Counter reflects the number of read transactions for the read AXI ID mentioned in register 'reg_measure_axi_id'</desc>
<sw_param offset="0xf8006284" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_perf_mon32_reg_num_words_rd_portn">
<name>reg_num_words_rd_portn</name>
<desc>Counter reflects the number of read transactions for the read AXI ID mentioned in register 'reg_measure_axi_id'</desc>
<sw_param offset="0xf8006288" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_perf_mon33_reg_num_words_rd_portn">
<name>reg_num_words_rd_portn</name>
<desc>Counter reflects the number of read transactions for the read AXI ID mentioned in register 'reg_measure_axi_id'</desc>
<sw_param offset="0xf800628c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_trusted_mem_cfg_reg_decprot">
<name>reg_decprot</name>
<desc>Sets the memory regions to be secure or non-secure. The memory is divided into 64Mb sections. For a 1 Gb part, the number of regions is 16. 0 - non-secure region 1 - secure region Reserved. Not used any more.</desc>
<sw_param offset="0xf8006290" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_excl_access_cfg0_reg_excl_acc_id1_port">
<name>reg_excl_acc_id1_port</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006294" start="17" end="9" />
</parameter>
<parameter uniqueid="ps7_ddrc_excl_access_cfg0_reg_excl_acc_id0_port">
<name>reg_excl_acc_id0_port</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006294" start="8" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_excl_access_cfg1_reg_excl_acc_id1_port">
<name>reg_excl_acc_id1_port</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006298" start="17" end="9" />
</parameter>
<parameter uniqueid="ps7_ddrc_excl_access_cfg1_reg_excl_acc_id0_port">
<name>reg_excl_acc_id0_port</name>
<desc>Reserved</desc>
<sw_param offset="0xf8006298" start="8" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_excl_access_cfg2_reg_excl_acc_id1_port">
<name>reg_excl_acc_id1_port</name>
<desc>Reserved</desc>
<sw_param offset="0xf800629c" start="17" end="9" />
</parameter>
<parameter uniqueid="ps7_ddrc_excl_access_cfg2_reg_excl_acc_id0_port">
<name>reg_excl_acc_id0_port</name>
<desc>Reserved</desc>
<sw_param offset="0xf800629c" start="8" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_excl_access_cfg3_reg_excl_acc_id1_port">
<name>reg_excl_acc_id1_port</name>
<desc>Reserved</desc>
<sw_param offset="0xf80062a0" start="17" end="9" />
</parameter>
<parameter uniqueid="ps7_ddrc_excl_access_cfg3_reg_excl_acc_id0_port">
<name>reg_excl_acc_id0_port</name>
<desc>Reserved</desc>
<sw_param offset="0xf80062a0" start="8" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_mode_reg_read_ddrc_reg_rd_mrr_data">
<name>ddrc_reg_rd_mrr_data</name>
<desc>Mode register read Data. Valid when ddrc_co_rd_mrr_data_valid is high. Bits[7:0] carry the 8-bit MRR value. Valid for LPDDR2 only.</desc>
<sw_param offset="0xf80062a4" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_lpddr_ctrl0_reg_ddrc_mr4_margin">
<name>reg_ddrc_mr4_margin</name>
<desc>UNUSED</desc>
<sw_param offset="0xf80062a8" start="11" end="4" />
</parameter>
<parameter uniqueid="ps7_ddrc_lpddr_ctrl0_reserved">
<name>reserved</name>
<desc>Reserved. Datasheet does not mention this field</desc>
<sw_param offset="0xf80062a8" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_ddrc_lpddr_ctrl0_reg_ddrc_derate_enable">
<name>reg_ddrc_derate_enable</name>
<desc>0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. Present only in designs configured to support LPDDR2.</desc>
<sw_param offset="0xf80062a8" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_ddrc_lpddr_ctrl0_reg_ddrc_per_bank_refresh">
<name>reg_ddrc_per_bank_refresh</name>
<desc>1:Per bank refresh 0:All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported on all LPDDR2 devices. Present only in designs configured to support LPDDR2.</desc>
<sw_param offset="0xf80062a8" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_ddrc_lpddr_ctrl0_reg_ddrc_lpddr2">
<name>reg_ddrc_lpddr2</name>
<desc>1=LPDDR2 DRAM device in Use. 0=non-LPDDR2 device in use Present only in designs configured to support LPDDR2.</desc>
<sw_param offset="0xf80062a8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_lpddr_ctrl1_reg_ddrc_mr4_read_interval">
<name>reg_ddrc_mr4_read_interval</name>
<desc>Interval between two MR4 reads, USED to derate the timing parameters. Present only in designs configured to support LPDDR2.</desc>
<sw_param offset="0xf80062ac" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_lpddr_ctrl2_reg_ddrc_t_mrw">
<name>reg_ddrc_t_mrw</name>
<desc>Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5.</desc>
<sw_param offset="0xf80062b0" start="21" end="12" />
</parameter>
<parameter uniqueid="ps7_ddrc_lpddr_ctrl2_reg_ddrc_idle_after_reset_x32">
<name>reg_ddrc_idle_after_reset_x32</name>
<desc>Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles.</desc>
<sw_param offset="0xf80062b0" start="11" end="4" />
</parameter>
<parameter uniqueid="ps7_ddrc_lpddr_ctrl2_reg_ddrc_min_stable_clock_x1">
<name>reg_ddrc_min_stable_clock_x1</name>
<desc>Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay.</desc>
<sw_param offset="0xf80062b0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_lpddr_ctrl3_reg_ddrc_dev_zqinit_x32">
<name>reg_ddrc_dev_zqinit_x32</name>
<desc>ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us.</desc>
<sw_param offset="0xf80062b4" start="17" end="8" />
</parameter>
<parameter uniqueid="ps7_ddrc_lpddr_ctrl3_reg_ddrc_max_auto_init_x1024">
<name>reg_ddrc_max_auto_init_x1024</name>
<desc>Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us.</desc>
<sw_param offset="0xf80062b4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_wr_lvl_fsm_phy_reg_wr_level_fsm_slice3">
<name>phy_reg_wr_level_fsm_slice3</name>
<desc>Write Leveling State information from Slice 3.</desc>
<sw_param offset="0xf80062b8" start="14" end="12" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_wr_lvl_fsm_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xf80062b8" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_wr_lvl_fsm_phy_reg_wr_level_fsm_slice2">
<name>phy_reg_wr_level_fsm_slice2</name>
<desc>Write Leveling State information from Slice 2.</desc>
<sw_param offset="0xf80062b8" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_wr_lvl_fsm_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xf80062b8" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_wr_lvl_fsm_phy_reg_wr_level_fsm_slice1">
<name>phy_reg_wr_level_fsm_slice1</name>
<desc>Write Leveling State information from Slice 1.</desc>
<sw_param offset="0xf80062b8" start="6" end="4" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_wr_lvl_fsm_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf80062b8" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_wr_lvl_fsm_phy_reg_wr_level_fsm_slice0">
<name>phy_reg_wr_level_fsm_slice0</name>
<desc>Write Leveling State information from Slice 0.</desc>
<sw_param offset="0xf80062b8" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_rd_lvl_fsm_phy_reg_rd_level_fsm_slice3">
<name>phy_reg_rd_level_fsm_slice3</name>
<desc>Read Leveling State information from Slice 3.</desc>
<sw_param offset="0xf80062bc" start="15" end="12" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_rd_lvl_fsm_phy_reg_rd_level_fsm_slice2">
<name>phy_reg_rd_level_fsm_slice2</name>
<desc>Read Leveling State information from Slice 2.</desc>
<sw_param offset="0xf80062bc" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_rd_lvl_fsm_phy_reg_rd_level_fsm_slice1">
<name>phy_reg_rd_level_fsm_slice1</name>
<desc>Read Leveling State information from Slice 1.</desc>
<sw_param offset="0xf80062bc" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_rd_lvl_fsm_phy_reg_rd_level_fsm_slice0">
<name>phy_reg_rd_level_fsm_slice0</name>
<desc>Read Leveling State information from Slice 0.</desc>
<sw_param offset="0xf80062bc" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_gate_lvl_fsm_phy_reg_gate_level_fsm_slice3">
<name>phy_reg_gate_level_fsm_slice3</name>
<desc>Gate Leveling State information from Slice 3.</desc>
<sw_param offset="0xf80062c0" start="14" end="12" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_gate_lvl_fsm_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xf80062c0" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_gate_lvl_fsm_phy_reg_gate_level_fsm_slice2">
<name>phy_reg_gate_level_fsm_slice2</name>
<desc>Gate Leveling State information from Slice 2.</desc>
<sw_param offset="0xf80062c0" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_gate_lvl_fsm_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xf80062c0" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_gate_lvl_fsm_phy_reg_gate_level_fsm_slice1">
<name>phy_reg_gate_level_fsm_slice1</name>
<desc>Gate Leveling State information from Slice 1.</desc>
<sw_param offset="0xf80062c0" start="6" end="4" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_gate_lvl_fsm_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf80062c0" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_ddrc_phy_gate_lvl_fsm_phy_reg_gate_level_fsm_slice0">
<name>phy_reg_gate_level_fsm_slice0</name>
<desc>Gate Leveling State information from Slice 0.</desc>
<sw_param offset="0xf80062c0" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_MASK_DATA_0_LSW_MASK_0_LSW">
<name>MASK_0_LSW</name>
<desc>Mask values to be applied on writes to the corresponding GPIO pins
0 = pin value is updated
1 = pin is masked
Each bit controls the corresponding pin within the 16-bit half-bank
Write Only, Read back as zero</desc>
<sw_param offset="0xe000a000" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gpio_MASK_DATA_0_LSW_DATA_0_LSW">
<name>DATA_0_LSW</name>
<desc>Data values read from or written to the corresponding GPIO pins
Each bit controls the corresponding pin within the 16-bit half-bank Note: Bit[6], bit[7] default value = 0</desc>
<sw_param offset="0xe000a000" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_MASK_DATA_0_MSW_MASK_0_MSW">
<name>MASK_0_MSW</name>
<desc>Mask values to be applied on writes to the corresponding GPIO pins
0 = pin value is updated
1 = pin is masked
Each bit controls the corresponding pin within the 16-bit half-bank
Write Only, Read back as zero</desc>
<sw_param offset="0xe000a004" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gpio_MASK_DATA_0_MSW_DATA_0_MSW">
<name>DATA_0_MSW</name>
<desc>Data values read from or written to the corresponding GPIO pins
Each bit controls the corresponding pin within the 16-bit half-bank</desc>
<sw_param offset="0xe000a004" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_MASK_DATA_1_LSW_MASK_1_LSW">
<name>MASK_1_LSW</name>
<desc>Mask values to be applied on writes to the corresponding GPIO pins
0 = pin value is updated
1 = pin is masked
Each bit controls the corresponding pin within the 16-bit half-bank
Write Only, Read back as zero</desc>
<sw_param offset="0xe000a008" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gpio_MASK_DATA_1_LSW_DATA_1_LSW">
<name>DATA_1_LSW</name>
<desc>Data values read from or written to the corresponding GPIO pins
Each bit controls the corresponding pin within the 16-bit half-bank</desc>
<sw_param offset="0xe000a008" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_MASK_DATA_1_MSW_MASK_1_MSW">
<name>MASK_1_MSW</name>
<desc>Mask values to be applied on writes to the corresponding GPIO pins
0 = pin value is updated
1 = pin is masked
Each bit controls the corresponding pin within the 16-bit half-bank
Write Only, Read back as zero</desc>
<sw_param offset="0xe000a00c" start="21" end="16" />
</parameter>
<parameter uniqueid="ps7_gpio_MASK_DATA_1_MSW_reserved">
<name>reserved</name>
<desc>Not used, read back as zero</desc>
<sw_param offset="0xe000a00c" start="15" end="6" />
</parameter>
<parameter uniqueid="ps7_gpio_MASK_DATA_1_MSW_DATA_1_MSW">
<name>DATA_1_MSW</name>
<desc>Data values read from or written to the corresponding GPIO pins
Each bit controls the corresponding pin within the 16-bit half-bank</desc>
<sw_param offset="0xe000a00c" start="5" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_MASK_DATA_2_LSW_MASK_2_LSW">
<name>MASK_2_LSW</name>
<desc>Mask values to be applied on writes to the corresponding GPIO pins
0 = pin value is updated
1 = pin is masked
Each bit controls the corresponding pin within the 16-bit half-bank
Write Only, Read back as zero</desc>
<sw_param offset="0xe000a010" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gpio_MASK_DATA_2_LSW_DATA_2_LSW">
<name>DATA_2_LSW</name>
<desc>Data values read from or written to the corresponding GPIO pins
Each bit controls the corresponding pin within the 16-bit half-bank</desc>
<sw_param offset="0xe000a010" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_MASK_DATA_2_MSW_MASK_2_MSW">
<name>MASK_2_MSW</name>
<desc>Mask values to be applied on writes to the corresponding GPIO pins
0 = pin value is updated
1 = pin is masked
Each bit controls the corresponding pin within the 16-bit half-bank
Write Only, Read back as zero</desc>
<sw_param offset="0xe000a014" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gpio_MASK_DATA_2_MSW_DATA_2_MSW">
<name>DATA_2_MSW</name>
<desc>Data values read from or written to the corresponding GPIO pins
Each bit controls the corresponding pin within the 16-bit half-bank</desc>
<sw_param offset="0xe000a014" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_MASK_DATA_3_LSW_MASK_3_LSW">
<name>MASK_3_LSW</name>
<desc>Mask values to be applied on writes to the corresponding GPIO pins
0 = pin value is updated
1 = pin is masked
Each bit controls the corresponding pin within the 16-bit half-bank
Write Only, Read back as zero</desc>
<sw_param offset="0xe000a018" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gpio_MASK_DATA_3_LSW_DATA_3_LSW">
<name>DATA_3_LSW</name>
<desc>Data values read from or written to the corresponding GPIO pins
Each bit controls the corresponding pin within the 16-bit half-bank</desc>
<sw_param offset="0xe000a018" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_MASK_DATA_3_MSW_MASK_3_MSW">
<name>MASK_3_MSW</name>
<desc>Mask values to be applied on writes to the corresponding GPIO pins
0 = pin value is updated
1 = pin is masked
Each bit controls the corresponding pin within the 16-bit half-bank
Write Only, Read back as zero</desc>
<sw_param offset="0xe000a01c" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_gpio_MASK_DATA_3_MSW_DATA_3_MSW">
<name>DATA_3_MSW</name>
<desc>Data values read from or written to the corresponding GPIO pins
Each bit controls the corresponding pin within the 16-bit half-bank</desc>
<sw_param offset="0xe000a01c" start="15" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_DATA_0_DATA_0">
<name>DATA_0</name>
<desc>Data values read from or written to the corresponding GPIO pins
Each bit controls the corresponding pin within the 32-bit bank. Note: Bit[6], bit[7] default value = 0</desc>
<sw_param offset="0xe000a040" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_DATA_1_DATA_1">
<name>DATA_1</name>
<desc>Data values read from or written to the corresponding GPIO pins
Each bit controls the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a044" start="21" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_DATA_2_DATA_2">
<name>DATA_2</name>
<desc>Data values read from or written to the corresponding GPIO pins
Each bit controls the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a048" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_DATA_3_DATA_3">
<name>DATA_3</name>
<desc>Data values read from or written to the corresponding GPIO pins
Each bit controls the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a04c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_DATA_0_RO_DATA_0_RO">
<name>DATA_0_RO</name>
<desc>GPIO pin values, independent of the read, write, and direction settings.
Each bit provides a pin value within the 32-bit bank Note :Bit[6], bit[7] default value = 0</desc>
<sw_param offset="0xe000a060" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_DATA_1_RO_DATA_1_RO">
<name>DATA_1_RO</name>
<desc>GPIO pin values, independent of the read, write, and direction settings.
Each bit provides a pin value within the 32-bit bank</desc>
<sw_param offset="0xe000a064" start="21" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_DATA_2_RO_DATA_2_RO">
<name>DATA_2_RO</name>
<desc>GPIO pin values, independent of the read, write, and direction settings.
Each bit provides a pin value within the 32-bit bank</desc>
<sw_param offset="0xe000a068" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_DATA_3_RO_DATA_3_RO">
<name>DATA_3_RO</name>
<desc>GPIO pin values, independent of the read, write, and direction settings.
Each bit provides a pin value within the 32-bit bank</desc>
<sw_param offset="0xe000a06c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_BYPM_0_BYPASS_MODE_0">
<name>BYPASS_MODE_0</name>
<desc>Bypass configuration for bank 0
0 = software controlled mode
1 = bypass mode
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a200" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_DIRM_0_DIRECTION_0">
<name>DIRECTION_0</name>
<desc>Direction mode for bank 0
0 = input
1 = output
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a204" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_OEN_0_OP_ENABLE_0">
<name>OP_ENABLE_0</name>
<desc>Output enables for bank 0
0 = disabled
1 = enabled
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a208" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_INT_MASK_0_INT_MASK_0">
<name>INT_MASK_0</name>
<desc>Interrupt mask for bank 0
0 = interrupt source enabled
1 = interrupt source masked
Each bit reports the status for the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a20c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_INT_EN_0_INT_ENABLE_0">
<name>INT_ENABLE_0</name>
<desc>Interrupt enable for bank 0
0 = no change
1 = clear interrupt mask
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a210" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_INT_DIS_0_INT_DISABLE_0">
<name>INT_DISABLE_0</name>
<desc>Interrupt disable for bank 0
0 = no change
1 = set interrupt mask
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a214" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_INT_STAT_0_INT_STATUS_0">
<name>INT_STATUS_0</name>
<desc>Interrupt status for bank 0
Upon read:
0 = no interrupt
1 = interrupt event has occurred
Upon write:
0 = no action
1 = clear interrupt status bit
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a218" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_INT_TYPE_0_INT_TYPE_0">
<name>INT_TYPE_0</name>
<desc>Interrupt type for bank 0
0 = level-sensitive
1 = edge-sensitive
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a21c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_INT_POLARITY_0_INT_POL_0">
<name>INT_POL_0</name>
<desc>Interrupt polarity for bank 0
0 = active low or falling edge
1 = active high or rising edge
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a220" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_INT_ANY_0_INT_ON_ANY_0">
<name>INT_ON_ANY_0</name>
<desc>Interrupt edge triggering mode for bank 0
0 = trigger on single edge, using configured interrupt polarity
1 = trigger on both edges
This value is ignored if corresponding interrupt source is configured to be level-sensitive
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a224" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_BYPM_1_BYPASS_MODE_1">
<name>BYPASS_MODE_1</name>
<desc>Bypass configuration for bank 1
0 = software controlled mode
1 = bypass mode
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a240" start="21" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_DIRM_1_DIRECTION_1">
<name>DIRECTION_1</name>
<desc>Direction mode for bank 1
0 = input
1 = output
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a244" start="21" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_OEN_1_OP_ENABLE_1">
<name>OP_ENABLE_1</name>
<desc>Output enables for bank 1
0 = disabled
1 = enabled
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a248" start="21" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_INT_MASK_1_INT_MASK_1">
<name>INT_MASK_1</name>
<desc>Interrupt mask for bank 1
0 = interrupt source enabled
1 = interrupt source masked
Each bit reports the status for the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a24c" start="21" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_INT_EN_1_INT_ENABLE_1">
<name>INT_ENABLE_1</name>
<desc>Interrupt enable for bank 1
0 = no change
1 = clear interrupt mask
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a250" start="21" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_INT_DIS_1_INT_DISABLE_1">
<name>INT_DISABLE_1</name>
<desc>Interrupt disable for bank 1
0 = no change
1 = set interrupt mask
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a254" start="21" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_INT_STAT_1_INT_STATUS_1">
<name>INT_STATUS_1</name>
<desc>Interrupt status for bank 1
Upon read:
0 = no interrupt
1 = interrupt event has occurred
Upon write:
0 = no action
1 = clear interrupt status bit
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a258" start="21" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_INT_TYPE_1_INT_TYPE_1">
<name>INT_TYPE_1</name>
<desc>Interrupt type for bank 1
0 = level-sensitive
1 = edge-sensitive
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a25c" start="21" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_INT_POLARITY_1_INT_POL_1">
<name>INT_POL_1</name>
<desc>Interrupt polarity for bank 1
0 = active low or falling edge
1 = active high or rising edge
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a260" start="21" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_INT_ANY_1_INT_ON_ANY_1">
<name>INT_ON_ANY_1</name>
<desc>Interrupt edge triggering mode for bank 1
0 = trigger on single edge, using configured interrupt polarity
1 = trigger on both edges
This value is ignored if corresponding interrupt source is configured to be level-sensitive
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a264" start="21" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_BYPM_2_BYPASS_MODE_2">
<name>BYPASS_MODE_2</name>
<desc>Bypass configuration for bank 2
0 = software controlled mode
1 = bypass mode
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a280" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_DIRM_2_DIRECTION_2">
<name>DIRECTION_2</name>
<desc>Direction mode for bank 2
0 = input
1 = output
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a284" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_OEN_2_OP_ENABLE_2">
<name>OP_ENABLE_2</name>
<desc>Output enables for bank 2
0 = disabled
1 = enabled
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a288" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_INT_MASK_2_INT_MASK_2">
<name>INT_MASK_2</name>
<desc>Interrupt mask for bank 2
0 = interrupt source enabled
1 = interrupt source masked
Each bit reports the status for the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a28c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_INT_EN_2_INT_ENABLE_2">
<name>INT_ENABLE_2</name>
<desc>Interrupt enable for bank 2
0 = no change
1 = clear interrupt mask
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a290" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_INT_DIS_2_INT_DISABLE_2">
<name>INT_DISABLE_2</name>
<desc>Interrupt disable for bank 2
0 = no change
1 = set interrupt mask
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a294" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_INT_STAT_2_INT_STATUS_2">
<name>INT_STATUS_2</name>
<desc>Interrupt status for bank 2
Upon read:
0 = no interrupt
1 = interrupt event has occurred
Upon write:
0 = no action
1 = clear interrupt status bit
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a298" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_INT_TYPE_2_INT_TYPE_2">
<name>INT_TYPE_2</name>
<desc>Interrupt type for bank 2
0 = level-sensitive
1 = edge-sensitive
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a29c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_INT_POLARITY_2_INT_POL_2">
<name>INT_POL_2</name>
<desc>Interrupt polarity for bank 2
0 = active low or falling edge
1 = active high or rising edge
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a2a0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_INT_ANY_2_INT_ON_ANY_2">
<name>INT_ON_ANY_2</name>
<desc>Interrupt edge triggering mode for bank 2
0 = trigger on single edge, using configured interrupt polarity
1 = trigger on both edges
This value is ignored if corresponding interrupt source is configured to be level-sensitive
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a2a4" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_BYPM_3_BYPASS_MODE_3">
<name>BYPASS_MODE_3</name>
<desc>Bypass configuration for bank 3
0 = software controlled mode
1 = bypass mode
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a2c0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_DIRM_3_DIRECTION_3">
<name>DIRECTION_3</name>
<desc>Direction mode for bank 3
0 = input
1 = output
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a2c4" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_OEN_3_OP_ENABLE_3">
<name>OP_ENABLE_3</name>
<desc>Output enables for bank 3
0 = disabled
1 = enabled
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a2c8" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_INT_MASK_3_INT_MASK_3">
<name>INT_MASK_3</name>
<desc>Interrupt mask for bank 3
0 = interrupt source enabled
1 = interrupt source masked
Each bit reports the status for the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a2cc" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_INT_EN_3_INT_ENABLE_3">
<name>INT_ENABLE_3</name>
<desc>Interrupt enable for bank 3
0 = no change
1 = clear interrupt mask
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a2d0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_INT_DIS_3_INT_DISABLE_3">
<name>INT_DISABLE_3</name>
<desc>Interrupt disable for bank 3
0 = no change
1 = set interrupt mask
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a2d4" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_INT_STAT_3_INT_STATUS_3">
<name>INT_STATUS_3</name>
<desc>Interrupt status for bank 3
Upon read:
0 = no interrupt
1 = interrupt event has occurred
Upon write:
0 = no action
1 = clear interrupt status bit
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a2d8" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_INT_TYPE_3_INT_TYPE_3">
<name>INT_TYPE_3</name>
<desc>Interrupt type for bank 3
0 = level-sensitive
1 = edge-sensitive
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a2dc" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_INT_POLARITY_3_INT_POL_3">
<name>INT_POL_3</name>
<desc>Interrupt polarity for bank 3
0 = active low or falling edge
1 = active high or rising edge
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a2e0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_gpio_INT_ANY_3_INT_ON_ANY_3">
<name>INT_ON_ANY_3</name>
<desc>Interrupt edge triggering mode for bank 3
0 = trigger on single edge, using configured interrupt polarity
1 = trigger on both edges
This value is ignored if corresponding interrupt source is configured to be level-sensitive
Each bit configures the corresponding pin within the 32-bit bank</desc>
<sw_param offset="0xe000a2e4" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_devcfg_CTRL_FORCE_RST">
<name>FORCE_RST</name>
<desc>Force PS in to secure reset</desc>
<sw_param offset="0xf8007000" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_devcfg_CTRL_PCFG_PROG_B">
<name>PCFG_PROG_B</name>
<desc>Program Signal used to reset FPGA.
It is used to drive pcfg_program signal to FPGA.
It acts as PROG_b signal in FPGA fabric.</desc>
<sw_param offset="0xf8007000" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_devcfg_CTRL_PCFG_POR_CNT_4K">
<name>PCFG_POR_CNT_4K</name>
<desc>This is to indicate to the FPGA fabric what timer to use
0 - use 64K timer
1 - use 4K timer</desc>
<sw_param offset="0xf8007000" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_devcfg_CTRL_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8007000" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_devcfg_CTRL_PCAP_PR">
<name>PCAP_PR</name>
<desc>This signal is used to enable Internal Partial Re-Configuration from PCAP. Default internal Partial Reconfiguration Path is through ICAP. In order to use PCAP or ICAP Partial Reconfiguration, FPGA configuration memory bit ICAP_EN bit must be set through FPGA bitstream
0 - ICAP as Internal FPGA Partial Reconfiguration Path
1 - PCAP as Internal
FPGA Partial Reconfiguration Path
This bit will be forced to 0 if APB unlock (0x034) is not done correctly</desc>
<sw_param offset="0xf8007000" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_devcfg_CTRL_PCAP_MODE">
<name>PCAP_MODE</name>
<desc>Enable PCAP interface and disable all FPGA external programming interface</desc>
<sw_param offset="0xf8007000" start="26" end="26" />
</parameter>
<parameter uniqueid="ps7_devcfg_CTRL_QUARTER_PCAP_RATE_EN">
<name>QUARTER_PCAP_RATE_EN</name>
<desc>This bit is used to force only one data is send data to FPGA every 4 PCAP clock cycles by toggling chip select output every 4 clock cycles. This is required when AES engine in FPGA is enabled for bitstream decryption. But it should also work in normal mode with quarter throughput although it is not recommended method to reduce throughput</desc>
<sw_param offset="0xf8007000" start="25" end="25" />
</parameter>
<parameter uniqueid="ps7_devcfg_CTRL_MULTIBOOT_EN">
<name>MULTIBOOT_EN</name>
<desc>This bit enables multi-boot out of reset. This is power on reset register
0 - Boot from default boot image base address
1 - Boot from multi-boot offset address</desc>
<sw_param offset="0xf8007000" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_devcfg_CTRL_JTAG_CHAIN_DIS">
<name>JTAG_CHAIN_DIS</name>
<desc>This bit is used to disable JTAG Scan chain to protect JTAG access to FPGA Fabric</desc>
<sw_param offset="0xf8007000" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_devcfg_CTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xf8007000" start="22" end="16" />
</parameter>
<parameter uniqueid="ps7_devcfg_CTRL_USER_MODE">
<name>USER_MODE</name>
<desc>Indicates which mode the CPU is running
0 - CPU is running in ROM Mode
1 - CPU is running in User Mode</desc>
<sw_param offset="0xf8007000" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_devcfg_CTRL_RD_ISS_IS_1">
<name>RD_ISS_IS_1</name>
<desc>AXI read issuing capability is 1, if set, else the issuing capability is determined by bit 3 of the Config Register at offset 0x008</desc>
<sw_param offset="0xf8007000" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_devcfg_CTRL_WR_ISS_IS_1">
<name>WR_ISS_IS_1</name>
<desc>AXI write issuing capability is 1, if set, else the issuing capability is determined by bit 2 of Config Register at offset 0x008</desc>
<sw_param offset="0xf8007000" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_devcfg_CTRL_PCFG_AES_FUSE">
<name>PCFG_AES_FUSE</name>
<desc>(Lockable, see 0x004, bit 4)
This is to indicate to the FGPA fabric the source of the AES key.
0 - BBRAM
1 - eFuse</desc>
<sw_param offset="0xf8007000" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_devcfg_CTRL_PCFG_AES_EN">
<name>PCFG_AES_EN</name>
<desc>(Lockable, see 0x004, bit 3)
Enable AES engine within FPGA Configuration Logic. The three bits are combined to form a single bit to enable the 'DEC' bit in FPGA configuration logic.
The three bits need to be either all 0's or 1's, any inconsistency will lead to security reset.
0 - Disable AES engine
1-
Enable AES engine
These bits will be forced to 0 if unlock (0x034) is not done correctly.</desc>
<sw_param offset="0xf8007000" start="11" end="9" />
</parameter>
<parameter uniqueid="ps7_devcfg_CTRL_SEU_EN">
<name>SEU_EN</name>
<desc>(Lockable, see 0x004, bit 2)
This is read/write control register with locking capability.
This is set only on power on reset.
0 - Ignore SEU signal from FPGA.
1 - Reset PS when SEU is on</desc>
<sw_param offset="0xf8007000" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_devcfg_CTRL_SEC_EN">
<name>SEC_EN</name>
<desc>(Lockable, see 0x004, bit 1)
This bit is used to indicate whether PS is secured. Secure Boot ROM code will set this bit and locked before it passes control to user code. In that sense, this is Read Only bit from user stand point of view.
0 - PS is non-secured
1 - PS is secured</desc>
<sw_param offset="0xf8007000" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_devcfg_CTRL_SPNIDEN">
<name>SPNIDEN</name>
<desc>(Lockable, see 0x004, bit 0)
Secure/priviledged Non-Invasive Debug Enable
0 - Disable
1 - Enable</desc>
<sw_param offset="0xf8007000" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_devcfg_CTRL_SPIDEN">
<name>SPIDEN</name>
<desc>(Lockable, see 0x004, bit 0)
Secure/privileged Invasive Debug Enable
0 - Disable
1 - Enable</desc>
<sw_param offset="0xf8007000" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_devcfg_CTRL_NIDEN">
<name>NIDEN</name>
<desc>(Lockable, see 0x004, bit 0)
Non-Invasive Debug Enable
0 - Disable
1 - Enable</desc>
<sw_param offset="0xf8007000" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_devcfg_CTRL_DBGEN">
<name>DBGEN</name>
<desc>(Lockable, see 0x004, bit 0)
Invasive Debug Enable
0 - Disable
1 - Enable</desc>
<sw_param offset="0xf8007000" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_devcfg_CTRL_DAP_EN">
<name>DAP_EN</name>
<desc>(Lockable, see 0x004, bit 0)
This is software control to signals to put ARM DAP AP into dummy bypass mode. It should be default at bypass mode when system is out of reset. Software could change its value until DBG_LOCK bit is on.
111 - Enable ARM DAP
Others - ARM DAP will be bypassed</desc>
<sw_param offset="0xf8007000" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_devcfg_LOCK_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8007004" start="31" end="5" />
</parameter>
<parameter uniqueid="ps7_devcfg_LOCK_AES_FUSE_LOCK">
<name>AES_FUSE_LOCK</name>
<desc>This register bit is used to lock PCFG_AES_FUSE.
It requires power on reset to restore back to default 0.
0 - Open
1 - Lock</desc>
<sw_param offset="0xf8007004" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_devcfg_LOCK_AES_EN_LOCK">
<name>AES_EN_LOCK</name>
<desc>This register is used to lock PCFG_AES_EN update. It requires power on reset to restore back to default 0.
0 - Open
1 - Lock</desc>
<sw_param offset="0xf8007004" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_devcfg_LOCK_SEU_LOCK">
<name>SEU_LOCK</name>
<desc>This register is used to lock SEU_En
update. It requires power on reset to restore back to default 0.
0 - Open
1 - Lock</desc>
<sw_param offset="0xf8007004" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_devcfg_LOCK_SEC_LOCK">
<name>SEC_LOCK</name>
<desc>This bit locks SEC_EN, USER_MODE. This bit is software set only. It requires power on reset to restore back to default 0.
0 - Open
1 - Locked</desc>
<sw_param offset="0xf8007004" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_devcfg_LOCK_DBG_LOCK">
<name>DBG_LOCK</name>
<desc>This bit locks security configuration bits include: DAP_En,
DBGEN, DBGEN,
NIDEN, SPNIEN. This bit is software set only. It requires power on reset to restore back to default 0.
0 - Open
1 - Locked</desc>
<sw_param offset="0xf8007004" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_devcfg_CFG_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8007008" start="31" end="12" />
</parameter>
<parameter uniqueid="ps7_devcfg_CFG_RFIFO_TH">
<name>RFIFO_TH</name>
<desc>These two bits define Rx FIFO level that sets interrupt flag
00 - One fourth
full for read
01 - Half full for read
10 - Three fourth full for read
11 - Full for read(User could use this signal to trigger interrupt when read FIFO overflow)</desc>
<sw_param offset="0xf8007008" start="11" end="10" />
</parameter>
<parameter uniqueid="ps7_devcfg_CFG_WFIFO_TH">
<name>WFIFO_TH</name>
<desc>These two bits define Tx FIFO level that sets interrupt flag
00 - One fourth empty for write
01 - Half empty for write
10 - Three fourth empty for write
11 - empty for write</desc>
<sw_param offset="0xf8007008" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_devcfg_CFG_RCLK_EDGE">
<name>RCLK_EDGE</name>
<desc>Read data active clock edge
0 - falling edge
1 - rising edge</desc>
<sw_param offset="0xf8007008" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_devcfg_CFG_WCLK_EDGE">
<name>WCLK_EDGE</name>
<desc>Write data active clock edge
0 - falling edge
1 - rising edge</desc>
<sw_param offset="0xf8007008" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_devcfg_CFG_DISABLE_SRC_INC">
<name>DISABLE_SRC_INC</name>
<desc>Disable automatic DMA AXI source address increment, if set, to allow AXI read from a keyhole address</desc>
<sw_param offset="0xf8007008" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_devcfg_CFG_DISABLE_DST_INC">
<name>DISABLE_DST_INC</name>
<desc>Disable automatic DMA AXI destination address increment, if set, to allow AXI read from a keyhole address</desc>
<sw_param offset="0xf8007008" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_devcfg_CFG_RD_ISSUE">
<name>RD_ISSUE</name>
<desc>AXI read issuing capability
0 - 4
1 - 8</desc>
<sw_param offset="0xf8007008" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_devcfg_CFG_WR_ISSUE">
<name>WR_ISSUE</name>
<desc>AXI write issuing capability
0 - 2
1 - 4</desc>
<sw_param offset="0xf8007008" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_devcfg_CFG_RDLEN">
<name>RDLEN</name>
<desc>AXI read burst length
0 - burst-of-8
1 - burst-of-16</desc>
<sw_param offset="0xf8007008" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_devcfg_CFG_WRLEN">
<name>WRLEN</name>
<desc>AXI write burst length
0 - burst-of-8
1 - burst-of-16</desc>
<sw_param offset="0xf8007008" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_STS_PSS_GTS_USR_B_INT">
<name>PSS_GTS_USR_B_INT</name>
<desc>Tri-state IO during HIZ, both edges</desc>
<sw_param offset="0xf800700c" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_STS_PSS_FST_CFG_B_INT">
<name>PSS_FST_CFG_B_INT</name>
<desc>First configuration done, both edges</desc>
<sw_param offset="0xf800700c" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_STS_PSS_GPWRDWN_B_INT">
<name>PSS_GPWRDWN_B_INT</name>
<desc>Global power down, both edges</desc>
<sw_param offset="0xf800700c" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_STS_PSS_GTS_CFG_B_INT">
<name>PSS_GTS_CFG_B_INT</name>
<desc>Tri-state IO during configuration, both edges</desc>
<sw_param offset="0xf800700c" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_STS_PSS_CFG_RESET_B_INT">
<name>PSS_CFG_RESET_B_INT</name>
<desc>Config reset, both edges</desc>
<sw_param offset="0xf800700c" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_STS_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf800700c" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_STS_AXI_WTO_INT">
<name>AXI_WTO_INT</name>
<desc>AXI write address, data or response time out (&gt; 6144 cpu_1x clock cycles)</desc>
<sw_param offset="0xf800700c" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_STS_AXI_WERR_INT">
<name>AXI_WERR_INT</name>
<desc>AXI write response error</desc>
<sw_param offset="0xf800700c" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_STS_AXI_RTO_INT">
<name>AXI_RTO_INT</name>
<desc>AXI read address or response time out (&gt; 2048 cpu_1x clock cylces)</desc>
<sw_param offset="0xf800700c" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_STS_AXI_RERR_INT">
<name>AXI_RERR_INT</name>
<desc>AXI read response error</desc>
<sw_param offset="0xf800700c" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_STS_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xf800700c" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_STS_RX_FIFO_OV_INT">
<name>RX_FIFO_OV_INT</name>
<desc>This bit is used to indicate that RX FIFO overflows. Incoming read data from PCAP will be dropped.
This
bit is cleared by writing a 1 to reg 0x080 bit 1.</desc>
<sw_param offset="0xf800700c" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_STS_WR_FIFO_LVL_INT">
<name>WR_FIFO_LVL_INT</name>
<desc>Tx FIFO level &lt; threshold, see reg 0x008</desc>
<sw_param offset="0xf800700c" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_STS_RD_FIFO_LVL_INT">
<name>RD_FIFO_LVL_INT</name>
<desc>Rx FIFO level &gt;= threshold, see reg 0x008</desc>
<sw_param offset="0xf800700c" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_STS_DMA_CMD_ERR_INT">
<name>DMA_CMD_ERR_INT</name>
<desc>Illegal DMA command (see description in 3.1.2)</desc>
<sw_param offset="0xf800700c" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_STS_DMA_Q_OV_INT">
<name>DMA_Q_OV_INT</name>
<desc>DMA command queue overflows</desc>
<sw_param offset="0xf800700c" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_STS_DMA_DONE_INT">
<name>DMA_DONE_INT</name>
<desc>This bit is used to indicate a DMA command
is done.
The bit is set either as soon as DMA is done (
PCAP may yet to finish) or both DMA and PCAP are done (see Section 3.1.2 for more details)</desc>
<sw_param offset="0xf800700c" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_STS_D_P_DONE_INT">
<name>D_P_DONE_INT</name>
<desc>Both DMA and PCAP transfers are done for intermediate and final transfers.</desc>
<sw_param offset="0xf800700c" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_STS_P2D_LEN_ERR_INT">
<name>P2D_LEN_ERR_INT</name>
<desc>Inconsistent PCAP to DMA transfer length error</desc>
<sw_param offset="0xf800700c" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_STS_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xf800700c" start="10" end="7" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_STS_PCFG_HMAC_ERR_INT">
<name>PCFG_HMAC_ERR_INT</name>
<desc>HMAC error from FPGA</desc>
<sw_param offset="0xf800700c" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_STS_PCFG_SEU_ERR_INT">
<name>PCFG_SEU_ERR_INT</name>
<desc>SEU status from FPGA</desc>
<sw_param offset="0xf800700c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_STS_PCFG_POR_B_INT">
<name>PCFG_POR_B_INT</name>
<desc>FPGA POR Indication</desc>
<sw_param offset="0xf800700c" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_STS_PCFG_CFG_RST_INT">
<name>PCFG_CFG_RST_INT</name>
<desc>Signal used to indicate FPGA under reset</desc>
<sw_param offset="0xf800700c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_STS_PCFG_DONE_INT">
<name>PCFG_DONE_INT</name>
<desc>This is 'Done' Read-Only Status signal from FPGA</desc>
<sw_param offset="0xf800700c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_STS_PCFG_INIT_PE_INT">
<name>PCFG_INIT_PE_INT</name>
<desc>This detects +ve edge of 'Init' signal from FPGA</desc>
<sw_param offset="0xf800700c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_STS_PCFG_INIT_NE_INT">
<name>PCFG_INIT_NE_INT</name>
<desc>This detects -ve edge of 'Init' signal from FPGA</desc>
<sw_param offset="0xf800700c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_MASK_M_PSS_GTS_USR_B_INT">
<name>M_PSS_GTS_USR_B_INT</name>
<desc>Interrupt mask for tri-state IO during HIZ, both edges</desc>
<sw_param offset="0xf8007010" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_MASK_M_PSS_FST_CFG_B_INT">
<name>M_PSS_FST_CFG_B_INT</name>
<desc>Interrupt mask for first config done, both edges</desc>
<sw_param offset="0xf8007010" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_MASK_M_PSS_GPWRDWN_B_INT">
<name>M_PSS_GPWRDWN_B_INT</name>
<desc>Interrupt mask for global power down, both edges</desc>
<sw_param offset="0xf8007010" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_MASK_M_PSS_GTS_CFG_B_INT">
<name>M_PSS_GTS_CFG_B_INT</name>
<desc>Interrupt mask for tri-state IO in config, both edges</desc>
<sw_param offset="0xf8007010" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_MASK_M_PSS_CFG_RESET_B_INT">
<name>M_PSS_CFG_RESET_B_INT</name>
<desc>Interrupt mask for config reset, both edges</desc>
<sw_param offset="0xf8007010" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_MASK_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8007010" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_MASK_M_AXI_WTO_INT">
<name>M_AXI_WTO_INT</name>
<desc>Interrupt mask for AXI write time out interrupt</desc>
<sw_param offset="0xf8007010" start="23" end="23" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_MASK_M_AXI_WERR_INT">
<name>M_AXI_WERR_INT</name>
<desc>Interrupt mask for AXI write response error interrupt</desc>
<sw_param offset="0xf8007010" start="22" end="22" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_MASK_M_AXI_RTO_INT">
<name>M_AXI_RTO_INT</name>
<desc>Interrupt mask for AXI read time out interrupt</desc>
<sw_param offset="0xf8007010" start="21" end="21" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_MASK_M_AXI_RERR_INT">
<name>M_AXI_RERR_INT</name>
<desc>Interrupt mask for AXI read response error interrupt</desc>
<sw_param offset="0xf8007010" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_MASK_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xf8007010" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_MASK_M_RX_FIFO_OV_INT">
<name>M_RX_FIFO_OV_INT</name>
<desc>Interrupt mask for Rx FIFO overflow interrupt</desc>
<sw_param offset="0xf8007010" start="18" end="18" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_MASK_M_WR_FIFO_LVL_INT">
<name>M_WR_FIFO_LVL_INT</name>
<desc>Interrupt mask for Tx FIFO level &lt; threshold interrupt</desc>
<sw_param offset="0xf8007010" start="17" end="17" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_MASK_M_RD_FIFO_LVL_INT">
<name>M_RD_FIFO_LVL_INT</name>
<desc>Interrupt mask for Rx FIFO level &gt; threshold interrupt</desc>
<sw_param offset="0xf8007010" start="16" end="16" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_MASK_M_DMA_CMD_ERR_INT">
<name>M_DMA_CMD_ERR_INT</name>
<desc>Interrupt mask for illegal DMA command interrupt</desc>
<sw_param offset="0xf8007010" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_MASK_M_DMA_FIFO_OV_INT">
<name>M_DMA_FIFO_OV_INT</name>
<desc>Interrupt mask for DMA command FIFO overflows</desc>
<sw_param offset="0xf8007010" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_MASK_M_DMA_DONE_INT">
<name>M_DMA_DONE_INT</name>
<desc>Interrupt mask for DMA command done interrupt</desc>
<sw_param offset="0xf8007010" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_MASK_M_D_P_DONE_INT">
<name>M_D_P_DONE_INT</name>
<desc>Interrupt mask for DMA and PCAP done interrupt</desc>
<sw_param offset="0xf8007010" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_MASK_M_P2D_LEN_ERR_INT">
<name>M_P2D_LEN_ERR_INT</name>
<desc>Interrupt mask Inconsistent xfer length error interrupt</desc>
<sw_param offset="0xf8007010" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_MASK_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xf8007010" start="10" end="7" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_MASK_M_PCFG_HMAC_ERR_INT">
<name>M_PCFG_HMAC_ERR_INT</name>
<desc>Interrupt mask for HMAC error</desc>
<sw_param offset="0xf8007010" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_MASK_M_PCFG_SEU_ERR_INT">
<name>M_PCFG_SEU_ERR_INT</name>
<desc>Interrupt mask for PCFG_SEU_ERR interrupt</desc>
<sw_param offset="0xf8007010" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_MASK_M_PCFG_POR_B_INT">
<name>M_PCFG_POR_B_INT</name>
<desc>Interrupt mask for PCFG_POR_B Interrupt</desc>
<sw_param offset="0xf8007010" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_MASK_M_PCFG_CFG_RST_INT">
<name>M_PCFG_CFG_RST_INT</name>
<desc>Interrupt mask for PCFG_CFG_RESET interrupt</desc>
<sw_param offset="0xf8007010" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_MASK_M_PCFG_DONE_INT">
<name>M_PCFG_DONE_INT</name>
<desc>Interrupt mask for PCFG_DONE interrupt</desc>
<sw_param offset="0xf8007010" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_MASK_M_PCFG_INIT_PE_INT">
<name>M_PCFG_INIT_PE_INT</name>
<desc>Interrupt mask for PCFG_INIT_PE interrupt</desc>
<sw_param offset="0xf8007010" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_devcfg_INT_MASK_M_PCFG_INIT_NE_INT">
<name>M_PCFG_INIT_NE_INT</name>
<desc>Interrupt mask for PCFG_INIT_NE interrupt</desc>
<sw_param offset="0xf8007010" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_devcfg_STATUS_DMA_CMD_Q_F">
<name>DMA_CMD_Q_F</name>
<desc>DMA command queue full, if set</desc>
<sw_param offset="0xf8007014" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_devcfg_STATUS_DMA_CMD_Q_E">
<name>DMA_CMD_Q_E</name>
<desc>DMA command queue empty, if set</desc>
<sw_param offset="0xf8007014" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_devcfg_STATUS_DMA_DONE_CNT">
<name>DMA_DONE_CNT</name>
<desc>Number of completed DMA transfers that have not been acknowledged by software:
00 - all finished transfers have been acknowledged
01 - one finished transfer outstanding
10 - two finished transfers outstanding
11 - three or more finished transfers outstanding
A finished transfer is acknowledged by clearing the interrupt status flag, i.e., bit 9 of the interrupt status register 0x00C.
This count is cleared by writing a 1 to either bit location.</desc>
<sw_param offset="0xf8007014" start="29" end="28" />
</parameter>
<parameter uniqueid="ps7_devcfg_STATUS_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8007014" start="27" end="25" />
</parameter>
<parameter uniqueid="ps7_devcfg_STATUS_RX_FIFO_LVL">
<name>RX_FIFO_LVL</name>
<desc>This register is used to indicate how many valid 32-Bit words in the Rx FIFO, max. is 31</desc>
<sw_param offset="0xf8007014" start="24" end="20" />
</parameter>
<parameter uniqueid="ps7_devcfg_STATUS_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xf8007014" start="19" end="19" />
</parameter>
<parameter uniqueid="ps7_devcfg_STATUS_TX_FIFO_LVL">
<name>TX_FIFO_LVL</name>
<desc>This register is used to indicate how many valid 32-Bit words in the Tx FIFO, max. is 127</desc>
<sw_param offset="0xf8007014" start="18" end="12" />
</parameter>
<parameter uniqueid="ps7_devcfg_STATUS_PSS_GTS_USR_B">
<name>PSS_GTS_USR_B</name>
<desc>Tri-state IO during HIZ, active low</desc>
<sw_param offset="0xf8007014" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_devcfg_STATUS_PSS_FST_CFG_B">
<name>PSS_FST_CFG_B</name>
<desc>First config done, active low.</desc>
<sw_param offset="0xf8007014" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_devcfg_STATUS_PSS_GPWRDWN_B">
<name>PSS_GPWRDWN_B</name>
<desc>Global power down, active low</desc>
<sw_param offset="0xf8007014" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_devcfg_STATUS_PSS_GTS_CFG_B">
<name>PSS_GTS_CFG_B</name>
<desc>Tri-state IO during config, active low</desc>
<sw_param offset="0xf8007014" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_devcfg_STATUS_SECURE_RST">
<name>SECURE_RST</name>
<desc>This is POR only clear register used to remember secure violation reset</desc>
<sw_param offset="0xf8007014" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_devcfg_STATUS_ILLEGAL_APB_ACCESS">
<name>ILLEGAL_APB_ACCESS</name>
<desc>The first APB access is not done correctly, if set. POR clear</desc>
<sw_param offset="0xf8007014" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_devcfg_STATUS_PSS_CFG_RESET_B">
<name>PSS_CFG_RESET_B</name>
<desc>PS configuration reset, active low.</desc>
<sw_param offset="0xf8007014" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_devcfg_STATUS_PCFG_INIT">
<name>PCFG_INIT</name>
<desc>Input signal from FPGA to indicate the init status.
+ve and -ve edge of the signal generate maskable interrupts indicated in 0x00C.</desc>
<sw_param offset="0xf8007014" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_devcfg_STATUS_EFUSE_SW_RESERVE">
<name>EFUSE_SW_RESERVE</name>
<desc>Input signal from FPGA to indicate efuse status. This register is sticky to high.
Value depends on the efuse state.</desc>
<sw_param offset="0xf8007014" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_devcfg_STATUS_EFUSE_SEC_EN">
<name>EFUSE_SEC_EN</name>
<desc>Input signal from FPGA to indicate efuse status. This register is sticky to high.
Value depends on the efuse state.</desc>
<sw_param offset="0xf8007014" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_devcfg_STATUS_EFUSE_JTAG_DIS">
<name>EFUSE_JTAG_DIS</name>
<desc>Input signal from FPGA to indicate efuse status. This register is sticky to high.
Value depends on the efuse state.</desc>
<sw_param offset="0xf8007014" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_devcfg_STATUS_SECURE_DIS">
<name>SECURE_DIS</name>
<desc>Indicate security is disabled, if asserted. CPU should check this signal first before boot sequence starts. If this signal is asserted, CPU will enter halt mode immediately</desc>
<sw_param offset="0xf8007014" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_devcfg_DMA_SRC_ADDR_ADDR">
<name>ADDR</name>
<desc>Source address for DMA transfer of AXI read</desc>
<sw_param offset="0xf8007018" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_devcfg_DMA_DST_ADDR_ADDR">
<name>ADDR</name>
<desc>Destination address for DMA transfer of AXI write</desc>
<sw_param offset="0xf800701c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_devcfg_DMA_SRC_LEN_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8007020" start="31" end="27" />
</parameter>
<parameter uniqueid="ps7_devcfg_DMA_SRC_LEN_LEN">
<name>LEN</name>
<desc>Up to 512MB data</desc>
<sw_param offset="0xf8007020" start="26" end="0" />
</parameter>
<parameter uniqueid="ps7_devcfg_DMA_DEST_LEN_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8007024" start="31" end="27" />
</parameter>
<parameter uniqueid="ps7_devcfg_DMA_DEST_LEN_LEN">
<name>LEN</name>
<desc>Up to 512MB data</desc>
<sw_param offset="0xf8007024" start="26" end="0" />
</parameter>
<parameter uniqueid="ps7_devcfg_ROM_SHADOW_ROM_SHADOW_EN">
<name>ROM_SHADOW_EN</name>
<desc>32-Bit Shadow Register controls RAM shadow of 32 4-K ROM page in user mode</desc>
<sw_param offset="0xf8007028" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_devcfg_MULTIBOOT_ADDR_MULTIBOOT_ADDR">
<name>MULTIBOOT_ADDR</name>
<desc>Multi-Boot offset address</desc>
<sw_param offset="0xf800702c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_devcfg_SW_ID_SW_ID">
<name>SW_ID</name>
<desc>Software ID</desc>
<sw_param offset="0xf8007030" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_devcfg_UNLOCK_UNLOCK">
<name>UNLOCK</name>
<desc>Unlock value.</desc>
<sw_param offset="0xf8007034" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_devcfg_MCTRL_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8007080" start="31" end="5" />
</parameter>
<parameter uniqueid="ps7_devcfg_MCTRL_INT_PCAP_LPBK">
<name>INT_PCAP_LPBK</name>
<desc>Internal PCAP loopback, if set</desc>
<sw_param offset="0xf8007080" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_devcfg_MCTRL_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xf8007080" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_devcfg_MCTRL_RFIFO_FLUSH">
<name>RFIFO_FLUSH</name>
<desc>Flush Rx FIFO by writing a 1 to this bit location, the value is not sticky</desc>
<sw_param offset="0xf8007080" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_devcfg_MCTRL_WFIFO_FLUSH">
<name>WFIFO_FLUSH</name>
<desc>Flush Tx FIFO by writing a 1 to this bit location, the value is not sticky</desc>
<sw_param offset="0xf8007080" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_CFG_ENABLE">
<name>ENABLE</name>
<desc>Enable PS access of the XADC, if set</desc>
<sw_param offset="0xf8007100" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_CFG_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8007100" start="30" end="24" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_CFG_CFIFOTH">
<name>CFIFOTH</name>
<desc>Command FIFO level threshold.
Interrupt status flag is set if the FIFO level is less than or equal to the threshold</desc>
<sw_param offset="0xf8007100" start="23" end="20" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_CFG_DFIFOTH">
<name>DFIFOTH</name>
<desc>Data FIFO level threshold.
Interrupt status flag is set if FIFO level is greater than the threshold</desc>
<sw_param offset="0xf8007100" start="19" end="16" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_CFG_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xf8007100" start="15" end="14" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_CFG_WEDGE">
<name>WEDGE</name>
<desc>Write launch edge : 0 - falling edge, 1 - rising edge</desc>
<sw_param offset="0xf8007100" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_CFG_REDGE">
<name>REDGE</name>
<desc>Read capture edge : 0 - falling edge, 1 - rising edge</desc>
<sw_param offset="0xf8007100" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_CFG_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xf8007100" start="11" end="10" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_CFG_TCKRATE">
<name>TCKRATE</name>
<desc>XADC clock frequency control.
The base frequency is pcap_2x clock which has a nominal frequency of 200 MHz.
00 - 1/2 of pcap_2x clock frequency
01 - 1/4
of pcac_2x clock frequency
10 - 1/8 of pcap_2x clock frequency
11 - 1/16 of pcap_2x clock frequency</desc>
<sw_param offset="0xf8007100" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_CFG_reserved_3">
<name>reserved_3</name>
<desc>Reserved</desc>
<sw_param offset="0xf8007100" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_CFG_IGAP">
<name>IGAP</name>
<desc>Minimum idle gap between successive commands.</desc>
<sw_param offset="0xf8007100" start="4" end="0" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_INT_STS_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8007104" start="31" end="10" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_INT_STS_CFIFO_LTH">
<name>CFIFO_LTH</name>
<desc>Command FIFO level less than or equal to the threshold (see register 0x100).</desc>
<sw_param offset="0xf8007104" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_INT_STS_DFIFO_GTH">
<name>DFIFO_GTH</name>
<desc>Data FIFO level greater than threshold (see register 0x100).</desc>
<sw_param offset="0xf8007104" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_INT_STS_OT">
<name>OT</name>
<desc>Over temperature alarm from XADC.
This is a latched version of the raw signal which is also available in register 0x10C</desc>
<sw_param offset="0xf8007104" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_INT_STS_ALM">
<name>ALM</name>
<desc>Alarm signals from XADC.
These are latched version of the raw input alarm signals which are also available in register 0x10C</desc>
<sw_param offset="0xf8007104" start="6" end="0" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_INT_MASK_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8007108" start="31" end="10" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_INT_MASK_M_CFIFO_LTH">
<name>M_CFIFO_LTH</name>
<desc>Interrupt mask for command FIFO level threshold interrupt.</desc>
<sw_param offset="0xf8007108" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_INT_MASK_M_DFIFO_GTH">
<name>M_DFIFO_GTH</name>
<desc>Interrupt mask Data FIFO level greater than threshold interrupt.</desc>
<sw_param offset="0xf8007108" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_INT_MASK_M_OT">
<name>M_OT</name>
<desc>Interrupt mask for over temperature alarm interrupt</desc>
<sw_param offset="0xf8007108" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_INT_MASK_M_ALM">
<name>M_ALM</name>
<desc>Interrupt mask for alarm signals from XADC.</desc>
<sw_param offset="0xf8007108" start="6" end="0" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_MSTS_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf800710c" start="31" end="20" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_MSTS_CFIFO_LVL">
<name>CFIFO_LVL</name>
<desc>Command FIFO level.</desc>
<sw_param offset="0xf800710c" start="19" end="16" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_MSTS_DFIFO_LVL">
<name>DFIFO_LVL</name>
<desc>Data FIFO level.</desc>
<sw_param offset="0xf800710c" start="15" end="12" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_MSTS_CFIFOF">
<name>CFIFOF</name>
<desc>Command FIFO full.</desc>
<sw_param offset="0xf800710c" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_MSTS_CFIFOE">
<name>CFIFOE</name>
<desc>Command FIFO empty.</desc>
<sw_param offset="0xf800710c" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_MSTS_DFIFOF">
<name>DFIFOF</name>
<desc>Data FIFO full.</desc>
<sw_param offset="0xf800710c" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_MSTS_DFIFOE">
<name>DFIFOE</name>
<desc>Data FIFO empty.</desc>
<sw_param offset="0xf800710c" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_MSTS_OT">
<name>OT</name>
<desc>Raw over temperature alarm from the XADC.
Latched version of the signal is available in the interrupt status register.</desc>
<sw_param offset="0xf800710c" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_MSTS_ALM">
<name>ALM</name>
<desc>Raw alarm signals from the XADC.
Latched version of the signals are available in the interrupt status register.</desc>
<sw_param offset="0xf800710c" start="6" end="0" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_CMDFIFO_CMD">
<name>CMD</name>
<desc>32-bit command.</desc>
<sw_param offset="0xf8007110" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_RDFIFO_RDDATA">
<name>RDDATA</name>
<desc>32-bit read data.</desc>
<sw_param offset="0xf8007114" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_MCTL_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8007118" start="31" end="5" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_MCTL_RESET">
<name>RESET</name>
<desc>This bit drives the XADC reset signal</desc>
<sw_param offset="0xf8007118" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_MCTL_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xf8007118" start="3" end="1" />
</parameter>
<parameter uniqueid="ps7_devcfg_XADCIF_MCTL_FLUSH">
<name>FLUSH</name>
<desc>Write to this bit location to flush the command and data FIFOs, this is a write only bit (for debugging)</desc>
<sw_param offset="0xf8007118" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_CONTROL_REGISTER_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8f00000" start="31" end="7" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_CONTROL_REGISTER_IC_standby_enable">
<name>IC_standby_enable</name>
<desc>When set, this stops the Interrupt Controller clock when no interrupts are pending, and no CPU is performing a read/write request.</desc>
<sw_param offset="0xf8f00000" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_CONTROL_REGISTER_SCU_standby_enable">
<name>SCU_standby_enable</name>
<desc>When set, SCU CLK is turned off when all processors are in WFI mode,
there is no pending request on the ACP (if implemented), and there is no
remaining activity in the SCU.
When SCU CLK is off, ARREADYS, AWREADYS and WREADYS on
the ACP are forced LOW. The clock is turned on when any processor
leaves WFI mode, or if there is a new request on the ACP.</desc>
<sw_param offset="0xf8f00000" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_CONTROL_REGISTER_Force_all_Device_to_port0_enable">
<name>Force_all_Device_to_port0_enable</name>
<desc>When set, all requests from the ACP or processors with AxCACHE =
NonCacheable Bufferable are forced to be issued on the AXI Master port
M0.</desc>
<sw_param offset="0xf8f00000" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_CONTROL_REGISTER_SCU_Speculative_linefills_enable">
<name>SCU_Speculative_linefills_enable</name>
<desc>When set, coherent linefill requests are sent speculatively to the L2C-310
in parallel with the tag look-up. If the tag look-up misses, the confirmed
linefill is sent to the L2C-310 and gets RDATA earlier because the data
request was already initiated by the speculative request. This feature works
only if the L2C-310 is present in the design.</desc>
<sw_param offset="0xf8f00000" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_CONTROL_REGISTER_SCU_RAMs_Parity_enable">
<name>SCU_RAMs_Parity_enable</name>
<desc>1 = Parity on.
0 = Parity off. This is the default setting.
This bit is always zero if support for parity is not implemented.</desc>
<sw_param offset="0xf8f00000" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_CONTROL_REGISTER_Address_filtering_enable">
<name>Address_filtering_enable</name>
<desc>1 = Addressing filtering on.
0 = Addressing filtering off.
The default value is the value of FILTEREN sampled when nSCURESET
is deasserted.
This bit is always zero if the SCU is implemented in the single master port
configuration.</desc>
<sw_param offset="0xf8f00000" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_CONTROL_REGISTER_SCU_enable">
<name>SCU_enable</name>
<desc>1 = SCU enable.
0 = SCU disable. This is the default setting</desc>
<sw_param offset="0xf8f00000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_CONFIGURATION_REGISTER_reserved_1">
<name>reserved_1</name>
<desc>Should Be Zero (SBZ)</desc>
<sw_param offset="0xf8f00004" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_CONFIGURATION_REGISTER_Tag_RAM_sizes">
<name>Tag_RAM_sizes</name>
<desc>Bits [15:14] indicate Cortex-A9 processor CPU3 tag RAM size if present.
Bits [13:12] indicate Cortex-A9 processor CPU2 tag RAM size if present.
Bits [11:10] indicate Cortex-A9 processor CPU1 tag RAM size if present.
Bits [9:8] indicate Cortex-A9 processor CPU0 tag RAM size.
The encoding is as follows:
b11 = reserved
b10 = 64KB cache, 256 indexes per tag RAM
b01 = 32KB cache, 128 indexes per tag RAM
b00 = 16KB cache, 64 indexes per tag RAM.</desc>
<sw_param offset="0xf8f00004" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_CONFIGURATION_REGISTER_CPUs_SMP">
<name>CPUs_SMP</name>
<desc>Shows the Cortex-A9 processors that are in Symmetric Multi-processing (SMP) or
Asymmetric Multi-processing (AMP) mode.
0 = this Cortex-A9 processor is in AMP mode not taking part in coherency or not present.
1 = this Cortex-A9 processor is in SMP mode taking part in coherency.
Bit 7 is for CPU3
Bit 6 is for CPU2
Bit 5 is for CPU1
Bit 4 is for CPU0.</desc>
<sw_param offset="0xf8f00004" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_CONFIGURATION_REGISTER_reserved">
<name>reserved</name>
<desc>Should Be Zero (SBZ)</desc>
<sw_param offset="0xf8f00004" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_CONFIGURATION_REGISTER_CPU_number">
<name>CPU_number</name>
<desc>Number of CPUs present in the Cortex-A9 MPCore processor
b11 = four Cortex-A9 processors, CPU0, CPU1, CPU2, and CPU3
b10 = three Cortex-A9 processors, CPU0, CPU1, and CPU2
b01 = two Cortex-A9 processors, CPU0 and CPU1
b00 = one Cortex-A9 processor, CPU0.</desc>
<sw_param offset="0xf8f00004" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_CPU_Power_Status_Register_reserved_3">
<name>reserved_3</name>
<desc>Should Be Zero (SBZ)</desc>
<sw_param offset="0xf8f00008" start="31" end="26" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_CPU_Power_Status_Register_CPU3_status">
<name>CPU3_status</name>
<desc>Power status of the Cortex-A9 processor:
b00: Normal mode.
b01: Reserved.
b10: the Cortex-A9 processor is about to enter (or is in) dormant mode. No coherency
request is sent to the Cortex-A9 processor.
b11: the Cortex-A9 processor is about to enter (or is in) powered-off mode, or is nonpresent.
No coherency request is sent to the Cortex-A9 processor.</desc>
<sw_param offset="0xf8f00008" start="25" end="24" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_CPU_Power_Status_Register_reserved_2">
<name>reserved_2</name>
<desc>Should Be Zero (SBZ)</desc>
<sw_param offset="0xf8f00008" start="23" end="18" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_CPU_Power_Status_Register_CPU2_status">
<name>CPU2_status</name>
<desc>Power status of the Cortex-A9 processor</desc>
<sw_param offset="0xf8f00008" start="17" end="16" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_CPU_Power_Status_Register_reserved_1">
<name>reserved_1</name>
<desc>Should Be Zero (SBZ)</desc>
<sw_param offset="0xf8f00008" start="15" end="10" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_CPU_Power_Status_Register_CPU1_status">
<name>CPU1_status</name>
<desc>Power status of the Cortex-A9 processor</desc>
<sw_param offset="0xf8f00008" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_CPU_Power_Status_Register_reserved">
<name>reserved</name>
<desc>Should Be Zero (SBZ)</desc>
<sw_param offset="0xf8f00008" start="7" end="2" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_CPU_Power_Status_Register_CPU0_status">
<name>CPU0_status</name>
<desc>Power status of the Cortex-A9 processor</desc>
<sw_param offset="0xf8f00008" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_Invalidate_All_Registers_in_Secure_State_NA">
<name>NA</name>
<desc>NA</desc>
<sw_param offset="0xf8f0000c" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_Invalidate_All_Registers_in_Secure_State_CPU3_ways">
<name>CPU3_ways</name>
<desc>Specifies the ways that must be invalidated for CPU3. Writing to these bits has no effect if the
Cortex-A9 MPCore processor has fewer than four processors.</desc>
<sw_param offset="0xf8f0000c" start="15" end="12" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_Invalidate_All_Registers_in_Secure_State_CPU2_ways">
<name>CPU2_ways</name>
<desc>Specifies the ways that must be invalidated for CPU2. Writing to these bits has no effect if the
Cortex-A9 MPCore processor has fewer than three processors</desc>
<sw_param offset="0xf8f0000c" start="11" end="8" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_Invalidate_All_Registers_in_Secure_State_CPU1_ways">
<name>CPU1_ways</name>
<desc>Specifies the ways that must be invalidated for CPU1. Writing to these bits has no effect if the
Cortex-A9 MPCore processor has fewer than two processors.</desc>
<sw_param offset="0xf8f0000c" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_Invalidate_All_Registers_in_Secure_State_CPU0_ways">
<name>CPU0_ways</name>
<desc>Specifies the ways that must be invalidated for CPU0</desc>
<sw_param offset="0xf8f0000c" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_Filtering_Start_Address_Register_Filtering_start_address">
<name>Filtering_start_address</name>
<desc>Start address for use with master port 1 in a two-master port configuration when
address filtering is enabled.
The default value is the value of FILTERSTART sampled on exit from reset. The
value on the pin gives the upper address bits with 1MB granularity.</desc>
<sw_param offset="0xf8f00040" start="31" end="20" />
</parameter>
<parameter uniqueid="ps7_mpcore_Filtering_Start_Address_Register_SBZ">
<name>SBZ</name>
<desc>SBZ</desc>
<sw_param offset="0xf8f00040" start="19" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_Filtering_End_Address_Register_Filtering_end_address">
<name>Filtering_end_address</name>
<desc>End address for use with master port 1 in a two-master port configuration, when
address filtering is enabled.
The default value is the value of FILTEREND sampled on exit from reset. The value
on the pin gives the upper address bits with 1MB granularity.</desc>
<sw_param offset="0xf8f00044" start="31" end="20" />
</parameter>
<parameter uniqueid="ps7_mpcore_Filtering_End_Address_Register_SBZ">
<name>SBZ</name>
<desc>SBZ</desc>
<sw_param offset="0xf8f00044" start="19" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_Access_Control_Register_SAC_a">
<name>a</name>
<desc>SBZ</desc>
<sw_param offset="0xf8f00050" start="31" end="4" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_Access_Control_Register_SAC_CPU3">
<name>CPU3</name>
<desc>0 = CPU3 cannot access the components.
1 = CPU3 can access the components. This is the default.</desc>
<sw_param offset="0xf8f00050" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_Access_Control_Register_SAC_CPU2">
<name>CPU2</name>
<desc>0 = CPU2 cannot access the components.
1 = CPU2 can access the components. This is the default.</desc>
<sw_param offset="0xf8f00050" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_Access_Control_Register_SAC_CPU1">
<name>CPU1</name>
<desc>0 = CPU1 cannot access the components.
1 = CPU1 can access the components. This is the default.</desc>
<sw_param offset="0xf8f00050" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_Access_Control_Register_SAC_CPU0">
<name>CPU0</name>
<desc>0 = CPU0 cannot access the components.
1 = CPU0 can access the components. This is the default.</desc>
<sw_param offset="0xf8f00050" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_Non_secure_Access_Control_Register_SBZ">
<name>SBZ</name>
<desc>SBZ</desc>
<sw_param offset="0xf8f00054" start="31" end="12" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_Non_secure_Access_Control_Register_CPU3_global_timer">
<name>CPU3_global_timer</name>
<desc>same as above</desc>
<sw_param offset="0xf8f00054" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_Non_secure_Access_Control_Register_CPU2_global_timer">
<name>CPU2_global_timer</name>
<desc>same as above</desc>
<sw_param offset="0xf8f00054" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_Non_secure_Access_Control_Register_CPU1_global_timer">
<name>CPU1_global_timer</name>
<desc>same as above</desc>
<sw_param offset="0xf8f00054" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_Non_secure_Access_Control_Register_CPU0_global_timer">
<name>CPU0_global_timer</name>
<desc>Non-secure access to the global timer for CPU&lt;n&gt;.
* &lt;n&gt; is 3 for bit[11]
* &lt;n&gt; is 2 for bit[10]
* &lt;n&gt; is 1 for bit[9]
* &lt;n&gt; is 0 for bit[8].
0 = Secure accesses only. This is the default value.
1 = Secure accesses and Non-Secure accesses.</desc>
<sw_param offset="0xf8f00054" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_Non_secure_Access_Control_Register_Private_timers_for_CPU3">
<name>Private_timers_for_CPU3</name>
<desc>same as above</desc>
<sw_param offset="0xf8f00054" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_Non_secure_Access_Control_Register_Private_timers_for_CPU2">
<name>Private_timers_for_CPU2</name>
<desc>same as above</desc>
<sw_param offset="0xf8f00054" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_Non_secure_Access_Control_Register_Private_timers_for_CPU1">
<name>Private_timers_for_CPU1</name>
<desc>same as above</desc>
<sw_param offset="0xf8f00054" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_Non_secure_Access_Control_Register_Private_timers_for_CPU0">
<name>Private_timers_for_CPU0</name>
<desc>Non-secure access to the private timer and watchdog for CPU&lt;n&gt;.
* &lt;n&gt; is 3 for bit[7]
* &lt;n&gt; is 2 for bit[6]]
* &lt;n&gt; is 1 for bit[5]
* &lt;n&gt; is 0 for bit[4].
0 = Secure accesses only. Non-secure reads return 0. This is the default value.
1 = Secure accesses and Non-secure accesses.</desc>
<sw_param offset="0xf8f00054" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_Non_secure_Access_Control_Register_Component_access_for_CPU3">
<name>Component_access_for_CPU3</name>
<desc>same as above</desc>
<sw_param offset="0xf8f00054" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_Non_secure_Access_Control_Register_Component_access_for_CPU2">
<name>Component_access_for_CPU2</name>
<desc>same as above</desc>
<sw_param offset="0xf8f00054" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_Non_secure_Access_Control_Register_Component_access_for_CPU1">
<name>Component_access_for_CPU1</name>
<desc>same as above</desc>
<sw_param offset="0xf8f00054" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_mpcore_SCU_Non_secure_Access_Control_Register_Component_access_for_CPU0">
<name>Component_access_for_CPU0</name>
<desc>Non-secure access to the components for CPU&lt;n&gt;.
* &lt;n&gt; is 3 for bit[3]
* &lt;n&gt; is 2 for bit[2]]
* &lt;n&gt; is 1 for bit[1]
* &lt;n&gt; is 0 for bit[0].
0 = CPU cannot write the componentsa
1 = CPU can access the componentsa.</desc>
<sw_param offset="0xf8f00054" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICCICR_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f00100" start="31" end="5" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICCICR_SBPR">
<name>SBPR</name>
<desc>Controls wheterh the CPU interface uses the Secure or Non-secure Binary Point Register for preemption.
0: use the Secure Binary Point Register for Secure interrupts, and use the Non-secure Binary Point Register for Non-secure interrupts.
1: use the Secure Binary Point Register for both Secure and Non-secure interrupts.</desc>
<sw_param offset="0xf8f00100" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICCICR_FIQEn">
<name>FIQEn</name>
<desc>Controls whether the GIC signals Secure interrupts to a target processor using the FIQ or the IRQ signal.
0: using IRQ, 1: using FIQ.
The GIC always signals Non-secure interrrupts using IRQ.</desc>
<sw_param offset="0xf8f00100" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICCICR_AckCtl">
<name>AckCtl</name>
<desc>Controls whether a Secure read of the ICCIAR, when the highest priority pending interrupt is Non-ssecure, causes the CPU interface to acknowledge the interrupt.</desc>
<sw_param offset="0xf8f00100" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICCICR_EnableNS">
<name>EnableNS</name>
<desc>An alias of the Enable bit in the Non-secure ICCICR.
This alias bit means Secure software can enable the aisngalling of Non-secure nterrupts.</desc>
<sw_param offset="0xf8f00100" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICCICR_EnableS">
<name>EnableS</name>
<desc>Global enable for the signalling of Secure interrupts by the CPU itnerfaces to the connected processors.</desc>
<sw_param offset="0xf8f00100" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICCPMR_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f00104" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICCPMR_Priority">
<name>Priority</name>
<desc>The priority mask level for the CPU interface.
If the priority of an interrupt is higher than the value indicated by this field, the interface signals the interrupt to the processor.</desc>
<sw_param offset="0xf8f00104" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICCBPR_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f00108" start="31" end="3" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICCBPR_Binary_point">
<name>Binary_point</name>
<desc>The value of this field controls thow the 8-bit interrupt priority field is split into a group priority field, used to determine interrupt preemptioin, and a subpriority field.</desc>
<sw_param offset="0xf8f00108" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICCIAR_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f0010c" start="31" end="13" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICCIAR_CPUID">
<name>CPUID</name>
<desc>Identifies the processor that requested the interrupt.
Returens the number of the CPU interface that made the request.</desc>
<sw_param offset="0xf8f0010c" start="12" end="10" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICCIAR_ACKINTID">
<name>ACKINTID</name>
<desc>The interrupt ID.
This read acts as an acknowledge for the interrupt.</desc>
<sw_param offset="0xf8f0010c" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICCEOIR_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f00110" start="31" end="13" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICCEOIR_CPUID">
<name>CPUID</name>
<desc>On completion of the processing of an SGI, this field contains the CPUID value from the corresponding ICCIAR access.</desc>
<sw_param offset="0xf8f00110" start="12" end="10" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICCEOIR_EOIINTID">
<name>EOIINTID</name>
<desc>The ACKINTID value from the corresponding ICCIAR access.</desc>
<sw_param offset="0xf8f00110" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICCRPR_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f00114" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICCRPR_Priority">
<name>Priority</name>
<desc>The priority value of the highest priority intrerrupt that is active on the CPU itnerface.</desc>
<sw_param offset="0xf8f00114" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICCHPIR_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f00118" start="31" end="13" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICCHPIR_CPUID">
<name>CPUID</name>
<desc>If the PENDINTID field returns the ID of an SGI, this field contatins the CPUID value for that interrupt.
The identifies the processor that generated the itnerrupt.</desc>
<sw_param offset="0xf8f00118" start="12" end="10" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICCHPIR_PENDINTID">
<name>PENDINTID</name>
<desc>The interrupt ID of the highest priority pending interrupt.</desc>
<sw_param offset="0xf8f00118" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICCABPR_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f0011c" start="31" end="3" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICCABPR_Binary_point">
<name>Binary_point</name>
<desc>Provides an alias of the Non-secure ICCBPR.</desc>
<sw_param offset="0xf8f0011c" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICCIDR_Part_number">
<name>Part_number</name>
<desc>Identifies the peripheral</desc>
<sw_param offset="0xf8f001fc" start="31" end="20" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICCIDR_Architecture_version">
<name>Architecture_version</name>
<desc>Identifies the architecture version</desc>
<sw_param offset="0xf8f001fc" start="19" end="16" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICCIDR_Revision_number">
<name>Revision_number</name>
<desc>Returns the revision number of the Interrupt Controller. The implementer defines the
format of this field.</desc>
<sw_param offset="0xf8f001fc" start="15" end="12" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICCIDR_Implementer">
<name>Implementer</name>
<desc>Returns the JEP106 code of the company that implemented the Cortex-A9 processor
interface RTL. It uses the following construct:
[11:8] the JEP106 continuation code of the implementer
[7] 0
[6:0] the JEP106 code [6:0] of the implementer</desc>
<sw_param offset="0xf8f001fc" start="11" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_Global_Timer_Counter_Register0_a">
<name>a</name>
<desc>There are two timer counter registers. They are the lower 32-bit timer counter at offset
0x00 and the upper 32-bit timer counter at offset 0x04.
You must access these registers with 32-bit accesses. You cannot use STRD/LDRD.
To modify the register proceed as follows:
1. Clear the timer enable bit in the Global Timer Control Register
2. Write the lower 32-bit timer counter register
3. Write the upper 32-bit timer counter register
4. Set the timer enable bit.
To get the value from the Global Timer Counter register proceed as follows:
1. Read the upper 32-bit timer counter register
2. Read the lower 32-bit timer counter register
3. Read the upper 32-bit timer counter register again. If the value is different to the
32-bit upper value read previously, go back to step 2. Otherwise the 64-bit timer
counter value is correct.</desc>
<sw_param offset="0xf8f00200" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_Global_Timer_Counter_Register1_a">
<name>a</name>
<desc>There are two timer counter registers. They are the lower 32-bit timer counter at offset
0x00 and the upper 32-bit timer counter at offset 0x04.
You must access these registers with 32-bit accesses. You cannot use STRD/LDRD.
To modify the register proceed as follows:
1. Clear the timer enable bit in the Global Timer Control Register
2. Write the lower 32-bit timer counter register
3. Write the upper 32-bit timer counter register
4. Set the timer enable bit.
To get the value from the Global Timer Counter register proceed as follows:
1. Read the upper 32-bit timer counter register
2. Read the lower 32-bit timer counter register
3. Read the upper 32-bit timer counter register again. If the value is different to the
32-bit upper value read previously, go back to step 2. Otherwise the 64-bit timer
counter value is correct.</desc>
<sw_param offset="0xf8f00204" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_Global_Timer_Control_Register_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xf8f00208" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_mpcore_Global_Timer_Control_Register_Prescaler">
<name>Prescaler</name>
<desc>The prescaler modifies the clock period for the decrementing event for the Counter
Register. See Calculating timer intervals on page 4-2 for the equation</desc>
<sw_param offset="0xf8f00208" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_mpcore_Global_Timer_Control_Register_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8f00208" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_mpcore_Global_Timer_Control_Register_a">
<name>a</name>
<desc>This bit is banked per Cortex-A9 processor.
1'b0: single shot mode.
When the counter reaches the comparator value, sets the event flag. It is the responsibility
of software to update the comparator value to get further events.
1'b1: auto increment mode.
Each time the counter reaches the comparator value, the comparator register is
incremented with the auto-increment register, so that further events can be set periodically
without any software updates.</desc>
<sw_param offset="0xf8f00208" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_mpcore_Global_Timer_Control_Register_IRQ_Enable">
<name>IRQ_Enable</name>
<desc>This bit is banked per Cortex-A9 processor.
If set, the interrupt ID 27 is set as pending in the Interrupt Distributor when the event flag
is set in the Timer Status Register.</desc>
<sw_param offset="0xf8f00208" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_mpcore_Global_Timer_Control_Register_Comp_Enablea">
<name>Comp_Enablea</name>
<desc>This bit is banked per Cortex-A9 processor.
If set, it allows the comparison between the 64-bit Timer Counter and the related 64-bit
Comparator Register.</desc>
<sw_param offset="0xf8f00208" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_mpcore_Global_Timer_Control_Register_Timer_Enable">
<name>Timer_Enable</name>
<desc>Timer enable
1'b0 = Timer is disabled and the counter does not increment.
All registers can still be read and written
1'b1 = Timer is enabled and the counter increments normally</desc>
<sw_param offset="0xf8f00208" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_Global_Timer_Interrupt_Status_Register_reserved">
<name>reserved</name>
<desc>UNK/SBZP</desc>
<sw_param offset="0xf8f0020c" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_mpcore_Global_Timer_Interrupt_Status_Register_Event_flag">
<name>Event_flag</name>
<desc>This is a banked register for all Cortex-A9 processors present.
The event flag is a sticky bit that is automatically set when the Counter Register reaches
the Comparator Register value. If the timer interrupt is enabled, Interrupt ID 27 is set as
pending in the Interrupt Distributor after the event flag is set. The event flag is cleared
when written to 1. Figure 4-7 shows the Global Timer Interrupt Status Register bit
assignment.</desc>
<sw_param offset="0xf8f0020c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_Comparator_Value_Register0_a">
<name>a</name>
<desc>There are two 32-bit registers, the lower 32-bit comparator value register at offset 0x10
and the upper 32-bit comparator value register at offset 0x14.
You must access these registers with 32-bit accesses. You cannot use STRD/LDRD. There
is a Comparator Value Register for each Cortex-A9 processor.
To ensure that updates to this register do not set the Interrupt Status Register proceed as
follows:
1. Clear the Comp Enable bit in the Timer Control Register.
2. Write the lower 32-bit Comparator Value Register.
3. Write the upper 32-bit Comparator Value Register.
4. Set the Comp Enable bit and, if necessary, the IRQ enable bit.</desc>
<sw_param offset="0xf8f00210" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_Comparator_Value_Register1_a">
<name>a</name>
<desc>There are two 32-bit registers, the lower 32-bit comparator value register at offset 0x10
and the upper 32-bit comparator value register at offset 0x14.
You must access these registers with 32-bit accesses. You cannot use STRD/LDRD. There
is a Comparator Value Register for each Cortex-A9 processor.
To ensure that updates to this register do not set the Interrupt Status Register proceed as
follows:
1. Clear the Comp Enable bit in the Timer Control Register.
2. Write the lower 32-bit Comparator Value Register.
3. Write the upper 32-bit Comparator Value Register.
4. Set the Comp Enable bit and, if necessary, the IRQ enable bit.</desc>
<sw_param offset="0xf8f00214" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_Auto_increment_Register_a">
<name>a</name>
<desc>Auto-increment Register
This 32-bit register gives the increment value of the Comparator Register when the
Auto-increment bit is set in the Timer Control Register. Each Cortex-A9 processor
present has its own Auto-increment Register
If the comp enable and auto-increment bits are set when the global counter reaches the
Comparator Register value, the comparator is incremented by the auto-increment value,
so that a new event can be set periodically.
The global timer is not affected and goes on incrementing</desc>
<sw_param offset="0xf8f00218" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_Private_Timer_Load_Register_a">
<name>a</name>
<desc>The Timer Load Register contains the value copied to the Timer Counter Register when
it decrements down to zero with auto reload mode enabled. Writing to the Timer Load
Register means that you also write to the Timer Counter Register.</desc>
<sw_param offset="0xf8f00600" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_Private_Timer_Counter_Register_a">
<name>a</name>
<desc>The Timer Counter Register is a decrementing counter.
The Timer Counter Register decrements if the timer is enabled using the timer enable
bit in the Timer Control Register. If a Cortex-A9 processor timer is in debug state, the
counter only decrements when the Cortex-A9 processor returns to non debug state.
When the Timer Counter Register reaches zero and auto reload mode is enabled, it
reloads the value in the Timer Load Register and then decrements from that value. If
auto reload mode is not enabled, the Timer Counter Register decrements down to zero
and stops.
When the Timer Counter Register reaches zero, the timer interrupt status event flag is
set and the interrupt ID 29 is set as pending in the Interrupt Distributor, if interrupt
generation is enabled in the Timer Control Register.
Writing to the Timer Counter Register or Timer Load Register forces the Timer Counter
Register to decrement from the newly written value.</desc>
<sw_param offset="0xf8f00604" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_Private_Timer_Control_Register_SBZP">
<name>SBZP</name>
<desc>UNK/SBZP.</desc>
<sw_param offset="0xf8f00608" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_mpcore_Private_Timer_Control_Register_Prescaler">
<name>Prescaler</name>
<desc>The prescaler modifies the clock period for the decrementing event for the Counter
Register. See Calculating timer intervals on page 4-2 for the equation.\'5c</desc>
<sw_param offset="0xf8f00608" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_mpcore_Private_Timer_Control_Register_UNK_SBZP">
<name>UNK_SBZP</name>
<desc>UNK/SBZP.</desc>
<sw_param offset="0xf8f00608" start="7" end="3" />
</parameter>
<parameter uniqueid="ps7_mpcore_Private_Timer_Control_Register_IRQ_Enable">
<name>IRQ_Enable</name>
<desc>If set, the interrupt ID 29 is set as pending in the Interrupt Distributor when the event flag
is set in the Timer Status Register.</desc>
<sw_param offset="0xf8f00608" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_mpcore_Private_Timer_Control_Register_Auto_reload">
<name>Auto_reload</name>
<desc>1'b0 = Single shot mode.
Counter decrements down to zero, sets the event flag and stops.
1'b1 = Auto-reload mode.
Each time the Counter Register reaches zero, it is reloaded with the value contained in the
Timer Load Register.</desc>
<sw_param offset="0xf8f00608" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_mpcore_Private_Timer_Control_Register_Timer_Enable">
<name>Timer_Enable</name>
<desc>Timer enable
1'b0 = Timer is disabled and the counter does not decrement.
All registers can still be read and written
1'b1 = Timer is enabled and the counter decrements normally</desc>
<sw_param offset="0xf8f00608" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_Private_Timer_Interrupt_Status_Register_UNK_SBZP">
<name>UNK_SBZP</name>
<desc>UNK/SBZP</desc>
<sw_param offset="0xf8f0060c" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_mpcore_Private_Timer_Interrupt_Status_Register_a">
<name>a</name>
<desc>This is a banked register for all Cortex-A9 processors present.
The event flag is a sticky bit that is automatically set when the Counter Register reaches
zero. If the timer interrupt is enabled, Interrupt ID 29 is set as pending in the Interrupt
Distributor after the event flag is set. The event flag is cleared when written to 1.</desc>
<sw_param offset="0xf8f0060c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_Watchdog_Load_Register_a">
<name>a</name>
<desc>Watchdog Load Register
The Watchdog Load Register contains the value copied to the Watchdog Counter
Register when it decrements down to zero with auto reload mode enabled, in Timer
mode. Writing to the Watchdog Load Register means that you also write to the
Watchdog Counter Register</desc>
<sw_param offset="0xf8f00620" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_Watchdog_Counter_Register_a">
<name>a</name>
<desc>Watchdog Counter Register
The Watchdog Counter Register is a down counter.
It decrements if the Watchdog is enabled using the Watchdog enable bit in the Watchdog
Control Register. If the Cortex-A9 processor associated with the Watchdog is in debug
state, the counter does not decrement until the Cortex-A9 processor returns to non
debug state.
When the Watchdog Counter Register reaches zero and auto reload mode is enabled,
and in timer mode, it reloads the value in the Watchdog Load Register and then
decrements from that value. If auto reload mode is not enabled or the watchdog is not
in timer mode, the Watchdog Counter Register decrements down to zero and stops.
When in watchdog mode the only way to update the Watchdog Counter Register is to
write to the Watchdog Load Register. When in timer mode the Watchdog Counter
Register is write accessible.
The behavior of the watchdog when the Watchdog Counter Register reaches zero
depends on its current mode:
Timer mode When the Watchdog Counter Register reaches zero, the watchdog
interrupt status event flag is set and the interrupt ID 30 is set as pending
in the Interrupt Distributor, if interrupt generation is enabled in the
Watchdog Control Register.
Watchdog mode
If a software failure prevents the Watchdog Counter Register from being
refreshed, the Watchdog Counter Register reaches zero, the Watchdog
reset status flag is set and the associated WDRESETREQ reset request
output pin is asserted. The external reset source is then responsible for
resetting all or part of the Cortex-A9 MPCore design.</desc>
<sw_param offset="0xf8f00624" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_Watchdog_Control_Register_reserved">
<name>reserved</name>
<desc>Reserved.</desc>
<sw_param offset="0xf8f00628" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_mpcore_Watchdog_Control_Register_Prescaler">
<name>Prescaler</name>
<desc>The prescaler modifies the clock period for the decrementing event for the Counter
Register.</desc>
<sw_param offset="0xf8f00628" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_mpcore_Watchdog_Control_Register_a">
<name>a</name>
<desc>Reserved.</desc>
<sw_param offset="0xf8f00628" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_mpcore_Watchdog_Control_Register_Watchdog_mode">
<name>Watchdog_mode</name>
<desc>1'b0 = Timer mode, default
Writing a zero to this bit has no effect. You must use the Watchdog Disable Register to
put the watchdog into timer mode. See Watchdog Disable Register on page 4-9.
1'b1 = Watchdog mode.</desc>
<sw_param offset="0xf8f00628" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_mpcore_Watchdog_Control_Register_IT_Enable">
<name>IT_Enable</name>
<desc>If set, the interrupt ID 30 is set as pending in the Interrupt Distributor when the event flag
is set in the watchdog Status Register.
In watchdog mode this bit is ignored</desc>
<sw_param offset="0xf8f00628" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_mpcore_Watchdog_Control_Register_Auto_reload">
<name>Auto_reload</name>
<desc>1'b0 = Single shot mode.
Counter decrements down to zero, sets the event flag and stops.
1'b1 = Auto-reload mode.
Each time the Counter Register reaches zero, it is reloaded with the value contained in the
Load Register and then continues decrementing.</desc>
<sw_param offset="0xf8f00628" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_mpcore_Watchdog_Control_Register_Watchdog_Enable">
<name>Watchdog_Enable</name>
<desc>Global watchdog enable
1'b0 = Watchdog is disabled and the counter does not decrement. All registers can still be
read and /or written
1'b1 = Watchdog is enabled and the counter decrements normally.</desc>
<sw_param offset="0xf8f00628" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_Watchdog_Interrupt_Status_Register_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8f0062c" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_mpcore_Watchdog_Interrupt_Status_Register_Event_flag">
<name>Event_flag</name>
<desc>The event flag is a sticky bit that is automatically set when the Counter Register reaches
zero in timer mode. If the watchdog interrupt is enabled, Interrupt ID 30 is set as
pending in the Interrupt Distributor after the event flag is set. The event flag is cleared
when written with a value of 1. Trying to write a zero to the event flag or a one when it
is not set has no effect.</desc>
<sw_param offset="0xf8f0062c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_Watchdog_Reset_Status_Register_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8f00630" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_mpcore_Watchdog_Reset_Status_Register_Reset_flag">
<name>Reset_flag</name>
<desc>The reset flag is a sticky bit that is automatically set when the Counter Register reaches
zero and a reset request is sent accordingly. (In watchdog mode)
The reset flag is cleared when written with a value of 1. Trying to write a zero to the
reset flag or a one when it is not set has no effect. This flag is not reset by normal
Cortex-A9 processor resets but has its own reset line, nWDRESET. nWDRESET must
not be asserted when the Cortex-A9 processor reset assertion is the result of a watchdog
reset request with WDRESETREQ. This distinction enables software to differentiate
between a normal boot sequence, reset flag is zero, and one caused by a previous
watchdog time-out, reset flag set to one.</desc>
<sw_param offset="0xf8f00630" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_Watchdog_Disable_Register_a">
<name>a</name>
<desc>Watchdog Disable Register
Use the Watchdog Disable Register to switch from watchdog to timer mode. The
software must write 0x12345678 then 0x87654321 successively to the Watchdog Disable
Register so that the watchdog mode bit in the Watchdog Control Register is set to zero.
If one of the values written to the Watchdog Disable Register is incorrect or if any other
write occurs in between the two word writes, the watchdog remains in its current state.
To reactivate the Watchdog, the software must write 1 to the watchdog mode bit of the
Watchdog Control Register.</desc>
<sw_param offset="0xf8f00634" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDDCR_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8f01000" start="31" end="2" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDDCR_Enable_Non_secure">
<name>Enable_Non_secure</name>
<desc>0 = disables all Non-secure interrupts control bits in the distributor from changing state
because of any external stimulus change that occurs on the corresponding SPI or PPI
signals
1 = enables the distributor to update register locations for Non-secure interrupts
FOR: ICDDCR_for_Non_secure_mode
31,1 --&gt; Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8f01000" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDDCR_Enable_secure">
<name>Enable_secure</name>
<desc>0 = disables all Secure interrupt control bits in the distributor from changing state
because of any external stimulus change that occurs on the corresponding SPI or PPI
signals.
1 = enables the distributor to update register locations for Secure interrupts.
FOR: ICDDCR_for_Non_secure_mode
0 --&gt; Enable_Non_secure --&gt; 0 = disables all Non-secure interrupts control bits in the
distributor from changing state because of any external
stimulus change that occurs on the corresponding SPI or
PPI signals
1 = enables the distributor to update register locations for
Non-secure interrupts</desc>
<sw_param offset="0xf8f01000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDICTR_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero.</desc>
<sw_param offset="0xf8f01004" start="31" end="29" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDICTR_LSPI">
<name>LSPI</name>
<desc>Returns the number of Lockable Shared Peripheral Interrupts (LSPIs) that the controller
contains. The encoding is:
b11111 = 31 LSPIs, which are the interrupts of IDs 32-62.
When CFGSDISABLE is HIGH then the interrupt controller prevents writes to any
register locations that control the operating state of an LSPI.</desc>
<sw_param offset="0xf8f01004" start="15" end="11" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDICTR_SecurityExtn">
<name>SecurityExtn</name>
<desc>Returns the number of security domains that the controller contains:
1 = the controller contains two security domains.
This bit always returns the value one.</desc>
<sw_param offset="0xf8f01004" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDICTR_SBZ">
<name>SBZ</name>
<desc>Reserved</desc>
<sw_param offset="0xf8f01004" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDICTR_CPU_Number">
<name>CPU_Number</name>
<desc>The encoding is:
b000 the Cortex-A9 MPCore configuration contains one Cortex-A9 processor.
b001 the Cortex-A9 MPCore configuration contains two Cortex-A9 processors.
b010 the Cortex-A9 MPCore configuration contains three Cortex-A9 processors.
b011 the Cortex-A9 MPCore configuration contains four Cortex-A9 processors.
b1xx: Unused values.</desc>
<sw_param offset="0xf8f01004" start="7" end="5" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDICTR_IT_Lines_Number">
<name>IT_Lines_Number</name>
<desc>The encoding is:
b00000 = the distributor provides 32 interruptsa, no external interrupt lines.
b00001 = the distributor provides 64 interrupts, 32 external interrupt lines.
b00010 = the distributor provides 96 interrupts, 64 external interrupt lines.
b00011 = the distributor provide 128 interrupts, 96 external interrupt lines.
b00100 = the distributor provides 160 interrupts, 128 external interrupt lines.
b00101 = the distributor provides 192 interrupts, 160 external interrupt lines.
b00110 = the distributor provides 224 interrupts, 192 external interrupt lines.
b00111 = the distributor provides 256 interrupts, 224 external interrupt lines.
All other values not used.</desc>
<sw_param offset="0xf8f01004" start="4" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIIDR_Implementation_Version">
<name>Implementation_Version</name>
<desc>Gives implementation version number</desc>
<sw_param offset="0xf8f01008" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIIDR_Revision_Number">
<name>Revision_Number</name>
<desc>Return the revision number of the controller</desc>
<sw_param offset="0xf8f01008" start="23" end="12" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIIDR_Implementer">
<name>Implementer</name>
<desc>Implementer Number</desc>
<sw_param offset="0xf8f01008" start="11" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDISR0_Security_Status">
<name>Security_Status</name>
<desc>The ICDISRn provide a Security status bit for each interupt supported by the GIC.
Each bit controls the security status of the corresponding interrupt.
Acessible by Secure accesses only.
The register addresses are RAZ/WI to Non-secure accesses.
ICDISR0 is banked for each connected processor.</desc>
<sw_param offset="0xf8f01080" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDISR1_Security_Status">
<name>Security_Status</name>
<desc>The ICDISRn provide a Security status bit for each interupt supported by the GIC.
Each bit controls the security status of the corresponding interrupt.
Acessible by Secure accesses only.
The register addresses are RAZ/WI to Non-secure accesses.
ICDISR0 is banked for each connected processor.</desc>
<sw_param offset="0xf8f01084" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDISR2_Security_Status">
<name>Security_Status</name>
<desc>The ICDISRn provide a Security status bit for each interupt supported by the GIC.
Each bit controls the security status of the corresponding interrupt.
Acessible by Secure accesses only.
The register addresses are RAZ/WI to Non-secure accesses.
ICDISR0 is banked for each connected processor.</desc>
<sw_param offset="0xf8f01088" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDISER0_Set">
<name>Set</name>
<desc>The ICDISERs provide a Set-enable bit for each interrupt supported by the GIC.
Writing 1 to a Set-enable bit enables forwarding of the corresponding interrupt to the CPU interfaces.
A register bit that corresponds to a Secure interrupt is RAZ/WI to Non-secure access.
ICDISER0 is banked for each connected processor.</desc>
<sw_param offset="0xf8f01100" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDISER1_Set">
<name>Set</name>
<desc>The ICDISERs provide a Set-enable bit for each interrupt supported by the GIC.
Writing 1 to a Set-enable bit enables forwarding of the corresponding interrupt to the CPU interfaces.
A register bit that corresponds to a Secure interrupt is RAZ/WI to Non-secure access.</desc>
<sw_param offset="0xf8f01104" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDISER2_Set">
<name>Set</name>
<desc>The ICDISERs provide a Set-enable bit for each interrupt supported by the GIC.
Writing 1 to a Set-enable bit enables forwarding of the corresponding interrupt to the CPU interfaces.
A register bit that corresponds to a Secure interrupt is RAZ/WI to Non-secure access.</desc>
<sw_param offset="0xf8f01108" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDICER0_Clear">
<name>Clear</name>
<desc>The ICDICERs provide a Clear-enable bit for each interrupt supported by the GIC.
Writing 1 to a Clear-enable bit disables forwarding of the corresponding interrupt to the CPU interfaces.
A register bit that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDICER0 is banked for each connected processor.</desc>
<sw_param offset="0xf8f01180" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDICER1_Clear">
<name>Clear</name>
<desc>The ICDICERs provide a Clear-enable bit for each interrupt supported by the GIC.
Writing 1 to a Clear-enable bit disables forwarding of the corresponding interrupt to the CPU interfaces.
A register bit that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.</desc>
<sw_param offset="0xf8f01184" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDICER2_Clear">
<name>Clear</name>
<desc>The ICDICERs provide a Clear-enable bit for each interrupt supported by the GIC.
Writing 1 to a Clear-enable bit disables forwarding of the corresponding interrupt to the CPU interfaces.
A register bit that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.</desc>
<sw_param offset="0xf8f01188" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDISPR0_Set">
<name>Set</name>
<desc>The ICDISPRs provide a Set-pending bit for each interrupt supported by the GIC.
Writing 1 to a Set-pending bit sets the status of the corresponding peripheral interrupt to pending.
A register bit that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDISPR0 is banked for each connected processor.</desc>
<sw_param offset="0xf8f01200" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDISPR1_Set">
<name>Set</name>
<desc>The ICDISPRs provide a Set-pending bit for each interrupt supported by the GIC.
Writing 1 to a Set-pending bit sets the status of the corresponding peripheral interrupt to pending.
A register bit that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDISPR0 is banked for each connected processor.</desc>
<sw_param offset="0xf8f01204" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDISPR2_Set">
<name>Set</name>
<desc>The ICDISPRs provide a Set-pending bit for each interrupt supported by the GIC.
Writing 1 to a Set-pending bit sets the status of the corresponding peripheral interrupt to pending.
A register bit that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDISPR0 is banked for each connected processor.</desc>
<sw_param offset="0xf8f01208" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDICPR0_Clear">
<name>Clear</name>
<desc>The ICDICPRs provide a Clear-pending bit for each interrupt supported by the GIC.
Writing 1 to a Clear-pending bit clears the status of the corresponding peripheral interrupt to pending.
A register bit that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDICPR0 is banked for each connected processor.</desc>
<sw_param offset="0xf8f01280" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDICPR1_Clear">
<name>Clear</name>
<desc>The ICDICPRs provide a Clear-pending bit for each interrupt supported by the GIC.
Writing 1 to a Clear-pending bit clears the status of the corresponding peripheral interrupt to pending.
A register bit that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDICPR0 is banked for each connected processor.</desc>
<sw_param offset="0xf8f01284" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDICPR2_Clear">
<name>Clear</name>
<desc>The ICDICPRs provide a Clear-pending bit for each interrupt supported by the GIC.
Writing 1 to a Clear-pending bit clears the status of the corresponding peripheral interrupt to pending.
A register bit that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDICPR0 is banked for each connected processor.</desc>
<sw_param offset="0xf8f01288" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDABR0_Active">
<name>Active</name>
<desc>The ICDABRs provide an Active bit for each interrupt supported by the GIC.
The bit reads as one if the status of the interrupt is active or acitve and pending.
Read the ICDSPR or ICDCPR to find the pending status of the interrupt.
ICDABR0 is banked for each connected processor.</desc>
<sw_param offset="0xf8f01300" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDABR1_Active">
<name>Active</name>
<desc>The ICDABRs provide an Active bit for each interrupt supported by the GIC.
The bit reads as one if the status of the interrupt is active or acitve and pending.
Read the ICDSPR or ICDCPR to find the pending status of the interrupt.
ICDABR0 is banked for each connected processor.</desc>
<sw_param offset="0xf8f01304" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDABR2_Active">
<name>Active</name>
<desc>The ICDABRs provide an Active bit for each interrupt supported by the GIC.
The bit reads as one if the status of the interrupt is active or acitve and pending.
Read the ICDSPR or ICDCPR to find the pending status of the interrupt.
ICDABR0 is banked for each connected processor.</desc>
<sw_param offset="0xf8f01308" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPR0_Priority">
<name>Priority</name>
<desc>The ICDIPRs provide an 8-bit Priority field for each interrupt supported by the GIC.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPR0 to ICDIPR7 are banekd for each connectred processor</desc>
<sw_param offset="0xf8f01400" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPR1_Priority">
<name>Priority</name>
<desc>The ICDIPRs provide an 8-bit Priority field for each interrupt supported by the GIC.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPR0 to ICDIPR7 are banekd for each connectred processor</desc>
<sw_param offset="0xf8f01404" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPR2_Priority">
<name>Priority</name>
<desc>The ICDIPRs provide an 8-bit Priority field for each interrupt supported by the GIC.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPR0 to ICDIPR7 are banekd for each connectred processor</desc>
<sw_param offset="0xf8f01408" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPR3_Priority">
<name>Priority</name>
<desc>The ICDIPRs provide an 8-bit Priority field for each interrupt supported by the GIC.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPR0 to ICDIPR7 are banekd for each connectred processor</desc>
<sw_param offset="0xf8f0140c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPR4_Priority">
<name>Priority</name>
<desc>The ICDIPRs provide an 8-bit Priority field for each interrupt supported by the GIC.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPR0 to ICDIPR7 are banekd for each connectred processor</desc>
<sw_param offset="0xf8f01410" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPR5_Priority">
<name>Priority</name>
<desc>The ICDIPRs provide an 8-bit Priority field for each interrupt supported by the GIC.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPR0 to ICDIPR7 are banekd for each connectred processor</desc>
<sw_param offset="0xf8f01414" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPR6_Priority">
<name>Priority</name>
<desc>The ICDIPRs provide an 8-bit Priority field for each interrupt supported by the GIC.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPR0 to ICDIPR7 are banekd for each connectred processor</desc>
<sw_param offset="0xf8f01418" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPR7_Priority">
<name>Priority</name>
<desc>The ICDIPRs provide an 8-bit Priority field for each interrupt supported by the GIC.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPR0 to ICDIPR7 are banekd for each connectred processor</desc>
<sw_param offset="0xf8f0141c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPR8_Priority">
<name>Priority</name>
<desc>The ICDIPRs provide an 8-bit Priority field for each interrupt supported by the GIC.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPR0 to ICDIPR7 are banekd for each connectred processor</desc>
<sw_param offset="0xf8f01420" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPR9_Priority">
<name>Priority</name>
<desc>The ICDIPRs provide an 8-bit Priority field for each interrupt supported by the GIC.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPR0 to ICDIPR7 are banekd for each connectred processor</desc>
<sw_param offset="0xf8f01424" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPR10_Priority">
<name>Priority</name>
<desc>The ICDIPRs provide an 8-bit Priority field for each interrupt supported by the GIC.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPR0 to ICDIPR7 are banekd for each connectred processor</desc>
<sw_param offset="0xf8f01428" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPR11_Priority">
<name>Priority</name>
<desc>The ICDIPRs provide an 8-bit Priority field for each interrupt supported by the GIC.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPR0 to ICDIPR7 are banekd for each connectred processor</desc>
<sw_param offset="0xf8f0142c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPR12_Priority">
<name>Priority</name>
<desc>The ICDIPRs provide an 8-bit Priority field for each interrupt supported by the GIC.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPR0 to ICDIPR7 are banekd for each connectred processor</desc>
<sw_param offset="0xf8f01430" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPR13_Priority">
<name>Priority</name>
<desc>The ICDIPRs provide an 8-bit Priority field for each interrupt supported by the GIC.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPR0 to ICDIPR7 are banekd for each connectred processor</desc>
<sw_param offset="0xf8f01434" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPR14_Priority">
<name>Priority</name>
<desc>The ICDIPRs provide an 8-bit Priority field for each interrupt supported by the GIC.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPR0 to ICDIPR7 are banekd for each connectred processor</desc>
<sw_param offset="0xf8f01438" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPR15_Priority">
<name>Priority</name>
<desc>The ICDIPRs provide an 8-bit Priority field for each interrupt supported by the GIC.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPR0 to ICDIPR7 are banekd for each connectred processor</desc>
<sw_param offset="0xf8f0143c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPR16_Priority">
<name>Priority</name>
<desc>The ICDIPRs provide an 8-bit Priority field for each interrupt supported by the GIC.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPR0 to ICDIPR7 are banekd for each connectred processor</desc>
<sw_param offset="0xf8f01440" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPR17_Priority">
<name>Priority</name>
<desc>The ICDIPRs provide an 8-bit Priority field for each interrupt supported by the GIC.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPR0 to ICDIPR7 are banekd for each connectred processor</desc>
<sw_param offset="0xf8f01444" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPR18_Priority">
<name>Priority</name>
<desc>The ICDIPRs provide an 8-bit Priority field for each interrupt supported by the GIC.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPR0 to ICDIPR7 are banekd for each connectred processor</desc>
<sw_param offset="0xf8f01448" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPR19_Priority">
<name>Priority</name>
<desc>The ICDIPRs provide an 8-bit Priority field for each interrupt supported by the GIC.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPR0 to ICDIPR7 are banekd for each connectred processor</desc>
<sw_param offset="0xf8f0144c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPR20_Priority">
<name>Priority</name>
<desc>The ICDIPRs provide an 8-bit Priority field for each interrupt supported by the GIC.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPR0 to ICDIPR7 are banekd for each connectred processor</desc>
<sw_param offset="0xf8f01450" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPR21_Priority">
<name>Priority</name>
<desc>The ICDIPRs provide an 8-bit Priority field for each interrupt supported by the GIC.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPR0 to ICDIPR7 are banekd for each connectred processor</desc>
<sw_param offset="0xf8f01454" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPR22_Priority">
<name>Priority</name>
<desc>The ICDIPRs provide an 8-bit Priority field for each interrupt supported by the GIC.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPR0 to ICDIPR7 are banekd for each connectred processor</desc>
<sw_param offset="0xf8f01458" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPR23_Priority">
<name>Priority</name>
<desc>The ICDIPRs provide an 8-bit Priority field for each interrupt supported by the GIC.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPR0 to ICDIPR7 are banekd for each connectred processor</desc>
<sw_param offset="0xf8f0145c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPTR0_Target">
<name>Target</name>
<desc>The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
Theis field stroes the lists of processors that the interrupt is sent to if it is asserted.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPTR0 to ICDIPTR7 are read-only, and each field returns a value corresponding only to the processor reading the register.
Meaning of CPU tagets field bit values:
0bxxxxxxx1: CPU interface 0
0bxxxxxx1x: CPU interface 1</desc>
<sw_param offset="0xf8f01800" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPTR1_Target">
<name>Target</name>
<desc>The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
Theis field stroes the lists of processors that the interrupt is sent to if it is asserted.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPTR0 to ICDIPTR7 are read-only, and each field returns a value corresponding only to the processor reading the register.
Meaning of CPU tagets field bit values:
0bxxxxxxx1: CPU interface 0
0bxxxxxx1x: CPU interface 1</desc>
<sw_param offset="0xf8f01804" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPTR2_Target">
<name>Target</name>
<desc>The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
Theis field stroes the lists of processors that the interrupt is sent to if it is asserted.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPTR0 to ICDIPTR7 are read-only, and each field returns a value corresponding only to the processor reading the register.
Meaning of CPU tagets field bit values:
0bxxxxxxx1: CPU interface 0
0bxxxxxx1x: CPU interface 1</desc>
<sw_param offset="0xf8f01808" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPTR3_Target">
<name>Target</name>
<desc>The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
Theis field stroes the lists of processors that the interrupt is sent to if it is asserted.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPTR0 to ICDIPTR7 are read-only, and each field returns a value corresponding only to the processor reading the register.
Meaning of CPU tagets field bit values:
0bxxxxxxx1: CPU interface 0
0bxxxxxx1x: CPU interface 1</desc>
<sw_param offset="0xf8f0180c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPTR4_Target">
<name>Target</name>
<desc>The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
Theis field stroes the lists of processors that the interrupt is sent to if it is asserted.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPTR0 to ICDIPTR7 are read-only, and each field returns a value corresponding only to the processor reading the register.
Meaning of CPU tagets field bit values:
0bxxxxxxx1: CPU interface 0
0bxxxxxx1x: CPU interface 1</desc>
<sw_param offset="0xf8f01810" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPTR5_Target">
<name>Target</name>
<desc>The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
Theis field stroes the lists of processors that the interrupt is sent to if it is asserted.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPTR0 to ICDIPTR7 are read-only, and each field returns a value corresponding only to the processor reading the register.
Meaning of CPU tagets field bit values:
0bxxxxxxx1: CPU interface 0
0bxxxxxx1x: CPU interface 1</desc>
<sw_param offset="0xf8f01814" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPTR6_Target">
<name>Target</name>
<desc>The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
Theis field stroes the lists of processors that the interrupt is sent to if it is asserted.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPTR0 to ICDIPTR7 are read-only, and each field returns a value corresponding only to the processor reading the register.
Meaning of CPU tagets field bit values:
0bxxxxxxx1: CPU interface 0
0bxxxxxx1x: CPU interface 1</desc>
<sw_param offset="0xf8f01818" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPTR7_Target">
<name>Target</name>
<desc>The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
Theis field stroes the lists of processors that the interrupt is sent to if it is asserted.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPTR0 to ICDIPTR7 are read-only, and each field returns a value corresponding only to the processor reading the register.
Meaning of CPU tagets field bit values:
0bxxxxxxx1: CPU interface 0
0bxxxxxx1x: CPU interface 1</desc>
<sw_param offset="0xf8f0181c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPTR8_Target">
<name>Target</name>
<desc>The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
Theis field stroes the lists of processors that the interrupt is sent to if it is asserted.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPTR0 to ICDIPTR7 are read-only, and each field returns a value corresponding only to the processor reading the register.
Meaning of CPU tagets field bit values:
0bxxxxxxx1: CPU interface 0
0bxxxxxx1x: CPU interface 1</desc>
<sw_param offset="0xf8f01820" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPTR9_Target">
<name>Target</name>
<desc>The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
Theis field stroes the lists of processors that the interrupt is sent to if it is asserted.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPTR0 to ICDIPTR7 are read-only, and each field returns a value corresponding only to the processor reading the register.
Meaning of CPU tagets field bit values:
0bxxxxxxx1: CPU interface 0
0bxxxxxx1x: CPU interface 1</desc>
<sw_param offset="0xf8f01824" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPTR10_Target">
<name>Target</name>
<desc>The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
Theis field stroes the lists of processors that the interrupt is sent to if it is asserted.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPTR0 to ICDIPTR7 are read-only, and each field returns a value corresponding only to the processor reading the register.
Meaning of CPU tagets field bit values:
0bxxxxxxx1: CPU interface 0
0bxxxxxx1x: CPU interface 1</desc>
<sw_param offset="0xf8f01828" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPTR11_Target">
<name>Target</name>
<desc>The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
Theis field stroes the lists of processors that the interrupt is sent to if it is asserted.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPTR0 to ICDIPTR7 are read-only, and each field returns a value corresponding only to the processor reading the register.
Meaning of CPU tagets field bit values:
0bxxxxxxx1: CPU interface 0
0bxxxxxx1x: CPU interface 1</desc>
<sw_param offset="0xf8f0182c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPTR12_Target">
<name>Target</name>
<desc>The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
Theis field stroes the lists of processors that the interrupt is sent to if it is asserted.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPTR0 to ICDIPTR7 are read-only, and each field returns a value corresponding only to the processor reading the register.
Meaning of CPU tagets field bit values:
0bxxxxxxx1: CPU interface 0
0bxxxxxx1x: CPU interface 1</desc>
<sw_param offset="0xf8f01830" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPTR13_Target">
<name>Target</name>
<desc>The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
Theis field stroes the lists of processors that the interrupt is sent to if it is asserted.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPTR0 to ICDIPTR7 are read-only, and each field returns a value corresponding only to the processor reading the register.
Meaning of CPU tagets field bit values:
0bxxxxxxx1: CPU interface 0
0bxxxxxx1x: CPU interface 1</desc>
<sw_param offset="0xf8f01834" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPTR14_Target">
<name>Target</name>
<desc>The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
Theis field stroes the lists of processors that the interrupt is sent to if it is asserted.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPTR0 to ICDIPTR7 are read-only, and each field returns a value corresponding only to the processor reading the register.
Meaning of CPU tagets field bit values:
0bxxxxxxx1: CPU interface 0
0bxxxxxx1x: CPU interface 1</desc>
<sw_param offset="0xf8f01838" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPTR15_Target">
<name>Target</name>
<desc>The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
Theis field stroes the lists of processors that the interrupt is sent to if it is asserted.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPTR0 to ICDIPTR7 are read-only, and each field returns a value corresponding only to the processor reading the register.
Meaning of CPU tagets field bit values:
0bxxxxxxx1: CPU interface 0
0bxxxxxx1x: CPU interface 1</desc>
<sw_param offset="0xf8f0183c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPTR16_Target">
<name>Target</name>
<desc>The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
Theis field stroes the lists of processors that the interrupt is sent to if it is asserted.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPTR0 to ICDIPTR7 are read-only, and each field returns a value corresponding only to the processor reading the register.
Meaning of CPU tagets field bit values:
0bxxxxxxx1: CPU interface 0
0bxxxxxx1x: CPU interface 1</desc>
<sw_param offset="0xf8f01840" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPTR17_Target">
<name>Target</name>
<desc>The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
Theis field stroes the lists of processors that the interrupt is sent to if it is asserted.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPTR0 to ICDIPTR7 are read-only, and each field returns a value corresponding only to the processor reading the register.
Meaning of CPU tagets field bit values:
0bxxxxxxx1: CPU interface 0
0bxxxxxx1x: CPU interface 1</desc>
<sw_param offset="0xf8f01844" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPTR18_Target">
<name>Target</name>
<desc>The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
Theis field stroes the lists of processors that the interrupt is sent to if it is asserted.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPTR0 to ICDIPTR7 are read-only, and each field returns a value corresponding only to the processor reading the register.
Meaning of CPU tagets field bit values:
0bxxxxxxx1: CPU interface 0
0bxxxxxx1x: CPU interface 1</desc>
<sw_param offset="0xf8f01848" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPTR19_Target">
<name>Target</name>
<desc>The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
Theis field stroes the lists of processors that the interrupt is sent to if it is asserted.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPTR0 to ICDIPTR7 are read-only, and each field returns a value corresponding only to the processor reading the register.
Meaning of CPU tagets field bit values:
0bxxxxxxx1: CPU interface 0
0bxxxxxx1x: CPU interface 1</desc>
<sw_param offset="0xf8f0184c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPTR20_Target">
<name>Target</name>
<desc>The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
Theis field stroes the lists of processors that the interrupt is sent to if it is asserted.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPTR0 to ICDIPTR7 are read-only, and each field returns a value corresponding only to the processor reading the register.
Meaning of CPU tagets field bit values:
0bxxxxxxx1: CPU interface 0
0bxxxxxx1x: CPU interface 1</desc>
<sw_param offset="0xf8f01850" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPTR21_Target">
<name>Target</name>
<desc>The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
Theis field stroes the lists of processors that the interrupt is sent to if it is asserted.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPTR0 to ICDIPTR7 are read-only, and each field returns a value corresponding only to the processor reading the register.
Meaning of CPU tagets field bit values:
0bxxxxxxx1: CPU interface 0
0bxxxxxx1x: CPU interface 1</desc>
<sw_param offset="0xf8f01854" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPTR22_Target">
<name>Target</name>
<desc>The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
Theis field stroes the lists of processors that the interrupt is sent to if it is asserted.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPTR0 to ICDIPTR7 are read-only, and each field returns a value corresponding only to the processor reading the register.
Meaning of CPU tagets field bit values:
0bxxxxxxx1: CPU interface 0
0bxxxxxx1x: CPU interface 1</desc>
<sw_param offset="0xf8f01858" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDIPTR23_Target">
<name>Target</name>
<desc>The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
Theis field stroes the lists of processors that the interrupt is sent to if it is asserted.
These registers are byte accessible.
A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
ICDIPTR0 to ICDIPTR7 are read-only, and each field returns a value corresponding only to the processor reading the register.
Meaning of CPU tagets field bit values:
0bxxxxxxx1: CPU interface 0
0bxxxxxx1x: CPU interface 1</desc>
<sw_param offset="0xf8f0185c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDICFR0_Config">
<name>Config</name>
<desc>The ICDICFRs provide a 2-bit Int_config field for each interrupt supported by the GIC.
A register field that corresponds to Secure interrupt is RAZ/WI to Non-secure accesses.
ICDICFR0 is read-only.
Meaning of each 2-bit Int_config:
SGI: both bits are read-only; always 0b10
PPI: both bits are read-only; always 0b01 (active LOW level sensitive) for PPI[1], and [4]; always 0b11(rising-edge sensitive) for PPI[0], [2], and [3].
SPI: LSB is read-only, and is alwyas 1;
0b01=active HIGHT level sensitive; 0b11=rising-edge sensitive.</desc>
<sw_param offset="0xf8f01c00" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDICFR1_Config">
<name>Config</name>
<desc>(ditto)
ICDICFR1 is banked for each connected processor.</desc>
<sw_param offset="0xf8f01c04" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDICFR2_Config">
<name>Config</name>
<desc>(ditto)</desc>
<sw_param offset="0xf8f01c08" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDICFR3_Config">
<name>Config</name>
<desc>(ditto)</desc>
<sw_param offset="0xf8f01c0c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDICFR4_Config">
<name>Config</name>
<desc>(ditto)</desc>
<sw_param offset="0xf8f01c10" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDICFR5_Config">
<name>Config</name>
<desc>(ditto)</desc>
<sw_param offset="0xf8f01c14" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ppi_status_reserved">
<name>reserved</name>
<desc>Reserved. Writes are ignored, read data is always zero</desc>
<sw_param offset="0xf8f01d00" start="31" end="16" />
</parameter>
<parameter uniqueid="ps7_mpcore_ppi_status_ppi_status">
<name>ppi_status</name>
<desc>Returns the status of the PPI(4:0) inputs on the distributor:
* PPI[4] is nIRQ
* PPI[3] is the private watchdog
* PPI[2] is the private timer
* PPI[1] is nFIQ
* PPI[0] is the global timer.
PPI[1] and PPI[4] are active LOW
PPI[0], PPI[2] and PPI[3] are active HIGH.
Note
These bits return the actual status of the PPI(4:0) signals. The ICDISPRn and ICDICPRn registers
can also provide the PPI(4:0) status but because you can write to these registers then they might
not contain the actual status of the PPI(4:0) signals.</desc>
<sw_param offset="0xf8f01d00" start="15" end="11" />
</parameter>
<parameter uniqueid="ps7_mpcore_ppi_status_SBZ">
<name>SBZ</name>
<desc>SBZ</desc>
<sw_param offset="0xf8f01d00" start="10" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_spi_status_0_spi_status">
<name>spi_status</name>
<desc>Returns the status of the IRQS[31:0] inputs on the distributor.
These bits return the actual status of the IRQS signals.
Note:
The ICDISPRn and ICDICPRn registers
can also provide the IRQS status but because you can write to these registers then they might not
contain the actual status of the IRQS signals.</desc>
<sw_param offset="0xf8f01d04" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_spi_status_1_spi_status">
<name>spi_status</name>
<desc>Returns the status of the IRQS[63:32] inputs on the distributor.</desc>
<sw_param offset="0xf8f01d08" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_spi_status_2_spi_status">
<name>spi_status</name>
<desc>Returns the status of the IRQS[95:64] inputs on the distributor.</desc>
<sw_param offset="0xf8f01d0c" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDSGIR_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f01f00" start="31" end="26" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDSGIR_TargetListFilter">
<name>TargetListFilter</name>
<desc>0b00: send the interrupt ot the CPU interfaces specified in the CPUTargetList field
0b01: send the interrupt to all CPU interfaces except the CPU itnerface that requested the interrupt
0b10: send the interrupt on ly to the CPU interface that requested the interrupt
0b11: reserved</desc>
<sw_param offset="0xf8f01f00" start="25" end="24" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDSGIR_CPUTargetList">
<name>CPUTargetList</name>
<desc>When TargetListFilter is 0b00, defines the CPU interfaces the Distributor must send the interrupt to.
Each bit refers to the corresponding CPU interface.</desc>
<sw_param offset="0xf8f01f00" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDSGIR_SATT">
<name>SATT</name>
<desc>Determines the condition for sending the SGI specified in the SGIINTID field to a specified CPU interfaces:
0: only if the SGI is configured as Secure on that interface.
1: only if the SGI is configured as Non-secure on that interface.</desc>
<sw_param offset="0xf8f01f00" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDSGIR_SBZ">
<name>SBZ</name>
<desc>SBZ</desc>
<sw_param offset="0xf8f01f00" start="14" end="4" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICDSGIR_SGIINTID">
<name>SGIINTID</name>
<desc>The Interrupt ID of the SGI to send to the specifed CPU itnerfaces.</desc>
<sw_param offset="0xf8f01f00" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICPIDR4_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f01fd0" start="31" end="4" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICPIDR4_ContinuationCode">
<name>ContinuationCode</name>
<desc>ARM-defined ContinuationCode field</desc>
<sw_param offset="0xf8f01fd0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICPIDR5_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8f01fd4" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICPIDR6_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8f01fd8" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICPIDR7_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8f01fdc" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICPIDR0_reserved">
<name>reserved</name>
<desc>reseved</desc>
<sw_param offset="0xf8f01fe0" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICPIDR0_DevID_low">
<name>DevID_low</name>
<desc>ARM-defined DevID[7:0] field</desc>
<sw_param offset="0xf8f01fe0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICPIDR1_reserved">
<name>reserved</name>
<desc>reseved</desc>
<sw_param offset="0xf8f01fe4" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICPIDR1_ARchID_low">
<name>ARchID_low</name>
<desc>ARM-defined ArchID[3:0] field</desc>
<sw_param offset="0xf8f01fe4" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICPIDR1_DevID_high">
<name>DevID_high</name>
<desc>ARM-defined DevID[11:8] field</desc>
<sw_param offset="0xf8f01fe4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICPIDR2_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f01fe8" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICPIDR2_ArchRev">
<name>ArchRev</name>
<desc>ARM-defined ArchRev field</desc>
<sw_param offset="0xf8f01fe8" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICPIDR2_UsesJEPcode">
<name>UsesJEPcode</name>
<desc>ARM-defined ContinuationCode field</desc>
<sw_param offset="0xf8f01fe8" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICPIDR2_ArchID_high">
<name>ArchID_high</name>
<desc>ARM-defined ArchID[6:4] field</desc>
<sw_param offset="0xf8f01fe8" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICPIDR3_reserved_1">
<name>reserved_1</name>
<desc>reserved</desc>
<sw_param offset="0xf8f01fec" start="31" end="8" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICPIDR3_Revision">
<name>Revision</name>
<desc>ARM-defined Revision field</desc>
<sw_param offset="0xf8f01fec" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICPIDR3_reserved">
<name>reserved</name>
<desc>reserved</desc>
<sw_param offset="0xf8f01fec" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICCIDR0_a">
<name>a</name>
<desc>ARM-defined fixed values for the preamble for component discovery</desc>
<sw_param offset="0xf8f01ff0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICCIDR1_a">
<name>a</name>
<desc>ARM-defined fixed values for the preamble for component discovery</desc>
<sw_param offset="0xf8f01ff4" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICCIDR2_a">
<name>a</name>
<desc>ARM-defined fixed values for the preamble for component discovery</desc>
<sw_param offset="0xf8f01ff8" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_mpcore_ICCIDR3_a">
<name>a</name>
<desc>ARM-defined fixed values for the preamble for component discovery</desc>
<sw_param offset="0xf8f01ffc" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_RDP_a">
<name>a</name>
<desc>Defines the depth, in words, of the trace RAM.</desc>
<sw_param offset="0xf8801004" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_STS_FtEmpty">
<name>FtEmpty</name>
<desc>Formatter pipeline empty. All data stored to RAM.</desc>
<sw_param offset="0xf880100c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_etb_STS_AcqComp">
<name>AcqComp</name>
<desc>Acquisition complete.
The acquisition complete flag indicates that capture has been completed when the formatter stops because of any of the methods defined in the Formatter and Flush Control Register, or TraceCaptEn = 0. This also results in FtStopped in the Formatter and Flush Status Register going HIGH.</desc>
<sw_param offset="0xf880100c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_etb_STS_Triggered">
<name>Triggered</name>
<desc>The Triggered bit is set when a trigger has been observed. This does not indicate that a trigger has been embedded in the trace data by the formatter, but is determined by the programming of the Formatter and Flush Control Register.</desc>
<sw_param offset="0xf880100c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_etb_STS_Full">
<name>Full</name>
<desc>RAM Full.
The flag indicates when the RAM write pointer has wrapped around.</desc>
<sw_param offset="0xf880100c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_RRD_a">
<name>a</name>
<desc>Data read from the ETB Trace RAM.</desc>
<sw_param offset="0xf8801010" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_RRP_a">
<name>a</name>
<desc>Sets the read pointer used to read entries from the Trace RAM over the APB interface.</desc>
<sw_param offset="0xf8801014" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_RWP_a">
<name>a</name>
<desc>Sets the write pointer used to write entries from the CoreSight bus into the Trace RAM</desc>
<sw_param offset="0xf8801018" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_TRG_a">
<name>a</name>
<desc>The counter is used as follows:
- Trace after
The counter is set to a large value, slightly less than the number of entries in the RAM.
- Trace before
The counter is set to a small value.
- Trace about
The counter is set to half the depth of the Trace RAM.
This register must not be written to when trace capture is enabled (FtStopped=0, TraceCaptEn=1). If a write is attempted, the register is not updated. A read access is permitted with trace capture enabled.</desc>
<sw_param offset="0xf880101c" start="9" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_CTL_TraceCaptEn">
<name>TraceCaptEn</name>
<desc>ETB Trace Capture Enable.
1 = enable trace capture
0 = disable trace capture.
This is the master enable bit forcing FtStopped HIGH when TraceCaptEn is LOW.
When capture is disabled, any remaining data in the ATB formatter is stored to RAM.
When all data is stored the formatter outputs FtStopped. Capture is fully disabled, or complete, when FtStopped goes HIGH.</desc>
<sw_param offset="0xf8801020" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_RWD_a">
<name>a</name>
<desc>Data written to the ETB Trace RAM.
When trace capture is disabled, the contents of this register are placed into the ETB Trace RAM when this register is written to.
Writing to this register increments the RAM Write Pointer Register.
If trace capture is enabled, and this register is accessed, then a read from this register outputs 0xFFFFFFFF. Reads of this register never increment the RAM Write Pointer Register. A constant stream of 1s being output corresponds to a synchronization output from the ETB. If a write access is attempted, the data is not written into Trace RAM.</desc>
<sw_param offset="0xf8801024" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_FFSR_FtStopped">
<name>FtStopped</name>
<desc>Formatter stopped. The formatter has received a stop request signal and all trace data and post-amble has been output. Any more trace data on the ATB interface is ignored and ATREADYS goes HIGH.</desc>
<sw_param offset="0xf8801300" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_etb_FFSR_FlInProg">
<name>FlInProg</name>
<desc>Flush In Progress. This is an indication of the current state of AFVALIDS.</desc>
<sw_param offset="0xf8801300" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_FFCR_StopTrig">
<name>StopTrig</name>
<desc>Stop the formatter when a Trigger Event has been observed.</desc>
<sw_param offset="0xf8801304" start="13" end="13" />
</parameter>
<parameter uniqueid="ps7_debug_etb_FFCR_StopFl">
<name>StopFl</name>
<desc>Stop the formatter when a flush has completed (return of AFREADYS). This forces the FIFO to drain off any part-completed packets. Setting this bit enables this function but this is clear on reset (disabled).</desc>
<sw_param offset="0xf8801304" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_debug_etb_FFCR_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8801304" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_debug_etb_FFCR_TrigFl">
<name>TrigFl</name>
<desc>Indicate a trigger on Flush completion (AFREADYS being returned).</desc>
<sw_param offset="0xf8801304" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_debug_etb_FFCR_TrigEvt">
<name>TrigEvt</name>
<desc>Indicate a trigger on a Trigger Event.</desc>
<sw_param offset="0xf8801304" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_debug_etb_FFCR_TrigIn">
<name>TrigIn</name>
<desc>Indicate a trigger on TRIGIN being asserted.</desc>
<sw_param offset="0xf8801304" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_etb_FFCR_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xf8801304" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_debug_etb_FFCR_FOnMan">
<name>FOnMan</name>
<desc>Manually generate a flush of the system. Setting this bit causes a flush to be generated. This is cleared when the flush has been serviced. This bit is clear on reset.</desc>
<sw_param offset="0xf8801304" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_debug_etb_FFCR_FOnTrig">
<name>FOnTrig</name>
<desc>Generate flush using Trigger event. Set this bit to cause a flush of data in the system when a Trigger Event occurs. This bit is clear on reset.</desc>
<sw_param offset="0xf8801304" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_debug_etb_FFCR_FOnFlIn">
<name>FOnFlIn</name>
<desc>Generate flush using the FLUSHIN interface. Set this bit to enable use of the FLUSHIN connection. This bit is clear on reset.</desc>
<sw_param offset="0xf8801304" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_etb_FFCR_reserved_2">
<name>reserved_2</name>
<desc>Reserved</desc>
<sw_param offset="0xf8801304" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_etb_FFCR_EnFCont">
<name>EnFCont</name>
<desc>Continuous Formatting. Continuous mode in the ETB corresponds to normal mode with the embedding of triggers. Can only be changed when FtStopped is HIGH. This bit is clear on reset.</desc>
<sw_param offset="0xf8801304" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_etb_FFCR_EnFTC">
<name>EnFTC</name>
<desc>Enable Formatting. Do not embed Triggers into the formatted stream. Trace disable cycles and triggers are indicated by TRACECTL, where fitted. Can only be changed when FtStopped is HIGH. This bit is clear on reset.</desc>
<sw_param offset="0xf8801304" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_ITMISCOP0_FULL">
<name>FULL</name>
<desc>Set the value of FULL</desc>
<sw_param offset="0xf8801ee0" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_etb_ITMISCOP0_ACQCOMP">
<name>ACQCOMP</name>
<desc>Set the value of ACQCOMP</desc>
<sw_param offset="0xf8801ee0" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_ITTRFLINACK_FLUSHINACK">
<name>FLUSHINACK</name>
<desc>Set the value of FLUSHINACK</desc>
<sw_param offset="0xf8801ee4" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_etb_ITTRFLINACK_TRIGINACK">
<name>TRIGINACK</name>
<desc>Set the value of TRIGINACK</desc>
<sw_param offset="0xf8801ee4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_ITTRFLIN_FLUSHIN">
<name>FLUSHIN</name>
<desc>Read the value of FLUSHIN</desc>
<sw_param offset="0xf8801ee8" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_etb_ITTRFLIN_TRIGIN">
<name>TRIGIN</name>
<desc>Read the value of TRIGIN</desc>
<sw_param offset="0xf8801ee8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_ITATBDATA0_ATDATA31">
<name>ATDATA31</name>
<desc>Read the value of ATDATA[31]</desc>
<sw_param offset="0xf8801eec" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_etb_ITATBDATA0_ATDATA23">
<name>ATDATA23</name>
<desc>Read the value of ATDATA[23]</desc>
<sw_param offset="0xf8801eec" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_etb_ITATBDATA0_ATDATA15">
<name>ATDATA15</name>
<desc>Read the value of ATDATA[15]</desc>
<sw_param offset="0xf8801eec" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_etb_ITATBDATA0_ATDATA7">
<name>ATDATA7</name>
<desc>Read the value of ATDATA[7]</desc>
<sw_param offset="0xf8801eec" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_etb_ITATBDATA0_ATDATA0">
<name>ATDATA0</name>
<desc>Read the value of ATDATA[0]</desc>
<sw_param offset="0xf8801eec" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_ITATBCTR2_AFVALIDS">
<name>AFVALIDS</name>
<desc>Set the value of AFVALIDS</desc>
<sw_param offset="0xf8801ef0" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_etb_ITATBCTR2_ATREADYS">
<name>ATREADYS</name>
<desc>Set the value of ATREADYS</desc>
<sw_param offset="0xf8801ef0" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_ITATBCTR1_ATID">
<name>ATID</name>
<desc>Read the value of ATIDS</desc>
<sw_param offset="0xf8801ef4" start="6" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_ITATBCTR0_ATBYTES">
<name>ATBYTES</name>
<desc>Read the value of ATBYTES</desc>
<sw_param offset="0xf8801ef8" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_debug_etb_ITATBCTR0_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xf8801ef8" start="7" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_etb_ITATBCTR0_AFREADY">
<name>AFREADY</name>
<desc>Read the value of AFREADYS</desc>
<sw_param offset="0xf8801ef8" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_etb_ITATBCTR0_ATVALID">
<name>ATVALID</name>
<desc>Read the value of ATVALIDS</desc>
<sw_param offset="0xf8801ef8" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_IMCR_a">
<name>a</name>
<desc>Enable Integration Test registers.</desc>
<sw_param offset="0xf8801f00" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_CTSR_a">
<name>a</name>
<desc>The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed.
Read:
1= Claim tag is implemented, 0 = Claim tag is not implemented
Write:
1= Set claim tag bit, 0= No effect</desc>
<sw_param offset="0xf8801fa0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_CTCR_a">
<name>a</name>
<desc>The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed.
Read: Current value of claim tag.
Write: 1= Clear claim tag bit, 0= No effect</desc>
<sw_param offset="0xf8801fa4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_LAR_a">
<name>a</name>
<desc>Write Access Code.
Write behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
After reset (via PRESETDBGn), ETB is locked, i.e., writes to all other registers using lower 2GB addresses are ignored.
To unlock, 0xC5ACCE55 must be written this register.
After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register.
- PADDRDBG31=1 (upper 2GB):
ETB is unlocked when upper 2GB addresses are used to write to all the registers.
However, write to this register is ignored using a upper 2GB address!
Note: read from this register always returns 0, regardless of PADDRDBG31.</desc>
<sw_param offset="0xf8801fb0" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_LSR_n8BIT">
<name>n8BIT</name>
<desc>Set to 0 since ETB implements a 32-bit lock access register</desc>
<sw_param offset="0xf8801fb4" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_debug_etb_LSR_STATUS">
<name>STATUS</name>
<desc>Read behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
When a lower 2GB address is used to read this register, this bit indicates whether ETB is in locked state
(1= locked, 0= unlocked).
- PADDRDBG31=1 (upper 2GB):
always returns 0.</desc>
<sw_param offset="0xf8801fb4" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_debug_etb_LSR_IMP">
<name>IMP</name>
<desc>Read behavior depends on PADDRDBG31 pin:
- PADDRDBG31=0 (lower 2GB):
always returns 1, meaning lock mechanism are implemented.
- PADDRDBG31=1 (upper 2GB):
always returns 0, meaning lock mechanism is NOT implemented.</desc>
<sw_param offset="0xf8801fb4" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_ASR_a">
<name>a</name>
<desc>Indicates functionality not implemented</desc>
<sw_param offset="0xf8801fb8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_DEVID_SyncATCLK">
<name>SyncATCLK</name>
<desc>ETB RAM is synchronous to ATCLK</desc>
<sw_param offset="0xf8801fc8" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_debug_etb_DEVID_InputMux">
<name>InputMux</name>
<desc>no input multiplexing</desc>
<sw_param offset="0xf8801fc8" start="4" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_DTIR_a">
<name>a</name>
<desc>A trace sink and specifically an ETB</desc>
<sw_param offset="0xf8801fcc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_PERIPHID4_n4KB_count">
<name>n4KB_count</name>
<desc>4KB Count, set to 0</desc>
<sw_param offset="0xf8801fd0" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_etb_PERIPHID4_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 continuation code</desc>
<sw_param offset="0xf8801fd0" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_PERIPHID5_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf8801fd4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_PERIPHID6_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf8801fd8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_PERIPHID7_a">
<name>a</name>
<desc>reserved</desc>
<sw_param offset="0xf8801fdc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_PERIPHID0_a">
<name>a</name>
<desc>PartNumber0</desc>
<sw_param offset="0xf8801fe0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_PERIPHID1_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 Identity Code [3:0]</desc>
<sw_param offset="0xf8801fe4" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_etb_PERIPHID1_PartNumber1">
<name>PartNumber1</name>
<desc>PartNumber1</desc>
<sw_param offset="0xf8801fe4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_PERIPHID2_RevNum">
<name>RevNum</name>
<desc>Revision number of Peripheral</desc>
<sw_param offset="0xf8801fe8" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_etb_PERIPHID2_JEDEC">
<name>JEDEC</name>
<desc>Indicates that a JEDEC assigned value is used</desc>
<sw_param offset="0xf8801fe8" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_debug_etb_PERIPHID2_JEP106ID">
<name>JEP106ID</name>
<desc>JEP106 Identity Code [6:4]</desc>
<sw_param offset="0xf8801fe8" start="2" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_PERIPHID3_RevAnd">
<name>RevAnd</name>
<desc>RevAnd, at top level</desc>
<sw_param offset="0xf8801fec" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_debug_etb_PERIPHID3_CustMod">
<name>CustMod</name>
<desc>Customer Modified</desc>
<sw_param offset="0xf8801fec" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_COMPID0_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8801ff0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_COMPID1_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8801ff4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_COMPID2_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8801ff8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_debug_etb_COMPID3_a">
<name>a</name>
<desc>Preamble</desc>
<sw_param offset="0xf8801ffc" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_memc_status_raw_ecc_int1">
<name>raw_ecc_int1</name>
<desc>Raw status of the ECC interrupt on interface 1</desc>
<sw_param offset="0xe000e000" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_smcc_memc_status_raw_ecc_int0">
<name>raw_ecc_int0</name>
<desc>Raw status of the ECC interrupt on interface 0</desc>
<sw_param offset="0xe000e000" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_smcc_memc_status_ecc_int1">
<name>ecc_int1</name>
<desc>Status of the ECC interrupt on interface 1</desc>
<sw_param offset="0xe000e000" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_smcc_memc_status_ecc_int0">
<name>ecc_int0</name>
<desc>Status of the ECC interrupt on interface 0</desc>
<sw_param offset="0xe000e000" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_smcc_memc_status_ecc_int1_en">
<name>ecc_int1_en</name>
<desc>Status of the ECC interrupt enable on interface 1</desc>
<sw_param offset="0xe000e000" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_smcc_memc_status_ecc_int0_en">
<name>ecc_int0_en</name>
<desc>Status of the ECC interrupt enable on interface 0</desc>
<sw_param offset="0xe000e000" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_smcc_memc_status_raw_int_status1">
<name>raw_int_status1</name>
<desc>Current raw interrupt status for interface 1</desc>
<sw_param offset="0xe000e000" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_smcc_memc_status_raw_int_status0">
<name>raw_int_status0</name>
<desc>Current raw interrupt status for interface 0</desc>
<sw_param offset="0xe000e000" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_smcc_memc_status_int_status1">
<name>int_status1</name>
<desc>Current interrupt status for interface 1</desc>
<sw_param offset="0xe000e000" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_smcc_memc_status_int_status0">
<name>int_status0</name>
<desc>Current interrupt status for interface 0</desc>
<sw_param offset="0xe000e000" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_smcc_memc_status_int_en1">
<name>int_en1</name>
<desc>Status of memory interface 1 interrupt enable</desc>
<sw_param offset="0xe000e000" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_smcc_memc_status_int_en0">
<name>int_en0</name>
<desc>Status of memory interface 0 interrupt enable</desc>
<sw_param offset="0xe000e000" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_smcc_memc_status_state">
<name>state</name>
<desc>Operating state of the SMC:
0 = SMC is in the ready state
1 = SMC is in the low-power state.</desc>
<sw_param offset="0xe000e000" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_memif_cfg_exclusive_monitors">
<name>exclusive_monitors</name>
<desc>Returns the number of exclusive access monitor resources that are implemented in the SMC.
b00 = 0 monitors
b01 = 1 monitor
b10 = 2 monitors
b11 = 4 monitors.</desc>
<sw_param offset="0xe000e004" start="17" end="16" />
</parameter>
<parameter uniqueid="ps7_smcc_memif_cfg_reserved_1">
<name>reserved_1</name>
<desc>Reserved</desc>
<sw_param offset="0xe000e004" start="15" end="15" />
</parameter>
<parameter uniqueid="ps7_smcc_memif_cfg_remap1">
<name>remap1</name>
<desc>Returns the value of the remap_1 input.</desc>
<sw_param offset="0xe000e004" start="14" end="14" />
</parameter>
<parameter uniqueid="ps7_smcc_memif_cfg_memory_width1">
<name>memory_width1</name>
<desc>Returns the maximum width of the SMC memory data bus for interface 1:
b00 = 8 bits
b01 = 16 bits
b10 = 32 bits
b11 = reserved.</desc>
<sw_param offset="0xe000e004" start="13" end="12" />
</parameter>
<parameter uniqueid="ps7_smcc_memif_cfg_memory_chips1">
<name>memory_chips1</name>
<desc>Returns the number of different chip selects that the memory interface 1 supports:
b00 = 1 chip
b01 = 2 chips
b10 = 3 chips
b11 = 4 chips.</desc>
<sw_param offset="0xe000e004" start="11" end="10" />
</parameter>
<parameter uniqueid="ps7_smcc_memif_cfg_memory_type1">
<name>memory_type1</name>
<desc>Returns the memory interface 1 type: b00 = Configuration does not include this memory interface
b01 = SRAM non-multiplexed
b10 = NAND
b11 = SRAM multiplexed.
If b00, the remaining bit slices for memory interface 1 are always read as 0.</desc>
<sw_param offset="0xe000e004" start="9" end="8" />
</parameter>
<parameter uniqueid="ps7_smcc_memif_cfg_reserved">
<name>reserved</name>
<desc>Reserved</desc>
<sw_param offset="0xe000e004" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_smcc_memif_cfg_remap0">
<name>remap0</name>
<desc>Returns the value of the remap_0 input</desc>
<sw_param offset="0xe000e004" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_smcc_memif_cfg_memory_width0">
<name>memory_width0</name>
<desc>Returns the maximum width of the SMC memory data bus for interface 0:
b00 = 8 bits
b01 = 16 bits
b10 = 32 bits
b11 = reserved.</desc>
<sw_param offset="0xe000e004" start="5" end="4" />
</parameter>
<parameter uniqueid="ps7_smcc_memif_cfg_memory_chips0">
<name>memory_chips0</name>
<desc>Returns the number of different chip selects that the memory interface 0 supports:
b00 = 1 chip
b01 = 2 chips
b10 = 3 chips
b11 = 4 chips.</desc>
<sw_param offset="0xe000e004" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_smcc_memif_cfg_memory_type0">
<name>memory_type0</name>
<desc>Returns the memory interface 0 type:
b00 =reserved
b01 = SRAM non-multiplexed
b10 = NAND
b11 = SRAM multiplexed.</desc>
<sw_param offset="0xe000e004" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_memc_cfg_set_ecc_int_enable1">
<name>ecc_int_enable1</name>
<desc>0 = No effect
1 = ECC interrupt enable, memory interface 1.</desc>
<sw_param offset="0xe000e008" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_smcc_memc_cfg_set_ecc_int_enable0">
<name>ecc_int_enable0</name>
<desc>0 = No effect
1 = ECC interrupt enable, memory interface 0.</desc>
<sw_param offset="0xe000e008" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_smcc_memc_cfg_set_reserved">
<name>reserved</name>
<desc>Reserved, write as zero.</desc>
<sw_param offset="0xe000e008" start="4" end="3" />
</parameter>
<parameter uniqueid="ps7_smcc_memc_cfg_set_low_power_req">
<name>low_power_req</name>
<desc>0 = No effect
1 = Request the SMC to enter low-power state when it next becomes idle.</desc>
<sw_param offset="0xe000e008" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_smcc_memc_cfg_set_int_enable1">
<name>int_enable1</name>
<desc>0 = No effect
1 = Interrupt enable, memory interface 1.</desc>
<sw_param offset="0xe000e008" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_smcc_memc_cfg_set_int_enable0">
<name>int_enable0</name>
<desc>0 = No effect
1 = Interrupt enable, memory interface 0.</desc>
<sw_param offset="0xe000e008" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_memc_cfg_clr_ecc_int_disable1">
<name>ecc_int_disable1</name>
<desc>0 = No effect
1 = Disable ECC Interrupt on IF1.</desc>
<sw_param offset="0xe000e00c" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_smcc_memc_cfg_clr_ecc_int_disable0">
<name>ecc_int_disable0</name>
<desc>0 = No effect
1 = Disable ECC Interrupt on IF0.</desc>
<sw_param offset="0xe000e00c" start="5" end="5" />
</parameter>
<parameter uniqueid="ps7_smcc_memc_cfg_clr_int_clr_1">
<name>int_clr_1</name>
<desc>0 = No effect
1 = Clear SMC Interrupt 1 as an alternative to an AXI read.</desc>
<sw_param offset="0xe000e00c" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_smcc_memc_cfg_clr_int_clr_0">
<name>int_clr_0</name>
<desc>0 = No effect
1 = Clear SMC Interrupt 0 (as an alternative to an AXI read).</desc>
<sw_param offset="0xe000e00c" start="3" end="3" />
</parameter>
<parameter uniqueid="ps7_smcc_memc_cfg_clr_low_power_exit">
<name>low_power_exit</name>
<desc>0 = No effect
1 = Request the SMC to exit low-power state.</desc>
<sw_param offset="0xe000e00c" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_smcc_memc_cfg_clr_int_disable1">
<name>int_disable1</name>
<desc>0 = No effect
1 = Interrupt disable, memory interface 1.</desc>
<sw_param offset="0xe000e00c" start="1" end="1" />
</parameter>
<parameter uniqueid="ps7_smcc_memc_cfg_clr_int_disable0">
<name>int_disable0</name>
<desc>0 = No effect
1 = Interrupt disable, memory interface 0.</desc>
<sw_param offset="0xe000e00c" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_direct_cmd_chip_select">
<name>chip_select</name>
<desc>Selects chip configuration register bank to update, and enables chip mode register access depending on cmd_type. The encoding is:
b000-b011 = Chip selects 1-4 on interface 0 (NOR only has 2 CS so only b000/b001 are valid)
b100-b111 = Chip selects 1-4 on interface 1 (NAND only has 1 CS so only b100 is valid)</desc>
<sw_param offset="0xe000e010" start="25" end="23" />
</parameter>
<parameter uniqueid="ps7_smcc_direct_cmd_cmd_type">
<name>cmd_type</name>
<desc>Selects the command type:
b00 = UpdateRegs and AXI
b01 = ModeReg
b10 = UpdateRegs
b11 = ModeReg and UpdateRegs.</desc>
<sw_param offset="0xe000e010" start="22" end="21" />
</parameter>
<parameter uniqueid="ps7_smcc_direct_cmd_set_cre">
<name>set_cre</name>
<desc>Maps to the configuration register enable signal, cre, when a ModeReg command is issued. The encoding is:
0 = cre is LOW
1 = cre is HIGH when ModeReg write occurs.</desc>
<sw_param offset="0xe000e010" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_smcc_direct_cmd_addr">
<name>addr</name>
<desc>When cmd_type = UpdateRegs and AXI then:
[[*]] bits [15:0] are used to match wdata[15:0]
[[*]] bits [19:16] are reserved. Write as zero.
When cmd_type = ModeReg or ModeReg and UpdateRegs, these bits map to the external memory address bits [19:0].
When cmd_type = UpdateRegs, these bits are reserved. Write as zero.</desc>
<sw_param offset="0xe000e010" start="19" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_set_cycles_Set_t6">
<name>Set_t6</name>
<desc>Contains the value to be written to either the:
[[*]] we_time bit of the sram_cycles Register The permitted values are 0x0 and 0x1.
[[*]] t_rr field of the nand_cycles Register.</desc>
<sw_param offset="0xe000e014" start="23" end="20" />
</parameter>
<parameter uniqueid="ps7_smcc_set_cycles_Set_t5">
<name>Set_t5</name>
<desc>Contains the value to be written to either the:
[[*]] t_tr field of the sram_cycles Register.
[[*]] t_ar field of the nand_cycles Register.</desc>
<sw_param offset="0xe000e014" start="19" end="17" />
</parameter>
<parameter uniqueid="ps7_smcc_set_cycles_Set_t4">
<name>Set_t4</name>
<desc>Contains the value to be written to either the:
[[*]] t_pc field of the sram_cycles Register.
[[*]] t_clr field of the nand_cycles Register.</desc>
<sw_param offset="0xe000e014" start="16" end="14" />
</parameter>
<parameter uniqueid="ps7_smcc_set_cycles_Set_t3">
<name>Set_t3</name>
<desc>Contains the value to be written to the t_wp field in either the:
[[*]] sram_cycles Register
[[*]] nand_cycles Register.</desc>
<sw_param offset="0xe000e014" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_smcc_set_cycles_Set_t2">
<name>Set_t2</name>
<desc>Contains the value to be written to either the:
[[*]] t_ceoe field of the sram_cycles Register
[[*]] t_rea field of the nand_cycles Register .</desc>
<sw_param offset="0xe000e014" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_smcc_set_cycles_Set_t1">
<name>Set_t1</name>
<desc>Contains the value to be written to the t_wc field in either the:
[[*]] sram_cycles Register
[[*]] nand_cycles Register.</desc>
<sw_param offset="0xe000e014" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_smcc_set_cycles_Set_t0">
<name>Set_t0</name>
<desc>Contains the value to be written to the t_rc field in either the:
[[*]] sram_cycles Register
[[*]] nand_cycles Register.</desc>
<sw_param offset="0xe000e014" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_set_opmode_set_burst_align">
<name>set_burst_align</name>
<desc>Contains the value to be written to the specific SRAM chip opmode Register burst_align field. When you configure the SMC to perform synchronous transfersa, these bits control if memory bursts are split on memory burst boundaries:
b000 = bursts can cross any address boundary
b001 = burst split on memory burst boundary, that is, 32 beats for continuous
b010 = burst split on 64 beat boundary
b011 = burst split on 128 beat boundary
b100 = burst split on 256 beat boundary
b101-b111 = reserved.
For a NAND memory interface these bits are reserved, and written as zero.</desc>
<sw_param offset="0xe000e018" start="15" end="13" />
</parameter>
<parameter uniqueid="ps7_smcc_set_opmode_set_bls">
<name>set_bls</name>
<desc>Contains the value to be written to the specific SRAM chip opmode Register byte lane strobe (bls) bit. This bit affects the assertion of the byte-lane strobe outputs.
0 = bls timing equals chip select timing. This is the default setting.
1 = bls timing equals we_n timing. This setting is used for eight memories that have no bls_n inputs. In this case, the bls_n output of the SMC is connected to the we_n memory input.
For a NAND memory interface this bit is reserved, and written as zero.</desc>
<sw_param offset="0xe000e018" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_smcc_set_opmode_set_adv">
<name>set_adv</name>
<desc>Contains the value to be written to the specific SRAM chip opmode Register address valid (adv) bit. The memory uses the address advance signal adv_n when set.
For a NAND memory interface this bit is reserved, and written as zero.</desc>
<sw_param offset="0xe000e018" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_smcc_set_opmode_set_baa">
<name>set_baa</name>
<desc>Contains the value to be written to the specific SRAM chip opmode Register burst address advance (baa) bit. The memory uses the baa_n signal when set.
For a NAND memory interface this bit is reserved, and written as zero.</desc>
<sw_param offset="0xe000e018" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_smcc_set_opmode_set_wr_bl">
<name>set_wr_bl</name>
<desc>Contains the value to be written to the specific SRAM chip opmode Register wr_bl field.
Encodes the memory burst length:
b000 = 1 beat
b001 = 4 beats
b010 = 8 beats
b011 = 16 beats
b100 = 32 beats
b101 = continuous
b110-b111 = reserved.
For a NAND memory interface these bits are reserved, and written as zero.</desc>
<sw_param offset="0xe000e018" start="9" end="7" />
</parameter>
<parameter uniqueid="ps7_smcc_set_opmode_set_wr_sync">
<name>set_wr_sync</name>
<desc>Contains the value to be written to the specific SRAM chip opmode Register wr_sync bit. The memory writes are synchronous when set.
For a NAND memory interface this bit is reserved, and written as zero</desc>
<sw_param offset="0xe000e018" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_smcc_set_opmode_set_rd_bl">
<name>set_rd_bl</name>
<desc>Contains the value to be written to the specific SRAM chip opmode Register rd_bl field.
Encodes the memory burst length:
b000 = 1 beat
b001 = 4 beats
b010 = 8 beats
b011 = 16 beats
b100 = 32 beats
b101 = continuous
b110-b111 = reserved.
For a NAND memory interface these bits are reserved, and written as zero.</desc>
<sw_param offset="0xe000e018" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_smcc_set_opmode_set_rd_sync">
<name>set_rd_sync</name>
<desc>Contains the value to be written to the specific SRAM chip opmode Register rd_sync bit. Memory in sync mode when set.
For a NAND memory interface this bit is reserved, and written as zero.</desc>
<sw_param offset="0xe000e018" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_smcc_set_opmode_set_mw">
<name>set_mw</name>
<desc>Contains the value to be written to the specific chip opmode Register memory width (mw) field.
Encodes the memory data bus width:
b00 = 8 bitsb
b01 = 16 bitsb
b10 = 32 bits
b11 = reserved.
You can program this to the configured width, or half that width.</desc>
<sw_param offset="0xe000e018" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_refresh_period_0_period">
<name>period</name>
<desc>Sets the number of consecutive memory burstsa that are permitted, prior to the SMC deasserting chip select to enable the PSRAM to initiate a refresh cycle. The options are:
b0000 = disables the insertion of idle cycles between consecutive bursts
b0001 = an idle cycle occurs after each burst
b0010 = an idle cycle occurs after 2 consecutive bursts
b0011 = an idle cycle occurs after 3 consecutive bursts
b0100 = an idle cycle occurs after 4 consecutive bursts
.
.
.
b1111 = an idle cycle occurs after 15 consecutive bursts.</desc>
<sw_param offset="0xe000e020" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_refresh_period_1_period">
<name>period</name>
<desc>Sets the number of consecutive memory burstsa that are permitted, prior to the SMC deasserting chip select to enable the PSRAM to initiate a refresh cycle. The options are:
b0000 = disables the insertion of idle cycles between consecutive bursts
b0001 = an idle cycle occurs after each burst
b0010 = an idle cycle occurs after 2 consecutive bursts
b0011 = an idle cycle occurs after 3 consecutive bursts
b0100 = an idle cycle occurs after 4 consecutive bursts
.
.
.
b1111 = an idle cycle occurs after 15 consecutive bursts.</desc>
<sw_param offset="0xe000e024" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_sram_cycles0_0_we_time">
<name>we_time</name>
<desc>For asynchronous multiplexed transfers this bit controls when the SMC asserts we_n:
0 = SMC asserts we_n two mclk cycles after asserting cs_n.
1 = SMC asserts we_n and cs_n together.</desc>
<sw_param offset="0xe000e100" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_smcc_sram_cycles0_0_t_tr">
<name>t_tr</name>
<desc>Turnaround time for SRAM chip configurations.Minimum permitted value = 1.</desc>
<sw_param offset="0xe000e100" start="19" end="17" />
</parameter>
<parameter uniqueid="ps7_smcc_sram_cycles0_0_t_pc">
<name>t_pc</name>
<desc>Page cycle time for SRAM chip configurations.Minimum permitted value = 1.</desc>
<sw_param offset="0xe000e100" start="16" end="14" />
</parameter>
<parameter uniqueid="ps7_smcc_sram_cycles0_0_t_wp">
<name>t_wp</name>
<desc>we_n assertion delay.Minimum permitted value = 1.</desc>
<sw_param offset="0xe000e100" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_smcc_sram_cycles0_0_t_ceoe">
<name>t_ceoe</name>
<desc>oe_n assertion delay for SRAM chip configurations.Minimum permitted value = 1.</desc>
<sw_param offset="0xe000e100" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_smcc_sram_cycles0_0_t_wc">
<name>t_wc</name>
<desc>Write cycle time.Minimum permitted value = 2.</desc>
<sw_param offset="0xe000e100" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_smcc_sram_cycles0_0_t_rc">
<name>t_rc</name>
<desc>Read cycle time.Minimum permitted value = 2.</desc>
<sw_param offset="0xe000e100" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode0_0_address_match">
<name>address_match</name>
<desc>Returns the value of this tie-off. This is the comparison value for address bits [31:24] to determine the chip that is selected.</desc>
<sw_param offset="0xe000e104" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode0_0_address_mask">
<name>address_mask</name>
<desc>Returns the value of this tie-off. This is the mask for address bits[31:24] to determine the chip that must be selected. A logic 1 indicates the bit is used for comparison.</desc>
<sw_param offset="0xe000e104" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode0_0_burst_align">
<name>burst_align</name>
<desc>When you configure the SMC to perform synchronous transfersa, these bits control if memory bursts are split on memory burst boundaries:
b000 = bursts can cross any address boundary
b001 = burst split on memory burst boundary, that is, 32 beats for continuous
b010 = burst split on 64 beat boundary
b011 = burst split on 128 beat boundary
b100 = burst split on 256 beat boundary
b101-b111 = reserved.
For a NAND memory interface these bits are reserved.</desc>
<sw_param offset="0xe000e104" start="15" end="13" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode0_0_bls">
<name>bls</name>
<desc>This bit affects the assertion of the byte-lane strobe outputs:
0 = bls timing equals chip select timing. This is the default setting.
1 = bls timing equals we_n timing. This setting is used for 8-bit memories that have no bls inputs. In this case, the bls_n output of the SMC is connected to the we_n memory input.
For a NAND memory interface this bit is reserved.</desc>
<sw_param offset="0xe000e104" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode0_0_adv">
<name>adv</name>
<desc>The memory uses the address advance signal, adv_n, when set.
For a NAND memory interface this bit is reserved.</desc>
<sw_param offset="0xe000e104" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode0_0_baa">
<name>baa</name>
<desc>The memory uses the burst address advance signal, baa_n, when set.
For a NAND memory interface this bit is reserved.</desc>
<sw_param offset="0xe000e104" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode0_0_wr_bl">
<name>wr_bl</name>
<desc>Selects the memory burst length for writes:
b000 = 1 beat
b001 = 4 beats
b010 = 8 beats
b011 = 16 beats
b100 = 32 beats
b101 = continuous
b110-b111 = reserved.
For a NAND memory interface these bits are reserved.</desc>
<sw_param offset="0xe000e104" start="9" end="7" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode0_0_wr_sync">
<name>wr_sync</name>
<desc>When set, the memory operates in write sync mode.
For a NAND memory interface this bit is reserved.</desc>
<sw_param offset="0xe000e104" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode0_0_rd_bl">
<name>rd_bl</name>
<desc>Selects the memory burst length for reads:
b000 = 1 beat
b001 = 4 beats
b010 = 8 beats
b011 = 16 beats
b100 = 32 beats
b101 = continuous
b110-b111 = reserved.
For a NAND memory interface these bits are reserved.</desc>
<sw_param offset="0xe000e104" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode0_0_rd_sync">
<name>rd_sync</name>
<desc>When set, the memory operates in read sync mode.
For a NAND memory interface this bit is reserved.</desc>
<sw_param offset="0xe000e104" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode0_0_mw">
<name>mw</name>
<desc>Selects the SMC memory data bus width:
b00 = 8 bits
b01 = 16 bits
b10 = 32 bits
b11 = reserved.</desc>
<sw_param offset="0xe000e104" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_sram_cycles0_1_we_time">
<name>we_time</name>
<desc>For asynchronous multiplexed transfers this bit controls when the SMC asserts we_n:
0 = SMC asserts we_n two mclk cycles after asserting cs_n.
1 = SMC asserts we_n and cs_n together.</desc>
<sw_param offset="0xe000e120" start="20" end="20" />
</parameter>
<parameter uniqueid="ps7_smcc_sram_cycles0_1_t_tr">
<name>t_tr</name>
<desc>Turnaround time for SRAM chip configurations.Minimum permitted value = 1.</desc>
<sw_param offset="0xe000e120" start="19" end="17" />
</parameter>
<parameter uniqueid="ps7_smcc_sram_cycles0_1_t_pc">
<name>t_pc</name>
<desc>Page cycle time for SRAM chip configurations.Minimum permitted value = 1.</desc>
<sw_param offset="0xe000e120" start="16" end="14" />
</parameter>
<parameter uniqueid="ps7_smcc_sram_cycles0_1_t_wp">
<name>t_wp</name>
<desc>we_n assertion delay.Minimum permitted value = 1.</desc>
<sw_param offset="0xe000e120" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_smcc_sram_cycles0_1_t_ceoe">
<name>t_ceoe</name>
<desc>oe_n assertion delay for SRAM chip configurations.Minimum permitted value = 1.</desc>
<sw_param offset="0xe000e120" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_smcc_sram_cycles0_1_t_wc">
<name>t_wc</name>
<desc>Write cycle time.Minimum permitted value = 2.</desc>
<sw_param offset="0xe000e120" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_smcc_sram_cycles0_1_t_rc">
<name>t_rc</name>
<desc>Read cycle time.Minimum permitted value = 2.</desc>
<sw_param offset="0xe000e120" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode0_1_address_match">
<name>address_match</name>
<desc>Returns the value of this tie-off. This is the comparison value for address bits [31:24] to determine the chip that is selected.</desc>
<sw_param offset="0xe000e124" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode0_1_address_mask">
<name>address_mask</name>
<desc>Returns the value of this tie-off. This is the mask for address bits[31:24] to determine the chip that must be selected. A logic 1 indicates the bit is used for comparison.</desc>
<sw_param offset="0xe000e124" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode0_1_burst_align">
<name>burst_align</name>
<desc>When you configure the SMC to perform synchronous transfersa, these bits control if memory bursts are split on memory burst boundaries:
b000 = bursts can cross any address boundary
b001 = burst split on memory burst boundary, that is, 32 beats for continuous
b010 = burst split on 64 beat boundary
b011 = burst split on 128 beat boundary
b100 = burst split on 256 beat boundary
b101-b111 = reserved.
For a NAND memory interface these bits are reserved.</desc>
<sw_param offset="0xe000e124" start="15" end="13" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode0_1_bls">
<name>bls</name>
<desc>This bit affects the assertion of the byte-lane strobe outputs:
0 = bls timing equals chip select timing. This is the default setting.
1 = bls timing equals we_n timing. This setting is used for 8-bit memories that have no bls inputs. In this case, the bls_n output of the SMC is connected to the we_n memory input.
For a NAND memory interface this bit is reserved.</desc>
<sw_param offset="0xe000e124" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode0_1_adv">
<name>adv</name>
<desc>The memory uses the address advance signal, adv_n, when set.
For a NAND memory interface this bit is reserved.</desc>
<sw_param offset="0xe000e124" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode0_1_baa">
<name>baa</name>
<desc>The memory uses the burst address advance signal, baa_n, when set.
For a NAND memory interface this bit is reserved.</desc>
<sw_param offset="0xe000e124" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode0_1_wr_bl">
<name>wr_bl</name>
<desc>Selects the memory burst length for writes:
b000 = 1 beat
b001 = 4 beats
b010 = 8 beats
b011 = 16 beats
b100 = 32 beats
b101 = continuous
b110-b111 = reserved.
For a NAND memory interface these bits are reserved.</desc>
<sw_param offset="0xe000e124" start="9" end="7" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode0_1_wr_sync">
<name>wr_sync</name>
<desc>When set, the memory operates in write sync mode.
For a NAND memory interface this bit is reserved.</desc>
<sw_param offset="0xe000e124" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode0_1_rd_bl">
<name>rd_bl</name>
<desc>Selects the memory burst length for reads:
b000 = 1 beat
b001 = 4 beats
b010 = 8 beats
b011 = 16 beats
b100 = 32 beats
b101 = continuous
b110-b111 = reserved.
For a NAND memory interface these bits are reserved.</desc>
<sw_param offset="0xe000e124" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode0_1_rd_sync">
<name>rd_sync</name>
<desc>When set, the memory operates in read sync mode.
For a NAND memory interface this bit is reserved.</desc>
<sw_param offset="0xe000e124" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode0_1_mw">
<name>mw</name>
<desc>Selects the SMC memory data bus width:
b00 = 8 bits
b01 = 16 bits
b10 = 32 bits
b11 = reserved.</desc>
<sw_param offset="0xe000e124" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_nand_cycles1_0_t_rr">
<name>t_rr</name>
<desc>busy to re_n for NAND chip configurations.Minimum permitted value = 0.</desc>
<sw_param offset="0xe000e180" start="23" end="20" />
</parameter>
<parameter uniqueid="ps7_smcc_nand_cycles1_0_t_ar">
<name>t_ar</name>
<desc>ID read time for NAND chip configurations.Minimum permitted value = 0.</desc>
<sw_param offset="0xe000e180" start="19" end="17" />
</parameter>
<parameter uniqueid="ps7_smcc_nand_cycles1_0_t_clr">
<name>t_clr</name>
<desc>Status read time for NAND chip configurations.Minimum permitted value = 0.</desc>
<sw_param offset="0xe000e180" start="16" end="14" />
</parameter>
<parameter uniqueid="ps7_smcc_nand_cycles1_0_t_wp">
<name>t_wp</name>
<desc>we_n de-assertion delay.Minimum permitted value = 1.</desc>
<sw_param offset="0xe000e180" start="13" end="11" />
</parameter>
<parameter uniqueid="ps7_smcc_nand_cycles1_0_t_rea">
<name>t_rea</name>
<desc>re_n assertion delay for NAND chip configurations.Minimum permitted value = 1.</desc>
<sw_param offset="0xe000e180" start="10" end="8" />
</parameter>
<parameter uniqueid="ps7_smcc_nand_cycles1_0_t_wc">
<name>t_wc</name>
<desc>Write cycle time.Minimum permitted value = 2.</desc>
<sw_param offset="0xe000e180" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_smcc_nand_cycles1_0_t_rc">
<name>t_rc</name>
<desc>Read cycle time.Minimum permitted value = 2.</desc>
<sw_param offset="0xe000e180" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode1_0_address_match">
<name>address_match</name>
<desc>Returns the value of this tie-off. This is the comparison value for address bits [31:24] to determine the chip that is selected.</desc>
<sw_param offset="0xe000e184" start="31" end="24" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode1_0_address_mask">
<name>address_mask</name>
<desc>Returns the value of this tie-off. This is the mask for address bits[31:24] to determine the chip that must be selected. A logic 1 indicates the bit is used for comparison.</desc>
<sw_param offset="0xe000e184" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode1_0_burst_align">
<name>burst_align</name>
<desc>When you configure the SMC to perform synchronous transfersa, these bits control if memory bursts are split on memory burst boundaries:
b000 = bursts can cross any address boundary
b001 = burst split on memory burst boundary, that is, 32 beats for continuous
b010 = burst split on 64 beat boundary
b011 = burst split on 128 beat boundary
b100 = burst split on 256 beat boundary
b101-b111 = reserved.
For a NAND memory interface these bits are reserved.</desc>
<sw_param offset="0xe000e184" start="15" end="13" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode1_0_bls">
<name>bls</name>
<desc>This bit affects the assertion of the byte-lane strobe outputs:
0 = bls timing equals chip select timing. This is the default setting.
1 = bls timing equals we_n timing. This setting is used for 8-bit memories that have no bls inputs. In this case, the bls_n output of the SMC is connected to the we_n memory input.
For a NAND memory interface this bit is reserved.</desc>
<sw_param offset="0xe000e184" start="12" end="12" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode1_0_adv">
<name>adv</name>
<desc>The memory uses the address advance signal, adv_n, when set.
For a NAND memory interface this bit is reserved.</desc>
<sw_param offset="0xe000e184" start="11" end="11" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode1_0_baa">
<name>baa</name>
<desc>The memory uses the burst address advance signal, baa_n, when set.
For a NAND memory interface this bit is reserved.</desc>
<sw_param offset="0xe000e184" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode1_0_wr_bl">
<name>wr_bl</name>
<desc>Selects the memory burst length for writes:
b000 = 1 beat
b001 = 4 beats
b010 = 8 beats
b011 = 16 beats
b100 = 32 beats
b101 = continuous
b110-b111 = reserved.
For a NAND memory interface these bits are reserved.</desc>
<sw_param offset="0xe000e184" start="9" end="7" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode1_0_wr_sync">
<name>wr_sync</name>
<desc>When set, the memory operates in write sync mode.
For a NAND memory interface this bit is reserved.</desc>
<sw_param offset="0xe000e184" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode1_0_rd_bl">
<name>rd_bl</name>
<desc>Selects the memory burst length for reads:
b000 = 1 beat
b001 = 4 beats
b010 = 8 beats
b011 = 16 beats
b100 = 32 beats
b101 = continuous
b110-b111 = reserved.
For a NAND memory interface these bits are reserved.</desc>
<sw_param offset="0xe000e184" start="5" end="3" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode1_0_rd_sync">
<name>rd_sync</name>
<desc>When set, the memory operates in read sync mode.
For a NAND memory interface this bit is reserved.</desc>
<sw_param offset="0xe000e184" start="2" end="2" />
</parameter>
<parameter uniqueid="ps7_smcc_opmode1_0_mw">
<name>mw</name>
<desc>Selects the SMC memory data bus width:
b00 = 8 bits
b01 = 16 bits
b10 = 32 bits
b11 = reserved.</desc>
<sw_param offset="0xe000e184" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_user_status_user_status">
<name>user_status</name>
<desc>This value returns the state of the user_status[7:0] inputs</desc>
<sw_param offset="0xe000e200" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_user_config_user_config">
<name>user_config</name>
<desc>This value sets the state of the user_config[7:0] outputs</desc>
<sw_param offset="0xe000e204" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_status_0_ecc_read">
<name>ecc_read</name>
<desc>Read flags for ECC blocks. Indicates whether the stored ECC value for each block has been read from memory
0 = not read
1 = read.</desc>
<sw_param offset="0xe000e300" start="29" end="25" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_status_0_ecc_can_correct">
<name>ecc_can_correct</name>
<desc>Correctable flag for each ECC block. Indicates if the detected error is correctable.
0 = not correctable
1 = correctable.</desc>
<sw_param offset="0xe000e300" start="24" end="20" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_status_0_ecc_fail">
<name>ecc_fail</name>
<desc>Pass/fail flag for each ECC block</desc>
<sw_param offset="0xe000e300" start="19" end="15" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_status_0_ecc_value_valid">
<name>ecc_value_valid</name>
<desc>Valid flag for each ECC block.</desc>
<sw_param offset="0xe000e300" start="14" end="10" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_status_0_ecc_read_not_write">
<name>ecc_read_not_write</name>
<desc>0 = write
1 = read.</desc>
<sw_param offset="0xe000e300" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_status_0_ecc_last_status">
<name>ecc_last_status</name>
<desc>b00 = Completed successfully
b01 = Unaligned Address, or out-of-range
b10 = Data stop after incomplete block
b11 = Data stopped but values not read/written because of ecc_jump value.
Note
The ecc_last_status bit is only updated at the completion of an ECC calculation.</desc>
<sw_param offset="0xe000e300" start="8" end="7" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_status_0_ecc_status">
<name>ecc_status</name>
<desc>Describes the status of the ECC block
0 = idle
1 = busy.</desc>
<sw_param offset="0xe000e300" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_status_0_raw_int_status">
<name>raw_int_status</name>
<desc>The interrupts are:
[5] Abort.
[4] Extra block (if used).
[3] Block 3.
[2] Block 2.
[1] Block 1.
[0] Block 0.
To clear the interrupt, you must write a 1 to the appropriate bit</desc>
<sw_param offset="0xe000e300" start="5" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcfg_0_ecc_extra_block_size">
<name>ecc_extra_block_size</name>
<desc>The size of the extra block in memory after the last 512 block:
b00 = 4 bytes
b01 = 8 bytes
b10 = 16 bytes
b11 = 32 bytes.
Note
These bits are only present if you configure the SMC to use the ECC Extra Block Enable option</desc>
<sw_param offset="0xe000e304" start="12" end="11" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcfg_0_ecc_extra_block">
<name>ecc_extra_block</name>
<desc>If configured, this enables a small block for extra information after the last 512 bytes block in the page.
Note
These bits are only present if the ECC Extra Block Enable option is configured.</desc>
<sw_param offset="0xe000e304" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcfg_0_ecc_int_abort">
<name>ecc_int_abort</name>
<desc>Interrupt on ECC abort</desc>
<sw_param offset="0xe000e304" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcfg_0_ecc_int_pass">
<name>ecc_int_pass</name>
<desc>Interrupt when a correct ECC value is read from memory.</desc>
<sw_param offset="0xe000e304" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcfg_0_ecc_ignore_add_eight">
<name>ecc_ignore_add_eight</name>
<desc>This bit is used to indicate if A8 is output with the address, required to find the aligned start of blocks:
0 = A8 is output
1 = A8 is not output.</desc>
<sw_param offset="0xe000e304" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcfg_0_ecc_jump">
<name>ecc_jump</name>
<desc>Indicates that the memory supports column change address commands:
b00 = no jumping, reads and writes only occur at end of page
b01 = jump using column change commands
b10 = jump using full command
b11 = reserved.</desc>
<sw_param offset="0xe000e304" start="6" end="5" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcfg_0_ecc_read_end">
<name>ecc_read_end</name>
<desc>Indicates when ECC values are read from memory:
0 = the ECC value for a block must be read immediately after the block. Data access must stop on a 512 byte boundary.
1 = ECC values for all blocks are read at the end of the page.</desc>
<sw_param offset="0xe000e304" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcfg_0_ecc_mode">
<name>ecc_mode</name>
<desc>This specifies the mode of the ECC block:
b00 = bypassed.
b01 = ECC values are calculated and made available on the APB interface. But they are not read to or written from memory.
b10 = ECC values and calculated and read/written to memory. For a read, the ECC value is checked and the result of the check is made available on the APB interface.
b11 = reserved.</desc>
<sw_param offset="0xe000e304" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcfg_0_page_size">
<name>page_size</name>
<desc>The number of 512 byte blocks in a page:
b00 = No 512 byte blocks. Reserved if an ecc_extra_block is not configured and enabled.
b01 = One 512 byte block.
b10 = Two 512 byte blocks.
b11 = Four 512 byte blocks.</desc>
<sw_param offset="0xe000e304" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcommand1_0_nand_rd_cmd_end_valid">
<name>nand_rd_cmd_end_valid</name>
<desc>Use end command</desc>
<sw_param offset="0xe000e308" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcommand1_0_nand_rd_cmd_end">
<name>nand_rd_cmd_end</name>
<desc>The NAND command used to initiate a write (0x30)</desc>
<sw_param offset="0xe000e308" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcommand1_0_nand_rd_cmd">
<name>nand_rd_cmd</name>
<desc>The NAND command used to initiate a read (0x00)</desc>
<sw_param offset="0xe000e308" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcommand1_0_nand_wr_cmd">
<name>nand_wr_cmd</name>
<desc>The NAND command used to initiate a write (0x80)</desc>
<sw_param offset="0xe000e308" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcommand2_0_nand_rd_col_change_end_valid">
<name>nand_rd_col_change_end_valid</name>
<desc>Use end command</desc>
<sw_param offset="0xe000e30c" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcommand2_0_nand_rd_col_change_end">
<name>nand_rd_col_change_end</name>
<desc>The NAND command used to initiate a write</desc>
<sw_param offset="0xe000e30c" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcommand2_0_nand_rd_col_change">
<name>nand_rd_col_change</name>
<desc>The NAND command used to initiate a read or Spare bits pointer command</desc>
<sw_param offset="0xe000e30c" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcommand2_0_nand_wr_col_change">
<name>nand_wr_col_change</name>
<desc>The NAND command used to initiate a write</desc>
<sw_param offset="0xe000e30c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_addr0_0_ecc_addr">
<name>ecc_addr</name>
<desc>Address bits 31 to 0</desc>
<sw_param offset="0xe000e310" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_addr1_0_ecc_addr">
<name>ecc_addr</name>
<desc>Address bits 55 to 32</desc>
<sw_param offset="0xe000e314" start="23" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value0_0_ecc_int">
<name>ecc_int</name>
<desc>Interrupt flag for this value</desc>
<sw_param offset="0xe000e318" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value0_0_ecc_valid">
<name>ecc_valid</name>
<desc>Indicates if this value is valid</desc>
<sw_param offset="0xe000e318" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value0_0_ecc_read">
<name>ecc_read</name>
<desc>Indicates if the ECC value has been read from memory</desc>
<sw_param offset="0xe000e318" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value0_0_ecc_fail">
<name>ecc_fail</name>
<desc>Indicates if this value has failed</desc>
<sw_param offset="0xe000e318" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value0_0_ecc_correct">
<name>ecc_correct</name>
<desc>Indicates if this block is correctable</desc>
<sw_param offset="0xe000e318" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value0_0_reserved">
<name>reserved</name>
<desc>Reserved, read undefined</desc>
<sw_param offset="0xe000e318" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value0_0_ecc_value">
<name>ecc_value</name>
<desc>ECC value of check result for block, depending on ECC configuration</desc>
<sw_param offset="0xe000e318" start="23" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value1_0_ecc_int">
<name>ecc_int</name>
<desc>Interrupt flag for this value</desc>
<sw_param offset="0xe000e31c" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value1_0_ecc_valid">
<name>ecc_valid</name>
<desc>Indicates if this value is valid</desc>
<sw_param offset="0xe000e31c" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value1_0_ecc_read">
<name>ecc_read</name>
<desc>Indicates if the ECC value has been read from memory</desc>
<sw_param offset="0xe000e31c" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value1_0_ecc_fail">
<name>ecc_fail</name>
<desc>Indicates if this value has failed</desc>
<sw_param offset="0xe000e31c" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value1_0_ecc_correct">
<name>ecc_correct</name>
<desc>Indicates if this block is correctable</desc>
<sw_param offset="0xe000e31c" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value1_0_reserved">
<name>reserved</name>
<desc>Reserved, read undefined</desc>
<sw_param offset="0xe000e31c" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value1_0_ecc_value">
<name>ecc_value</name>
<desc>ECC value of check result for block, depending on ECC configuration</desc>
<sw_param offset="0xe000e31c" start="23" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value2_0_ecc_int">
<name>ecc_int</name>
<desc>Interrupt flag for this value</desc>
<sw_param offset="0xe000e320" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value2_0_ecc_valid">
<name>ecc_valid</name>
<desc>Indicates if this value is valid</desc>
<sw_param offset="0xe000e320" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value2_0_ecc_read">
<name>ecc_read</name>
<desc>Indicates if the ECC value has been read from memory</desc>
<sw_param offset="0xe000e320" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value2_0_ecc_fail">
<name>ecc_fail</name>
<desc>Indicates if this value has failed</desc>
<sw_param offset="0xe000e320" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value2_0_ecc_correct">
<name>ecc_correct</name>
<desc>Indicates if this block is correctable</desc>
<sw_param offset="0xe000e320" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value2_0_reserved">
<name>reserved</name>
<desc>Reserved, read undefined</desc>
<sw_param offset="0xe000e320" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value2_0_ecc_value">
<name>ecc_value</name>
<desc>ECC value of check result for block, depending on ECC configuration</desc>
<sw_param offset="0xe000e320" start="23" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value3_0_ecc_int">
<name>ecc_int</name>
<desc>Interrupt flag for this value</desc>
<sw_param offset="0xe000e324" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value3_0_ecc_valid">
<name>ecc_valid</name>
<desc>Indicates if this value is valid</desc>
<sw_param offset="0xe000e324" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value3_0_ecc_read">
<name>ecc_read</name>
<desc>Indicates if the ECC value has been read from memory</desc>
<sw_param offset="0xe000e324" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value3_0_ecc_fail">
<name>ecc_fail</name>
<desc>Indicates if this value has failed</desc>
<sw_param offset="0xe000e324" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value3_0_ecc_correct">
<name>ecc_correct</name>
<desc>Indicates if this block is correctable</desc>
<sw_param offset="0xe000e324" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value3_0_reserved">
<name>reserved</name>
<desc>Reserved, read undefined</desc>
<sw_param offset="0xe000e324" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value3_0_ecc_value">
<name>ecc_value</name>
<desc>ECC value of check result for block, depending on ECC configuration</desc>
<sw_param offset="0xe000e324" start="23" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_status_1_ecc_read">
<name>ecc_read</name>
<desc>Read flags for ECC blocks. Indicates whether the stored ECC value for each block has been read from memory
0 = not read
1 = read.</desc>
<sw_param offset="0xe000e400" start="29" end="25" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_status_1_ecc_can_correct">
<name>ecc_can_correct</name>
<desc>Correctable flag for each ECC block. Indicates if the detected error is correctable.
0 = not correctable
1 = correctable.</desc>
<sw_param offset="0xe000e400" start="24" end="20" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_status_1_ecc_fail">
<name>ecc_fail</name>
<desc>Pass/fail flag for each ECC block</desc>
<sw_param offset="0xe000e400" start="19" end="15" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_status_1_ecc_value_valid">
<name>ecc_value_valid</name>
<desc>Valid flag for each ECC block.</desc>
<sw_param offset="0xe000e400" start="14" end="10" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_status_1_ecc_read_not_write">
<name>ecc_read_not_write</name>
<desc>0 = write
1 = read.</desc>
<sw_param offset="0xe000e400" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_status_1_ecc_last_status">
<name>ecc_last_status</name>
<desc>b00 = Completed successfully
b01 = Unaligned Address, or out-of-range
b10 = Data stop after incomplete block
b11 = Data stopped but values not read/written because of ecc_jump value.
Note
The ecc_last_status bit is only updated at the completion of an ECC calculation.</desc>
<sw_param offset="0xe000e400" start="8" end="7" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_status_1_ecc_status">
<name>ecc_status</name>
<desc>Describes the status of the ECC block
0 = idle
1 = busy.</desc>
<sw_param offset="0xe000e400" start="6" end="6" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_status_1_raw_int_status">
<name>raw_int_status</name>
<desc>The interrupts are:
[5] Abort.
[4] Extra block (if used).
[3] Block 3.
[2] Block 2.
[1] Block 1.
[0] Block 0.
To clear the interrupt, you must write a 1 to the appropriate bit</desc>
<sw_param offset="0xe000e400" start="5" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcfg_1_ecc_extra_block_size">
<name>ecc_extra_block_size</name>
<desc>The size of the extra block in memory after the last 512 block:
b00 = 4 bytes
b01 = 8 bytes
b10 = 16 bytes
b11 = 32 bytes.
Note
These bits are only present if you configure the SMC to use the ECC Extra Block Enable option</desc>
<sw_param offset="0xe000e404" start="12" end="11" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcfg_1_ecc_extra_block">
<name>ecc_extra_block</name>
<desc>If configured, this enables a small block for extra information after the last 512 bytes block in the page.
Note
These bits are only present if the ECC Extra Block Enable option is configured.</desc>
<sw_param offset="0xe000e404" start="10" end="10" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcfg_1_ecc_int_abort">
<name>ecc_int_abort</name>
<desc>Interrupt on ECC abort</desc>
<sw_param offset="0xe000e404" start="9" end="9" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcfg_1_ecc_int_pass">
<name>ecc_int_pass</name>
<desc>Interrupt when a correct ECC value is read from memory.</desc>
<sw_param offset="0xe000e404" start="8" end="8" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcfg_1_ecc_ignore_add_eight">
<name>ecc_ignore_add_eight</name>
<desc>This bit is used to indicate if A8 is output with the address, required to find the aligned start of blocks:
0 = A8 is output
1 = A8 is not output.</desc>
<sw_param offset="0xe000e404" start="7" end="7" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcfg_1_ecc_jump">
<name>ecc_jump</name>
<desc>Indicates that the memory supports column change address commands:
b00 = no jumping, reads and writes only occur at end of page
b01 = jump using column change commands
b10 = jump using full command
b11 = reserved.</desc>
<sw_param offset="0xe000e404" start="6" end="5" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcfg_1_ecc_read_end">
<name>ecc_read_end</name>
<desc>Indicates when ECC values are read from memory:
0 = the ECC value for a block must be read immediately after the block. Data access must stop on a 512 byte boundary.
1 = ECC values for all blocks are read at the end of the page.</desc>
<sw_param offset="0xe000e404" start="4" end="4" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcfg_1_ecc_mode">
<name>ecc_mode</name>
<desc>This specifies the mode of the ECC block:
b00 = bypassed.
b01 = ECC values are calculated and made available on the APB interface. But they are not read to or written from memory.
b10 = ECC values and calculated and read/written to memory. For a read, the ECC value is checked and the result of the check is made available on the APB interface.
b11 = reserved.</desc>
<sw_param offset="0xe000e404" start="3" end="2" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcfg_1_page_size">
<name>page_size</name>
<desc>The number of 512 byte blocks in a page:
b00 = No 512 byte blocks. Reserved if an ecc_extra_block is not configured and enabled.
b01 = One 512 byte block.
b10 = Two 512 byte blocks.
b11 = Four 512 byte blocks.</desc>
<sw_param offset="0xe000e404" start="1" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcommand1_1_nand_rd_cmd_end_valid">
<name>nand_rd_cmd_end_valid</name>
<desc>Use end command</desc>
<sw_param offset="0xe000e408" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcommand1_1_nand_rd_cmd_end">
<name>nand_rd_cmd_end</name>
<desc>The NAND command used to initiate a write (0x30)</desc>
<sw_param offset="0xe000e408" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcommand1_1_nand_rd_cmd">
<name>nand_rd_cmd</name>
<desc>The NAND command used to initiate a read (0x00)</desc>
<sw_param offset="0xe000e408" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcommand1_1_nand_wr_cmd">
<name>nand_wr_cmd</name>
<desc>The NAND command used to initiate a write (0x80)</desc>
<sw_param offset="0xe000e408" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcommand2_1_nand_rd_col_change_end_valid">
<name>nand_rd_col_change_end_valid</name>
<desc>Use end command</desc>
<sw_param offset="0xe000e40c" start="24" end="24" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcommand2_1_nand_rd_col_change_end">
<name>nand_rd_col_change_end</name>
<desc>The NAND command used to initiate a write</desc>
<sw_param offset="0xe000e40c" start="23" end="16" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcommand2_1_nand_rd_col_change">
<name>nand_rd_col_change</name>
<desc>The NAND command used to initiate a read or Spare bits pointer command</desc>
<sw_param offset="0xe000e40c" start="15" end="8" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_memcommand2_1_nand_wr_col_change">
<name>nand_wr_col_change</name>
<desc>The NAND command used to initiate a write</desc>
<sw_param offset="0xe000e40c" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_addr0_1_ecc_addr">
<name>ecc_addr</name>
<desc>Address bits 31 to 0</desc>
<sw_param offset="0xe000e410" start="31" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_addr1_1_ecc_addr">
<name>ecc_addr</name>
<desc>Address bits 55 to 32</desc>
<sw_param offset="0xe000e414" start="23" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value0_1_ecc_int">
<name>ecc_int</name>
<desc>Interrupt flag for this value</desc>
<sw_param offset="0xe000e418" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value0_1_ecc_valid">
<name>ecc_valid</name>
<desc>Indicates if this value is valid</desc>
<sw_param offset="0xe000e418" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value0_1_ecc_read">
<name>ecc_read</name>
<desc>Indicates if the ECC value has been read from memory</desc>
<sw_param offset="0xe000e418" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value0_1_ecc_fail">
<name>ecc_fail</name>
<desc>Indicates if this value has failed</desc>
<sw_param offset="0xe000e418" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value0_1_ecc_correct">
<name>ecc_correct</name>
<desc>Indicates if this block is correctable</desc>
<sw_param offset="0xe000e418" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value0_1_reserved">
<name>reserved</name>
<desc>Reserved, read undefined</desc>
<sw_param offset="0xe000e418" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value0_1_ecc_value">
<name>ecc_value</name>
<desc>ECC value of check result for block, depending on ECC configuration</desc>
<sw_param offset="0xe000e418" start="23" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value1_1_ecc_int">
<name>ecc_int</name>
<desc>Interrupt flag for this value</desc>
<sw_param offset="0xe000e41c" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value1_1_ecc_valid">
<name>ecc_valid</name>
<desc>Indicates if this value is valid</desc>
<sw_param offset="0xe000e41c" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value1_1_ecc_read">
<name>ecc_read</name>
<desc>Indicates if the ECC value has been read from memory</desc>
<sw_param offset="0xe000e41c" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value1_1_ecc_fail">
<name>ecc_fail</name>
<desc>Indicates if this value has failed</desc>
<sw_param offset="0xe000e41c" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value1_1_ecc_correct">
<name>ecc_correct</name>
<desc>Indicates if this block is correctable</desc>
<sw_param offset="0xe000e41c" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value1_1_reserved">
<name>reserved</name>
<desc>Reserved, read undefined</desc>
<sw_param offset="0xe000e41c" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value1_1_ecc_value">
<name>ecc_value</name>
<desc>ECC value of check result for block, depending on ECC configuration</desc>
<sw_param offset="0xe000e41c" start="23" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value2_1_ecc_int">
<name>ecc_int</name>
<desc>Interrupt flag for this value</desc>
<sw_param offset="0xe000e420" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value2_1_ecc_valid">
<name>ecc_valid</name>
<desc>Indicates if this value is valid</desc>
<sw_param offset="0xe000e420" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value2_1_ecc_read">
<name>ecc_read</name>
<desc>Indicates if the ECC value has been read from memory</desc>
<sw_param offset="0xe000e420" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value2_1_ecc_fail">
<name>ecc_fail</name>
<desc>Indicates if this value has failed</desc>
<sw_param offset="0xe000e420" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value2_1_ecc_correct">
<name>ecc_correct</name>
<desc>Indicates if this block is correctable</desc>
<sw_param offset="0xe000e420" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value2_1_reserved">
<name>reserved</name>
<desc>Reserved, read undefined</desc>
<sw_param offset="0xe000e420" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value2_1_ecc_value">
<name>ecc_value</name>
<desc>ECC value of check result for block, depending on ECC configuration</desc>
<sw_param offset="0xe000e420" start="23" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value3_1_ecc_int">
<name>ecc_int</name>
<desc>Interrupt flag for this value</desc>
<sw_param offset="0xe000e424" start="31" end="31" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value3_1_ecc_valid">
<name>ecc_valid</name>
<desc>Indicates if this value is valid</desc>
<sw_param offset="0xe000e424" start="30" end="30" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value3_1_ecc_read">
<name>ecc_read</name>
<desc>Indicates if the ECC value has been read from memory</desc>
<sw_param offset="0xe000e424" start="29" end="29" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value3_1_ecc_fail">
<name>ecc_fail</name>
<desc>Indicates if this value has failed</desc>
<sw_param offset="0xe000e424" start="28" end="28" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value3_1_ecc_correct">
<name>ecc_correct</name>
<desc>Indicates if this block is correctable</desc>
<sw_param offset="0xe000e424" start="27" end="27" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value3_1_reserved">
<name>reserved</name>
<desc>Reserved, read undefined</desc>
<sw_param offset="0xe000e424" start="26" end="24" />
</parameter>
<parameter uniqueid="ps7_smcc_ecc_value3_1_ecc_value">
<name>ecc_value</name>
<desc>ECC value of check result for block, depending on ECC configuration</desc>
<sw_param offset="0xe000e424" start="23" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_integration_test_Undefined">
<name>Undefined</name>
<desc>Read undefined. Write as zero.</desc>
<sw_param offset="0xe000ee00" start="31" end="1" />
</parameter>
<parameter uniqueid="ps7_smcc_integration_test_int_test_en">
<name>int_test_en</name>
<desc>When set, outputs are driven from the integration test registers and tied-off, and inputs can change for integration testing</desc>
<sw_param offset="0xe000ee00" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_periph_id_0_part_number_0">
<name>part_number_0</name>
<desc>These bits read back as 0x5x</desc>
<sw_param offset="0xe000efe0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_periph_id_1_designer_0">
<name>designer_0</name>
<desc>These bits read back as 0x1</desc>
<sw_param offset="0xe000efe4" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_smcc_periph_id_1_part_number_1">
<name>part_number_1</name>
<desc>These bits read back as 0x3</desc>
<sw_param offset="0xe000efe4" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_periph_id_2_revision">
<name>revision</name>
<desc>These bits read back as:
[[*]] 0x1 for r1p0
[[*]] 0x2 for r1p1
[[*]] 0x3 for r1p2
[[*]] 0x4 for r2p0
[[*]] 0x5 for r2p1.</desc>
<sw_param offset="0xe000efe8" start="7" end="4" />
</parameter>
<parameter uniqueid="ps7_smcc_periph_id_2_designer_1">
<name>designer_1</name>
<desc>These bits read back as 0x4</desc>
<sw_param offset="0xe000efe8" start="3" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_periph_id_3_integration_cfg">
<name>integration_cfg</name>
<desc>When set, the integration test register map at address offset 0xE00 is present for reading and writing. If clear, the integration test registers have not been implemented</desc>
<sw_param offset="0xe000efec" start="0" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_pcell_id_0_pcell_id_0">
<name>pcell_id_0</name>
<desc>These bits read back as 0x0D</desc>
<sw_param offset="0xe000eff0" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_pcell_id_1_pcell_id_1">
<name>pcell_id_1</name>
<desc>These bits read back as 0xF0</desc>
<sw_param offset="0xe000eff4" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_pcell_id_2_pcell_id_2">
<name>pcell_id_2</name>
<desc>These bits read back as 0x5</desc>
<sw_param offset="0xe000eff8" start="7" end="0" />
</parameter>
<parameter uniqueid="ps7_smcc_pcell_id_3_pcell_id_3">
<name>pcell_id_3</name>
<desc>These bits read back as 0xB1</desc>
<sw_param offset="0xe000effc" start="7" end="0" />
</parameter>
</parameters>
