
*** Running vivado
    with args -log System_wrapper.vdi -applog -m64 -messageDb vivado.pb -mode batch -source System_wrapper.tcl -notrace


****** Vivado v2014.2 (64-bit)
  **** SW Build 928826 on Thu Jun  5 18:17:50 MDT 2014
  **** IP Build 924643 on Fri May 30 09:20:16 MDT 2014
    ** Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.

Sourcing tcl script 'C:\Users\024974\AppData\Roaming/Xilinx/Vivado/init.tcl'
source -notrace "C:/Users/024974/AppData/Roaming/Xilinx/Vivado/init.tcl"
source System_wrapper.tcl -notrace
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Project 1-479] Netlist was created with Vivado 2014.2
Loading clock regions from C:/Xilinx/Vivado/2014.2/data\parts/xilinx/zynq/zynq/xc7z010/ClockRegion.xml
Loading clock buffers from C:/Xilinx/Vivado/2014.2/data\parts/xilinx/zynq/zynq/xc7z010/ClockBuffers.xml
Loading clock placement rules from C:/Xilinx/Vivado/2014.2/data/parts/xilinx/zynq/ClockPlacerRules.xml
Loading package pin functions from C:/Xilinx/Vivado/2014.2/data\parts/xilinx/zynq/PinFunctions.xml...
Loading package from C:/Xilinx/Vivado/2014.2/data\parts/xilinx/zynq/zynq/xc7z010/clg400/Package.xml
Loading io standards from C:/Xilinx/Vivado/2014.2/data\./parts/xilinx/zynq/IOStandards.xml
INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers.
INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers.
Parsing XDC File [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/System_processing_system7_0_0.xdc] for cell 'System_i/processing_system7_0/inst'
Finished Parsing XDC File [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/System_processing_system7_0_0.xdc] for cell 'System_i/processing_system7_0/inst'
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

link_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 445.598 ; gain = 259.934
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.294 . Memory (MB): peak = 449.188 ; gain = 0.566
INFO: [Timing 38-35] Done setting XDC timing constraints.

Starting Logic Optimization Task

Phase 1 Retarget

INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 22311f6e1

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.062 . Memory (MB): peak = 862.945 ; gain = 0.000

Phase 2 Constant Propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-10] Eliminated 0 cells.
Phase 2 Constant Propagation | Checksum: 22311f6e1

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.139 . Memory (MB): peak = 862.945 ; gain = 0.000

Phase 3 Sweep
INFO: [Opt 31-12] Eliminated 19 unconnected nets.
INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers.
INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers.
INFO: [Opt 31-11] Eliminated 90 unconnected cells.
Phase 3 Sweep | Checksum: 1e74eb5db

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.492 . Memory (MB): peak = 862.945 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 1e74eb5db

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.509 . Memory (MB): peak = 862.945 ; gain = 0.000
Implement Debug Cores | Checksum: 22311f6e1
Logic Optimization | Checksum: 22311f6e1

Starting Power Optimization Task
INFO: [Pwropt 34-132] Will skip clock gating for clocks with period < 3.13 ns.
Ending Power Optimization Task | Checksum: 1e74eb5db

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 862.945 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 862.945 ; gain = 417.348
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.341 . Memory (MB): peak = 862.945 ; gain = 0.000
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
Running DRC as a precondition to command place_design
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Phase 1 Placer Runtime Estimator
Phase 1 Placer Runtime Estimator | Checksum: 18daa171d

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.090 . Memory (MB): peak = 862.945 ; gain = 0.000

Phase 2 Placer Initialization

Phase 2.1 Placer Initialization Core
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 862.945 ; gain = 0.000

Phase 2.1.1 Mandatory Logic Optimization
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 862.945 ; gain = 0.000
Phase 2.1.1 Mandatory Logic Optimization | Checksum: a0cc9548

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.135 . Memory (MB): peak = 862.945 ; gain = 0.000

Phase 2.1.2 Build Super Logic Region (SLR) Database
Phase 2.1.2 Build Super Logic Region (SLR) Database | Checksum: a0cc9548

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.151 . Memory (MB): peak = 862.945 ; gain = 0.000

Phase 2.1.3 Add Constraints
Phase 2.1.3 Add Constraints | Checksum: a0cc9548

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.152 . Memory (MB): peak = 862.945 ; gain = 0.000

Phase 2.1.4 Build Shapes/ HD Config

Phase 2.1.4.1 Build Macros
Phase 2.1.4.1 Build Macros | Checksum: 1427c44b2

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.232 . Memory (MB): peak = 862.945 ; gain = 0.000
Phase 2.1.4 Build Shapes/ HD Config | Checksum: 1427c44b2

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.233 . Memory (MB): peak = 862.945 ; gain = 0.000

Phase 2.1.5 IO Placement/ Clock Placement/ Build Placer Device

Phase 2.1.5.1 Pre-Place Cells
Phase 2.1.5.1 Pre-Place Cells | Checksum: a0cc9548

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.250 . Memory (MB): peak = 862.945 ; gain = 0.000
WARNING: [Place 30-12] An IO Bus FIXED_IO_mio with more than one IO standard is found. Components associated with this bus are: 
	FIXED_IO_mio[53] of IOStandard LVCMOS18
	FIXED_IO_mio[52] of IOStandard LVCMOS18
	FIXED_IO_mio[51] of IOStandard LVCMOS18
	FIXED_IO_mio[50] of IOStandard LVCMOS18
	FIXED_IO_mio[49] of IOStandard LVCMOS18
	FIXED_IO_mio[48] of IOStandard LVCMOS18
	FIXED_IO_mio[47] of IOStandard LVCMOS18
	FIXED_IO_mio[46] of IOStandard LVCMOS18
	FIXED_IO_mio[45] of IOStandard LVCMOS18
	FIXED_IO_mio[44] of IOStandard LVCMOS18
	FIXED_IO_mio[43] of IOStandard LVCMOS18
	FIXED_IO_mio[42] of IOStandard LVCMOS18
	FIXED_IO_mio[41] of IOStandard LVCMOS18
	FIXED_IO_mio[40] of IOStandard LVCMOS18
	FIXED_IO_mio[39] of IOStandard LVCMOS18
	FIXED_IO_mio[38] of IOStandard LVCMOS18
	FIXED_IO_mio[37] of IOStandard LVCMOS18
	FIXED_IO_mio[36] of IOStandard LVCMOS18
	FIXED_IO_mio[35] of IOStandard LVCMOS18
	FIXED_IO_mio[34] of IOStandard LVCMOS18
	FIXED_IO_mio[33] of IOStandard LVCMOS18
	FIXED_IO_mio[32] of IOStandard LVCMOS18
	FIXED_IO_mio[31] of IOStandard LVCMOS18
	FIXED_IO_mio[30] of IOStandard LVCMOS18
	FIXED_IO_mio[29] of IOStandard LVCMOS18
	FIXED_IO_mio[28] of IOStandard LVCMOS18
	FIXED_IO_mio[27] of IOStandard LVCMOS18
	FIXED_IO_mio[26] of IOStandard LVCMOS18
	FIXED_IO_mio[25] of IOStandard LVCMOS18
	FIXED_IO_mio[24] of IOStandard LVCMOS18
	FIXED_IO_mio[23] of IOStandard LVCMOS18
	FIXED_IO_mio[22] of IOStandard LVCMOS18
	FIXED_IO_mio[21] of IOStandard LVCMOS18
	FIXED_IO_mio[20] of IOStandard LVCMOS18
	FIXED_IO_mio[19] of IOStandard LVCMOS18
	FIXED_IO_mio[18] of IOStandard LVCMOS18
	FIXED_IO_mio[17] of IOStandard LVCMOS18
	FIXED_IO_mio[16] of IOStandard LVCMOS18
	FIXED_IO_mio[15] of IOStandard LVCMOS33
	FIXED_IO_mio[14] of IOStandard LVCMOS33
	FIXED_IO_mio[13] of IOStandard LVCMOS33
	FIXED_IO_mio[12] of IOStandard LVCMOS33
	FIXED_IO_mio[11] of IOStandard LVCMOS33
	FIXED_IO_mio[10] of IOStandard LVCMOS33
	FIXED_IO_mio[9] of IOStandard LVCMOS33
	FIXED_IO_mio[8] of IOStandard LVCMOS33
	FIXED_IO_mio[7] of IOStandard LVCMOS33
	FIXED_IO_mio[6] of IOStandard LVCMOS33
	FIXED_IO_mio[5] of IOStandard LVCMOS33
	FIXED_IO_mio[4] of IOStandard LVCMOS33
	FIXED_IO_mio[3] of IOStandard LVCMOS33
	FIXED_IO_mio[2] of IOStandard LVCMOS33
	FIXED_IO_mio[1] of IOStandard LVCMOS33
	FIXED_IO_mio[0] of IOStandard LVCMOS33
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 2.1.5.2 IO & Clk Clean Up
Phase 2.1.5.2 IO & Clk Clean Up | Checksum: a0cc9548

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.882 . Memory (MB): peak = 862.945 ; gain = 0.000

Phase 2.1.5.3 Implementation Feasibility check On IDelay
Phase 2.1.5.3 Implementation Feasibility check On IDelay | Checksum: a0cc9548

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.884 . Memory (MB): peak = 862.945 ; gain = 0.000

Phase 2.1.5.4 Commit IO Placement
Phase 2.1.5.4 Commit IO Placement | Checksum: a0cc9548

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.885 . Memory (MB): peak = 862.945 ; gain = 0.000
Phase 2.1.5 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1427c44b2

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.886 . Memory (MB): peak = 862.945 ; gain = 0.000

Phase 2.1.6 Build Placer Netlist Model

Phase 2.1.6.1 Place Init Design

Phase 2.1.6.1.1 Init Lut Pin Assignment
Phase 2.1.6.1.1 Init Lut Pin Assignment | Checksum: 1e78be39c

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 862.945 ; gain = 0.000
Phase 2.1.6.1 Place Init Design | Checksum: 1f5d45c0e

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 862.945 ; gain = 0.000
Phase 2.1.6 Build Placer Netlist Model | Checksum: 1f5d45c0e

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 862.945 ; gain = 0.000

Phase 2.1.7 Constrain Clocks/Macros
Phase 2.1.7 Constrain Clocks/Macros | Checksum: 1f5d45c0e

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 862.945 ; gain = 0.000
Phase 2.1 Placer Initialization Core | Checksum: 1f5d45c0e

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 862.945 ; gain = 0.000
Phase 2 Placer Initialization | Checksum: 1f5d45c0e

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 862.945 ; gain = 0.000

Phase 3 Final Placement Cleanup
Phase 3 Final Placement Cleanup | Checksum: 1f5d45c0e

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 862.945 ; gain = 0.000
INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed
Ending Placer Task | Checksum: 1427c44b2

Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 862.945 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
28 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.186 . Memory (MB): peak = 862.945 ; gain = 0.000
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 862.945 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
Running DRC as a precondition to command route_design
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs

Starting Route Task

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: defd9fd6

Time (s): cpu = 00:00:19 ; elapsed = 00:00:18 . Memory (MB): peak = 940.473 ; gain = 77.527

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: defd9fd6

Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 940.473 ; gain = 77.527
 Number of Nodes with overlaps = 0

Phase 2.2 Update Timing
Phase 2.2 Update Timing | Checksum: 91dcb6d6

Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 946.246 ; gain = 83.301
INFO: [Route 35-57] Estimated Timing Summary | WNS=1.#J   | TNS=0      | WHS=1.#J   | THS=0      |

Phase 2 Router Initialization | Checksum: 91dcb6d6

Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 946.246 ; gain = 83.301

Phase 3 Initial Routing
 Number of Nodes with overlaps = 0
Phase 3 Initial Routing | Checksum: d3f00f07

Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 946.246 ; gain = 83.301

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0

Phase 4.1.1 Update Timing
Phase 4.1.1 Update Timing | Checksum: d3f00f07

Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 946.246 ; gain = 83.301
INFO: [Route 35-57] Estimated Timing Summary | WNS=1.#J   | TNS=0      | WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: d3f00f07

Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 946.246 ; gain = 83.301

Phase 4.2 Global Iteration 1

Phase 4.2.1 Update Timing
Phase 4.2.1 Update Timing | Checksum: d3f00f07

Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 946.246 ; gain = 83.301
INFO: [Route 35-57] Estimated Timing Summary | WNS=1.#J   | TNS=0      | WHS=N/A    | THS=N/A    |

Phase 4.2 Global Iteration 1 | Checksum: d3f00f07

Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 946.246 ; gain = 83.301

Phase 4.3 Global Iteration 2

Phase 4.3.1 Update Timing
Phase 4.3.1 Update Timing | Checksum: d3f00f07

Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 946.246 ; gain = 83.301
INFO: [Route 35-57] Estimated Timing Summary | WNS=1.#J   | TNS=0      | WHS=N/A    | THS=N/A    |

Phase 4.3 Global Iteration 2 | Checksum: d3f00f07

Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 946.246 ; gain = 83.301

Phase 4.4 Global Iteration 3

Phase 4.4.1 Update Timing
Phase 4.4.1 Update Timing | Checksum: d3f00f07

Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 946.246 ; gain = 83.301
INFO: [Route 35-57] Estimated Timing Summary | WNS=1.#J   | TNS=0      | WHS=N/A    | THS=N/A    |

Phase 4.4 Global Iteration 3 | Checksum: d3f00f07

Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 946.246 ; gain = 83.301

Phase 4.5 Global Iteration 4

Phase 4.5.1 Update Timing
Phase 4.5.1 Update Timing | Checksum: d3f00f07

Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 946.246 ; gain = 83.301
INFO: [Route 35-57] Estimated Timing Summary | WNS=1.#J   | TNS=0      | WHS=N/A    | THS=N/A    |

Phase 4.5 Global Iteration 4 | Checksum: d3f00f07

Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 946.246 ; gain = 83.301
Phase 4 Rip-up And Reroute | Checksum: d3f00f07

Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 946.246 ; gain = 83.301

Phase 5 Delay CleanUp

Phase 5.1 Update Timing
Phase 5.1 Update Timing | Checksum: d3f00f07

Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 946.246 ; gain = 83.301
INFO: [Route 35-57] Estimated Timing Summary | WNS=1.#J   | TNS=0      | WHS=N/A    | THS=N/A    |

Phase 5 Delay CleanUp | Checksum: d3f00f07

Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 946.246 ; gain = 83.301

Phase 6 Clock Skew Optimization
Phase 6 Clock Skew Optimization | Checksum: d3f00f07

Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 946.246 ; gain = 83.301

Phase 7 Post Hold Fix

Phase 7.1 Update Timing
Phase 7.1 Update Timing | Checksum: d3f00f07

Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 946.246 ; gain = 83.301
INFO: [Route 35-57] Estimated Timing Summary | WNS=1.#J   | TNS=0      | WHS=1.#J   | THS=0      |

Phase 7 Post Hold Fix | Checksum: d3f00f07

Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 946.246 ; gain = 83.301

Phase 8 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 0 %
  Global Horizontal Routing Utilization  = 0 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 8 Route finalize | Checksum: d3f00f07

Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 946.246 ; gain = 83.301

Phase 9 Verifying routed nets

 Verification completed successfully
Phase 9 Verifying routed nets | Checksum: d3f00f07

Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 947.797 ; gain = 84.852

Phase 10 Depositing Routes
Phase 10 Depositing Routes | Checksum: d3f00f07

Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 947.797 ; gain = 84.852

Phase 11 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=1.#J   | TNS=0      | WHS=1.#J   | THS=0      |

INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 11 Post Router Timing | Checksum: d3f00f07

Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 947.797 ; gain = 84.852
INFO: [Route 35-16] Router Completed Successfully
Ending Route Task | Checksum: d3f00f07

Time (s): cpu = 00:00:00 ; elapsed = 00:00:20 . Memory (MB): peak = 947.797 ; gain = 84.852

Routing Is Done.

Time (s): cpu = 00:00:00 ; elapsed = 00:00:21 . Memory (MB): peak = 947.797 ; gain = 84.852
INFO: [Common 17-83] Releasing license: Implementation
45 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 947.797 ; gain = 84.852
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.210 . Memory (MB): peak = 947.797 ; gain = 0.000
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.runs/impl_1/System_wrapper_drc_routed.rpt.
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Constraints type: SDC.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
Running DRC as a precondition to command write_bitstream
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./System_wrapper.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Common 17-83] Releasing license: Implementation
write_bitstream: Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 1274.453 ; gain = 321.902
INFO: [Common 17-206] Exiting Vivado at Wed Jun 11 13:22:59 2014...
