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// IP VLNV: xilinx.com:ip:processing_system7:5.4
// IP Revision: 1

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
System_processing_system7_0_0 your_instance_name (
  .TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),            // output wire TTC0_WAVE0_OUT
  .TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),            // output wire TTC0_WAVE1_OUT
  .TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),            // output wire TTC0_WAVE2_OUT
  .USB0_PORT_INDCTL(USB0_PORT_INDCTL),        // output wire [1 : 0] USB0_PORT_INDCTL
  .USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),  // output wire USB0_VBUS_PWRSELECT
  .USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),    // input wire USB0_VBUS_PWRFAULT
  .FCLK_CLK0(FCLK_CLK0),                      // output wire FCLK_CLK0
  .FCLK_RESET0_N(FCLK_RESET0_N),              // output wire FCLK_RESET0_N
  .MIO(MIO),                                  // inout wire [53 : 0] MIO
  .DDR_CAS_n(DDR_CAS_n),                      // inout wire DDR_CAS_n
  .DDR_CKE(DDR_CKE),                          // inout wire DDR_CKE
  .DDR_Clk_n(DDR_Clk_n),                      // inout wire DDR_Clk_n
  .DDR_Clk(DDR_Clk),                          // inout wire DDR_Clk
  .DDR_CS_n(DDR_CS_n),                        // inout wire DDR_CS_n
  .DDR_DRSTB(DDR_DRSTB),                      // inout wire DDR_DRSTB
  .DDR_ODT(DDR_ODT),                          // inout wire DDR_ODT
  .DDR_RAS_n(DDR_RAS_n),                      // inout wire DDR_RAS_n
  .DDR_WEB(DDR_WEB),                          // inout wire DDR_WEB
  .DDR_BankAddr(DDR_BankAddr),                // inout wire [2 : 0] DDR_BankAddr
  .DDR_Addr(DDR_Addr),                        // inout wire [14 : 0] DDR_Addr
  .DDR_VRN(DDR_VRN),                          // inout wire DDR_VRN
  .DDR_VRP(DDR_VRP),                          // inout wire DDR_VRP
  .DDR_DM(DDR_DM),                            // inout wire [3 : 0] DDR_DM
  .DDR_DQ(DDR_DQ),                            // inout wire [31 : 0] DDR_DQ
  .DDR_DQS_n(DDR_DQS_n),                      // inout wire [3 : 0] DDR_DQS_n
  .DDR_DQS(DDR_DQS),                          // inout wire [3 : 0] DDR_DQS
  .PS_SRSTB(PS_SRSTB),                        // inout wire PS_SRSTB
  .PS_CLK(PS_CLK),                            // inout wire PS_CLK
  .PS_PORB(PS_PORB)                          // inout wire PS_PORB
);
// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file System_processing_system7_0_0.v when simulating
// the core, System_processing_system7_0_0. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.

