<?xml version="1.0" encoding="UTF-8" ?> 
<!DOCTYPE codegen PUBLIC "codegen" "codegen.dtd" >
<codegen version="">
  <funcname name="ps7_clock_init_data_2_0"/>  
  <group cmt="SLCR Settings">
    <force param="ps7_slcr_slcr_unlock_unlock_key" value="0xDF0D" />
  </group>  
    <group cmt="Clock control SLCR registers ">
      <param param="ps7_slcr_DCI_CLK_CTRL_CLKACT"/>
      <param param="ps7_slcr_DCI_CLK_CTRL_DIVISOR0"/>
      <param param="ps7_slcr_DCI_CLK_CTRL_DIVISOR1"/>
      <param param="ps7_slcr_USB0_CLK_CTRL_CLKACT"/>
      <param param="ps7_slcr_USB0_CLK_CTRL_SRCSEL"/>
      <param param="ps7_slcr_USB0_CLK_CTRL_DIVISOR0"/>
      <param param="ps7_slcr_USB0_CLK_CTRL_DIVISOR1"/>
      <param param="ps7_slcr_USB1_CLK_CTRL_CLKACT"/>
      <param param="ps7_slcr_USB1_CLK_CTRL_SRCSEL"/>
      <param param="ps7_slcr_USB1_CLK_CTRL_DIVISOR0"/>
      <param param="ps7_slcr_USB1_CLK_CTRL_DIVISOR1"/>
      <param param="ps7_slcr_GEM0_RCLK_CTRL_CLKACT"/>
      <param param="ps7_slcr_GEM0_RCLK_CTRL_SRCSEL"/>
      <param param="ps7_slcr_GEM1_RCLK_CTRL_CLKACT"/>
      <param param="ps7_slcr_GEM1_RCLK_CTRL_SRCSEL"/>
      <param param="ps7_slcr_GEM0_CLK_CTRL_CLKACT"/>
      <param param="ps7_slcr_GEM0_CLK_CTRL_SRCSEL"/>
      <param param="ps7_slcr_GEM0_CLK_CTRL_DIVISOR"/>
      <param param="ps7_slcr_GEM0_CLK_CTRL_DIVISOR1"/>
      <param param="ps7_slcr_GEM1_CLK_CTRL_CLKACT"/>
      <param param="ps7_slcr_GEM1_CLK_CTRL_SRCSEL"/>
      <param param="ps7_slcr_GEM1_CLK_CTRL_DIVISOR"/>
      <param param="ps7_slcr_GEM1_CLK_CTRL_DIVISOR1"/>
      <param param="ps7_slcr_SMC_CLK_CTRL_CLKACT"/>
      <param param="ps7_slcr_SMC_CLK_CTRL_SRCSEL"/>
      <param param="ps7_slcr_SMC_CLK_CTRL_DIVISOR"/>
      <param param="ps7_slcr_LQSPI_CLK_CTRL_CLKACT"/>
      <param param="ps7_slcr_LQSPI_CLK_CTRL_SRCSEL"/>
      <param param="ps7_slcr_LQSPI_CLK_CTRL_DIVISOR"/>
      <param param="ps7_slcr_SDIO_CLK_CTRL_CLKACT0"/>
      <param param="ps7_slcr_SDIO_CLK_CTRL_CLKACT1"/>
      <param param="ps7_slcr_SDIO_CLK_CTRL_SRCSEL"/>
      <param param="ps7_slcr_SDIO_CLK_CTRL_DIVISOR"/>
      <param param="ps7_slcr_UART_CLK_CTRL_CLKACT0"/>
      <param param="ps7_slcr_UART_CLK_CTRL_CLKACT1"/>
      <param param="ps7_slcr_UART_CLK_CTRL_SRCSEL"/>
      <param param="ps7_slcr_UART_CLK_CTRL_DIVISOR"/>
      <param param="ps7_slcr_SPI_CLK_CTRL_CLKACT0"/>
      <param param="ps7_slcr_SPI_CLK_CTRL_CLKACT1"/>
      <param param="ps7_slcr_SPI_CLK_CTRL_SRCSEL"/>
      <param param="ps7_slcr_SPI_CLK_CTRL_DIVISOR"/>
      <param param="ps7_slcr_CAN_CLK_CTRL_CLKACT0"/>
      <param param="ps7_slcr_CAN_CLK_CTRL_CLKACT1"/>
      <param param="ps7_slcr_CAN_CLK_CTRL_SRCSEL"/>
      <param param="ps7_slcr_CAN_CLK_CTRL_DIVISOR0"/>
      <param param="ps7_slcr_CAN_CLK_CTRL_DIVISOR1"/>
      <param param="ps7_slcr_CAN_MIOCLK_CTRL_CAN0_MUX"/>
      <param param="ps7_slcr_CAN_MIOCLK_CTRL_CAN0_REF_SEL"/>
      <param param="ps7_slcr_CAN_MIOCLK_CTRL_CAN1_MUX"/>
      <param param="ps7_slcr_CAN_MIOCLK_CTRL_CAN1_REF_SEL"/>
      <param param="ps7_slcr_DBG_CLK_CTRL_CLKACT_TRC"/>
      <param param="ps7_slcr_DBG_CLK_CTRL_CPU_1XCLKACT"/>
      <param param="ps7_slcr_DBG_CLK_CTRL_SRCSEL"/>
      <param param="ps7_slcr_DBG_CLK_CTRL_DIVISOR"/>
      <param param="ps7_slcr_PCAP_CLK_CTRL_CLKACT"/>
      <param param="ps7_slcr_PCAP_CLK_CTRL_SRCSEL"/>
      <param param="ps7_slcr_PCAP_CLK_CTRL_DIVISOR"/>
      <param param="ps7_slcr_TOPSW_CLK_CTRL_CLK_DIS"/>
      <param param="ps7_slcr_FPGA0_CLK_CTRL_SRCSEL"/>
      <param param="ps7_slcr_FPGA0_CLK_CTRL_DIVISOR0"/>
      <param param="ps7_slcr_FPGA0_CLK_CTRL_DIVISOR1"/>
      <param param="ps7_slcr_FPGA1_CLK_CTRL_SRCSEL"/>
      <param param="ps7_slcr_FPGA1_CLK_CTRL_DIVISOR0"/>
      <param param="ps7_slcr_FPGA1_CLK_CTRL_DIVISOR1"/>
      <param param="ps7_slcr_FPGA2_CLK_CTRL_SRCSEL"/>
      <param param="ps7_slcr_FPGA2_CLK_CTRL_DIVISOR0"/>
      <param param="ps7_slcr_FPGA2_CLK_CTRL_DIVISOR1"/>
      <param param="ps7_slcr_FPGA3_CLK_CTRL_SRCSEL"/>
      <param param="ps7_slcr_FPGA3_CLK_CTRL_DIVISOR0"/>
      <param param="ps7_slcr_FPGA3_CLK_CTRL_DIVISOR1"/>
      <param param="ps7_slcr_CLK_621_TRUE_CLK_621_TRUE"/>
      <param param="ps7_slcr_APER_CLK_CTRL_DMA_CPU_2XCLKACT"/>
      <param param="ps7_slcr_APER_CLK_CTRL_USB0_CPU_1XCLKACT"/>
      <param param="ps7_slcr_APER_CLK_CTRL_USB1_CPU_1XCLKACT"/>
      <param param="ps7_slcr_APER_CLK_CTRL_GEM0_CPU_1XCLKACT"/>
      <param param="ps7_slcr_APER_CLK_CTRL_GEM1_CPU_1XCLKACT"/>
      <param param="ps7_slcr_APER_CLK_CTRL_SDI0_CPU_1XCLKACT"/>
      <param param="ps7_slcr_APER_CLK_CTRL_SDI1_CPU_1XCLKACT"/>
      <param param="ps7_slcr_APER_CLK_CTRL_SPI0_CPU_1XCLKACT"/>
      <param param="ps7_slcr_APER_CLK_CTRL_SPI1_CPU_1XCLKACT"/>
      <param param="ps7_slcr_APER_CLK_CTRL_CAN0_CPU_1XCLKACT"/>
      <param param="ps7_slcr_APER_CLK_CTRL_CAN1_CPU_1XCLKACT"/>
      <param param="ps7_slcr_APER_CLK_CTRL_I2C0_CPU_1XCLKACT"/>
      <param param="ps7_slcr_APER_CLK_CTRL_I2C1_CPU_1XCLKACT"/>
      <param param="ps7_slcr_APER_CLK_CTRL_UART0_CPU_1XCLKACT"/>
      <param param="ps7_slcr_APER_CLK_CTRL_UART1_CPU_1XCLKACT"/>
      <param param="ps7_slcr_APER_CLK_CTRL_GPIO_CPU_1XCLKACT"/>
      <param param="ps7_slcr_APER_CLK_CTRL_LQSPI_CPU_1XCLKACT"/>
      <param param="ps7_slcr_APER_CLK_CTRL_SMC_CPU_1XCLKACT"/>
      <param param="ps7_slcr_PICTURE_DBG_START"/>
      <param param="ps7_slcr_PICTURE_DBG_TRIGGER_SEL"/>
      <param param="ps7_slcr_PICTURE_DBG_CNT_LOAD"/>
      <param param="ps7_slcr_PICTURE_DBG_TRIGGER_EN"/>
      <param param="ps7_slcr_PICTURE_DBG_CLOCK_SEL"/>
      <param param="ps7_slcr_PICTURE_DBG_UCNT_COUNT_UPPER"/>
      <param param="ps7_slcr_PICTURE_DBG_LCNT_COUNT_LOWER"/>
      <param param="ps7_slcr_PSS_RST_CTRL_SOFT_RST"/>
      <param param="ps7_slcr_DDR_RST_CTRL_DDR_RST"/>
      <param param="ps7_slcr_DMAC_RST_CTRL_DMAC_RST"/>
      <param param="ps7_slcr_USB_RST_CTRL_USB0_CPU1X_RST"/>
      <param param="ps7_slcr_USB_RST_CTRL_USB1_CPU1X_RST"/>
      <param param="ps7_slcr_GEM_RST_CTRL_GEM0_CPU1X_RST"/>
      <param param="ps7_slcr_GEM_RST_CTRL_GEM1_CPU1X_RST"/>
      <param param="ps7_slcr_GEM_RST_CTRL_GEM0_RX_RST"/>
      <param param="ps7_slcr_GEM_RST_CTRL_GEM1_RX_RST"/>
      <param param="ps7_slcr_GEM_RST_CTRL_GEM0_REF_RST"/>
      <param param="ps7_slcr_GEM_RST_CTRL_GEM1_REF_RST"/>
      <param param="ps7_slcr_SDIO_RST_CTRL_SDIO0_CPU1X_RST"/>
      <param param="ps7_slcr_SDIO_RST_CTRL_SDIO1_CPU1X_RST"/>
      <param param="ps7_slcr_SDIO_RST_CTRL_SDIO0_REF_RST"/>
      <param param="ps7_slcr_SDIO_RST_CTRL_SDIO1_REF_RST"/>
      <param param="ps7_slcr_SPI_RST_CTRL_SPI0_CPU1X_RST"/>
      <param param="ps7_slcr_SPI_RST_CTRL_SPI1_CPU1X_RST"/>
      <param param="ps7_slcr_SPI_RST_CTRL_SPI0_REF_RST"/>
      <param param="ps7_slcr_SPI_RST_CTRL_SPI1_REF_RST"/>
      <param param="ps7_slcr_CAN_RST_CTRL_CAN0_CPU1X_RST"/>
      <param param="ps7_slcr_CAN_RST_CTRL_CAN1_CPU1X_RST"/>
      <param param="ps7_slcr_CAN_RST_CTRL_CAN0_REF_RST"/>
      <param param="ps7_slcr_CAN_RST_CTRL_CAN1_REF_RST"/>
      <param param="ps7_slcr_I2C_RST_CTRL_I2C0_CPU1X_RST"/>
      <param param="ps7_slcr_I2C_RST_CTRL_I2C1_CPU1X_RST"/>
      <param param="ps7_slcr_UART_RST_CTRL_UART0_CPU1X_RST"/>
      <param param="ps7_slcr_UART_RST_CTRL_UART1_CPU1X_RST"/>
      <param param="ps7_slcr_UART_RST_CTRL_UART0_REF_RST"/>
      <param param="ps7_slcr_UART_RST_CTRL_UART1_REF_RST"/>
      <param param="ps7_slcr_GPIO_RST_CTRL_GPIO_CPU1X_RST"/>
      <param param="ps7_slcr_LQSPI_RST_CTRL_LQSPI_CPU1X_RST"/>
      <param param="ps7_slcr_LQSPI_RST_CTRL_QSPI_REF_RST"/>
      <param param="ps7_slcr_SMC_RST_CTRL_SMC_CPU1X_RST"/>
      <param param="ps7_slcr_SMC_RST_CTRL_SMC_REF_RST"/>
      <param param="ps7_slcr_OCM_RST_CTRL_OCM_RST"/>
      <param param="ps7_slcr_DEVCI_RST_CTRL_PCAP2X_RST"/>
      <param param="ps7_slcr_DEVCI_RST_CTRL_DEVCI_CPU1X_RST"/>
      <param param="ps7_slcr_FPGA_RST_CTRL_FPGA0_OUT_RST"/>
      <param param="ps7_slcr_FPGA_RST_CTRL_FPGA1_OUT_RST"/>
      <param param="ps7_slcr_FPGA_RST_CTRL_FPGA2_OUT_RST"/>
      <param param="ps7_slcr_FPGA_RST_CTRL_FPGA3_OUT_RST"/>
      <param param="ps7_slcr_FPGA_RST_CTRL_FPGA_DMA0_RST"/>
      <param param="ps7_slcr_FPGA_RST_CTRL_FPGA_DMA1_RST"/>
      <param param="ps7_slcr_FPGA_RST_CTRL_FPGA_DMA2_RST"/>
      <param param="ps7_slcr_FPGA_RST_CTRL_FPGA_DMA3_RST"/>
      <param param="ps7_slcr_FPGA_RST_CTRL_FPGA_FMSW0_RST"/>
      <param param="ps7_slcr_FPGA_RST_CTRL_FPGA_FMSW1_RST"/>
      <param param="ps7_slcr_FPGA_RST_CTRL_FSSW0_FPGA_RST"/>
      <param param="ps7_slcr_FPGA_RST_CTRL_FSSW1_FPGA_RST"/>
      <param param="ps7_slcr_FPGA_RST_CTRL_FPGA_AXDS0_RST"/>
      <param param="ps7_slcr_FPGA_RST_CTRL_FPGA_AXDS1_RST"/>
      <param param="ps7_slcr_FPGA_RST_CTRL_FPGA_AXDS2_RST"/>
      <param param="ps7_slcr_FPGA_RST_CTRL_FPGA_AXDS3_RST"/>
      <param param="ps7_slcr_FPGA_RST_CTRL_FPGA_ACP_RST"/>
      <param param="ps7_slcr_A9_CPU_RST_CTRL_A9_RST0"/>
      <param param="ps7_slcr_A9_CPU_RST_CTRL_A9_RST1"/>
      <param param="ps7_slcr_A9_CPU_RST_CTRL_A9_CLKSTOP0"/>
      <param param="ps7_slcr_A9_CPU_RST_CTRL_A9_CLKSTOP1"/>
      <param param="ps7_slcr_A9_CPU_RST_CTRL_PERI_RST"/>
      <param param="ps7_slcr_RS_AWDT_CTRL_CTRL0"/>
      <param param="ps7_slcr_RS_AWDT_CTRL_CTRL1"/>
      <param param="ps7_slcr_RST_REASON_CLR_CLEAR"/>
      <param param="ps7_slcr_RST_REASON_SWDT_RST"/>
      <param param="ps7_slcr_RST_REASON_AWDT0_RST"/>
      <param param="ps7_slcr_RST_REASON_AWDT1_RST"/>
      <param param="ps7_slcr_RST_REASON_SLC_RST"/>
      <param param="ps7_slcr_RST_REASON_DBG_RST"/>
      <param param="ps7_slcr_RST_REASON_SRST_B"/>
      <param param="ps7_slcr_RST_REASON_POR"/>
      <param param="ps7_slcr_REBOOT_STATUS_REBOOT_STATE"/>
      <param param="ps7_slcr_BOOT_MODE_BOOT_MODE"/>
      <param param="ps7_slcr_BOOT_MODE_PLL_BYPASS"/>
      <param param="ps7_slcr_APU_CTRL_CP15SDISABLE"/>
      <param param="ps7_slcr_APU_CTRL_CFGSDISABLE"/>
      <param param="ps7_slcr_WDT_CLK_SEL_SEL"/>
      <param param="ps7_slcr_DBG_CTRL_SRST_B_TRI_B"/>
      <param param="ps7_slcr_DDR_URGENT_S0_AWURGENT"/>
      <param param="ps7_slcr_DDR_URGENT_S1_AWURGENT"/>
      <param param="ps7_slcr_DDR_URGENT_S2_AWURGENT"/>
      <param param="ps7_slcr_DDR_URGENT_S3_AWURGENT"/>
      <param param="ps7_slcr_DDR_URGENT_S0_ARURGENT"/>
      <param param="ps7_slcr_DDR_URGENT_S1_ARURGENT"/>
      <param param="ps7_slcr_DDR_URGENT_S2_ARURGENT"/>
      <param param="ps7_slcr_DDR_URGENT_S3_ARURGENT"/>
      <param param="ps7_slcr_DDR_REF_START_START_REF"/>
      <param param="ps7_slcr_DDR_CMD_STA_CMD_Q_NEMPTY"/>
      <param param="ps7_slcr_DDR_URGENT_SEL_S0_AWQOS_MODE"/>
      <param param="ps7_slcr_DDR_URGENT_SEL_S1_AWQOS_MODE"/>
      <param param="ps7_slcr_DDR_URGENT_SEL_S2_AWQOS_MODE"/>
      <param param="ps7_slcr_DDR_URGENT_SEL_S3_AWQOS_MODE"/>
      <param param="ps7_slcr_DDR_URGENT_SEL_S0_ARQOS_MODE"/>
      <param param="ps7_slcr_DDR_URGENT_SEL_S1_ARQOS_MODE"/>
      <param param="ps7_slcr_DDR_URGENT_SEL_S2_ARQOS_MODE"/>
      <param param="ps7_slcr_DDR_URGENT_SEL_S3_ARQOS_MODE"/>
  </group>
  <group cmt="this should be blank ">
    <param param="ps7_sd0_Debug_Selection_Debug_sel"/>
    <param param="ps7_sd1_Debug_Selection_Debug_sel"/>
  </group>  
  <group cmt="Lock it back">
    <force param="ps7_slcr_slcr_lock_lock_key" value="0x767B"/>
  </group>
</codegen>
