#-----------------------------------------------------------
# Vivado v2014.2 (64-bit)
# SW Build 928826 on Thu Jun  5 18:17:50 MDT 2014
# IP Build 924643 on Fri May 30 09:20:16 MDT 2014
# Start of session at: Wed Jun 11 13:20:32 2014
# Process ID: 8312
# Log file: C:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.runs/synth_1/System_wrapper.vds
# Journal file: C:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.runs/synth_1\vivado.jou
#-----------------------------------------------------------
Sourcing tcl script 'C:\Users\024974\AppData\Roaming/Xilinx/Vivado/init.tcl'
source "C:/Users/024974/AppData/Roaming/Xilinx/Vivado/init.tcl"
# set_param project.boardPartRepoPaths.editable true
# set_param project.boardPartRepoPaths C:/AvnetBoards
source System_wrapper.tcl
# set_param gui.test TreeTableDev
# set_param project.boardPartRepoPaths.editable 1
# set_msg_config -id {HDL 9-1061} -limit 100000
# set_msg_config -id {HDL 9-1654} -limit 100000
# create_project -in_memory -part xc7z010clg400-1
# set_property target_language Verilog [current_project]
# set_property board_part_repo_paths C:/AvnetBoards [current_project]
# set_property board_part em.avnet.com:microzed_7010:part0:1.0 [current_project]
# set_param project.compositeFile.enableAutoGeneration 0
# set_property default_lib xil_defaultlib [current_project]
# add_files C:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/System.bd
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2014.2/data/ip'.
# set_property used_in_implementation false [get_files -all c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/System_processing_system7_0_0.xdc]
# set_property used_in_implementation false [get_files -all C:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/System_ooc.xdc]
# set_msg_config -id {IP_Flow 19-2162} -severity warning -new_severity info
# set_property is_locked true [get_files C:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/System.bd]
# read_verilog -library xil_defaultlib C:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/hdl/System_wrapper.v
WARNING: [filemgmt 20-1763] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [C:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/hdl/System_wrapper.v]
# read_xdc dont_touch.xdc
# set_property used_in_implementation false [get_files dont_touch.xdc]
# set_param synth.vivado.isSynthRun true
# set_property webtalk.parent_dir C:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.cache/wt [current_project]
# set_property parent.project_dir C:/Avnet/MicroZed/Projects/MZ_Basic_System [current_project]
# catch { write_hwdef -file System_wrapper.hwdef }
# synth_design -top System_wrapper -part xc7z010clg400-1
Command: synth_design -top System_wrapper -part xc7z010clg400-1

Starting synthesis...

Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010'
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:12 . Memory (MB): peak = 249.281 ; gain = 115.773
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'System_wrapper' [C:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/hdl/System_wrapper.v:12]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [C:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/hdl/System_wrapper.v:78]
INFO: [Synth 8-638] synthesizing module 'System' [C:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/hdl/System.v:13]
INFO: [Synth 8-638] synthesizing module 'GND' [C:/Xilinx/Vivado/2014.2/scripts/rt/data/unisim_comp.v:3852]
INFO: [Synth 8-256] done synthesizing module 'GND' (1#1) [C:/Xilinx/Vivado/2014.2/scripts/rt/data/unisim_comp.v:3852]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [C:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/hdl/System.v:82]
INFO: [Synth 8-638] synthesizing module 'System_processing_system7_0_0' [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/synth/System_processing_system7_0_0.v:57]
INFO: [Synth 8-638] synthesizing module 'processing_system7_v5_4_processing_system7' [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:153]
	Parameter C_USE_DEFAULT_ACP_USER_VAL bound to: 0 - type: integer 
	Parameter C_S_AXI_ACP_ARUSER_VAL bound to: 31 - type: integer 
	Parameter C_S_AXI_ACP_AWUSER_VAL bound to: 31 - type: integer 
	Parameter C_M_AXI_GP0_THREAD_ID_WIDTH bound to: 12 - type: integer 
	Parameter C_M_AXI_GP1_THREAD_ID_WIDTH bound to: 12 - type: integer 
	Parameter C_M_AXI_GP0_ENABLE_STATIC_REMAP bound to: 0 - type: integer 
	Parameter C_M_AXI_GP1_ENABLE_STATIC_REMAP bound to: 0 - type: integer 
	Parameter C_M_AXI_GP0_ID_WIDTH bound to: 12 - type: integer 
	Parameter C_M_AXI_GP1_ID_WIDTH bound to: 12 - type: integer 
	Parameter C_S_AXI_GP0_ID_WIDTH bound to: 6 - type: integer 
	Parameter C_S_AXI_GP1_ID_WIDTH bound to: 6 - type: integer 
	Parameter C_S_AXI_HP0_ID_WIDTH bound to: 6 - type: integer 
	Parameter C_S_AXI_HP1_ID_WIDTH bound to: 6 - type: integer 
	Parameter C_S_AXI_HP2_ID_WIDTH bound to: 6 - type: integer 
	Parameter C_S_AXI_HP3_ID_WIDTH bound to: 6 - type: integer 
	Parameter C_S_AXI_ACP_ID_WIDTH bound to: 3 - type: integer 
	Parameter C_S_AXI_HP0_DATA_WIDTH bound to: 64 - type: integer 
	Parameter C_S_AXI_HP1_DATA_WIDTH bound to: 64 - type: integer 
	Parameter C_S_AXI_HP2_DATA_WIDTH bound to: 64 - type: integer 
	Parameter C_S_AXI_HP3_DATA_WIDTH bound to: 64 - type: integer 
	Parameter C_INCLUDE_ACP_TRANS_CHECK bound to: 0 - type: integer 
	Parameter C_NUM_F2P_INTR_INPUTS bound to: 1 - type: integer 
	Parameter C_FCLK_CLK0_BUF bound to: true - type: string 
	Parameter C_FCLK_CLK1_BUF bound to: false - type: string 
	Parameter C_FCLK_CLK2_BUF bound to: false - type: string 
	Parameter C_FCLK_CLK3_BUF bound to: false - type: string 
	Parameter C_EMIO_GPIO_WIDTH bound to: 64 - type: integer 
	Parameter C_INCLUDE_TRACE_BUFFER bound to: 0 - type: integer 
	Parameter C_TRACE_BUFFER_FIFO_SIZE bound to: 128 - type: integer 
	Parameter C_TRACE_BUFFER_CLOCK_DELAY bound to: 12 - type: integer 
	Parameter USE_TRACE_DATA_EDGE_DETECTOR bound to: 0 - type: integer 
	Parameter C_TRACE_PIPELINE_WIDTH bound to: 8 - type: integer 
	Parameter C_PS7_SI_REV bound to: PRODUCTION - type: string 
	Parameter C_EN_EMIO_ENET0 bound to: 0 - type: integer 
	Parameter C_EN_EMIO_ENET1 bound to: 0 - type: integer 
	Parameter C_EN_EMIO_TRACE bound to: 0 - type: integer 
	Parameter C_DQ_WIDTH bound to: 32 - type: integer 
	Parameter C_DQS_WIDTH bound to: 4 - type: integer 
	Parameter C_DM_WIDTH bound to: 4 - type: integer 
	Parameter C_MIO_PRIMITIVE bound to: 54 - type: integer 
	Parameter C_PACKAGE_NAME bound to: clg400 - type: string 
	Parameter C_IRQ_F2P_MODE bound to: DIRECT - type: string 
INFO: [Synth 8-638] synthesizing module 'BUFG' [C:/Xilinx/Vivado/2014.2/scripts/rt/data/unisim_comp.v:606]
INFO: [Synth 8-256] done synthesizing module 'BUFG' (2#1) [C:/Xilinx/Vivado/2014.2/scripts/rt/data/unisim_comp.v:606]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2217]
INFO: [Synth 8-638] synthesizing module 'BIBUF' [C:/Xilinx/Vivado/2014.2/scripts/rt/data/unisim_comp.v:268]
INFO: [Synth 8-256] done synthesizing module 'BIBUF' (3#1) [C:/Xilinx/Vivado/2014.2/scripts/rt/data/unisim_comp.v:268]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2218]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2219]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2220]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2221]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2222]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2223]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2224]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2225]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2226]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2227]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2228]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2229]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2230]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2235]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2241]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2241]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2241]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2247]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2247]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2247]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2247]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2247]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2247]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2247]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2247]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2247]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2247]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2247]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2247]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2247]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2247]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2247]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2253]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2253]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2253]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2253]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2259]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2259]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2259]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2259]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2259]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2259]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2259]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:2259]
INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-638] synthesizing module 'PS7' [C:/Xilinx/Vivado/2014.2/scripts/rt/data/unisim_comp.v:26452]
INFO: [Synth 8-256] done synthesizing module 'PS7' (4#1) [C:/Xilinx/Vivado/2014.2/scripts/rt/data/unisim_comp.v:26452]
WARNING: [Synth 8-3848] Net ENET0_GMII_TX_EN in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:212]
WARNING: [Synth 8-3848] Net ENET0_GMII_TX_ER in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:213]
WARNING: [Synth 8-3848] Net ENET0_GMII_TXD in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:229]
WARNING: [Synth 8-3848] Net ENET1_GMII_TX_EN in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:243]
WARNING: [Synth 8-3848] Net ENET1_GMII_TX_ER in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:244]
WARNING: [Synth 8-3848] Net ENET1_GMII_TXD in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:258]
WARNING: [Synth 8-3848] Net TRACE_CTL_PIPE[0] in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:1300]
WARNING: [Synth 8-3848] Net TRACE_DATA_PIPE[0] in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:1301]
WARNING: [Synth 8-3848] Net TRACE_CLK_OUT in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:405]
WARNING: [Synth 8-3848] Net ENET0_GMII_COL_i in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:1048]
WARNING: [Synth 8-3848] Net ENET0_GMII_CRS_i in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:1049]
WARNING: [Synth 8-3848] Net ENET0_GMII_RXD_i in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:1052]
WARNING: [Synth 8-3848] Net ENET0_GMII_RX_DV_i in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:1050]
WARNING: [Synth 8-3848] Net ENET0_GMII_RX_ER_i in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:1051]
WARNING: [Synth 8-3848] Net ENET1_GMII_COL_i in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:1057]
WARNING: [Synth 8-3848] Net ENET1_GMII_CRS_i in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:1058]
WARNING: [Synth 8-3848] Net ENET1_GMII_RXD_i in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:1061]
WARNING: [Synth 8-3848] Net ENET1_GMII_RX_DV_i in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:1059]
WARNING: [Synth 8-3848] Net ENET1_GMII_RX_ER_i in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:1060]
WARNING: [Synth 8-3848] Net FTMD_TRACEIN_ATID_i in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:1070]
WARNING: [Synth 8-3848] Net FTMD_TRACEIN_DATA_i in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:1068]
WARNING: [Synth 8-3848] Net FTMD_TRACEIN_VALID_i in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:1069]
INFO: [Synth 8-256] done synthesizing module 'processing_system7_v5_4_processing_system7' (5#1) [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:153]
WARNING: [Synth 8-350] instance 'inst' of module 'processing_system7_v5_4_processing_system7' requires 686 connections, but only 673 given [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/synth/System_processing_system7_0_0.v:188]
INFO: [Synth 8-256] done synthesizing module 'System_processing_system7_0_0' (6#1) [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/synth/System_processing_system7_0_0.v:57]
WARNING: [Synth 8-350] instance 'processing_system7_0' of module 'System_processing_system7_0_0' requires 29 connections, but only 22 given [C:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/hdl/System.v:82]
INFO: [Synth 8-256] done synthesizing module 'System' (7#1) [C:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/hdl/System.v:13]
INFO: [Synth 8-256] done synthesizing module 'System_wrapper' (8#1) [C:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/hdl/System_wrapper.v:12]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:14 . Memory (MB): peak = 283.332 ; gain = 149.824
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Optimization
---------------------------------------------------------------------------------

Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
Loading clock regions from C:/Xilinx/Vivado/2014.2/data\parts/xilinx/zynq/zynq/xc7z010/ClockRegion.xml
Loading clock buffers from C:/Xilinx/Vivado/2014.2/data\parts/xilinx/zynq/zynq/xc7z010/ClockBuffers.xml
Loading clock placement rules from C:/Xilinx/Vivado/2014.2/data/parts/xilinx/zynq/ClockPlacerRules.xml
Loading package pin functions from C:/Xilinx/Vivado/2014.2/data\parts/xilinx/zynq/PinFunctions.xml...
Loading package from C:/Xilinx/Vivado/2014.2/data\parts/xilinx/zynq/zynq/xc7z010/clg400/Package.xml
Loading io standards from C:/Xilinx/Vivado/2014.2/data\./parts/xilinx/zynq/IOStandards.xml

Processing XDC Constraints
Parsing XDC File [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/System_processing_system7_0_0.xdc] for cell 'System_i/processing_system7_0/inst'
Finished Parsing XDC File [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/System_processing_system7_0_0.xdc] for cell 'System_i/processing_system7_0/inst'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/System_processing_system7_0_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/System_wrapper_propImpl.xdc].
Resolution: To avoid this message, exclude constraints listed in [.Xil/System_wrapper_propImpl.xdc] from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [C:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.runs/synth_1/dont_touch.xdc]
Finished Parsing XDC File [C:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.runs/synth_1/dont_touch.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.runs/synth_1/dont_touch.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/System_wrapper_propImpl.xdc].
Resolution: To avoid this message, exclude constraints listed in [.Xil/System_wrapper_propImpl.xdc] from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints

INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

---------------------------------------------------------------------------------
Start RTL Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7z010clg400-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:18 ; elapsed = 00:00:31 . Memory (MB): peak = 490.297 ; gain = 356.789
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property DONT_TOUCH = true for System_i. (constraint file  C:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.runs/synth_1/dont_touch.xdc, line 5).
Applied set_property DONT_TOUCH = true for processing_system7_0. (constraint file  C:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.runs/synth_1/dont_touch.xdc, line 8).
Applied set_property DONT_TOUCH = true for inst. (constraint file  C:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.runs/synth_1/dont_touch.xdc, line 11).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:21 ; elapsed = 00:00:34 . Memory (MB): peak = 490.297 ; gain = 356.789
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:34 . Memory (MB): peak = 490.297 ; gain = 356.789
---------------------------------------------------------------------------------
WARNING: [Synth 8-3848] Net ENET0_GMII_TX_EN in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:212]
WARNING: [Synth 8-3848] Net ENET0_GMII_TX_ER in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:213]
WARNING: [Synth 8-3848] Net ENET0_GMII_TXD in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:229]
WARNING: [Synth 8-3848] Net ENET1_GMII_TX_EN in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:243]
WARNING: [Synth 8-3848] Net ENET1_GMII_TX_ER in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:244]
WARNING: [Synth 8-3848] Net ENET1_GMII_TXD in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:258]
WARNING: [Synth 8-3848] Net TRACE_CTL_PIPE[0] in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:1300]
WARNING: [Synth 8-3848] Net TRACE_DATA_PIPE[0] in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:1301]
WARNING: [Synth 8-3848] Net TRACE_CLK_OUT in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:405]
WARNING: [Synth 8-3848] Net ENET0_GMII_COL_i in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:1048]
WARNING: [Synth 8-3848] Net ENET0_GMII_CRS_i in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:1049]
WARNING: [Synth 8-3848] Net ENET0_GMII_RXD_i in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:1052]
WARNING: [Synth 8-3848] Net ENET0_GMII_RX_DV_i in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:1050]
WARNING: [Synth 8-3848] Net ENET0_GMII_RX_ER_i in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:1051]
WARNING: [Synth 8-3848] Net ENET1_GMII_COL_i in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:1057]
WARNING: [Synth 8-3848] Net ENET1_GMII_CRS_i in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:1058]
WARNING: [Synth 8-3848] Net ENET1_GMII_RXD_i in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:1061]
WARNING: [Synth 8-3848] Net ENET1_GMII_RX_DV_i in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:1059]
WARNING: [Synth 8-3848] Net ENET1_GMII_RX_ER_i in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:1060]
WARNING: [Synth 8-3848] Net FTMD_TRACEIN_ATID_i in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:1070]
WARNING: [Synth 8-3848] Net FTMD_TRACEIN_DATA_i in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:1068]
WARNING: [Synth 8-3848] Net FTMD_TRACEIN_VALID_i in module/entity processing_system7_v5_4_processing_system7 does not have driver. [c:/Avnet/MicroZed/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/ip/System_processing_system7_0_0/hdl/verilog/processing_system7_v5_4_processing_system7.v:1069]

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start RTL Component Statistics 
---------------------------------------------------------------------------------
Detailed RTL Component Info : 
---------------------------------------------------------------------------------
Finished RTL Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics 
---------------------------------------------------------------------------------
Hierarchical RTL Component report 
Module System_wrapper 
Detailed RTL Component Info : 
Module processing_system7_v5_4_processing_system7 
Detailed RTL Component Info : 
Module System_processing_system7_0_0 
Detailed RTL Component Info : 
Module System 
Detailed RTL Component Info : 
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 80 (col length:40)
BRAMs: 120 (col length: RAMB18 40 RAMB36 20)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
Workers Ready, Starting Parallel Section  : Time (s): cpu = 00:00:22 ; elapsed = 00:00:35 . Memory (MB): peak = 495.859 ; gain = 362.352
---------------------------------------------------------------------------------
Start Cross Boundary Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Cross Boundary Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:35 . Memory (MB): peak = 495.859 ; gain = 362.352
---------------------------------------------------------------------------------
Finished Parallel Reinfer  : Time (s): cpu = 00:00:22 ; elapsed = 00:00:35 . Memory (MB): peak = 495.859 ; gain = 362.352
---------------------------------------------------------------------------------
Start RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Area Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:35 . Memory (MB): peak = 514.992 ; gain = 381.484
---------------------------------------------------------------------------------
Finished Parallel Area Opt  : Time (s): cpu = 00:00:22 ; elapsed = 00:00:35 . Memory (MB): peak = 514.992 ; gain = 381.484
Finished Parallel Section  : Time (s): cpu = 00:00:22 ; elapsed = 00:00:35 . Memory (MB): peak = 514.992 ; gain = 381.484
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:39 ; elapsed = 00:00:54 . Memory (MB): peak = 730.531 ; gain = 597.023
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:39 ; elapsed = 00:00:54 . Memory (MB): peak = 746.066 ; gain = 612.559
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:40 ; elapsed = 00:00:54 . Memory (MB): peak = 750.918 ; gain = 617.410
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:41 ; elapsed = 00:00:56 . Memory (MB): peak = 750.918 ; gain = 617.410
---------------------------------------------------------------------------------

Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:41 ; elapsed = 00:00:56 . Memory (MB): peak = 750.918 ; gain = 617.410
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:41 ; elapsed = 00:00:56 . Memory (MB): peak = 750.918 ; gain = 617.410
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes: 
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage: 
+------+------+------+
|      |Cell  |Count |
+------+------+------+
|1     |BIBUF |   130|
|2     |BUFG  |     1|
|3     |GND   |     1|
|4     |LUT1  |    89|
|5     |PS7   |     1|
+------+------+------+

Report Instance Areas: 
+------+-------------------------+-------------------------------------------+------+
|      |Instance                 |Module                                     |Cells |
+------+-------------------------+-------------------------------------------+------+
|1     |top                      |                                           |   222|
|2     |  System_i               |System                                     |   222|
|3     |    processing_system7_0 |System_processing_system7_0_0              |   221|
|4     |      inst               |processing_system7_v5_4_processing_system7 |   221|
+------+-------------------------+-------------------------------------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:41 ; elapsed = 00:00:56 . Memory (MB): peak = 750.918 ; gain = 617.410
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 22 warnings.
Synthesis Optimization Complete : Time (s): cpu = 00:00:42 ; elapsed = 00:00:56 . Memory (MB): peak = 750.918 ; gain = 617.410
INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers.
INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

INFO: [Common 17-83] Releasing license: Synthesis
25 Infos, 146 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:40 ; elapsed = 00:00:53 . Memory (MB): peak = 753.406 ; gain = 550.355
# write_checkpoint System_wrapper.dcp
# report_utilization -file System_wrapper_utilization_synth.rpt -pb System_wrapper_utilization_synth.pb
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.090 . Memory (MB): peak = 753.406 ; gain = 0.000
INFO: [Common 17-206] Exiting Vivado at Wed Jun 11 13:21:31 2014...
