The kit provides the hardware environment for characterizing and evaluating the GTH and GTZ transceivers available on the Virtex-7 XC7VH580T-G2HCG1155E FPGA while allowing evaluation of the Integrated Bit Error Ratio Test (IBERT) demonstration using the Vivado® Design Suite. Each GTH and GTZ Quad and its associated reference clock are routed from the FPGA to SMA and Samtec BullsEye connector. A cable containing a BullsEye connector and standard SMA connectors allows users to connect to a broad range of evaluation platforms, from backplanes and optical evaluation boards to high speed test equipment. Each BullsEye connector handles a full GTH or GTZ Quad, four transmit/receive pairs, enabling the highest level of flexibility in testing custom applications.
VC7222 evaluation board featuring the Virtex-7 XC7VH580T-G2HCG1155E FPGA
Full seat Vivado® Design Suite: Design Edition
Node locked & Device-locked to the Virtex-7 XC7VH580T FPGA, with 1 year of updates and support