These 8-bit registers feature 3-state outputsdesigned specifically for driving highly capacitiveor relatively low-impedance loads. Thehigh-impedance 3-state and increasedhigh-logic-level drive provide these registers withthe capability of being connected directly to anddriving the bus lines in a bus-organized systemwithout need for interface or pullup components.These devices are particularly attractive forimplementing buffer registers, I/O ports,bidirectional bus drivers, and working registers.
The eight latches of the ’LS373 and ’S373 aretransparent D-type latches, meaning that whilethe enable (C or CLK) input is high, the Q outputsfollow the data (D) inputs. When C or CLK is takenlow, the output is latched at the level of the datathat was set up.
The eight flip-flops of the ’LS374 and ’S374 areedge-triggered D-type flip-flops. On the positivetransition of the clock, the Q outputs are set to thelogic states that were set up at the D inputs.
Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system designas ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A bufferedoutput-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logiclevels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus linessignificantly
OC does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or newdata can be entered, even while the outputs are off
Choice of Eight Latches or Eight D-Type
Flip-Flops in a Single Package
3-State Bus-Driving Outputs
Full Parallel Access for Loading
Buffered Control Inputs
Clock-Enable Input Has Hysteresis toImprove Noise Rejection