These dual 4-input positive-AND gates are designed for 2-V to 5.5-V VCC operation.
The 'LV21A devices perform the Boolean function Y = A • B 1 C • D or Y = (A\ + B\ + C\ + D\)\ in positive logic.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
2-V to 5.5-V VCC Operation
Max tpd of 6 ns at 5 V
Typical VOLP (Output Ground Bounce) <0.8 V at VCC, TA = 25°C
Typical VOHV (Output VOH Undershoot) >2.3 V at VCC, TA = 25°C
Ioff Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II