These 3-line to 8-line decoders/demultiplexers are designed for 2.7-V to 5.5-V VCC operation.
The 'LV138 are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
The SN74LV138 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LV138 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LV138 is characterized for operation from -40°C to 85°C.
EPICTM (Enhanced-Performance Implanted CMOS) 2-µ Process
Typical VOLP (Output Ground Bounce) < 0.8 V atVCC, TA = 25°C
Typical VOHV (Output VOH Undershoot)> 2 V at VCC, TA = 25°C
ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015;Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17