SN74AUP1G74DCURG4 by Texas Instruments | Flip Flops | Avnet AMERICAS
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SN74AUP1G74DCURG4

Texas Instruments

Flip Flop D-Type Pos-Edge 1-Element 8-Pin VSSOP T/R

Manufacturer Part #: SN74AUP1G74DCURG4

Alternate Part #: SN74AUP1G74DCURG4


legend RoHS Compliant

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The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).

This single positive-edge-triggered D-type flip-flop is designed for 0.8-V to 3.6-V VCC operation.

A low level at the preset (PRE\) or clear (CLR\) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for higher frequencies, the CLR\ input overrides the PRE\ input when they are both low.

NanoStar package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Key Features

  • Available in the Texas Instruments NanoStar™ Package
  • Low Static-Power Consumption:
    ICC = 0.9 µA Max
  • Low Dynamic-Power Consumption:
    Cpd = 5.5 pF Typ at 3.3 V
  • Low Input Capacitance: Ci = 1.5 pF Typ
  • Low Noise – Overshoot and Undershoot
    <10% of VCC
  • Ioff Supports Partial-Power-Down Mode Operation
  • Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise
    Immunity at the Input (Vhys = 250 mV Typ at 3.3 V)
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 5 ns Max at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Technical Attributes

    Description
    Value
    Find similar Parts
    Number of Elements per Chip
    1
    MSL Level
    1
    Fabrication Technology
    CMOS
    Number of Element Outputs
    1
    Maximum Operating Supply Voltage
    3.6 V
    Lead Finish
    Gold
    Typical Operating Supply Voltage
    1.8|2.5|3.3 V
    Maximum Low Level Output Current
    4 mA
    Propagation Delay Test Condition
    30 pF
    Output Signal Type
    Differential
    Logic Function
    D-Type
    Supplier Package
    VSSOP
    Minimum Operating Supply Voltage
    0.8 V
    Product Dimensions
    2.3 x 2 x 0.85 mm
    Polarity
    Inverting/Non-Inverting
    Input Signal Type
    Single-Ended
    Triggering Type
    Positive-Edge
    Maximum Propagation Delay Time @ Maximum CL
    27@1.2V|17@1.5V|13@1.8V|9@2.5V|7@3.3V ns
    Maximum High Level Output Current
    -4 mA
    Set/Reset
    Set/Reset
    Number of Element Inputs
    1
    Maximum Quiescent Current
    0.0005 mA
    Bus Hold
    No
    Number of Channels per Chip
    1
    Mounting
    Surface Mount
    Max Processing Temp
    260
    Operating Temperature
    -40 to 85 °C
    Pin Count
    8

    ECCN / UNSPSC

    Description
    Value
    ECCN:
    EAR99
    SCHEDULE B:
    8542310000
    UNSPSC:
    32101634
    UNSPSC VERSION:
    V15.1101

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