The SN74ACT2226 and SN74ACT2228 are dual FIFOs suited for a wide range of serial-data buffering applications, including elastic stores for frequencies up to T2 telecommunication rates. Each FIFO on the chip is arranged as 64 × 1 (SN74ACT2226) or 256 × 1 (SN74ACT2228) and has control signals and status flags for independent operation. Output flags for each FIFO include input ready (1IR or 2IR), output ready (1OR or 2OR), half full (1HF or 2HF), and almost full/almost empty (1AF/AE or 2AF/AE).
Serial data is written into a FIFO on the low-to-high transition of the write-clock (1WRTCLK or 2WRTCLK) input when the write-enable (1WRTEN or 2WRTEN) input and input-ready flag (1IR or 2IR) output are both high. Serial data is read from a FIFO on the low-to-high transition of the read-clock (1RDCLK or 2RDCLK) input when the read-enable (1RDEN or 2RDEN) input and output-ready flag (1OR or 2OR) output are both high. The read and write clocks of a FIFO can be asynchronous to one another.
Each input-ready flag (1IR or 2IR) is synchronized by two flip-flop stages to its write clock (1WRTCLK or 2WRTCLK), and each output-ready flag (1OR or 2OR) is synchronized by three flip-flop stages to its read clock (1RDCLK or 2RDCLK). This multistage synchronization ensures reliable flag-output states when data is written and read asynchronously.
A half-full flag (1HF or 2HF) is high when the number of bits stored in its FIFO is greater than or equal to half the depth of the FIFO. An almost-full/almost-empty flag (1AF/AE or 2AF/AE) is high when eight or fewer bits are stored in its FIFO and when eight or fewer empty locations are left in the FIFO. A bit present on the data output is not stored in the FIFO.
The SN74ACT2226 and SN74ACT2228 are characterized for operation from -40°C to 85°C.
Dual Independent FIFOs Organized as:
64 Words by 1 Bit Each - SN74ACT2226
256 Words by 1 Bit Each - SN74ACT2228
Free-Running Read and Write Clocks Can Be Asynchronous or Coincident on Each FIFO
Input-Ready Flags Synchronized to Write Clocks
Output-Ready Flags Synchronized to Read Clocks
Half-Full and Almost-Full/Almost-Empty Flags
Support Clock Frequencies up to 22 MHz
Access Times of 20 ns
Low-Power Advanced CMOS Technology
Packaged in 24-Pin Small-Outline Integrated-Circuit Package