The 'ABT8952 scan test devices with octal registered bus transceivers are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
In the normal mode, these devices are functionally equivalent to the 'BCT2952 and 'ABT2952 octal registered bus transceivers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self-test on the boundary-test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPETM octal registered bus transceivers.
In the test mode, the normal operation of the SCOPETM registered bus transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations as described in IEEE Standard 1149.1-1990.
Four dedicated test pins control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
The SN54ABT8952 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT8952 is characterized for operation from -40°C to 85°C.
Members of the Texas Instruments SCOPETM Family ofTestability Products
Compatible With the IEEE Standard 1149.1-1990 (JTAG) TestAccess Port and Boundary-Scan Architecture
Functionally Equivalent to 'BCT2952 and 'ABT2952 in theNormal-Function Mode
SCOPETM Instruction Set
IEEE Standard 1149.1-1990 Required Instructions, OptionalINTEST, CLAMP, and HIGHZ
Parallel-Signature Analysis at Inputs With Masking Option
Pseudo-Random Pattern Generation From Outputs
Sample Inputs/Toggle Outputs
Binary Count From Outputs
Two Boundary-Scan Cells Per I/O for Greater Flexibility
State-of-the-Art EPIC-IIBTM BiCMOS DesignSignificantly Reduces Power Dissipation
Package Options Include Shrink Small-Outline (DL) and PlasticSmall-Outline (DW) Packages, Ceramic Chip Carriers (FK), andStandard Ceramic DIPs (JT)