This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. In the1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinoutconfiguration, two devices per DIMM are required to drive 18 SDRAM loads.
All inputs are SSTL_18, except the reset (RESET) and control (Cn) inputs, which are LVCMOS. All outputs areedge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications, except theopen-drain error (QERR) output.
The 74SSTUB32864A operates from a differential clock (CLK and CLK). Data are registered at the crossing ofCLK going high and CLK going low.
The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) toregister-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. They should be hard-wiredto a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration,the A6, D6, and H6 terminals are driven low and are do-not-use (DNU) pins.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CLK andCLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register iscleared, and the data outputs are driven low quickly, relative to the time required to disable the differential inputreceivers. However, when coming out of reset, the register becomes active quickly, relative to the time requiredto enable the differential input receivers. As long as the data inputs are low, and the clock is stable during thetime from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the 74SSTUB32864A ensures that the outputs remain low, thus ensuring there will be no glitches on the output.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in thelow state during power up.
The device supports low-power standby operation. When RESET is low, the differential input receivers aredisabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, whenRESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET and Cn inputs alwaysmust be held at a valid logic high or low level.
Member of the Texas Instruments Widebus+™ Family
Supports SSTL_18 Data Inputs
Pinout Optimizes DDR2 DIMM PCB Layout
Differential Clock (CLK and CLK) Inputs
Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer
Supports LVCMOS Switching Levels on the Control and RESET Inputs
Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption
RESET Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low
Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line