The MC74AC273/74ACT273 has eight edge-triggered D-type flip-flops withindividual D inputs and Q outputs. The common buffered Clock (CP) and MasterReset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup timebefore the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOWvoltage level on the MR input. The device is useful for applications where the trueoutput only is required and the Clock and Master Reset are common to all storageelements.