74VHCT126PW-Q100J by Nexperia | Buffers & Line Drivers | Avnet AMERICAS
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74VHCT126PW-Q100J

Nexperia

Buffer/Line Driver 4-CH Non-Inverting 3-ST CMOS 14-Pin TSSOP T/R

Manufacturer Part #: 74VHCT126PW-Q100J

Alternate Part #: 74VHCT126PW-Q100J


legend RoHS Compliant

Descriptions

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Information

The 74VHC126-Q100; 74VHCT126-Q100 are high‑speed Si‑gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7‑A. The 74VHC126-Q100; 74VHCT126-Q100 provide four non-inverting buffer/line drivers with 3-state outputs. The output enable input (nOE) controls the 3‑state outputs (nY). A LOW‑level at pin nOE causes the outputs to assume a high-impedance OFF-state. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Key Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)
    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
  • Balanced propagation delays
  • All inputs have Schmitt-trigger action
  • Inputs accept voltages higher than VCC
  • Input levels:
    • The 74VHC126-Q100 operates with CMOS input level
    • The 74VHCT126-Q100 operates with TTL input level
  • ESD protection:
    • MIL-STD-883, method 3015 exceeds 2000 V
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
  • Multiple package options

Technical Attributes

Description
Value
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Screening Level
Automotive
Max Processing Temp
260
Supplier Package
TSSOP
Pin Count
14
Product Dimensions
5.1 x 4.5 x 0.95
Number of Output Enables per Chip
4 High
Logic Function
Buffer/Line Driver
Maximum Quiescent Current
2 uA
Maximum High Level Output Current
-8 mA
Typical Operating Supply Voltage
5 V
Maximum Propagation Delay Time @ Maximum CL
7.5@4.5V to 5.5V ns
Propagation Delay Test Condition
50 pF
Number of Outputs per Chip
4
Output Type
3-State
Maximum Low Level Output Current
8 mA
Number of Elements per Chip
4
Operating Temperature
-40 to 125 °C
Lead Finish
Gold Over Nickel Palladium
Mounting
Surface Mount
MSL Level
1
Input Signal Type
Single-Ended
Number of Channels per Chip
4
Polarity
Non-Inverting
Fabrication Technology
CMOS
Maximum Operating Supply Voltage
5.5 V
Minimum Operating Supply Voltage
4.5 V
Number of Inputs per Chip
4
Bus Hold
No

ECCN / UNSPSC

Description
Value
ECCN:
EAR99
SCHEDULE B:
8542390000
HTSN:
8542390001
UNSPSC:
32101600
UNSPSC VERSION:
V15.1101
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