The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE) control gates. Each register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop's Q output. When nOE is LOW, the data in the register appears at the outputs. When nOE is HIGH, the outputs are in high impedance OFF state. Operation of the nOE input does not affect the state of the flip-flops. The 74ALVCH16821 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.
Wide supply voltage range of 1.2 V to 3.6 V
Complies with JEDEC standard no. 8-1A
Current drive ±24 mA at 3.0 V
CMOS low power consumption
Direct interface with TTL levels
MULTIBYTE flow-through standard pin-out architecture
Low inductance multiple VCC and ground pins for minimum noise and ground bounce