The IS65WV12816BLL are high speed, 2M bit static RAMs organized as 128K words by 16 bits. It is fabricated using high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high performance and low power consumption devices. When CS1\ is HIGH (deselected) or when CS2 is LOW (deselected) or when CS1\ is LOW, CS2 is HIGH and both LB and UB are HIGH, the device assumes a standby mode at which the power dpation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE/) controls both writing and reading of the memory. A data byte allows Upper Byte (UB/) and Lower Byte (LB/) access. The IS65WV12816BLL are packged in the JEDEC standard 48-pin mini BGA (6mm x 8mm) and 44-Pin TSOP (TYPE II).
High-speed access time: 55ns, 70ns
CMOS low power operation
36 mW (typical) operating
9 µW (typical) CMOS standby
TTL compatible interface levels
Single power supply: 2.5V to 3.6V Vdd
Fully static operation: no Clock or refresh required