The IS61LPD51236 are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61LPD51236 is organized as 524,288 words 36 bits. Fabricated with advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. The byte write operation is performed by using the byte write enable (BWE\) input combined with one or more individual byte write signals (BWX\). In addition, Global Write (GW\) is available for writing all bytes at one time, regardless of the byte write controls. Bursts can be initiated with either ADSP\ (Address Status Processor) or ADSC\ (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV\ (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating.
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data and control
Burst sequence control using MODE input
Three chip enable option for simple depth expansion and address pipelining