IS46LR32160B-6BLA1-TR by ISSI | DRAM ICs | Avnet AMERICAS
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IS46LR32160B-6BLA1-TR

ISSI

DRAMs Parts and Modules

Manufacturer Part #: IS46LR32160B-6BLA1-TR

Alternate Part #: IS46LR32160B-6BLA1-TR


RoHS Compliant

Descriptions

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Information

The IS46LR32640A is 2,147,483,648 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 33,554,432 wordsx 32 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted on a 32-bit bus. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock.The data paths are internally pipelined and 2n-bits prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with LVCMOS.

Key Features

  • JEDEC standard 1.8V power supply
  • Vdd = 1.8V, Vddq = 1.8V
  • Four internal banks for concurrent operation
  • MRS cycle with address key programs
    • CAS latency 2, 3 (clock)
    • Burst length (2, 4, 8)
    • Burst type (sequential and interleave)
  • Fully differential clock inputs (CK, /CK)
  • All inputs except data and DM are sampled at the rising edge of the system clock
  • Data I/O transaction on both edges of data strobe
  • Bidirectional data strobe per byte of data (DQS)
  • DM for write masking only
  • Edge aligned data and data strobe output
  • Center aligned data and data strobe input
  • 64ms refresh period (8K cycle)
  • Auto and self refresh
  • Concurrent Auto Precharge
  • Maximum clock frequency up to 200MHZ
  • Maximum data rate up to 400Mbps/pin
  • Power Saving support
    • PASR (Partial Array Self Refresh)
    • Auto TCSR (Temperature Compensated Self Refresh)
    • Deep Power Down Mode
    • Programmable Driver Strength Control by Full Strength or 1/2, 1/4, or 1/8 of Full Strength
  • LVCMOS compatible inputs/outputs
  • 90-Ball FBGA package
  • 64Mx32 (two stacked 16Mx16x4 banks)

Technical Attributes

Description
Value
Find similar Parts
Mounting
Surface Mount
Data Bus Width
32 Bit
Operating Temperature
-40 to 85 °C
Operating Supply Voltage
1.8 V
Density
512 Mb
Family
IS46LR32160B
Maximum Random Access Time
8|5.5 ns
Screening Level
Automotive
Maximum Clock Rate
166 MHz
Number of Bits per Word
32 Bit
Organization
16M x 32
Type
Mobile DDR SDRAM
Lead Free
Yes
Number of I/O Lines
32 Bit
Address Bus Width
13 Bit
Number of Banks
4
Packaging
Tape and Reel
Maximum Operating Current
70 mA

ECCN / UNSPSC

Description
Value
ECCN:
EAR99
SCHEDULE B:
8542320015
HTSN:
8542320070
UNSPSC:
32101602
UNSPSC VERSION:
V15.1101
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