The 87016I is a low skew, 1:16 LVCMOS/LVTTL Clock Generator. The device has four banks of four outputs and each bank can be independently selected for ÷1 or ÷2 frequency operation. Each bank also has its own power supply pins so that the banks can operate at the following different voltage levels: 3.3V, 2.5V, and 1.8V. The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated transmission lines. The divide select inputs, DIV_SELA:DIV_SELD, control the output frequency of each bank. The output banks can be independently selected for ÷1 or ÷ 2operation. The bank enable inputs, CLK_ENA:CLK_END, support enabling and disabling each bank of outputs individually. The CLK_ENA:CLK_END circuitry has a synchronizer to prevent runt pulses when enabling or disabling the clock outputs. The master reset input, MR/OE, resets the ÷1 /÷2 flip flops and also controls the active and high impedance states of all outputs. This pin has an internal pull-up resistor and is normally used only for test purposes or in systems which use low power modes. The 87016I is characterized to operate with the core at 3.3V or 2.5V and the banks at 3.3V, 2.5V, or 1.8V. Guaranteed bank, output, and part-to-part skew characteristics make the 87016I ideal for those clock applications demanding well-defined performance and repeatability.
Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs)
Selectable differential CLK1/CLK1 or LVCMOS/LVTTL clock input
CLK1, CLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
CLK0 supports the following input types: LVCMOS, LVTTL
Maximum output frequency: 250MHz
Independent bank control for ÷1 or ÷2 operation
Independent output bank voltage settings for 3.3V, 2.5V, or 1.8V operation