74SSTUBF32865ABKG by Integrated Device Technology | Registers & Registered Buffers | Avnet AMERICAS
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74SSTUBF32865ABKG

Integrated Device Technology

28-Bit 1:2 Registered Buffer with Parity

Manufacturer Part #: 74SSTUBF32865ABKG

Avnet Manufacturer Part #: 74SSTUBF32865ABKG


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This 28-bit 1:2 registered buffer with parity is designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The IDT74SSTUBF32865A operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high, and CLK going low. The device supports low-power standby operation. When the reset input (RESET) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is low all registers are reset, and all outputs except PTYERR are forced low. The LVCMOS RESET input must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the IDT74SSTUBF32865A must ensure that the outputs will remain low, thus ensuring no glitches on the output. The IDT74SSTUBF32865A includes a parity checking function. The IDT74SSTUBF32865A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain PTYERR pin (active LOW).

Key Features

  • 28-bit 1:2 registered buffer with parity check functionality
  • Supports SSTL_18 JEDEC specification on data inputs and outputs
  • Supports LVCMOS switching levels on CSGateEN and RESET inputs
  • Low voltage operation: VDD = 1.7V to 1.9V
  • Available in 160-ball LFBGA packag

Technical Attributes

Description
Value
Find similar Parts
Product Dimensions
13 x 9 x 1.3 mm
Lead Finish
Tin/Silver/Copper
Logic Function
Registered Buffer with Parity Checker
Number of Element Inputs
28
Number of Channels per Chip
28
Output Signal Type
Single-Ended
Number of Elements per Chip
1
Minimum Operating Supply Voltage
1.7 V
Fabrication Technology
CMOS
Bus Hold
No
Input Signal Type
Single-Ended
Maximum Propagation Delay Time @ Maximum CL
1.5@1.8V ns
Triggering Type
Positive-Edge/Negative-Edge
Maximum High Level Output Current
-8 mA
Typical Operating Supply Voltage
1.8 V
Maximum Operating Supply Voltage
1.9 V
Maximum Low Level Output Current
8 mA
Reset Type
Asynchronous
Number of Element Outputs
56

ECCN / UNSPSC

Description
Value
ECCN:
EAR99
SCHEDULE B:
8542390000
HTSN:
8542390001
UNSPSC:
32101600
UNSPSC VERSION:
V15.1101

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