The IDT70V3399 is a high-speed 128K x 18 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70V3399 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70V3399 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) remains at 3.3V.
True Dual-Port memory cells which allow simultaneous access of the same memory location
High-speed data access
Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
Industrial: 4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode - Due to limited pin count PL/FT option is not supported on the 128-pin TQFP package. Device is pipelined outputs only on each port.
Counter enable and repeat features
Dual chip enables allow for depth expansion without additional logic
Full synchronous operation on both ports
6ns cycle time, 166MHz operation (6Gbps bandwidth)
Fast 3.6ns clock to data out
1.7ns setup to clock and 0.5ns hold on all control, data, and address inputs @ 166MHz Data input, address, byte enable and control registers
Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output mode
LVTTL- compatible, single 3.3V (±150mV) power supply for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V (±100mV) power supply for I/Os and control signals on each port
Industrial temperature range (-40°C to +85°C) is available at 133MHz.
Available in a 128-pin Thin Quad Flatpack, 208-pin fine pitch Ball Grid Array, and 256-pin Ball Grid Array
Supports JTAG features compliant to IEEE 1149.1 - Due to limited pin count, JTAG is not supported on the 128-pin TQFP package