The GS8662R08BD are built in compliance with the -II SRAM pin out standard for Common I/O synchronous SRAMs. They are 75,497,472-bit (72Mb) SRAMs. The GS8662R08BD -II SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.
Key Features
Simultaneous Read and Write ™ Interface
Common I/O bus
JEDEC-standard pin out and package
Double Data Rate interface
Byte Write (x36, x18 and x9) and Nibble Write (x8) function
Burst of 4 Read and Write
1.8 V +100/–100 mV core power supply
1.5 V or 1.8 V HSTL Interface
Pipelined read operation with self-timed Late Write
Fully coherent read and write pipelines
ZQ pin for programmable output drive strength
IEEE 1149.1 JTAG-compliant Boundary Scan
Pin-compatible with present 9Mb, 18Mb, 36Mb and 72Mb devices
You have successfully submitted your quote online.
Response time typically takes 2-4 business days depending on supplier feedback. You will receive an email and will be notified in the activity center when complete.