The GS81302T06E are built in compliance with the -II+ SRAM pin out standard for Common I/O synchronous SRAMs. They are 150,994,944-bit (144Mb) SRAMs. The GS81302T06E -II+ SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.
2.5 Clock Latency
Simultaneous Read and Write Sigma DDRTM Interface
JEDEC-standard pin out and package
Double Data Rate interface
Byte Write controls sampled at data-in time
Burst of 2 Read and Write
On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs