Kintex-7 Mini-Module Plus Kit The Kintex-7 Mini-Module Plus Kit is one of three components needed to create a Mini-Module Plus Development Kit. The kit includes the Mini-Module Plus SOM (based on Xilinx Kintex-7 FPGA XC7K410T- 1FFG676 or XC7K325T-1FFG676), and the cables needed to connect to the Mini-Module Baseboard.
Kintex-7 Mini-Module Plus SOM (AES-MMP-7K325T-SOM-G or AES-MMP-7K410T-SOM-G)
Micro USB Cables
8GB SD Card
Xilinx Vivado Design Edition (device locked to the appropriate device)
Mini-Module Plus Development Kit The Mini-Module Plus Development Kit is a modular customizable development kit system that is perfect for system architects and embedded designers looking for a flexible, high performance and upgradable platform. The Mini-Module Plus Kit can be combined with the Mini-Module Plus Baseboard II and a Mini-Module Plus Power Supply to provide an out-of-box development system ready for prototyping. The SOMs are pin compatible and are available with 4 different Xilinx devices.
PRODUCT FEATURES The Mini-Module Plus Development Kit consists of 3 separate components (purchased separately):
Mini-Module Plus Kit (SOM plus cabling)
Mini-Module Plus Baseboard
Mini-Module Plus Power Module
Advanced high-performance FPGA logic based on real 6-input lookup table (LUT) technology configurable as distributed memory.
36 Kb dual-port block RAM with built-in FIFO logic for on-chip data buffering.
High-performance SelectIO™ technology with support for DDR3 interfaces up to 1,866 Mb/s.
High-speed serial connectivity with built-in multi-gigabit transceivers from 600 Mb/s to maximum rates of 6.6 Gb/s up to 28.05 Gb/s, offering a special low-power mode, optimized for chip-to-chip interfaces.
A user configurable analog interface (XADC), incorporating dual 12-bit 1MSPS analog-to-digital converters with on-chip thermal and supply sensors.
DSP slices with 25 x 18 multiplier, 48-bit accumulator, and pre-adder for high-performance filtering, including optimized symmetric coefficient filtering.
Powerful clock management tiles (CMT), combining phase-locked loop (PLL) and mixed-mode clock manager (MMCM) blocks for high precision and low jitter.
Integrated block for PCI Express® (PCIe), for up to x8 Gen3 Endpoint and Root Port designs.
Wide variety of configuration options, including support for commodity memories, 256-bit AES encryption with HMAC/SHA-256 authentication, and built-in SEU detection and correction.
Low-cost, wire-bond, lidless flip-chip, and high signal integrity flipchip packaging offering easy migration between family members in the same package. All packages available in Pb-free and selected packages in Pb option.
Designed for high performance and lowest power with 28 nm, HKMG, HPL process, 1.0V core voltage process technology and 0.9V core voltage option for even lower power.