The Spartan®-3 family of Field-Programmable Gate Arrays is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The eight-member family offers densities ranging from 50,000 to 5,000,000 system gates.
The Spartan-3 family builds on the success of the earlier Spartan-IIE family by increasing the amount of logic resources, the capacity of internal RAM, the total number of I/Os, and the overall level of performance as well as by improving clock management functions. Numerous enhancements derive from the Virtex®-II platform technology. These Spartan-3 FPGA enhancements, combined with advanced process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry.
Because of their exceptionally low cost, Spartan-3 FPGAs are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection and digital television equipment.
The Spartan-3 family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs.
Low-cost, high-performance logic solution for high-volume, consumer-oriented applications
Densities up to 74,880 logic cells
SelectIO™ interface signaling
Up to 633 I/O pins
622+ Mb/s data transfer rate per I/O
18 single-ended signal standards
8 differential I/O standards including LVDS, RSDS
Termination by Digitally Controlled Impedance
Signal swing ranging from 1.14V to 3.465V
Double Data Rate (DDR) support
DDR, DDR2 SDRAM support up to 333 Mb/s
Abundant logic cells with shift register capability
Wide, fast multiplexers
Fast look-ahead carry logic
Dedicated 18 x 18 multipliers
JTAG logic compatible with IEEE 1149.1/1532
SelectRAM™ hierarchical memory
Up to 1,872 Kbits of total block RAM
Up to 520 Kbits of total distributed RAM
Digital Clock Manager (up to four DCMs)
Clock skew elimination
High resolution phase shifting
Eight global clock lines and abundant routing
Fully supported by Xilinx ISE® and WebPACK™ software development systems
MicroBlaze™ and PicoBlaze™ processor, PCI®, PCI Express® PIPE Endpoint, and other IP cores