The TI AM437xhigh-performance processors are based on the ARM Cortex-A9 core.
The processors are enhanced with 3D graphics acceleration for rich graphical user interfaces, as well as a coprocessor for deterministic, real-time processing including industrial communication protocols, such as EtherCAT, PROFIBUS, EnDat, and others. The devices support high-level operating systems (HLOS). Linux is available free of charge from TI. Other HLOSs are available from TI's Design Network and ecosystem partners.
These devices offer an upgrade to systems based on lower performance ARM cores and provide updated peripherals, including memory options such as QSPI-NOR and LPDDR2.
The processors contain the subsystems shown in , and a brief description of each follows.
The processor subsystem is based on the ARM Cortex-A9 core, and the POWERVR SGX graphics accelerator subsystem provides 3D graphics acceleration to support display and advanced user interfaces.
The programmable real-time unit subsystem and industrial communication subsystem (PRU-ICSS) is separate from the ARM core and allows independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, EnDat, and others. The PRU-ICSS enables EnDat and another industrial communication protocol in parallel. Additionally, the programmable nature of the PRU-ICSS, along with their access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast real-time responses, specialized data handling operations, custom peripheral interfaces, and in off-loading tasks from the other processor cores of the SoC.
High-performance interconnects provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals. The device also offers a comprehensive clock-management scheme.
One on-chip analog to digital converter (ADC0) can couple with the display subsystem to provide an integrated touch-screen solution. The other ADC (ADC1) can combine with the pulse width module to create a closed-loop motor control solution.
The real-time clock (RTC) provides a clock reference on a separate power domain. The clock reference enables a battery-backed clock reference.
The camera interface offers configuration for a single- or dual-camera parallel port.
Cryptographic acceleration is available in every AM437x device. Secure boot can also be made available for anticloning and illegal software update protection. For more information about secure boot, contact your TI sales representative.
Sitara™ ARM® Cortex®-A9 32-Bit RISC Processor With Processing Speed up to 1000 MHz
NEON™ SIMD Coprocessor and Vector Floating Point (VFPv3) Coprocessor
32KB of Both L1 Instruction and Data Cache
256KB of L2 Cache or L3 RAM
32-Bit LPDDR2, DDR3, and DDR3L Support
General-Purpose Memory Support (NAND, NOR, SRAM) Supporting up to 16-Bit ECC
SGX530 Graphics Engine
Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU- ICSS)
Real-Time Clock (RTC)
Up to Two USB 2.0 High-Speed Dual-Role (Host or Device) Ports With Integrated PHY
10, 100, and 1000 Ethernet Switch Supporting up to Two Ports
Two Controller Area Network (CAN) Ports
Six UARTs, Two McASPs, Five McSPIs, Three I2C Ports, One QSPI, and One HDQ or 1-Wire
Crypto Hardware Accelerators (AES, SHA, RNG, DES, and 3DES)
Two 12-Bit Successive Approximation Register (SAR) ADCs
Up to Three 32-Bit Enhanced Capture Modules (eCAPs)
Up to Three Enhanced Quadrature Encoder Pulse Modules (eQEPs)
Up to Six Enhanced High-Resolution PWM Modules (eHRPWMs)
ARM Cortex-A9 32-Bit RISC Microprocessor With Processing Speed up to 1000 MHz
32KB of Both L1 Instruction and Data Cache
256KB of L2 Cache (Option to Configure as L3 RAM)
256KB of On-Chip Boot ROM
64KB of On-Chip RAM
Secure Control Module (SCM)
Emulation and Debug
Embedded Trace Buffer
On-Chip Memory (Shared L3 RAM)
256KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
Accessible to All Masters
Supports Retention for Fast Wakeup
Up to 512KB of Total Internal RAM (256KB of ARM Memory Configured as L3 RAM + 256KB of OCMC RAM)
External Memory Interfaces (EMIFs)
LPDDR2: 266-MHz Clock (LPDDR2-533 Data Rate)
DDR3 and DDR3L: 400-MHz Clock (DDR- 800 Data Rate)
32-Bit Data Bus
2GB of Total Addressable Space
Supports One x32, Two x16, or Four x8 Memory Device Configurations
General-Purpose Memory Controller (GPMC)
Flexible 8- and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, and SRAM)
Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
Uses Hamming Code to Support 1-Bit ECC
Error Locator Module (ELM)
Used With the GPMC to Locate Addresses of Data Errors From Syndrome Polynomials Generated Using a BCH Algorithm
Supports 4-, 8-, and 16-Bit Per 512-Byte Block Error Location Based on BCH Algorithms