The VSP5610/11/12 are high-speed, high-performance, 16-bitanalog-to-digital-converters (ADCs) that have four independent sampling circuitchannels for multi-output charge-coupled device (CCD) and complementary metaloxide semiconductor (CMOS) line sensors. Pixel data from the sensor are sampledby the sample/hold (SH) or correlated double sampler (CDS) circuit, and are thenconverted to digital data by an ADC. Data output is selectable in low-voltagedifferential signaling (LVDS) or CMOS modes.
The VSP5610/11/12 include a programmable gain to support the pixel levelinflection caused by luminance. The integrated digital-to-analog-converter (DAC)can be used to adjust the offset level for the analog input signal. Furthermore,the timing generator (TG) is integrated in these devices for the control ofsensor operation.
The VSP5610/11/12 use 1.65 V to 1.95 V for the core voltage and 3.0 V to 3.6V for I/Os. The core voltage is supplied by a built-in low-dropout regulator(LDO).
Four-Channel CCD/CMOS Signal: 2-Channel, 3-Channel, and 4-Channel Selectable
Power Supply: 3.3 V Only, Typ (Built-in LDO, 3.3 V to 1.8 V)