The Texas Instruments TSB43AB23 device is an integrated 1394a-2000 OHCI PHY/link-layer controller (LLC) device that is fully compliant with the PCI Local Bus Specification, the PCI Bus Power Management Interface Specification (Revision 1.1), IEEE Std 1394-1995, IEEE Std 1394a-2000, and the 1394 Open Host Controller InterfaceSpecification (Release 1.1). It is capable of transferring data between the 33-MHz PCI bus and the 1394 bus at 100M bits/s, 200M bits/s, and 400M bits/s. The TSB43AB23 device provides three 1394 ports that have separate cable bias (TPBIAS). The TSB43AB23 device also supports the IEEE Std 1394a-2000 power-down features for battery-operated applications and arbitration enhancements.
As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std 1394a-2000, internal control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through configuration cycles specified by PCI, and it provides plug-and-play (PnP) compatibility. Furthermore, the TSB43AB23 device is compliant with the PCI Bus Power Management Interface Specification as specified by the PC 2001 Design Guide requirements. The TSB43AB23 device supports the D0, D1, D2, and D3 power states.
The TSB43AB23 design provides PCI bus master bursting, and it is capable of transferring a cacheline of data at 132M bytes/s after connection to the memory controller. Because PCI latency can be large, deep FIFOs are provided to buffer the 1394 data.
The TSB43AB23 device provides physical write posting buffers and a highly-tuned physical data path for SBP-2 performance. The TSB43AB23 device also provides multiple isochronous contexts, multiple cacheline burst transfers, and advanced internal arbitration.
An advanced CMOS process achieves low power consumption and allows the TSB43AB23 device to operate at PCI clock rates up to 33 MHz.
The TSB43AB23 PHY-layer provides the digital and analog transceiver functions needed to implement a three-port node in a cable-based 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission.
The TSB43AB23 PHY-layer requires only an external 24.576-MHz crystal as a reference for the cable ports. An external clock may be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216-MHz reference signal. This reference signal is internally divided to provide the clock signals that control transmission of the outbound encoded strobe and data information. A 49.152-MHz clock signal is supplied to the integrated LLC for synchronization and is used for resynchronization of the received data.
Fully compliant with 1394 Open Host Controller Interface Specification (Release 1.1)
Fully compliant with provisions of IEEE Std 1394-1995 for a high-performance serial bus and IEEE Std 1394a-2000
Fully interoperable with FireWire and i.LINK implementations of IEEE Std 1394
Compliant with Intel Mobile Power Guideline 2000
Full IEEE Std 1394a-2000 support includes: connection debounce, arbitrated short reset, multispeed concatenation, arbitration acceleration, fly-by concatenation, and port disable/suspend/resume
Power-down features to conserve energy in battery-powered applications include: automatic device power down during suspend, PCI power management for link-layer, and inactive ports powered down
Ultralow-power sleep mode
Three IEEE Std 1394a-2000 fully compliant cable ports at 100M bits/s, 200M bits/s, and 400M bits/s
Cable ports monitor line conditions for active connection to remote node
Cable power presence monitoring
Separate cable bias (TPBIAS) for each port
1.8-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
Physical write posting of up to three outstanding transactions
PCI burst transfers and deep FIFOs to tolerate large host latency
External cycle timer control for customized synchronization
Extended resume signaling for compatibility with legacy DV components
PHY-link logic performs system initialization and arbitration functions
PHY-link encode and decode functions included for data-strobe bit level encoding
PHY-link incoming data resynchronized to local clock
Low-cost 24.576-MHz crystal provides transmit and receive data at 100M bits/s, 200M bits/s, and 400M bits/s
Node power class information signaling for system power management
Serial ROM interface supports 2-wire serial EEPROM devices
Two general-purpose I/Os
Register bits give software control of contender bit, power class bits, link active control bit, and IEEE Std 1394a-2000 features
Fabricated in advanced low-power CMOS process
Isochronous receive dual-buffer mode
Out-of-order pipelining for asynchronous transmit requests
Register access fail interrupt when the PHY SCLK is not active
PCI power-management D0, D1, D2, and D3 power states
Initial bandwidth available and initial channels available registers
PME\ support per 1394 Open Host Controller Interface Specification