The TSB12LV21B (PCILynx-2) provides a high-performance IEEE 1394-1995 interface with the capability to transfer data between the 1394 PHY-link interface, the PCI bus interface, and external devices connected to the local bus interface. The 1394 PHY-link interface provides the connection to the 1394 physical layer device; it is supported by the onboard link layer controller (LLC). The LLC provides the control for transmitting and receiving 1394 packet data between the FIFO and PHY-link interface at rates of 100 Mbit/s, 200 Mbit/s, and 400 Mbit/s. The link layer also provides the capability to receive status from the physical layer device and to access the physical layer control and status registers by the application software. The PCILynx-2 complies with
PCI Local Bus Specification, Revision 2.1
IEEE Standard for a 1394-1995 High Performance Serial Bus
IEEE Standard 1212-1991
IEEE Standard Control and Status Register (CSR) Architecture for Microcomputer Buses
An internal 4 Kbyte memory can be configured as multiple variable-size FIFOs, eliminating the need for external FIFOs. Separate FIFOs are user configurable to support 1394 receive, asynchronous transmit, and isosynchronous transmit transfer operations.
The PCI interface supports 32-bit burst transfers up to 33 MHz and is capable of operating both as a master and as a target device. Configuration registers can be loaded from an external serial EEPROM, allowing board and system designers to assign their own unique identification codes. An autoboot mode allows data-moving systems (such as docking stations) to be designed to operate on the PCI bus without the need for a host CPU.
The DMA controller uses packet control list (PCL) data structures to control the transfer of data and allow the DMA to operate without host CPU intervention. These PCLs can reside in PCI memory or in memory that is connected to a local bus port. The PCLs implement an instruction set that allows linking, conditional branching, 1394 data transfer control, auxiliary support commands, and status reporting. Five DMA channels accommodate programmable data types. PCLs can be chained together to form a channel control program that can be developed to support each DMA channel. Data can be stored in either big endian or little endian format, eliminating the need for the host CPU to perform byte swapping. Data can be transferred either to 4-byte aligned locations, to provide the highest performance, or to nonaligned locations, to provide the best memory use.
The RAM, ROM, AUX, ZV, and general-purpose I/O (GPIO) ports collectively make up the local bus interface. These ports mapped into the PCI address, can be accessed either through the PCI bus or through internal DMA transactions. Internal transactions do not appear on the external PCI bus, thereby conserving PCI bandwidth. DMA packet control lists or other data may be stored in external RAM or ROM attached to the local bus interface. This further reduces PCI bus use and generally improves performance. The ZV local bus port is designed to transfer data from 1394 video devices to an external device connected to the PCILynx-2 ZV port. This interface provides a method for receiving 1394 digital camera packets directly from a ZV-compliant device attached to the local bus interface.
Built-in test registers, a dedicated test output terminal, and four GPIO terminals allow observation of internal states and provide a convenient software debug capability. Programmable interrupts are available to inform driver software of important events, such as 1394 bus resets and DMA-to-PCL transfer completion.
The 3.3-V internal operation provides reduced power consumption, while maintaining compatibility with 5-V signaling environments. The PCI interface is compatible with both 3-V and 5-V PCI systems.
One Assembly Site
One Test Site
One Fabrication Site
Extended Temperature Performance of -55°C to 125°C
Enhanced Diminishing Manufacturing Sources (DMS) Support
Enhanced Product-Change Notification
IEEE Standard for 1394-1995 Compliant
IEEE Standard for 1212-1991 Compliant
Supports IEEE 1394-1995 Link Layer Control
PCI Local Bus Specification Rev. 2.1 Compliant
Supports IEEE 1394 Transfer Rates of 100, 200, and 400 Mbit per Second
3.3-V Core Logic While Maintaining 5-V Tolerant Inputs
Performs the Function of 1394 Cycle Master
Provides 4 KBytes of Configurable FIFO RAM
Provides Five Scatter-Gather DMA Channels
Provides Software Control of Interrupt Events
Provides Four General-Purpose Input/Outputs
Supports Plug-and-Play (PnP) Specification
Generates 32-Bit CRC for Transmission of 1394 Packets
Performs 32-Bit CRC Checking on Reception of 1394 Packets
Provides PCI Bus Master Function for Supporting DMA Operations
Provides PCI Slave Function for Read/Write Access of Internal Registers
Supports Distributed DMA Transfers Between 1394 and Local Bus RAM, ROM, AUX, or Zoomed Video