The device is a FET-integrated synchronous buck regulator designed mainly for DDR termination. It can provide a regulated output at ½ VDDQwith bothsink and source capability. Thedevice employs D-CAP+ mode operationthat provides ease of use, low external componentcount and fast transientresponse. The device can also be used for other point-of-load (POL)regulationapplications requiring up to 6 A. In addition, the device supports full, 6-A,outputsinking current capability with tight voltage regulation.
The device features two switching frequency settings (600 kHz and 1 MHz),integrateddroop support, external tracking capability, pre-bias startup,output soft discharge, integratedbootstrap switch, power good function, V5INpin UVLO protection, and supports both ceramic andSP/POSCAP capacitors. Itsupports input voltages up to 6.0 V, and output voltages adjustable fromto2.0 V.
Thedevice is available in the 3.5 mm × 4 mm, 20-pin, VQFNpackage (GreenRoHs compliant and Pb free) with TI proprietary Integrated MOSFET and packaging technology and is specified from –40°C to 85°C.
For all availablepackages, see the orderable addendum at theend of the data sheet.
TI proprietary Integrated MOSFET and Packaging Technology
Supports DDR Memory Termination with up to 6-A Continuous Output Source or Sink Current
Minimum External ComponentsCount
to6-V Conversion Voltage
Supports All MLCC Output Capacitors andSP/POSCAP
Selectable SKIP Mode orForced CCM
Optimized Efficiency at Light and Heavy Loads
Selectable600-kHz or 1-MHz Switching Frequency
Selectable Overcurrent Limit(OCL)
Overvoltage, Over-Temperature and Hiccup Undervoltage Protection