The TMS320VC5503 fixed-point digital signal processor (DSP) is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal busstructure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two datatransfers per cycle independent of the CPU activity.
The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit × 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.
The C55x DSP generation supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.
The 64K bytes of on-chip memory on TMS320VC5503 is sufficient for many hand-held appliances, portable GPS systems, wireless speaker phones, portable PDAs, and gaming devices. Many of these appliances typically require 64K bytes or smaller amount of on-chip memory and need to operate in standby mode for morethan 60% to 70% of the time. For applications that require more than 64K bytes of on-chip memory but less than 128K bytes of memory, Texas Instruments (TI) offers the TMS320VC5507 device, which is based on the TMS320C55x DSP core.
The general-purpose input and output functions and the 10-bit A/D provide sufficient pins for status, interrupts, and bit I/O for LCDs, keyboards, and media interfaces. The parallel interface operates in twomodes, either as a slave to a microcontroller using the HPI port or as a parallel media interfaceusing the asynchronous EMIF. Serial media is supported through three McBSPs.
The 5503 peripheral set includes an external memory interface (EMIF) that provides glueless access toasynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronousDRAM. Additional peripherals include real-time clock, watchdog timer, and I2C multi-master andslave interface. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to avariety of industry-standard serial devices, and multichannel communication with up to 128 separately enabledchannels. The enhanced host-port interface (HPI) is a 16-bit parallel interface used to provide host processoraccess to 32K bytes of internal memory on the 5503. The HPI can be configured in either multiplexed ornon-multiplexed mode to provide glueless interface to a wide variety of host processors. The DMA controllerprovides data movement for six independent channel contexts without CPU intervention, providing DMA throughputof up to two 16-bit words per cycle. Two general-purpose timers, up to eight dedicated general-purpose I/O(GPIO) pins, and digital phase-locked loop (DPLL) clock generation are also included.
High-Performance, Low-Power, Fixed-Point TMS320C55™ Digital Signal Processor
9.26-, 6.95-, 5-ns Instruction Cycle Time
108-, 144-, 200-MHz Clock Rate
One/Two Instruction(s) Executed per Cycle
Dual Multipliers [Up to 400 Million Multiply-Accumulates per Second (MMACS)]
Two Arithmetic/Logic Units (ALUs)
Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses
32K × 16-Bit On-Chip RAM, Composed of:
64K Bytes of Dual-Access RAM (DARAM) 8 Blocks of 4K × 16-Bit
64K Bytes of One-Wait-State On-Chip ROM (32K × 16-Bit)
8M × 16-Bit Maximum Addressable External Memory Space (Synchronous DRAM)
16-Bit External Parallel Bus Memory Supporting Either:
External Memory Interface (EMIF) With GPIO Capabilities and Glueless Interface to:
Asynchronous Static RAM (SRAM)
Synchronous DRAM (SDRAM)
16-Bit Parallel Enhanced Host-Port Interface (EHPI) With GPIO Capabilities
Programmable Low-Power Control of Six Device Functional Domains
On-Chip Scan-Based Emulation Logic
Two 20-Bit Timers
Six-Channel Direct Memory Access (DMA) Controller
Three Multichannel Buffered Serial Ports (McBSPs)
Programmable Phase-Locked Loop Clock Generator
Seven (LQFP) or Eight (BGA) General-Purpose I/O (GPIO) Pins and a General- Purpose Output Pin (XF)
Inter-Integrated Circuit (I2C) Multi-Master and Slave Interface
Real-Time Clock (RTC) With Crystal Input, Separate Clock Domain, Separate Power Supply