The TMS320VC5441 fixed-point digital signal processor is a quad-core solution running at 532-MIPS performance. The 5441 consists of four DSP subsystems with shared program memory. Each subsystem consists of one TMS320C54x DSP core, 32K-word program/data DARAM, 64K-word data DARAM, three multichannel buffered serial ports, DMA logic, one watchdog timer, one general-purpose timer, and other miscellaneous circuitry.
The 5441 also contains a host-port interface (HPI) that allows the 5441 to be viewed as a memory-mapped peripheral to a host processor.
Each subsystem has its separate program and data spaces, allowing simultaneous accesses to program instructions and data. Two read operations and one write operation can be performed in one cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. Furthermore, data can be transferred between program and data spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. The 5441 includes the control mechanisms to manage interrupts, repeated operations, and function calls. In addition, the 5441 has a total of 256K words of shared program memory (128K words shared by subsystems A and B, and another 128K words shared by subsystems C and D).
The 5441 is intended as a high-performance, low-cost, high-density DSP for remote data access or voice-over IP subsystems. It is designed to maintain the current modem architecture with minimal hardware and software impacts, thus maximizing reuse of existing modem technologies and development efforts.
The 5441 is offered in two temperature ranges and individual part numbers are shown below.
Commercial temperature devices (0°C to 85°C) TMS320VC5441PGF532 (176-pin LQFP) TMS320VC5441GGU532 (169-ball BGA)
Industrial temperature range devices (–40°C to 100°C) TMS320VC5441APGF532 (176-pin LQFP) TMS320VC5441AGGU532 (169-ball BGA)
532-MIPS Quad-Core DSP Consisting of Four Independent Subsystems
Each Core has an Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Bus
40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel-Shifter and Two 40-Bit Accumulators Per Core
Each Core has a 17-Bit × 17-Bit Parallel Multiplier Coupled to a 40-Bit Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operations
Each Core has a Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
Each Core has an Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
Each Core has Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
Total 640K-Word × 16-Bit Dual-Access On-Chip RAM (256K-Word x 16-Bit Shared Memory and 96K-Word x 16-Bit Local Memory Per Subsystem)
Single-Instruction Repeat and Block-Repeat Operations
Instructions With 32-Bit Long Word Operands
Instructions With 2 or 3 Operand Reads
Fast Return From Interrupts
Arithmetic Instructions With Parallel Store and Parallel Load
Conditional Store Instructions
Output Control of CLKOUT
Output Control of Timer Output (TOUT)
Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions
Dual 1.6-V (Core) and 3.3-V (I/O) Power Supplies for Low-Power, Fast Operations
7.5-ns Single-Cycle Fixed-Point Instruction
Twenty-Four Channels of Direct Memory Access (DMA) for Data Transfers With No CPU Loading (Six Channels Per Subsystem)
Twelve Multichannel Buffered Serial Ports (McBSPs), Each With 128-Channel Selection Capability (Three McBSPs per Subsystem)