The TMS320VC33 DSP is a 32-bit, floating-point processor manufactured in 0.18-µm four-level-metal CMOS (TImeline) technology. The TMS320VC33 is part of the TMS320C3x generation of DSPs from Texas Instruments.
The TMS320C3x’s internal busing and special digital-signal-processing instruction set have the speed and flexibility to execute up to 150 million floating-point operations per second (MFLOPS). The TMS320VC33 optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip.
The TMS320VC33 can perform parallel multiply and ALU operations on integer or floating-point data in a single cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs, internal dual-access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time. High performance and ease of use are the results of these features.
General-purpose applications are greatly enhanced by the large address space, multiprocessor interface, internally and externally generated wait states, one external interface port, two timers, one serial port, and multiple-interrupt structure. The TMS320C3x supports a wide variety of system applications from host processor to dedicated coprocessor. High-level-language support is easily implemented through a register-based architecture, large address space, powerful addressing modes, flexible instruction set, and well-supported floating-point arithmetic.
The TMS320VC33 is a superset of the TMS320C31. Designers now have an additional 1M bits of on-chip SRAM, a maximum throughput of 150 MFLOPS, and several I/O enhancements that allow easy upgrades to current systems or creation of new baselines. This data sheet provides information required to fully utilize the new features of the TMS320VC33 device. For general TMS320C3x architecture and programming information, see the TMS320C3x User’s Guide (literature number SPRU031).
High-Performance Floating-Point Digital Signal Processor (DSP):
13-ns Instruction Cycle Time
150 Million Floating-Point Operations Per Second (MFLOPS)
75 Million Instructions Per Second (MIPS)
17-ns Instruction Cycle Time
34K × 32-Bit (1.1-Mbit) On-Chip Words of Dual-Access Static Random-Access Memory (SRAM) Configured in 2 × 16K Plus 2 × 1K Blocks to Improve Internal Performance
x5 Phase-Locked Loop (PLL) Clock Generator
Very Low Power: < 200 mW @ 150 MFLOPS
32-Bit High-Performance CPU
16-/32-Bit Integer and 32-/40-Bit Floating-Point Operations
Four Internally Decoded Page Strobes to Simplify Interface to I/O and Memory Devices
EDGEMODE Selectable External Interrupts
32-Bit Instruction Word, 24-Bit Addresses
Eight Extended-Precision Registers
On-Chip Memory-Mapped Peripherals:
One Serial Port
Two 32-Bit Timers
Direct Memory Access (DMA) Coprocessor for Concurrent I/O and CPU Operation
Fabricated Using the 0.18-µm (leff-Effective Gate Length) TImeline™ Technology by Texas Instruments (TI)