The TMS320C64x+ DSPs (including the TMS320DM6433 device) are thehighest-performance fixed-point DSP generation in the TMS320C6000 DSP platform.The DM6433 device is based on the third-generation high-performance, advancedVelociTI very-long-instruction-word (VLIW) architecture developed by TexasInstruments (TI), making these DSPs an excellent choice for digital mediaapplications. The C64x+ devices are upward code-compatible from previousdevices that are part of the C6000 DSP platform. The C64x DSPs support addedfunctionality and have an expanded instruction set from previous devices.
Any reference to the C64x DSP or C64x CPU also applies, unless otherwisenoted, to the C64x+ DSP and C64x+ CPU, respectively.
With performance of up to 4800 million instructions per second (MIPS) at aclock rate of 600 MHz, the C64x+ core offers solutions to high-performance DSPprogramming challenges. The DSP core possesses the operational flexibility ofhigh-speed controllers and the numerical capability of array processors. TheC64x+ DSP core processor has 64 general-purpose registers of 32-bit word lengthand eight highly independent functional units-two multipliers for a 32-bitresult and six arithmetic logic units (ALUs). The eight functional units includeinstructions to accelerate the performance in video and imaging applications.The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for atotal of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle fora total of 4800 MMACS. For more details on the C64x+ DSP, see theTMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature numberSPRU732).
The DM6433 also has application-specific hardware logic, on-chip memory, andadditional on-chip peripherals similar to the other C6000 DSP platform devices.The DM6433 core uses a two-level cache-based architecture. The Level 1 programmemory/cache (L1P) consists of a 256K-bit memory space that can be configured asmapped memory or direct mapped cache, and the Level 1 data (L1D) consists of a640K-bit memory space-384K-bit of which is mapped memory and 256K-bit of whichcan be configured as mapped memory or 2-way set-associative cache. The Level 2memory/cache (L2) consists of a 1M-bit memory space that is shared betweenprogram and data space. L2 memory can be configured as mapped memory, cache, orcombinations of the two.
The peripheral set includes: 1 configurable video port; a 10/100 Mb/sEthernet MAC (EMAC) with a management data input/output (MDIO) module; a 4-bittransmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) Businterface; a multichannel buffered serial port (McBSP0); a multichannel audioserial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers eachconfigurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; auser-configurable 16-bit host-port interface (HPI); up to 111-pins ofgeneral-purpose input/output (GPIO) with programmable interrupt/event generationmodes, multiplexed with other peripherals; a UART with hardware handshakingsupport; 3 pulse width modulator (PWM) peripherals; 1 peripheral componentinterconnect (PCI) [33 MHz]; and 2 glueless external memory interfaces: anasynchronous external memory interface (EMIFA) for slower memories/peripherals,and a higher speed synchronous memory interface for DDR2.
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High-Performance Digital Media Processor (DM6433)
2.5-, 2-, 1.67, 1.51-, 1.43-ns Instruction Cycle Time
400-, 500-, 600-, 660-, 700-MHz C64x+™ Clock Rate
Eight 32-Bit C64x+ Instructions/Cycle
3200, 4000, 4800, 5280, 5600 MIPS
Fully Software-Compatible With C64x
Commercial and Automotive (Q or S suffix) Grades
Low-Power Device (L suffix)
VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
Eight Highly Independent Functional Units With VelociTI.2 Extensions:
Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
Two Multipliers Support Four 16 × 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-Bit Multiplies (16-Bit Results) per Clock Cycle
Load-Store Architecture With Non-Aligned Support
64 32-Bit General-Purpose Registers
Instruction Packing Reduces Code Size
All Instructions Conditional
Additional C64x+™ Enhancements
Protected Mode Operation
Exceptions Support for Error Detection and Program Redirection
Hardware Support for Modulo Loop Auto-Focus Module Operation
C64x+ Instruction Set Features
Byte-Addressable (8-/16-/32-/64-Bit Data)
8-Bit Overflow Protection
Bit-Field Extract, Set, Clear
Normalization, Saturation, Bit-Counting
VelociTI.2 Increased Orthogonality
Compact 16-bit Instructions
Additional Instructions to Support Complex Multiplies
C64x+ L1/L2 Memory Architecture
256K-Bit (32K-Byte) L1P Program RAM/Cache [Flexible Allocation]
640K-Bit (80K-Byte) L1D Data RAM/Cache [Flexible Allocation]