The DP83865 is a fully featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-T, 100BASE-TX and 1000BASE-T Ethernet protocols.
The DP83865 is an ultra low power version of the DP83861 and DP83891. It uses advanced 0.18 um, 1.8 V CMOS technology, fabricated at National Semiconductors South Portland, Maine facility.
The DP83865 is designed for easy implementation of 10/100/1000 Mb/s Ethernet LANs. It interfaces directly to Twisted Pair media via an external transformer. This device interfaces directly to the MAC layer through the IEEE 802.3u Standard Media Independent Interface (MII), the IEEE 802.3z Gigabit Media Independent Interface (GMII), or Reduced GMII (RGMII).
The DP83865 is a fourth generation Gigabit PHY with field proven architecture and performance. Its robust performance ensures drop-in replacement of existing 10/100 Mbps equipment with ten to one hundred times the performance using the existing networking infrastructure.
Ultra low power consumption typically 1.1 watt
Fully compliant with IEEE 802.3 10BASE-T, 100BASE-TX and 1000BASE-T specifications
Integrated PMD sublayer featuring adaptive equalization and baseline wander compensation according to ANSI X3.T12
3.3V or 2.5V MAC interfaces:
IEEE 802.3u MII
IEEE 802.3z GMII
RGMII version 1.3
User programmable GMII pin ordering
IEEE 802.3u Auto-Negotiation and Parallel Detection
Fully Auto-Negotiates between 1000 Mb/s, 100 Mb/s, and 10 Mb/s full duplex and half duplex devices
Speed Fallback mode to achieve quality link
Cable length estimator
LED support for activity, full / half duplex, link1000, link100 and link10, user programmable (manual on/off), or reduced LED mode
Supports 25 MHz operation with crystal or oscillator.
Requires only two power supplies, 1.8V (core and analog) and 2.5V (analog and I/O). 3.3V issupported as an alternative supply for I/O voltage