CD4517B dual 64-stage static shift register consists of two independent registers each having a clock, data, and write enable input and outputs accessible at taps following the 16th, 32nd, 48th, and 64th stages. These taps also serve as input points allowing data to be inputted at the 17th, 33rd, and 49th stages when the write enable input is a logic 1 and the clock goes through a low-to-high transition. The truth table indicates how the clock and write enable inputs control the operation of the CD4517B. Inputs at the intermediate taps allow entry of 64 bits into the register with 16 clock pulses. The 3-state outputs permit connection of this device to an external bus.
The CD4517B is supplied in 16-lead hermetic dual-in-line ceramic packages (D and F suffixes), 16-lead dual-in-line plastic packages (E suffix), and in chip form (H suffix).
Low quiescent current - 10 nA/pkg (typ.) at VDD = 5 V
Clock frequency 12 MHz (typ.) at VDD = 10 V
Schmitt trigger clock inputs allow operation with very slow clock rise and fall times
Capable of driving two low-power TTL loads, one low-power Schottky TTL load, or two HTL loads
100% tested for quiescent current at 20 V
Standardized, symmetrical output characteristics
5-V, 10-V and 15-V parametric ratings
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices